TWI828206B - Memory device and operation method thereof for performing multiply-accumulate operation - Google Patents

Abstract

A memory device and an operation method thereof for performing a multiply-accumulate operation are provided. The memory device includes at least one memory string, a plurality of data lines and a string line. The memory string includes a plurality of unit cells having a plurality of stored values. The data lines are respectively connected to the unit cells to receive a plurality of data signals having a plurality of inputting values. When the data signals are inputted into the unit cells, a plurality of nodes among the unit cells are kept at identical voltages. The string line is connected to the memory string to receive a sensing signal and obtain a measured value representing a sum-of-product result of the inputting values and the stored values. The data signals and the sensing signal are received at different time.

Description

Memory device and operating method for performing multiplication and addition operations

The present disclosure relates to a semiconductor device and an operation method thereof, and in particular, to a memory device and an operation method thereof for performing multiplication and addition operations.

With the development of artificial intelligence technology (AI), in-memory-computing technology has been widely used in various electronic devices. In a memory device that performs multiply-and-accumulate operations, the input voltage of each memory cell string will be affected by the body effect and deviate, making it impossible to obtain a correct product sum result from the memory cell string. Therefore, it is extremely necessary to improve the problems of matrix effect and input voltage offset.

The present disclosure relates to a memory device and an operation method thereof for performing multiplication and addition operations. When data signals are input to the unit memory cells, the nodes between the unit memory cells can be maintained at the same voltage level. Therefore, the input to the unit memory cell The data signal will not be offset, and the sum of the products of the input value and the stored value can be correctly read from the memory cell string. Furthermore, the product sum results of neural network operations can be directly passed to the next layer. In this way, the computational efficiency and output capabilities of neural networks can be greatly improved.

According to one aspect of the present disclosure, a memory device is provided. The memory device includes at least one memory cell string, several data lines and a serial line. The memory cell string includes several unit memory cells. These unit memory cells have several stored values. These data lines are respectively connected to these unit memory cells to receive several data signals. These data signals have several input values. When these data signals are input to these unit memory cells, several nodes between these unit memory cells are at the same voltage level. Serial lines connect these memory cell strings to receive a sensing signal and obtain a measurement value. The measured value represents the sum of the products of these input values and one of these stored values. These data signals and sensing signals are received at different times.

According to another aspect of the present disclosure, a method of operating a memory device is provided to perform multiplication and addition operations. The operation method of the memory device includes the following steps. Input several data signals to at least one memory cell string. These data signals have several input values. The memory cell string includes several unit memory cells. These unit memory cells contain several stored values. Several nodes between these unit memory cells are at the same voltage level. A sensing signal is applied to the memory cell string to obtain a measurement value. The measured value represents the sum of the products of these input values and one of these stored values. The steps of inputting these data signals and applying the sensing signals are performed at different times.

In order to have a better understanding of the above and other aspects of the present disclosure, embodiments are given below and described in detail with reference to the accompanying drawings:

100,200,300,400: memory device

430: Voltage modulation circuit

C61,C62,C63,C64,C65,C66,C71,C72,C73,C74: Curve

CAj,CAj’,CAj”: electrical characteristics adjustable components

cp: capacitor

Dj: data signal

I1: sensing signal

I2: measured value

Ldj: data line

Ls: serial line

LY_s,LY_s+1,LY_s+2,LY_s+3: stratum

MS1, MS2: memory cell string

Nk: node

Rj: saved value

RTj, RTj’: resistance

S110, S120: steps

Sw: switching signal

TM: endpoint

ts1: first transistor

ts2: second transistor

UCj,UCj’,UCj”: unit memory cell

V1: measured value

V2: Sensing signal

Xj: input value

Figures 1A and 1B illustrate a memory device and a method of operating the same according to one embodiment.

Figures 2A and 2B illustrate a memory device and a method of operating the same according to one embodiment.

FIG. 3 illustrates a flowchart of an operating method of a memory device according to an embodiment.

Figures 4A and 4B illustrate detailed design views of the memory device of Figures 1A and 1B according to one embodiment.

Figures 5A and 5B illustrate detailed design views of the memory device of Figures 2A and 2B according to one embodiment.

Figure 6A shows a detailed design diagram of a unit memory cell according to an embodiment.

Figure 6B illustrates the change in the equivalent resistance value of a unit memory cell.

Figure 7A shows a detailed design diagram of a unit memory cell according to an embodiment.

Figure 7B illustrates the change in the equivalent resistance value of a unit memory cell.

Figures 8A to 8C illustrate a memory device and an operating method thereof according to another embodiment.

Figure 9 is a schematic diagram of a memory device according to another embodiment.

Please refer to FIGS. 1A and 1B , which illustrate a memory device 100 and a method of operating the same according to an embodiment. The memory device 100 includes at least one memory cell string MS1, a plurality of data lines Ldj and a series line Ls. The number of at least one memory cell string MS1 is one or more. In Figures 1A and 1B, only one memory cell string MS1 is shown. The memory cell string MS1 includes several unit memory cells UCj. These unit memory cells UCj are connected in series.

Each unit memory cell UCj has a stored value Rj. The stored value Rj is, for example, a resistance value. As shown in Figure 1A, the data lines Ldj are respectively connected to the unit memory cells UCj to receive the data signal Dj having the input value Xj. Each input value Xj can be a single value or the sum of a series of values in several steps. When the data signal Dj is input to the unit memory cell UCj, the nodes Nk between the unit memory cells UCj are at the same voltage level. For example, both ends of the memory cell string MS1 may be grounded. Alternatively, in another embodiment, the same voltage level may be applied to both ends of the memory cell string MS1. Since the node Nk connected to the unit memory cell UCj is at the same voltage level, the matrix effect will no longer occur.

The electrical characteristics of each unit memory cell UCj will change with the stored value Rj, input value and input value Xj. For example, the equivalent resistance value of the unit memory cell UCj is positively correlated with the input value Xj and the stored value Rj. Therefore, the equivalent resistance value of the unit memory cell UCj can be expressed as the product of the input value Xj and the stored value Rj.

Then, as shown in Figure 1B, the series line Ls connected to the memory cell string MS1 receives a sensing signal I1 to obtain a measurement value V1. The sensing signal I1 is, for example, a constant current flowing through the unit memory cell UCj, and the measurement value V1 is a voltage value that changes with all equivalent resistance values of the unit memory cell UCj. That is to say, the measured value V1 can be used to represent the sum of the products of the input value Xj and the stored value Rj.

Please refer to FIGS. 2A and 2B , which illustrate a memory device 200 and a method of operating the same according to an embodiment. The memory device 200 includes at least one memory cell string MS2, a data line Ldj and a serial line Ls. The number of at least one memory cell string MS2 is one or more. In Figures 2A and 2B, only one memory cell string MS2 is shown. The memory cell string MS2 includes several unit memory cells UCj. One end of each unit memory cell UCj is connected to the series line Ls.

Each unit memory cell UCj has a stored value Rj. The stored value Rj is, for example, a resistance value. As shown in Figure 2A, the data lines Ldj are respectively connected to the unit memory cells UCj to receive the data signal Dj having the input value Xj. When the data signal Dj is input to the unit memory cell UCj, the nodes Nk between the unit memory cells UCj are at the same voltage level. For example, both ends of the memory cell string MS2 can be grounded. Alternatively, in another embodiment, the same voltage level may be applied to both ends of the memory cell string MS2.

The electrical characteristics of each unit memory cell UCj will change with the stored value Rj and the input value Xj. For example, the equivalent resistance value of the unit memory cell UCj is positively correlated with the input value Xj and the stored value Rj, so the equivalent resistance value of the unit memory cell UCj can be expressed as the product of the input value Xj and the stored value Rj.

Then, as shown in Figure 2B, the series line Ls connected to the memory cell string MS2 receives a sensing signal V2 to obtain a measurement value I2. The sensing signal V2 is, for example, a certain voltage, and the measurement value I2 is a current value that changes with all equivalent resistance values of the unit memory cell UCj. That is to say, the measured value I2 can be used to represent the sum of the products of the input value Xj and the stored value Rj.

As mentioned above, the operating method of the memory device 100 in Figures 1A and 1B and the operating method of the memory device 200 in Figures 2A and 2B can be executed through the following flowchart. Please refer to FIG. 3 , which illustrates a flowchart of an operating method of the memory device 100, 200 according to an embodiment. In step S110, the data signal Dj having the input value Xj is input to the data line Ldj of at least one memory cell string MS1, MS2. In step S120, the sensing signals I1 and V2 are applied to the series lines Ls of the memory cell strings MS1 and MS2 to obtain the measurement values V1 and I2 representing the sum of the products of the input value Xj and the stored value Rj. Step S110 of inputting the data signal Dj to the data line Ldj and step S120 of applying the sensing signals I1 and V2 to the series line Ls are executed at different times, so that both ends of the memory cell strings MS1 and MS2 in step S110 can be grounded. or the same voltage level is applied. The data signal Dj and the sensing signals I1 and V2 are received at different times. For example, the data signal Dj is first received through the data line Ldj in step S110, and then the sensing signals I1 and V2 are received through the serial line Ls in step S120. When the data signal Dj is received by the data line Ldj in step S110, there is no need to use the series line Ls to receive the sensing signals I1 and V2. Therefore, both ends of the series line Ls of the memory cell strings MS1 and MS2 can be grounded or the same voltage can be applied. Level.

Please refer to Figures 4A and 4B, which illustrate Figures 1A, 1A and 4B according to an embodiment. Figure 1B is a detailed design diagram of the memory device 100. Each unit memory cell UCj includes a resistor RTj and an electrical characteristic adjustable element CAj. The resistor RTj can be a high-resistance metal material, a resistive memory (such as ReRAM, PCRAM), or a non-volatile memory (Non-Volatile Memory, NVM). The resistance value of resistor RTj represents the stored value Rj. The electrical characteristic adjustable element CAj is connected in parallel with the resistor RTj. The electrical characteristics of the electrical characteristic adjustable element CAj can be adjusted according to the data signal Dj. For example, the electrical characteristic of the electrical characteristic adjustable element CAj is, for example, a resistance value. When the electrical characteristics of the electrical characteristic adjustable element CAj change, the equivalent resistance value of the unit memory cell UCj will also change. When the data signal Dj is input to the unit memory cell UCj, the node Nk between the unit memory cells UCj is maintained at the same voltage level. Therefore, the data signal Dj input to the unit memory cell UCj will not be offset, and the sum of the products of the input value Xj and the stored value Rj can be correctly read from the memory cell string MS1.

Please refer to FIGS. 5A and 5B , which illustrate detailed design views of the memory device 200 of FIGS. 2A and 2B according to an embodiment. Each unit memory cell UCj includes a resistor RTj and an electrical characteristic adjustable element CAj. The resistance value of resistor RTj represents the stored value Rj. The electrical characteristic adjustable element CAj is connected in parallel with the resistor RTj. The electrical characteristics of the electrical characteristic adjustable element CAj can be adjusted according to the data signal Dj. For example, the electrical characteristic of the electrical characteristic adjustable element CAj is, for example, a resistance value. When the electrical characteristics of the electrical characteristic adjustable element CAj change, the equivalent resistance value of the unit memory cell UCj will also change. When the data signal Dj is input to the unit memory cell UCj, the node Nk between the unit memory cells UCj is maintained at the same voltage level. Therefore, the data signal Dj input to the unit memory cell UCj will not be offset, and the input value The product sum result of the stored value Rj can be correctly read from the memory cell string MS2.

Please refer to Figure 6A, which illustrates a detailed design of the unit memory cell UCj' according to an embodiment. The unit memory cell UCj' includes a resistor RTj' and an electrical characteristic adjustable element CAj'. The electrical characteristic adjustable element CAj' is, for example, an electrochemical random access memory (ECRAM), a resistive memory (memristor) or ReRAM. The resistance of a channel in ECRAM can be tuned by ion exchange at the interface between the channel and the electrolyte when an electric field is applied. Therefore, the resistance value of the electrical characteristic adjustable element CAj' can be adjusted according to the data signal Dj. The unit memory cell UCj' can be used in the memory device 100 of Figures 4A and 4B or the memory device 200 of Figures 5A and 5B.

Please refer to Figure 6B, which illustrates the change in the equivalent resistance value of the unit memory cell UCj’. Curves C61~C66 are different measurement results when the resistance value of resistor RTj’ is located at 0.5, 1, 2, 4, 8, and 16 units respectively. As shown in curve C66, the equivalent resistance value of the unit memory cell UCj' is positively correlated with the resistance value of the electrical characteristic adjustable element CAj'. As shown in the curves C61~C66, the equivalent resistance value of the unit memory cell UCj’ is also positively correlated with the resistance value of the resistor RTj’. In other words, the equivalent resistance value of the unit memory cell UCj' is positively correlated with the input value Xj and the stored value Rj. Therefore, the equivalent resistance value of the unit memory cell UCj' can be expressed as the sum of the input value product.

Please refer to Figure 7A, which illustrates a detailed design diagram of the unit memory cell UCj" according to an embodiment. The unit memory cell UCj" includes a resistor RTj" and an electrical characteristic adjustable element CAj". The electrical characteristic adjustable element CAj" includes a first transistor The body ts1, a capacitor cp (the capacitor cp can be a series capacitor or a parasitic capacitance of a transistor) and a second transistor ts2. The first transistor ts1 is used to receive the data signal Dj. The capacitor cp is connected to the first transistor ts1. The second transistor ts2 is connected to the capacitor cp. When the first transistor ts1 is turned on by the switching signal Sw, the data signal Dj can be stored in the capacitor cp. Therefore, the resistance value of the electrical characteristic adjustable element CAj″ can be adjusted according to the data signal Dj. The unit memory cell UCj″ can be used in the memory device 100 of Figures 4A and 4B or the memory device 200 of Figures 5A and 5B.

Please refer to Figure 7B, which illustrates the change in the equivalent resistance value of the unit memory cell UCj". Curves C71~C74 are different measurement results when the resistance value of the resistor RTj" is located at 1, 2, 3, and 4 units respectively. As shown in the curve C74, the equivalent resistance value of the unit memory cell UCj″ is positively correlated with the voltage input to the second transistor ts2. The voltage input to the second transistor ts2 is positively correlated with the input value Xj. As shown in the curve C71 As shown in ~C74, the equivalent resistance value of the unit memory cell UCj" is also positively correlated with the resistance value of the resistor RTj". In other words, the equivalent resistance value of the unit memory cell UCj" is related to the input value Xj and the stored value Rj There is a positive correlation, so the equivalent resistance value of the unit memory cell UCj" can be expressed as the product of the input value Xj and the stored value Rj.

Please refer to FIGS. 8A to 8C , which illustrate a memory device 300 and an operation method thereof according to another embodiment. As shown in FIG. 8A , the memory device 300 includes more than one set of memory cell strings MS1. The endpoint TM of the memory cell string MS1 of level LY_s is connected to a certain unit memory cell UCj of the memory cell string MS1 of level LY_s+1. The stored value Rj and the input value Xj have been stored in the memory cell string MS1 of level LY_s. The memory cell string MS1 of layer LY_s is applied with the sensing signal I1 to Obtain the measurement value V1. The measurement value V1 is passed to the memory cell string MS1 of level LY_s+1 and is used as a certain data signal Dj.

When the step S120 of applying the sensing signal I1 is performed to the memory cell string MS1 of the level LY_s, the step S110 of inputting the data signal Dj can be performed to the memory cell string MS1 of the level LY_s+1 at the same time.

Next, as shown in Figure 8B, when performing step S120 of applying the sensing signal I1 to the memory cell string MS1 of level LY_s+1, step S110 of inputting the data signal Dj to the memory cell string MS1 of level LY_s+2 can be performed at the same time. .

Then, as shown in Figure 8C, when performing step S120 of applying the sensing signal I1 to the memory cell string MS1 of level LY_s+2, step S110 of inputting the data signal Dj to the memory cell string MS1 of level LY_s+3 can be performed at the same time. . That is to say, step S110 and step S120 may be executed at each level in an interleaved manner.

In addition, please refer to FIG. 9 , which illustrates a schematic diagram of a memory device 400 according to another embodiment. The memory device 400 further includes a voltage modulation circuit 430 . After the measurement value V1 is obtained, the measurement value V1 is input to the voltage modulation circuit 430 . The voltage modulation circuit 430 is used to adjust the measurement value V1 to meet the requirements of the unit memory cell UCj of the level LY_s+1. The voltage modulation circuit 430 may perform modulation using mathematical calculation procedures required for neural network calculations.

The measurement value V1 is passed to the memory cell string MS1 of level LY_s+1 and is used as a certain data signal Dj. In other words, without using an analog-to-digital converter, the product sum result of the neural network operation can be directly passed to the next layer. In this way, the computational efficiency and output capabilities of neural networks can be greatly improved.

According to the above embodiment, when the data signal Dj is input to the unit memory cell UCj, the node Nk between the unit memory cells UCj can be maintained at the same voltage level. Therefore, the data signal Dj input to the unit memory cell UCj will not be offset, and the sum of the products of the input value Xj and the stored value Rj can be correctly read from the memory cell strings MS1 and MS2. Furthermore, the product sum results of neural network operations can be directly passed to the next layer. In this way, the computational efficiency and output capabilities of neural networks can be greatly improved.

In summary, although the present disclosure has been disclosed in the above embodiments, they are not used to limit the present disclosure. Those with ordinary knowledge in the technical field to which this disclosure belongs can make various modifications and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection scope of the present disclosure shall be subject to the scope of the appended patent application.

100:Memory device

Dj: data signal

Ldj: data line

Ls: serial line

MS1: memory cell string

Nk: node

Rj: saved value

UCj: unit memory cell

Xj: input value

Claims (10)

A memory device, including: at least one memory cell string, including a plurality of unit memory cells, the unit memory cells having a plurality of stored values; a plurality of data lines, respectively connected to the unit memory cells to receive a plurality of pens Data signals, these data signals have a plurality of input values. When the data signals are input to the unit memory cells, a plurality of nodes between the unit memory cells are at the same voltage level; and a series of lines connected The memory cell strings receive a sensing signal and obtain a measurement value, which represents the product sum of the input values and the stored values; wherein the data signals and the sensing The signals are received at different times. The memory device of claim 1, wherein the unit memory cells are connected in series. When the unit memory cells receive the data signals, both ends of each memory cell string are grounded. The memory device of claim 1, wherein each unit memory cell includes: a resistor, the resistance of each resistor represents the stored value; and an electrical characteristic adjustable component, each electrical characteristic can be The adjustable element is connected in parallel to each resistor, and one of the electrical characteristics of each electrical characteristic adjustable element is adjusted according to each data signal. The memory device of claim 3, wherein each of the electrical characteristic adjustable components includes: a first transistor, each first transistor is used to receive each of the data signals; a capacitor, each of the capacitors is connected to Each first transistor; and a second transistor, each second transistor is connected to each capacitor. The memory device of claim 1, wherein the number of the at least one memory cell string is a plurality, and one end of one of the memory cell strings is connected to the unit memory cells of another of the memory cell strings. one to enter the product sum result. The memory device of claim 1, wherein one end of each unit memory cell is connected to the series line, and the other end of each unit memory cell is grounded. An operating method of a memory device to perform multiplication and addition operations, including: inputting a plurality of data signals to at least one memory cell string, the data signals having a plurality of input values, the memory cell string including a plurality of unit memory cells, the Some unit memory cells include a plurality of stored values, and a plurality of nodes between the unit memory cells are at the same voltage level; a sensing signal is applied to the memory cell string to obtain a measurement value, and the measurement value Represents the sum of the products of the input values and one of the stored values; The step of inputting the data signals and the step of applying the sensing signal are performed at different times. The operating method of the memory device as described in claim 7, wherein the unit memory cells are connected in series, and in the step of inputting the data signals, both ends of each memory cell string are grounded. The operating method of the memory device according to claim 7, wherein the number of the at least one memory cell string is a plurality, and one end of one of the memory cell strings is connected to the other of the memory cell strings. One of the unit memory cells to input the sum of products result. The operating method of the memory device as claimed in claim 7, wherein one end of each unit memory cell is connected to a series line, and the other end of each unit memory cell is grounded.

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