TWI828118B - Detection device - Google Patents

Abstract

A detection device including a substrate, a gate line, a gate line driving circuit and a photoelectric element is provided. The substrate includes a detection area and a peripheral area surrounding the detection area. The gate line is disposed on the substrate and extends from the detection area to the peripheral area. The gate line driving circuit is arranged in the peripheral region of the substrate and includes a first transistor and a second transistor. The first transistor is coupled to the first clock signal and the gate line. The second transistor is coupled to the second clock signal and the first transistor. The photoelectric element is arranged in the detection area and is coupled to the gate line. The distance between the second transistor and the detection area is smaller than the distance between the first transistor and the detection area.

Description

detection device

The present invention relates to a device, and in particular to a detection device.

For general X-ray (X-ray) detectors, the threshold voltage of the transistor (transistor) installed in the X-ray detector for high-speed switching is easy to occur after a long period of operation. The phenomenon of voltage offset makes the detection signal generated by the X-ray detector prone to abnormalities accordingly, and it is unable to provide effective and/or correct light detection functions.

This disclosure is directed to a detection device that can achieve better detection functions.

According to an embodiment of the present disclosure, the detection device of the present disclosure includes a substrate, a gate line, a gate line driving circuit, and an optoelectronic component. The substrate includes a detection area and a peripheral area surrounding the detection area. The gate line is disposed on the substrate and extends from the detection area to the peripheral area. The gate line driving circuit is disposed in the peripheral area of the substrate and includes a first transistor and a second transistor. The first transistor is coupled to the first clock signal and the gate line. The second transistor is coupled to the second clock signal and the first transistor. The photoelectric element is disposed in the detection area and coupled to the gate line. The distance between the second transistor and the detection area is smaller than the distance between the first transistor and the detection area.

Based on the above, the detection device of the present disclosure can effectively improve or overcome the voltage offset effect of the transistor provided in the detection device, and can achieve better detection function.

In order to make the above features and advantages of the present disclosure more obvious and understandable, embodiments are given below and described in detail with reference to the accompanying drawings.

Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numbers are used in the drawings and description to refer to the same or similar parts.

Throughout this disclosure and the appended claims, certain words are used to refer to specific elements. Those skilled in the art will appreciate that manufacturers of electronic devices may refer to the same component by different names. This article is not intended to differentiate between components that have the same functionality but have different names. In the following description and patent application, the words "including" and "include" are open-ended words, so they should be interpreted to mean "including but not limited to...".

The directional terms mentioned in this article, such as: "up", "down", "front", "back", "left", "right", etc., are only for reference to the directions in the drawings. Accordingly, the directional terms used are illustrative and not limiting of the disclosure. In the drawings, each figure illustrates the general features of methods, structures, and/or materials used in particular embodiments. However, these drawings should not be interpreted as defining or limiting the scope or nature encompassed by these embodiments. For example, the relative sizes, thicknesses, and locations of various layers, regions, and/or structures may be reduced or exaggerated for clarity.

In some embodiments of the present disclosure, terms related to joining and connecting, such as "connection", "interconnection", etc., unless otherwise defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, where There are other structures located between these two structures. And the terms about joining and connecting can also include the situation where both structures are movable, or when both structures are fixed. Furthermore, the term "coupled" includes any direct or indirect means of electrical connection. In the case of direct electrical connection, the end points of the components on the two circuits are directly connected or connected to each other with a conductor segment, while in the case of indirect electrical connection, there are switches and diode between the end points of the components on the two circuits. body, capacitor, inductor, resistor, other suitable components, or a combination of the above components, but is not limited to this.

The terms "about", "equal to", "equal" or "the same", "substantially" or "substantially" are generally interpreted to mean within 20% of a given value or range, or to mean within a given value or range. Within 10%, 5%, 3%, 2%, 1% or 0.5% of the value or range.

In this disclosure, the thickness, length and width can be measured by using an optical microscope (OM), and the thickness or width can be measured by cross-sectional images in an electron microscope, but not by This is the limit. In addition, any two values or directions used for comparison may have certain errors. In addition, the terms "the given range is the first value to the second value" and "the given range falls within the range of the first value to the second value" mean that the given range includes the first value, the second value and their other values in between. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees. The angle between directions can be between 0 and 10 degrees.

The ordinal numbers used in the specification and the scope of the patent application, such as "first", "second", etc., are used to modify components. They themselves do not imply or represent that the component or components have any previous sequence number, nor do they mean that the component has any previous sequence number. It does not represent the order of one element with another element, or the order of the manufacturing method. The use of these numbers is only used to clearly distinguish an element with a certain name from another element with the same name. The same words may not be used in the patent application scope and the description. Accordingly, the first component in the description may be the second component in the patent application scope. It should be noted that in the following embodiments, the technical features in several different embodiments can be replaced, reorganized, and mixed to complete other embodiments without departing from the spirit of the present disclosure.

It should be noted that the following embodiments can be replaced, reorganized, and mixed with features of several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. Features in various embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with the relevant technology and the background or context of the present disclosure, and should not be interpreted in an idealized or overly formal manner. Unless otherwise defined in the embodiments of this disclosure.

In the present disclosure, the electronic device may include a display device, a backlight device, an antenna device, a sensing/detection device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing/detection device may be a device that senses capacitance, light, heat energy or ultrasonic waves, but is not limited thereto. In the present disclosure, the electronic device may include electronic components, and the electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light emitting diodes or photodiodes. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED) or a quantum dot light emitting diode (quantum LED). dot LED), but not limited to this. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any combination of the above, but is not limited thereto. In the following description, the detection device will be used as an electronic device or a splicing device to illustrate the disclosure, but the disclosure is not limited thereto.

FIG. 1 is a schematic diagram of a detection device according to an embodiment of the present disclosure. Referring to FIG. 1 , the detection device 100 includes gate lines G_1 to G_M, gate line driving circuits 110_1 to 110_M, photoelectric elements 120_1 to 120_N, and a substrate 105 , where M and N are positive integers respectively. The detection device 100 may be an X-ray detector, but is not limited thereto. From the top view direction of the detection device 100 (for example, the direction Z, where the substrate 105 of the detection device 100 is parallel to the plane formed along the direction X and the direction Y, and the direction X, the direction Y and the direction Z intersect each other, such as the direction From the perspective of X, direction Y and direction Z being perpendicular to each other), the substrate 105 includes a detection area 101 (or active area (Active Area, AA)) and a peripheral area 104. The peripheral area 104 surrounds the detection area 101 . The detection area 101 means that the photoelectric components in this area can transmit the detected signal strength to the outside of the detection device 100 in the form of electrical signals through active components (not shown), for example, providing the electrical signals to other Electronic devices are used for interpretation, but are not limited to this. In addition, when the detection device 100 is an X-ray detector, the substrate 105 may also include an X-ray irradiation area 103. Viewed from the direction Z, the range of the X-ray irradiation area 103 covers the range of the detection area 101. In other words, The area of the light irradiation area 103 is larger than the detection area 101 . The X-ray irradiation area 103 includes the detection area 101 and a portion of the peripheral area 104 adjacent to the detection area 101 . The peripheral area 104 is the area from the edge of the substrate 105 to the edge of the detection area 101 .

In this embodiment, the gate lines G_1 to G_M are disposed on the substrate 105 and extend from the detection area 101 to the peripheral area 104 . The gate line driving circuits 110_1~110_M are disposed in the peripheral area 104 of the substrate 105, and each includes a first transistor 111_1~111_M and a second transistor 112_1~112_M. For example, the gate line driving circuit 110_1 includes a first transistor 111_1 and a second transistor 112_1, the gate line driving circuit 110_2 includes a first transistor 111_2 and a second transistor 112_2, and so on. The gate line driving circuits 110_1~110_M may be disposed in the peripheral area 104 corresponding to one side of the detection area 101, but the disclosure is not limited thereto. In this embodiment, the gate line driving circuit 110_1 is coupled to the gate line G_1 and is coupled to the gate line driving circuit 110_2. The gate line driving circuit 110_2 is coupled to the gate line G_2 and coupled to the gate line driving circuit 110_3. By analogy, the gate line driving circuit 110_(M-1) is coupled to the gate line G_(M-1) and coupled to the gate line driving circuit 110_M. The gate line driving circuit 110_M is coupled to the gate line G_M. In another embodiment, in addition to setting the gate line driving circuit in the peripheral area 104 on one side of the detection area 101, a gate line driving circuit can also be provided in the peripheral area 104 on the opposite side of the detection area 101. pole line drive circuit. The transistor may include a gate and a semiconductor. The semiconductor may include a drain region, a source region and a channel region. The channel region is disposed between the drain region and the source region. In addition, a drain electrode and a source electrode may be included respectively coupled to the drain region and the source region of the semiconductor.

In this embodiment, the first transistors 111_1 ~ 111_M in the gate line driving circuits 110_1 ~ 110_M are respectively coupled to the corresponding gate lines. For example, the first transistor 111_1 of the gate line driving circuit 110_1 is coupled to the gate. Line G_1. The first transistor 111_2 of the gate line driving circuit 110_2 is coupled to the gate line G_2. By analogy, the first transistor 111_M of the gate line driving circuit 110_M is coupled to the gate line G_M. In this embodiment, the gate line driving circuits 110_1 ~ 110_M are respectively coupled to the first clock signal C1 and the second clock signal C2. The first transistors 111_1~111_M are respectively coupled to the corresponding second transistors 112_1~112_M. In this embodiment, the first transistor 111_1 of the gate line driving circuit 110_1 is coupled to the first clock signal C1, and the second transistor 112_1 is coupled to the second clock signal C2. The first transistor 111_2 of the gate line driving circuit 110_2 is coupled to the second clock signal C2, and the second transistor 112_2 is coupled to the first clock signal C1. By analogy, the first transistor 111_M of the gate line driving circuit 110_M is coupled to the first clock signal C1, and the second transistor 112_M is coupled to the second clock signal C2. In other words, the first transistor of the gate line driving circuit of odd rows may be coupled to the first clock signal C1, and the second transistor may be coupled to the second clock signal C2. The first transistor of the even-numbered row gate line driving circuit may be coupled to the second clock signal C2, and the second transistor may be coupled to the first clock signal C1. Regardless of the gate line driving circuit of odd-numbered rows or even-numbered rows, the second transistor is coupled to the first transistor. The photoelectric elements 120_1~120_N are arranged in the detection area 101. The gate line G_1 is coupled to a plurality of photoelectric components. The gate line G_2 is coupled to a plurality of photoelectric components. By analogy, the gate line G_M is coupled to multiple photoelectric elements.

In this embodiment, viewed from the top view direction of the detection device 100 (ie, direction Z), the distance d2 between the second transistors 112_1 ~ 112_M and the detection area 101 is smaller than the distance d2 between the first transistors 111_1 ~ 111_M and the detection area 101 respectively. The distance d1 between the measurement areas 101. The distance d1 and the distance d2, taking the gate line driving circuit 110_1 as an example, refer to the direction in which the respective semiconductors of the first transistor 111_1 and the second transistor 112_1 extend along the gate line G_1 (ie, the direction X ) to measure the shortest distance to the detection area 101. In this embodiment, the first transistors 111_1~111_M are respectively disposed in the peripheral area 104 outside the X-ray irradiation area 103, and the second transistors 112_1~112_M are respectively disposed in the X-ray irradiation area 103 outside the detection area 101. within.

In this embodiment, the photoelectric elements 120_1~120_N can be arranged in an array in the detection area 101, but are not limited thereto. The photoelectric elements 120_1 ~ 120_N may respectively include photodiodes, but are not limited thereto. The gate line driving circuits 110_1~110_M can each be coupled to the photoelectric elements 120_1~120_N through the gate lines G_1~G_M. In this embodiment, the gate line driving circuits 110_1 to 110_M are respectively coupled to multiple photoelectric elements in different rows of the photoelectric elements 120_1 to 120_N through the gate lines G_1 to G_M. The gate line driving circuits 110_1~110_M can drive the photoelectric elements 120_1~120_N through the gate lines G_1~G_M to perform the light detection function. In this embodiment, the semiconductors of the first transistors 111_1 to 111_M and the second transistors 112_1 to 112_M may each include silicon (Si) or metal oxide, for example, they may be amorphous silicon (a-Si) semiconductors. , polycrystalline silicon (Polycrystalline silicon, p-Si) semiconductor or indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) semiconductor, but is not limited to this. The semiconductor materials of the first transistors 111_1 to 111_M and the second transistors 112_1 to 112_M may be the same or different. In addition, the first transistors 111_1 to 111_M and the second transistors 112_1 to 112_M can be disposed on the substrate 105 using gate driving circuit substrate (Gate On Array, GOA) technology, but are not limited thereto.

It is worth noting that because the second transistors 112_1 ~ 112_M in different rows can receive the first clock signal C1 or the second clock signal C2, the number of times and/or the time they are driven will be higher than that of the first transistors in the same row. 111_1~111_M. Therefore, the second transistors 112_1~112_M of this embodiment are disposed in the X-ray irradiation area 103, so that the second transistors 112_1~112_M can increase the threshold voltage of the second transistors 112_1~112_M through X-ray irradiation. For example, a negative bias phenomenon is generated, which can improve the deviation of the threshold voltage of the second transistor 112_1~112_M.

FIG. 2 is a circuit diagram of a first gate line driving circuit according to an embodiment of the present disclosure. Referring to FIG. 1 and FIG. 2 , the gate line driving circuit 110_1 of FIG. 1 may include a circuit architecture as shown in FIG. 2 , but is not limited thereto. The gate line driving circuit 110_1 includes transistors T11~T15. In this embodiment, the first terminal of the transistor T11 is coupled to the start signal STV and the control terminal of the transistor T11 . The second terminal of the transistor T11 is coupled to the node P1. The first terminal of the transistor T12 (which can be used as the first transistor 111_1 in FIG. 1 ) is coupled to the first clock signal C1. The control terminal of transistor T12 is coupled to node P1. The second terminal of the transistor T12 is coupled to the gate line G_1 and the first terminal of the transistor T13. The control terminal of the transistor T13 is coupled to the gate line G_2 to receive the output result of the gate line driving circuit of the next row. The second terminal of the transistor T13 is coupled to the first voltage VSS (for example, the ground voltage). The first terminal of the transistor T14 (which can be used as the second transistor 112_1 in FIG. 1 ) is coupled to the node P1. The control terminal of the transistor T14 is coupled to the second clock signal C2. The second terminal of the transistor T14 is coupled to the first voltage VSS. The first terminal of the transistor T15 (which can be used as the second transistor 112_1 in FIG. 1 ) is coupled to the second terminal of the transistor T12 and the gate line G_1. The control terminal of the transistor T15 is coupled to the second clock signal C2. The second terminal of the transistor T15 is coupled to the first voltage VSS. In one embodiment, the gate line driving circuit 110_1 may include only one of the transistor T14 and the transistor T15, and is not limited to that shown in FIG. 2 .

FIG. 3 is a circuit diagram of a second gate line driving circuit according to an embodiment of the present disclosure. Referring to FIG. 1 and FIG. 3 , the gate line driving circuit 110_2 of FIG. 1 may include a specific circuit architecture as shown in FIG. 3 . The gate line driving circuit 110_2 includes transistors T21 to T25. In this embodiment, the first terminal of the transistor T21 is coupled to the gate line G_1 and the control terminal of the transistor T21 to receive the output result of the gate line driving circuit of the previous row. The second terminal of the transistor T21 is coupled to the node P2. The first terminal of the transistor T22 (which can be used as the first transistor 111_2 in FIG. 1 ) is coupled to the second clock signal C2. The control terminal of transistor T22 is coupled to node P2. The second terminal of the transistor T22 is coupled to the gate line G_2 and the first terminal of the transistor T23. The control end of the transistor T23 is coupled to the gate line G_3 to receive the output result of the next row of driving circuits. The second terminal of the transistor T23 is coupled to the first voltage VSS. The first terminal of the transistor T24 (which can be used as the second transistor 112_2 in FIG. 1 ) is coupled to the node P2. The control terminal of the transistor T24 is coupled to the first clock signal C1. The second terminal of the transistor T24 is coupled to the first voltage VSS. The first terminal of the transistor T25 (which can be used as the second transistor 112_2 in FIG. 1 ) is coupled to the second terminal of the transistor T22 and the gate line G_2. The control terminal of the transistor T25 is coupled to the first clock signal C1. The second terminal of the transistor T25 is coupled to the first voltage VSS. In one embodiment, the gate line driving circuit 110_2 may include only one of the transistor T24 and the transistor T25, and is not limited to that shown in FIG. 3 .

It is worth noting that the circuit architecture of the odd-numbered rows of the gate line driving circuits 110_3~110_M in Figure 1 can be derived by analogy from the circuit architecture shown in Figure 2, and the circuit architecture of the even-numbered rows of the gate line driving circuits 110_3~110_M can be derived from Figure 3 The circuit architecture shown is analogous and will not be described in detail here. The gate line driving circuit 110_1 (first row) can receive the start signal STV and the output result of the next row driving circuit. Each row of the gate line driving circuits 110_2~110_(M-1) can respectively receive the output result of the corresponding previous row driving circuit and the corresponding output result of the next row driving circuit. The gate line driving circuit 110_M (last row) can receive the output result of the corresponding driving circuit of the previous row.

FIG. 4 is a signal timing diagram according to an embodiment of the present disclosure. Referring to Figures 2 to 4, time t0 to time tp is the light detection period of a frame of the detection device, where p is a positive integer. In this embodiment, the gate line driving circuit 110_1 can receive the start signal STV, the first clock signal C1 and the second clock signal C2 as shown in FIG. 4 . The gate line driving circuit 110_2 can receive the driving signal GS1, the first clock signal C1 and the second clock signal C2 as shown in FIG. 4 . The first clock signal C1 and the second clock signal C2 are clock signals with different phases. Therefore, there is a phase difference between the first clock signal C1 and the second clock signal C2, so that the pulse waveforms of each other are staggered. The gate line driving circuit 110_1 can output the driving signal GS1 shown in Figure 4 to the corresponding photoelectric element through the gate line G_1, and the gate line driving circuit 110_2 can output the driving signal shown in Figure 4 through the gate line G_2 GS2 to the corresponding another photoelectric element to respectively drive the corresponding photoelectric element and the other photoelectric element to perform photosensitive operation.

Specifically, between time t0 and time t1 , the first end of the transistor T11 of the gate line driving circuit 110_1 may receive the starting signal STV having a voltage waveform with a high voltage level to start the gate line driving circuit. 110_1. The start signal STV has a continuous low voltage level voltage waveform between time t1 and time tp, but is not limited to this. Between time t1 and time t2, the first clock signal C1 has a pulse waveform with a high voltage level. At this time, since the node P1 is charged by the start signal STV with a voltage waveform of a high voltage level between time t0 and time t1, the control end of the transistor T12 of the gate line driving circuit 110_1 can receive the high voltage of the node P1 A voltage signal of a certain level causes the semiconductor of the transistor T12 to be turned on, and the transistor T12 turns on. Furthermore, the first terminal of the transistor T12 receives the first clock signal C1 having a pulse waveform with a high voltage level, so the second terminal of the transistor T12 can synchronously output the driving signal GS1 with a pulse waveform having a high voltage level to Gate line G_1.

Between time t2 and time t3, the second clock signal C2 has a pulse waveform with a high voltage level. At this time, the control terminals of the transistor T14 and the transistor T15 of the gate line driving circuit 110_1 receive the second clock signal C2 with a pulse waveform of a high voltage level to change the voltage level of the node P1 and the gate line G_1 drop down. As a result, the semiconductor of the transistor T12 of the gate line driving circuit 110_1 will be in a non-conducting state, and the transistor T12 will be turned off to avoid erroneous output of the driving signal. For the gate line driving circuit 110_2, since the circuit node P2 is charged by the driving signal GS1 with a pulse waveform of a high voltage level between time t1 and time t2, the control of the transistor T22 of the gate line driving circuit 110_2 The terminal can receive a high voltage level voltage signal of node P2 and be turned on. Furthermore, the first terminal of the transistor T22 receives the second clock signal C2 having a pulse waveform with a high voltage level, so the second terminal of the transistor T22 can synchronously output the driving signal GS2 with a pulse waveform having a high voltage level to Gate line G_2.

Between time t3 and time t4, the first clock signal C1 has a pulse waveform of a high voltage level, and the second clock signal C2 has a pulse waveform of a low voltage level. At this time, the control terminals of the transistor T24 and the transistor T25 of the gate line driving circuit 110_2 receive the first clock signal C1 with a pulse waveform of a high voltage level to change the voltage level of the node P2 and the gate line G_2 drop down. As a result, the transistor T22 of the gate line driving circuit 110_2 will be turned off to avoid erroneously outputting the driving signal. Moreover, for the gate line driving circuit 110_1, since the voltage level of the circuit node P1 is pulled down between time t2 and time t3, the gate line driving circuit 110_1 is maintained in a non-conducting state. It is worth noting that the gate line driving circuits 110_3~110_M in Figure 1 sequentially output driving signals between time t4 and time tp, and the specific operation timing can be determined by the above-mentioned gate line driving circuit 110_1 and the gate line driving circuit. The description of 110_2 is analogous.

In this embodiment, since the gate line driving circuit 110_1 can be used as the control end of the transistor T14 and the transistor T15 of the second transistor 112_1 of FIG. 1 and the gate line driving circuit 110_2 can be used as the control end of the transistor T15 of FIG. 1 The control terminals of the transistor T24 and the transistor T25 of the second transistor 112_2 are respectively coupled to the first clock signal C1 and the second clock signal C2. In other words, when the first clock signal C1 is The transistor T24 and the transistor T25 are driven when the second clock signal C2 is a high voltage level. Relatively speaking, the transistor T12 (can be used as the first transistor 111_1 of FIG. 1 ) is driven only when the node P1 is at a high voltage level, and the transistor T22 (which can be used as the first transistor 111_2 in FIG. 1 ) is only driven when the node P2 is at a high voltage level. Therefore, the transistor T14 and the transistor T15 are driven for a higher number of times and/or for a longer time than the transistor T12 , and the transistor T24 and the transistor T25 are driven for a higher number of times and/or for a longer time than the transistor T22 . Therefore, the gate of this embodiment is The transistors T14 and T15 of the electrode line driving circuit 110_1 and the transistors T24 and T25 of the gate line driving circuit 110_2 can be disposed in the X-ray irradiation area 103 as shown in FIG. 1, so that the transistors T14, The transistor T15, the transistor T24, and the transistor T25 adjust their threshold voltage shifts through X-ray irradiation. In this way, the deviation of the threshold voltage of the transistor T14, the transistor T15, the transistor T24, and the transistor T25 can be improved, and the gate line driving circuit 110_1 and the gate line driving circuit 110_2 can also provide better Gate drive function.

FIG. 5 is a schematic diagram of a detection device according to another embodiment of the present disclosure. Referring to FIG. 5 , the detection device 500 includes gate lines G_1 to G_M, gate line driving circuits 510_1 to 510_M, 530_1 to 530_M, photoelectric elements 520_1 to 520_N, and a substrate 505 . The substrate 505 includes a detection area 501, a scintillator layer (Scintilator) 502, an X-ray irradiation area 503 and a peripheral area 504. The peripheral area 504 surrounds the detection area 501 . The scintillator layer 502 is disposed on the photoelectric elements 520_1~520_N and covers the detection area 501. The range of the X-ray irradiation area 503 covers the range of the detection area 501 and the scintillator layer 502 . The area of the X-ray irradiation area 503 is larger than the area of the detection area 501 and the area of the scintillator layer 502 . The area of the scintillator layer 502 is larger than the area of the detection area 501 . In other words, the scintillator layer 502 and the X-ray irradiation area 503 will cover part of the peripheral area 504. The peripheral area 504 is the area from the edge of the substrate 505 to the edge of the detection area 501 . To further illustrate, the scintillator layer 502 can be used to receive X-rays and generate corresponding visible light according to the X-rays, so that the corresponding photoelectric element can realize the X-ray detection function by detecting the corresponding visible light.

In this embodiment, the gate lines G_1 to G_M are disposed on the substrate 505 and extend from the detection area 501 to the peripheral area 504 . The gate line driving circuits 510_1~510_M, 530_1~530_M are disposed in the peripheral area 504 of the substrate 505 and are respectively located on opposite sides of the detection area 501, and include first transistors 511_1~511_M, 531_1~531_M and second transistors. Crystals 512_1~512_M, 532_1~532_M. For example, the gate line driving circuits 510_1~510_M are arranged in the peripheral area 504 on the left side of the detection area 501, and the gate line driving circuits 530_1~530_M are arranged in the peripheral area 504 on the right side of the detection area 501. But this disclosure is not limited to this.

In this embodiment, the gate line driving circuit 510_1 and the gate line driving circuit 530_1 are both coupled to the gate line G_1. The gate line driving circuit 510_1 is also coupled to the gate line driving circuit 510_2, and the gate line driving circuit 530_1 is also coupled to the gate line driving circuit 530_2. The gate line driving circuit 510_2 and the gate line driving circuit 530_2 are both coupled to the gate line G_2. The gate line driving circuit 510_2 is also coupled to the gate line driving circuit 510_3, and the gate line driving circuit 530_2 is also coupled to the gate line driving circuit 530_3. By analogy, the gate line driving circuit 510_(M-1) and the gate line driving circuit 530_(M-1) are both coupled to the gate line G_(M-1). The gate line driving circuit 510_(M-1) is also coupled to the gate line driving circuit 510_M, and the gate line driving circuit 530_(M-1) is also coupled to the gate line driving circuit 530_M. The gate line driving circuit 510_M and the gate line driving circuit 530_M are both coupled to the gate line G_M.

In this embodiment, the first transistors 511_1 ~ 511_M and 531_1 ~ 531_M in the gate line driving circuits 510_1 ~ 510_M and 530_1 ~ 530_M are respectively coupled to the corresponding gate lines, such as the third transistor of the gate line driving circuit 510_1 A transistor 511_1 and a first transistor 531_1 of the gate line driving circuit 530_1 are coupled to the gate line G_1. The first transistor 511_2 of the gate line driving circuit 510_2 and the first transistor 531_2 of the gate line driving circuit 530_2 are coupled to the gate line G_2. By analogy, the first transistor 511_M of the gate line driving circuit 510_M and the first transistor 531_M of the gate line driving circuit 530_M are coupled to the gate line G_1. The first transistors 511_1 ~ 511_M of the gate line driving circuits 510_1 ~ 510_M are respectively coupled to the corresponding second transistors 512_1 ~ 512_M. The first transistors 531_1 ~ 531_M of the gate line driving circuits 530_1 ~ 530_M are respectively coupled to the corresponding second transistors 532_1 ~ 532_M.

In this embodiment, the first transistor 511_1 of the gate line driving circuit 510_1 is coupled to the first clock signal C1, and the second transistor 512_1 is coupled to the second clock signal C2. The first transistor 511_2 of the gate line driving circuit 510_2 is coupled to the second clock signal C2, and the second transistor 512_2 is coupled to the first clock signal C1. The first transistor 511_3 of the gate line driving circuit 510_3 is coupled to the first clock signal C1, and the second transistor 512_3 is coupled to the second clock signal C2. By analogy, the first transistors (odd numbers among the first transistors 511_1 ~ 511_M) of the gate line driving circuits 510_1~510_M in the odd-numbered rows can be coupled to the first clock signal C1, and the gate lines in the even-numbered rows The first transistors (an even number of the first transistors 511_1 - 511_M) of the driving circuits 510_1 ~ 510_M may be coupled to the second clock signal C2. The second transistors (odd numbers of the second transistors 512_1 ~ 512_M) of the odd-numbered rows of gate line driving circuits 510_1 ~ 510_M can be coupled to the second clock signal C2, and the even-numbered rows of the gate line driving circuits 510_1 ~ 510_M second transistors (an even number of second transistors 512_1 to 512_M) may be coupled to the first clock signal C1.

In this embodiment, the first transistor 531_1 of the gate line driving circuit 530_1 is coupled to the first clock signal C3, and the second transistor 532_1 is coupled to the second clock signal C4. The first transistor 531_2 of the gate line driving circuit 530_2 is coupled to the second clock signal C4, and the second transistor 532_2 is coupled to the first clock signal C3. The first transistor 531_3 of the gate line driving circuit 530_3 is coupled to the first clock signal C3, and the second transistor 532_3 is coupled to the second clock signal C4. By analogy, the first transistors (odd numbers of the first transistors 531_1 ~ 531_M) of the odd-numbered rows of gate line driving circuits 530_1~530_M can be coupled to the first clock signal C3, and the even-numbered rows of gate line drivers The first transistors of the circuits 530_1 to 530_M (an even number of the first transistors 531_1 to 531_M) may be coupled to the second clock signal C4. The second transistors (odd numbers of the second transistors 532_1 ~ 532_M) of the odd-numbered rows of gate line driving circuits 530_1 ~ 530_M can be coupled to the second clock signal C4, and the even-numbered rows of the gate line driving circuits 530_1 ~ 530_M second transistors (an even number of second transistors 532_1 ~ 532_M) may be coupled to the first clock signal C3.

In other words, the first transistors of the gate line driving circuits of the odd rows may be coupled to the first clock signal C1 and the first clock signal C3 respectively, and the second transistors may be coupled to the second clock signal C2 and the first clock signal C3 respectively. Two clock signals C4. The first transistors of the even-numbered rows of gate line driving circuits may be coupled to the second clock signal C2 and the second clock signal C4 respectively, and the second transistors may be coupled to the first clock signal C1 and the first clock signal respectively. Pulse signal C3. Regardless of the gate line driving circuit of odd-numbered rows or even-numbered rows, the second transistor is coupled to the first transistor. Photoelectric elements 520_1~520_N are arranged in the detection area 501. The gate line G_1 is coupled to a plurality of photoelectric components. The gate line G_2 is coupled to a plurality of photoelectric components. By analogy, the gate line G_M is coupled to multiple photoelectric elements.

In this embodiment, the first clock signal C1 may be equal to the first clock signal C3, and the second clock signal C2 may be equal to the second clock signal C4. However, in another embodiment, the gate line driving circuits 510_1 ~ 510_M and the gate line driving circuits 530_1 ~ 530_M may also be coupled to different gate lines. For example, the gate line driving circuit 510_1 is coupled to the gate line G_1, and the gate line driving circuit 530_1 is coupled to the gate line G_2. The gate line driving circuit 510_2 is coupled to the gate line G_3, and the gate line driving circuit 530_2 is coupled to the gate line G_4. By analogy, the gate line driving circuits 510_1~510_M can be coupled to the odd gate lines among the gate lines G_1~G_M, and the gate line driving circuits 530_1~530_M can be coupled to the even numbers among the gate lines G_1~G_M. Gate lines. Moreover, in an embodiment, the first clock signal C1 may not be equal to the first clock signal C3, and the second clock signal C2 may not be equal to the second clock signal C4. Alternatively, in another embodiment, the first clock signal C1 may be equal to the first clock signal C3, and the second clock signal C2 may be equal to the second clock signal C4, and the present disclosure is not limited thereto.

In this embodiment, viewed from the top view direction of the detection device 500 (ie, direction Z), the distance d4 between the second transistors 512_1 ~ 512_M, 532_1 ~ 532_M and the scintillator layer 502 is smaller than the first transistor 511_1 ~ The distance d3 between 511_M, 531_1~531_M and the scintillator layer 502. The distance d3 and the distance d4, taking the gate line driving circuit 510_1 as an example, refer to the direction in which the respective semiconductors of the first transistor 511_1 and the second transistor 512_1 extend along the gate line G_1 (ie, the direction X ) to measure the shortest distance from the scintillator layer 502. In this embodiment, the first transistors 511_1~511_M and 531_1~531_M are respectively disposed in the peripheral area 504 outside the X-ray irradiation area 503, and the second transistors 512_1~512_M and 532_1~532_M are respectively disposed in the scintillator layer 502 outside the X-ray irradiation area 503.

In this embodiment, the photoelectric elements 520_1 to 520_N may be arrayed in the detection area 501, but are not limited thereto. The photoelectric elements 520_1 ~ 520_N may respectively include photodiodes, but are not limited thereto. The gate line driving circuits 510_1~510_M and 530_1~530_M can each be coupled to the photoelectric elements 520_1~520_N through the gate lines G_1~G_M. In this embodiment, the gate line driving circuits 510_1 to 510_M and 530_1 to 530_M are respectively coupled to multiple photoelectric elements in different rows of the photoelectric elements 520_1 to 520_N through the gate lines G_1 to G_M. The gate line driving circuits 510_1~510_M and 530_1~530_M can drive the photoelectric elements 520_1~520_N through the gate lines G_1~G_M to perform the light detection function. In this embodiment, the semiconductors of the first transistors 111_1 to 111_M and the second transistors 512_1 to 512_M and 532_1 to 532_M may each include silicon (Si) or metal oxide, for example, they may be amorphous silicon semiconductors or polycrystalline silicon semiconductors. Or an indium gallium zinc oxide semiconductor, but is not limited to this. The semiconductor materials of the first transistors 111_1 to 111_M and the second transistors 112_1 to 112_M may be the same or different. In addition, the first transistors 111_1 to 111_M and the second transistors 512_1 to 512_M and 532_1 to 532_M can be disposed on the substrate 505 using gate drive circuit substrate technology, but are not limited thereto.

It is worth noting that because the second transistors 512_1~512_M and 532_1~532_M in different rows can receive the first clock signal C1, the first clock signal C3, the second clock signal C2 and the second clock signal C4. The number of times and/or time it is driven will be higher than that of the first transistors 511_1~511_M and 531_1~531_M. Therefore, the second transistors 512_1~512_M and 532_1~532_M of this embodiment are arranged in the X-ray irradiation area 503. , so that the second transistors 512_1 ~ 512_M, 532_1 ~ 532_M are irradiated with X-rays to cause the threshold voltages of the second transistors 512_1 ~ 512_M, 532_1 ~ 532_M to produce, for example, a negative bias phenomenon, thereby effectively improving or overcoming the second transistor. The deviation of the threshold voltage of crystals 512_1~512_M and 532_1~532_M.

In summary, the transistor that performs high-speed switching in the detection device of the present disclosure can be disposed in an area of the substrate that can be irradiated by X-rays to effectively compensate for the threshold voltage of the transistor caused by long-term high-speed switching. The phenomenon of offset allows the electrical signal transmitted in the detection device to remain normal. In this way, the reliability and durability of the detection device of the present disclosure can be effectively improved, and a stable and effective light detection function can be provided.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present disclosure, but not to limit it. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present disclosure. Scope.

100, 500: Detection device 110_1~110_M, 510_1~510_M, 530_1~530_M: Gate line drive circuit 111_1~111_M, 511_1~511_M, 531_1~531_M: first transistor 112_1~112_M, 512_1~512_M, 532_1~532_M: second transistor 120_1~120_N, 520_1~520_N: Optoelectronic components 101, 501: Detection area 103, 503: X-ray irradiation area 104, 504: Surrounding area 105, 505: Substrate 502:Scintillator layer C1, C3: first clock signal C2, C4: second clock signal d1, d2, d3, d4: distance G_1~G_M: Gate line T11~T15, T21~T25: transistor VSS: first voltage GS1, GS2: drive signal STV: start signal t0~Tp: time X, Y, Z: direction

FIG. 1 is a schematic diagram of a detection device according to an embodiment of the present disclosure. FIG. 2 is a circuit diagram of a first gate line driving circuit according to an embodiment of the present disclosure. FIG. 3 is a circuit diagram of a second gate line driving circuit according to an embodiment of the present disclosure. FIG. 4 is a signal timing diagram according to an embodiment of the present disclosure. FIG. 5 is a schematic diagram of a detection device according to another embodiment of the present disclosure.

100:Detection device 101:Detection area 103:X-ray irradiation area 104: Surrounding area 105:Substrate 110_1~110_M: Gate line drive circuit 111_1~111_M: first transistor 112_1~112_M: Second transistor 120_1~120_N: Optoelectronic components C1: first clock signal C2: Second clock signal d1, d2: distance G_1~G_M: Gate line X, Y, Z: direction

Claims (10)

A detection device including: A substrate including a detection area and a peripheral area surrounding the detection area; A gate line is provided on the substrate and extends from the detection area to the peripheral area; A gate line driving circuit is disposed in the peripheral area of the substrate and includes a first transistor and a second transistor, wherein the first transistor is coupled to a first clock signal and the a gate line, and the second transistor is coupled to a second clock signal and the first transistor; and A photoelectric element is disposed in the detection area and coupled to the gate line, Wherein, viewed from a top view direction of the detection device, the distance between the second transistor and the detection area is smaller than the distance between the first transistor and the detection area. The detection device as described in claim 1 also includes: An X-ray irradiation area, wherein the area of the X-ray irradiation area is larger than the detection area, and the second transistor is disposed in the X-ray irradiation area outside the detection area. The detection device according to claim 2, wherein the first transistor is disposed in the peripheral area outside the X-ray irradiation area. The detection device as described in claim 1 also includes: A scintillator layer is provided on the photoelectric element, and when viewed from the top view direction of the detection device, the scintillator layer covers the detection area, The area of the scintillator layer is larger than the area of the detection area. The detection device of claim 4, wherein the distance between the second transistor and the scintillator layer is smaller than the distance between the first transistor and the scintillator layer. The detection device according to claim 4, wherein the second transistor is disposed in the peripheral area outside the scintillator layer. The detection device of claim 1, wherein the first clock signal and the second clock signal are clock signals with different phases. The detection device of claim 1, wherein a first terminal of the first transistor is coupled to the first clock signal, and a second terminal of the first transistor is coupled to the gate. polar line, wherein a first terminal of the second transistor is coupled to the second terminal of the first transistor, a second terminal of the second transistor is coupled to a first voltage, and the second A control terminal of the transistor is coupled to the second clock signal. The detection device of claim 8, wherein the gate line driving circuit further includes another second transistor, and a first end of the other second transistor is coupled to a first end of the first transistor. A control terminal, a second terminal of the second transistor is coupled to the first voltage, and a control terminal of the second transistor is coupled to the second clock signal. The detection device of claim 1, wherein a first terminal of the first transistor is coupled to the first clock signal, and a second terminal of the first transistor is coupled to the gate. polar line, wherein a first terminal of the second transistor is coupled to a control terminal of the first transistor, a second terminal of the second transistor is coupled to a first voltage, and the second transistor A control terminal is coupled to the second clock signal.

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