TWI825828B - Method for manufacturing window ball grid array (wbga) package - Google Patents

Abstract

The present disclosure provides a method of manufacturing a WBGA package. The method includes providing a carrier having a first surface and a second surface opposite to the first surface of the carrier, wherein the carrier has a through hole extending between the first surface and the second surface of the carrier; disposing an electronic component on the second surface of the carrier, wherein the electronic component includes a first bonding pad and a second bonding pad; and electrically connecting the first bonding pad and the second bonding pad through a first bonding wire.

Description

Preparation method of window ball grid array (WBGA) package

This application claims priority to U.S. Patent Application Nos. 17/739,427 and 17/739,415 (that is, the priority date is "May 9, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a method of manufacturing a window ball grid array (WBGA) package, and in particular, to a method of manufacturing a WBGA package with bonding wires.

In a window ball grid array (WBGA) package, a carrier board can define a window in the center area of the electronic component and have wire bonding pads on the surface opposite the electronic component. The bonding pads of the electronic component may be electrically connected to the bonding pads by conductive elements including, for example, bonding wires. The wirebond pads may each be electrically coupled to corresponding input/output (I/O) terminal pads (eg, ball pads) through circuitry on the carrier board. The I/O terminal pads may each include or be electrically coupled to a ground reference node (GND) or a power supply node (VDD).

As WBGA packages become smaller and smaller and have more and more pads, the spacing or spacing between adjacent pads gradually becomes smaller. As a result, it becomes increasingly difficult to connect the electronic component's bonding pads to the corresponding I/O terminal pads on the carrier board. Due to this interconnect limitation, the final performance of the WBGA package may be degraded.

The above description of "prior art" is only to provide background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" None should form any part of this case.

One aspect of the present disclosure provides a window ball grid array (WBGA) package. The WBGA package includes a carrier board having a first surface and a second surface opposite to the first surface of the carrier board. The carrier board has a through hole filled with a first package and extending between the first surface and the second surface of the carrier board. The WBGA package also includes an electronic component disposed on the second surface of the carrier board. The electronic component includes a first bonding pad and a second bonding pad. The WBGA package also includes a first bonding wire electrically connected between the first bonding pad and the second bonding pad.

Another aspect of the present disclosure provides a WBGA package. The WBGA package includes a carrier board having a first surface and a second surface opposite to the first surface of the carrier board. The carrier board has a through hole filled with a first package and extending between the first surface and the second surface of the carrier board. The WBGA package also includes an electronic component disposed on the second surface of the carrier board. The electronic component includes a first bonding pad and a second bonding pad electrically connected to a node.

Another aspect of the present disclosure provides a method of manufacturing a WBGA package. The preparation method includes providing a carrier plate having a first surface and a second surface opposite to the first surface of the carrier plate. The carrier board has a through hole extending between the first surface and the second surface of the carrier board. The preparation method also includes arranging an electronic component on the second surface of the carrier board. The electronic component includes a first bonding pad and a second bonding pad. The preparation method also includes electrically connecting the first bonding pad and the second bonding pad through a first bonding wire.

According to some embodiments of the present disclosure, bonding pads on the electronic component are used to electrically connect adjacent bonding pads to wire bonding pads on the carrier board. In other words, the bonding pad can be regarded as a relay point or springboard connecting adjacent bonding pads and wire bonding pads. Bonding pads allow electrical connections to be made via bonding wires.

Through the electrical connection of bonding wires and bonding pads, the circuit of the carrier board can be more flexible, the interconnection per unit area can be increased, and the spacing or interval between adjacent bonding pads can be further reduced, thus making the package size smaller.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

Specific language will now be used to describe the embodiments, or examples, of the present disclosure illustrated in the drawings. It should be understood that there is no intention to limit the scope of the present disclosure. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are deemed to be commonly made by one of ordinary skill in the art to which this disclosure relates. Reference numbers may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment apply to another embodiment, even if they share the same reference number.

It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers or sections, these elements, elements, regions, layers or sections are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for describing particular embodiments only and is not intended to limit the concepts of the invention. As used herein, the singular forms "a", "an" and "the" also include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and "includes", when used in this specification, indicate the presence of stated features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other Characteristic, integer, step, operation, element, component, or group thereof.

FIG. 1A is a cross-sectional view illustrating a window ball grid array (WBGA) package 1 according to some embodiments of the present disclosure. The WBGA package 1 may include a WBGA type chip package. As shown in FIG. 1 , in some embodiments, the WBGA package 1 may include a carrier board 10 , electronic components 11 , electrical contacts 12 and package bodies 13 and 14 .

The carrier 10 may include a substrate. In some embodiments, carrier 10 may include semiconductor materials such as silicon, germanium, gallium, arsenic, and combinations thereof. In some embodiments, the carrier 10 may include plastic materials, ceramic materials, or similar materials.

In some embodiments, the carrier board 10 may include a core layer 10c and dielectric layers 10d1 and 10d2 disposed on opposite sides of the core layer 10c. The carrier board 10 may also include interconnects, circuits or layout circuits, such as one or more vias 10v and one or more conductive lines (or conductive traces) 10m.

The conductive lines 10m may be disposed on the core layer 10c. The vias 10v may include vias penetrating or passing through the core layer 10c to electrically connect the conductive lines 10m. A portion of the conductive line 10m may be exposed from the dielectric layers 10d1 and 10d2, while another portion of the conductive line 10m may be covered by the dielectric layers 10d1 and 10d2.

In some embodiments, the core layer 10c may include sheet insulation material (Prepreg, PP), Ajinomoto build-up film (ABF), or other suitable materials. In some embodiments, the via 10v and the conductive line 10m may each include a conductive material, such as metal or other suitable materials. For example, the through holes 10v and the conductive lines 10m may each include copper (Cu), silver (Ag), aluminum (Al), gold (Au), or alloys thereof. In some embodiments, dielectric layers 10d1 and 10d2 may each include a dielectric material, such as solder resist or other suitable materials.

The carrier 10 may have a surface 101 and a surface 102 opposite the surface 101 . In some embodiments, the carrier board 10 may include or define a through hole 10h penetrating or traversing the carrier board 10 . Via 10h may extend between surface 101 and surface 102. The through hole 10 h may include a window, opening or slot disposed in the center of the carrier board 10 . In some embodiments, the through hole 10 h may be adjacent or close to the edge of the carrier board 10 . In some embodiments, the through hole 10h may be provided at the edge of the carrier board 10 .

The exposed portions of the conductive lines 10m may include conductive pads for providing electrical connections between the carrier board 10 and the electronic components 11, and between the carrier board 10 and external electronic components (not shown).

For example, wire bonding pads 11p1_f and 11p1'_f may be defined on the surface 101 of the carrier board 10 . The wire bonding pads 11p1_f and 11p1'_f may be adjacent to the through hole 10h respectively.

Viewed from the cross-section, the wire bonding pads 11p1_f and 11p1'_f can be separated by the through hole 10h. For example, the wire bonding pad 11p1_f may be disposed on the left side of the through hole 10h, and the wire bonding pad 11p1'_f may be disposed on the right side of the through hole 10h.

The bonding pad 11p1'_f can be electrically connected to the bonding pad 11p1' of the electronic component 11 through the bonding wire 11p1'_w. The wire bonding pads 11p1'_f may also be electrically connected to input/output (I/O) terminal pads (eg, ball pads) on the surface 101 of the carrier board 10 through interconnections of the carrier board 10 .

For example, I/O terminal pads (such as ball pads) may be defined on surface 101 of carrier board 10 . The I/O terminal pads may be at the periphery of the carrier board 10 . The I/O terminal pads may be farther away from the through holes 10h than the wire bonding pads of the carrier board 10 . For example, the wire bonding pad 11p1_f may be disposed between the I/O terminal pad (in which the electrical contact 12 is disposed) and the through hole 10h.

In some embodiments, wire bonding pad 11p1_f and wire bonding pad 11p1'_f may be electrically disconnected from each other. For example, the wire bonding pad 11p1_f and the wire bonding pad 11p1'_f may not be electrically connected. For example, wire bonding pad 11p1'_f can be electrically connected to one of the I/O terminal pads, and wire bonding pad 11p1_f can be electrically disconnected from one of the I/O terminal pads. For example, bonding pad 11p1'_f may be electrically connected to a ground reference node (GND), while bonding pad 11p1_f may be electrically disconnected from GND. For example, the bonding pad 11p1'_f may be electrically connected to the power supply node (VDD), and the bonding pad 11p1_f may be electrically disconnected from VDD. For example, wire bonding pad 11p1'_f may be electrically connected to the voltage node, while wire bonding pad 11p1_f may be electrically disconnected from the voltage node.

Electrical contacts 12 may be provided on the I/O terminal pads. For example, electrical contacts 12 may be electrically connected to an underlying printed circuit board (PCB) (not shown) to provide electrical connections to carrier board 10, such as I/O connections. For example, electrical contact 12 may include or be electrically connected to a GND node, a VDD node, or a voltage node. In some embodiments, electrical contacts 12 may include controlled collapse die attach (C4) bumps, ball grid arrays (BGA), or ground grid arrays (LGA).

The electronic components 11 can be disposed on the surface 102 of the carrier board 10 . The electronic component 11 may cover one end of the through hole 10h. The central portion of the electronic component 11 may face or be exposed from the through hole 10h.

In some embodiments, electronic component 11 may have a surface 111 facing carrier board 10 , a surface 112 remote from carrier board 10 , and a surface 113 (or lateral surface) extending between surface 111 and surface 112 . Surface 111 may include an active surface and surface 112 may include a back surface. The bonding pads 11p1 and 11p1' may be disposed on the surface 111 of the electronic component 11.

The electronic component 11 may be attached to the surface 102 of the carrier board 10 through the adhesive layer 11g. Adhesion layer 11g may be adjacent to via 10h. The adhesive layer 11g may surround the through hole 10h. In some embodiments, the surface of the adhesive layer 11g may be substantially coplanar with the inner sidewalls of the through holes 10h. In some embodiments, the surface of the adhesive layer 11 g may be substantially coplanar with the surface 113 of the electronic component 11 . In some embodiments, surface 102 of carrier 10 may be partially exposed from adhesive layer 11g. The adhesive layer 11g may include adhesive materials, such as epoxy resin, die attach film (DAF), adhesive or similar materials.

In some embodiments, the electronic component 11 may include a semiconductor chip or die, such as a memory chip (eg, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, etc.); a A signal processing chip (e.g., digital signal processing (DSP) chip); a logic chip (e.g., application processor (AP), system on chip (SoC), central processing unit (CPU), graphics processing unit (GPU), micro controller, etc.); a power management chip (such as a power management integrated circuit (PMIC) chip); a radio frequency (RF) chip; a sensor chip; a microelectromechanical system (MEMS) chip; a front-end chip (such as an analog front-end (AFE) chip) or other active components.

In some embodiments, the bonding pads 11p1 and 11p1 ′ may be symmetrically arranged on the surface 111 of the electronic component 11 . For example, the bonding pads 11p1 and 11p1' may be symmetrical with respect to a dotted line passing through the center point of the electronic component 11. For example, the bonding pad 11p1 may be disposed on the left side of the dotted line, and the bonding pad 11p1' may be disposed on the right side of the dotted line.

In some embodiments, bonding pads 11p1 and 11p1' may be configured to be electrically connected to the same node. For example, bonding pads 11p1 and 11p1' may be configured to be electrically connected to the same GND or the same VDD.

In some embodiments, the bonding pad 11p1 may be closer to the wire bonding pad 11p1_f than the bonding pad 11p1'. In some embodiments, the bonding pad 11p1 may be close to the wire bonding pad 11p1_f and away from the wire bonding pad 11p1'_f. For example, the distance "d1" between the wire bonding pad 11p1_f and the surface of the bonding pad 11p1 may be smaller than the distance "d2" between the wire bonding pad 11p1'_f and the surface of the bonding pad 11p1.

In some embodiments, the bonding pad 11p1' may be closer to the bonding pad 11p1'_f than the bonding pad 11p1. In some embodiments, the bonding pad 11p1' may be close to the wire bonding pad 11p1'_f and away from the wire bonding pad 11p1_f. For example, the distance between the wire bonding pad 11p1 ′_f and the surface of the bonding pad 11p1 ′ may be smaller than the distance between the wire bonding pad 11p1_f and the surface of the bonding pad 11p1 ′.

In some embodiments, the top surfaces of the bonding pads 11p1 and 11p1 ′ may be recessed from the surface 102 of the carrier board 10 . For example, the bonding pads 11p1 and 11p1' may not exist in the through hole 10h. However, in some other embodiments, the top surfaces of the bonding pads 11p1 and 11p1' may be substantially coplanar with the surface 102 of the carrier board 10 . In some other embodiments, the top surfaces of the bonding pads 11p1 and 11p1' may exist in the through hole 10h.

In some embodiments, bonding pads 11p1 and 11p1' may be electrically connected to each other through bonding wires 11p1_w. The bonding pad 11p1' can be electrically connected to the wire bonding pad 11p1'_f through the bonding wire 11p1'_w. Therefore, the bonding pad 11p1 can be electrically connected to the wire bonding pad 11p1'_f by using the bonding pad 11p1' as a relay point or springboard. In other words, the bonding pad 11p1' is electrically connected between the bonding pad 11p1 and the wire bonding pad 11p1'_f. In other words, the bonding pad 11p1' exists in the electrical path between the bonding pad 11p1 and the wire bonding pad 11p1'_f.

In some embodiments, bonding pad 11p1_f is closer to bonding pad 11p1 than bonding pad 11p1'_f. For example, bonding pad 11p1_f is closer to bonding pad 11p1 than any other bonding pad on carrier board 10 . The bonding pad 11p1 is not electrically connected to the nearby bonding pad (ie, the bonding pad 11p1_f), but is electrically connected to the bonding pad 11p1'_f through the bonding pad 11p1'.

In some embodiments, bond wire 11p1_w may partially exist in via 10h. In some embodiments, bond wire 11p1'_w may extend through via 10h. In some embodiments, bonding wires 11p1_w and 11p1'_w may have different lengths. In some embodiments, the bonding line 11p1_w and the bonding line 11p1'_w may have different curvatures when viewed in cross section. In some embodiments, the bonding wires 11p1_w and 11p1'_w may extend in different directions from the bonding pad 11p1', such as in opposite directions.

The package body 13 may be disposed in the through hole 10h. The package body 13 can fill the through hole 10h. The package 13 can be disposed on the surface 101 of the carrier 10 and cover or contact a part thereof.

The package 13 can be disposed on the surface 111 of the electronic component 11 to cover or contact a part thereof. The package body 13 can be disposed on the adhesive layer 11g, covering or contacting at least a part thereof. The package body 13 can be disposed on the bonding pads 11p1 and 11p1', covering, contacting or surrounding at least a part thereof. The package 13 can be disposed on the bonding wires 11p1_w and 11p1'_w, covering, contacting or surrounding at least a part thereof. In some embodiments, bonding wires 11p1_w and 11p1'_w may be packaged by package 13 .

In some embodiments, the encapsulation body 13 may include molding materials, such as Novolac-based resin, epoxy-based resin, silicon-based resin, or other suitable encapsulants. Suitable fillers such as powdered SiO2 may also be included.

The package 14 can be disposed on the surface 102 of the carrier 10 to encapsulate or cover the electronic component 11 . The package 14 can be disposed on the surface 112 of the electronic component 11 to cover or contact the surface of the electronic component 11 . The package 14 can be disposed on the lateral surface 113 of the electronic component 11 to cover or contact the lateral surface. The package body 14 may be disposed on the adhesive layer 11g, covering or contacting at least a part thereof.

In some embodiments, the encapsulation body 14 may include molding materials, such as Novolac-based resin, epoxy-based resin, silicon-based resin, or other suitable encapsulants. Suitable fillers such as powdered SiO2 may also be included. In some embodiments, packages 13 and 14 may include the same material. In some embodiments, package 13 and package 14 may include different materials.

1B is an enlarged view illustrating partial enlarged views (a), (b) and (c) of a WBGA package according to some embodiments of the present disclosure. In some embodiments, the enlarged views (a), (b) and (c) may respectively illustrate a portion of the dashed box 1B of the WBGA package 1 in FIG. 1A.

Referring to the enlarged view (a) in FIG. 1B , the bonding posts 11p1'_s may be disposed on the bonding pads 11p1'. In some embodiments, the bonding wire 11p1_w and the bonding wire 11p1'_w can be connected to the bonding post 11p1'_s at different positions or different parts. For example, one end of the bonding wire 11p1_w on the bonding post 11p1'_s may be spaced apart from one end of the bonding wire 11p1'_w on the bonding post 11p1'_s. For example, the bonding wires 11p1_w and 11p1'_w can extend from different positions or different parts on the bonding posts 11p1'_s.

Referring to the enlarged view (b) in FIG. 1B , in some embodiments, the bonding wire 11p1_w and the bonding wire 11p1'_w may be connected to the bonding post 11p1'_s at the same position or part. For example, one end of the bonding wire 11p1_w on the bonding post 11p1'_s may be connected to one end of the bonding wire 11p1'_w on the bonding post 11p1'_s. For example, the bonding wire 11p1_w and the bonding wire 11p1'_w may extend from the same position or the same part on the bonding post 11p1'_s.

Referring to the enlarged view (c) in FIG. 1B , the bonding posts 11p1'_s1 and 11p1'_s2 may be disposed on the bonding pad 11p1'. Bonding post 11p1'_s1 may be adjacent to bonding post 11p1'_s2. Bonding post 11p1'_s1 may be spaced apart from bonding post 11p1'_s2. In some embodiments, the projected area of the bonding post 11p1'_s1 on the bonding pad 11p1' may be spaced apart from the projected area of the bonding post 11p1'_s1 on the bonding pad 11p1'. For example, the projection area of the bonding post 11p1'_s1 on the bonding pad 11p1' and the projection area of the bonding post 11p1'_s1 on the bonding pad 11p1' may not overlap.

In some embodiments, the surface area of bonding pad 11p1 ′ (or other bonding pads acting as relay points or springboards) may be larger than other bonding pads on electronic component 11 . For example, the surface area of the bonding pad 11p1' may be larger than the surface area of the bonding pad 11p1 shown in FIG. 1A.

In some embodiments, the area of bonding pad 11p1' (or other bonding pads that serve as relay points or springboards) may have sufficient surface area to accommodate and engage two bonding wires simultaneously.

In some embodiments, bonding wire 11p1_w can be connected to bonding post 11p1'_s1, and bonding wire 11p1'_w can be connected to bonding post 11p1'_s2. For example, the bonding wire 11p1_w may extend from the bonding post 11p1'_s1, and the bonding wire 11p1'_w may extend from the bonding post 11p1'_s2.

FIG. 2A is a top view illustrating a WBGA package according to some embodiments of the present disclosure. In some embodiments, the WBGA package 1 in FIG. 1A may be a cross-sectional view along line AA' of the WBGA package shown in FIG. 2A.

As shown, the surface 111 of the electronic component 11 may be at least partially exposed from the through hole 10h. In some embodiments, the carrier plate 10 may completely surround the through hole 10h. In some embodiments, the through hole 10h may have a quadrangular, rectangular, square, polygonal, oval, or circular shape, or any other suitable shape.

A plurality of bonding pads 11p0, 11p1, 11p2, 11p3 and 11p4 may be disposed on the surface 111 of the electronic component 11 and exposed from the through hole 10h.

The bonding pads 11p0, 11p1, 11p2, 11p3 and 11p4 can be arranged in a row or in a straight line. The bonding pads 11p0, 11p1, 11p2, 11p3 and 11p4 may be arranged along the reference Y-axis. The bonding pads 11p0, 11p1, 11p2, 11p3 and 11p4 may be arranged along the edge of the carrier board 10.

Similarly, a plurality of bonding pads CA, 11p1', 11p2', NC, 11p3' and 11p4' can be disposed on the surface 111 of the electronic component 11 and exposed from the through hole 10h.

The bonding pads CA, 11p1', 11p2', NC, 11p3' and 11p4' can be arranged in a row or in a straight line. Bonding pads CA, 11p1', 11p2', NC, 11p3' and 11p4' can be arranged along the reference Y-axis. The bonding pads CA, 11p1', 11p2', NC, 11p3' and 11p4' can be arranged along the edge of the carrier board 10.

Some of the bonding pads in the above two rows can be aligned along the reference X-axis. For example, the bonding pads 11p1 and 11p1' may be arranged along the reference X-axis. Bonding pads 11p2 and 11p2' may be aligned along the reference X-axis. Bonding pads 11p3 and 11p3' may be aligned along the reference X-axis. Bonding pads 11p4 and 11p4’ can be aligned along the reference X-axis.

In some embodiments, two aligned bond pads may be configured to electrically connect to the same node. For example, bond pads 11p1 and 11p1' may each be configured to be electrically connected to the same GND, the same VDD, or the same voltage node. For example, bond pads 11p2 and 11p2' may both be configured to be electrically connected to the same GND, the same VDD, or the same voltage node.

In some embodiments, the ground terminals of electronic component 11 may be symmetrically arranged on surface 111 . In some embodiments, the power terminals of electronic component 11 may be symmetrically arranged on surface 111 .

In some embodiments, bond pads 11p1, 11p1', 11p3, 11p3', 11p4, 11p4' may be ground terminals of electronic component 11 and may be configured to be electrically connected to ground. In some embodiments, bonding pads 11p2 and 11p2' may be power terminals for electronic component 11 and may be configured to electrically connect with a power source.

The arrangement of the ground terminal and the power terminal of the electronic component 11 may be different from the above arrangement and is not limited thereto. The arrangement of the ground terminals and power terminals of the electronic component 11 can be adjusted according to design requirements, such as layout specifications of the electronic component 11 .

In some embodiments, the bonding pad NC may include a dummy pad or an electrical floating pad. For example, there may not be an electrical connection on bond pad NC to establish a specific voltage. In some embodiments, bonding pad CA may include a bonding pad to connect to a common address node.

A plurality of wire bonding pads 11p0_f, 11p1_f, 11p2_f, 11p3_f and 11p4_f may be disposed on the surface 101 of the carrier board 10 .

Wire bonding pads 11p0_f, 11p1_f, 11p2_f, 11p3_f and 11p4_f can be arranged in a row or in a straight line. Wire bonding pads 11p0_f, 11p1_f, 11p2_f, 11p3_f and 11p4_f can be arranged along the reference Y axis. The wire bonding pads 11p0_f, 11p1_f, 11p2_f, 11p3_f and 11p4_f may be arranged along the edge of the carrier board 10.

Wire bonding pads 11p0_f, 11p1_f, 11p2_f, 11p3_f, and 11p4_f may be aligned with bonding pads 11p0, 11p1, 11p2, 11p3, and 11p4 along the reference X axis. For example, wire bonding pad 11p0_f may be aligned with bonding pad 11p0. For example, wire bonding pad 11p1_f may be aligned with bonding pad 11p1.

In some embodiments, the aligned pair of wire bonding pads and bonding pads may be the closest pair. For example, bonding pad 11p0_f may be closer to bonding pad 11p0 than any other bonding pad on surface 101 of carrier board 10 . For example, bonding pad 11p1_f may be closer to bonding pad 11p1 than any other bonding pad on surface 101 of carrier board 10 .

Similarly, a plurality of bonding pads 11p1'_f, 11p2'_f, 11p3'_f and 11p4'_f can be disposed on the surface 101 of the carrier board 10.

Wire bonding pads 11p1'_f, 11p2'_f, 11p3'_f and 11p4'_f can be arranged in a row or in a straight line. Wire bonding pads 11p1'_f, 11p2'_f, 11p3'_f and 11p4'_f can be arranged along the reference Y axis. The wire bonding pads 11p1'_f, 11p2'_f, 11p3'_f and 11p4'_f may be arranged along the edge of the carrier board 10.

Wire bonding pads 11p1'_f, 11p2'_f, 11p3'_f and 11p4'_f may be aligned with bonding pads 11p1', 11p2', 11p3' and 11p4' along the reference X-axis. For example, wire bonding pad 11p1'_f may be aligned with bonding pad 11p1'. For example, wire bonding pad 11p2'_f may be aligned with bonding pad 11p2'.

In some embodiments, the arranged pair of wire bonding pads and bonding pads may be the closest pair. For example, wire bond pad 11 p1 ′_f may be closer to bonding pad 11 p1 ′ than any other wire bond pad on surface 101 of carrier board 10 . For example, bonding pad 11p2'_f may be closer to bonding pad 11p2' than any other bonding pad on surface 101 of carrier board 10.

One or more wire bonding pads 11p0_f, 11p1_f, 11p2_f, 11p3_f, 11p4_f, 11p1'_f, 11p2'_f, 11p3'_f and 11p4'_f can be connected to I/O terminal pads (such as ball pads) via conductive lines 10m Electrical connections.

For example, the wire bonding pads 11p0_f and 11p2_f may be electrically connected to the I/O terminal pad 121_b. The electrical contact 121 may be disposed on the I/O terminal pad 121_b.

For example, wire bonding pads 11p1'_f, 11p3'_f, and 11p4'_f may be electrically connected to I/O terminal pad 122_b. The electrical contact 122 may be disposed on the I/O terminal pad 122_b.

For example, wire bonding pads 11p3_f and 11p4_f may be electrically connected to I/O terminal pad 123_b. The electrical contact 123 may be disposed on the I/O terminal pad 123_b.

In some embodiments, electrical contact 121 , electrical contact 122 , and electrical contact 123 may each include or be electrically connected to GND, VDD, or a voltage node. As an example, electrical contact 121 may include or be electrically connected to VDD. Both the electrical contact 122 and the electrical contact 123 may include or be electrically connected to GND.

One or more bonding pads 11p0, 11p1, 11p2, 11p3, 11p4, CA, 11p1', 11p2', 11p3' and 11p4' can be electrically connected to corresponding wire bonding pads, and the wire bonding pads can pass through the carrier board 10 The conductive wire 10m is electrically connected to GND, VDD or voltage node.

In some embodiments, in order to reduce the bonding length of the bonding wires, bonding pads 11p0, 11p1, 11p2, 11p3, 11p4, CA, 11p1', 11p2', 11p3', and 11p4' may be electrically connected to closer bonding pads . For example, the bonding pads 11p0 and 11p2 can be power terminals, and can be electrically connected to VDD through the wire bonding pads 11p0_f and 11p2_f (which can be through the conductive lines 10m, the I/O terminal pads 121_b and the electrical contacts 121 of the carrier board 10) ).

For example, the bonding pads 11p1' and 11p3' can be ground terminals, and can be passed through the wire bonding pads 11p1'_f and 11p3'_f (which can be through the conductive traces 10m of the carrier board 10, the I/O terminal pads 122_b and the electrical contacts 122) electrically connected to GND).

As WBGA packages become smaller in size and have more and more pads, the spacing or spacing between adjacent pads gradually becomes smaller. As a result, it becomes increasingly difficult to connect the electronic component's bonding pads to the corresponding I/O terminal pads on the carrier board.

For example, bond pad 11p1 may be a ground terminal, and bond pad 11p1_f (the closest bond pad to bond pad 11p1 ) may be at least partially connected by electrical contact 121 (which may be electrically connected to VDD) and bond pad 11p0_f and surrounded by 10m of conductive wires between the electrical contact 121 and the wire bonding pad 11p2_f.

Bonding pad 11p1 may not be connected to GND through wire bonding pad 11p1_f because wire bonding pad 11p1_f has limited layout space or routing space, so wire bonding pad 11p1_f cannot be connected to GND.

Therefore, the bonding pad 11p1 is not electrically connected to the nearby bonding pad (ie, the bonding pad 11p1_f), but is electrically connected to the bonding pad 11p1'_f through the bonding pad 11p1' and the bonding wire 11p1_w.

Similarly, bond pad 11p2' may be a power terminal, and bond pad 11p2'_f (the closest bond pad to bond pad 11p2') may be at least partially covered by electrical contact 122 (which may be electrically connected to GND) Surrounded by 10m of conductive wires between the wire bonding pad 11p1'_f and between the electrical contact 122 and the wire bonding pad 11p3'_f.

Since the layout space or wiring space of the wire bonding pad 11p2'_f is limited, the bonding pad 11p2' may not be connected to VDD through the wire bonding pad 11p2'_f, and therefore the wire bonding pad 11p2'_f cannot be connected to VDD.

Therefore, the bonding pad 11p2' is not electrically connected to the nearby bonding pad (ie, the bonding pad 11p2'_f), but is electrically connected to the bonding pad 11p2_f through the bonding pad 11p2 and the bonding wire 11p2'_w.

According to some embodiments of the present disclosure, a bonding pad (eg, bonding pad 11p1') on an electronic component (eg, electronic component 11) is used to connect an adjacent bonding pad (eg, bonding pad 11p1) to a carrier board (eg, The wire bonding pads (such as wire bonding pads 11p1'_f) on the carrier board 10) are electrically connected. In other words, the bonding pad 11p1' can be regarded as a relay point or springboard connecting the adjacent bonding pad 11p1 and the wire bonding pad 11p1'_f. The bonding pads 11p1 and 11p1' may be electrically connected through bonding wires (eg, bonding wires 11p1_w).

Through the electrical connection of the bonding wires 11p1 and 11p1', the circuit routing of the carrier board 10 can be more flexible, the interconnection per unit area can be increased, the spacing or intervals between adjacent bonding pads can be further reduced, and the package size can be further miniaturized.

FIG. 2B is a top view illustrating a WBGA package according to some embodiments of the present disclosure. The WBGA package in Figure 2B is similar to the WBGA package in Figure 2A, except that the bonding pad 11p3 is electrically connected to the wire bonding pad 11p3'_f through the bonding wire 11p3_w and the bonding pad 11p3'.

For example, bonding pad 11p3 may be a ground terminal and may be designed to connect to electrical contact 123 (via wirebond pad 11p3_f) or electrical contact 122 (via wirebond pad 11p3'_f).

In addition, the bonding pad 11p4 is electrically connected to the wire bonding pad 11p4'_f through the bonding wire 11p4_w and the bonding pad 11p4'.

For example, bonding pad 11p4 may be a ground terminal and may be designed to connect to electrical contact 123 (via wirebond pad 11p4_f) or electrical contact 122 (via wirebond pad 11p4'_f).

FIG. 2C is a top view illustrating a WBGA package according to some embodiments of the present disclosure. The WBGA package in Figure 2C is similar to the WBGA package in Figure 2A, except that the bonding pad 11p1 is electrically connected to the wire bonding pad 11p3'_f through the bonding wire 11p1_w, the bonding pad 11p3' and the bonding wire 11p3'_w.

In some embodiments, bonding wires 11p1_w and 11p2'_w may cross or span each other. In such embodiments, bonding wires 11p1_w and 11p2'_w may include insulated bonding wires. For example, an insulating coating may be provided on the bonding wires 11p1_w and 11p2'_w to allow the wires to touch or contact each other.

FIG. 2D is a top view illustrating a WBGA package according to some embodiments of the present disclosure. The WBGA package in Figure 2D is similar to the WBGA package in Figure 2A, except that bonding pad 11p1 is electrically connected to wire bonding pad 11p3'_f through bonding wire 11p2'_w, bonding pad 11p3', and bonding wire 11p3'_w.

In addition, the bonding pad 11p2' is electrically connected to the wire bonding pad 11p0_f through the bonding wire 11p2'_w, the bonding pad 11p0, and the bonding wire 11p0_w.

In some embodiments, bonding pads connected by bonding wires (eg, bonding pads 11p2' and 11p0) may be misaligned. For example, the bonding lines between the bonding pads may extend in an oblique direction relative to the reference Y-axis and/or the reference X-axis. For example, the bonding lines between the bonding pads may be at an angle relative to the reference Y-axis and/or the reference X-axis.

FIG. 3 is a cross-sectional view illustrating a WBGA package 3 according to some embodiments of the present disclosure. The WBGA package 3 in FIG. 3 is similar to the WBGA package 1 in FIG. 1A , except that the WBGA package 3 further includes a conductive layer 30 disposed on the outer surface of the package body 14 .

In some embodiments, conductive layer 30 may be conformal to the outer surface of package 14 . In some embodiments, conductive layer 30 may be in contact with carrier 10 . In some embodiments, conductive layer 30 may be connected to a ground line and thus be connected to ground. In some embodiments, conductive layer 30 may be connected to conductive lines (or conductive traces) 10m. In some embodiments, conductive layer 30 may be configured to connect with a ground node of carrier board 10 .

FIG. 4 is a cross-sectional view illustrating a WBGA package 4 according to some embodiments of the present disclosure. The WBGA package 4 in FIG. 4 is similar to the WBGA package 1 in FIG. 1A , except that the adhesive layer 11g′ of the WBGA package 4 and the surface 113 of the electronic component 11 are not coplanar.

In some embodiments, the adhesive layer 11g' may extend from the inner sidewall of the through hole 10h to the side surface of the carrier board 10. In some embodiments, the surface 102 of the carrier 10 may be completely covered by the adhesive layer 11g'.

FIG. 5 is a cross-sectional view illustrating a WBGA package 5 according to some embodiments of the present disclosure. The WBGA package 5 in Figure 5 is similar to the WBGA package 1 in Figure 1A , except that the bonding pads 11p1 and 11p1' of the WBGA package 5 are surrounded by the package body 14.

For example, a portion of the package 14 may be disposed between the surface 111 of the electronic component 11 and the package 13 .

6A, 6B, 6C, 6D, 6E and 6F are one or a plurality of preparation stages, illustrating the preparation method of the WBGA package according to some embodiments of the present disclosure. In order to better understand various aspects of the present disclosure, at least some of the figures have been simplified. In some embodiments, the WBGA package 1 in Figure 1A can be prepared by the following operations with respect to Figures 6A, 6B, 6C, 6D, 6E and 6F.

Referring to Figure 6A, a carrier board 10 is provided. The carrier 10 may have a surface 101 and a surface 102 opposite the surface 101 . In some embodiments, the carrier board 10 may include or define a through hole 10h penetrating or passing through the carrier board 10 . Via 10h may extend between surface 101 and surface 102. The carrier board 10 may include wire bonding pads 11p1_f and 11p1'_f.

Referring to FIG. 6B , the electronic component 11 is disposed on the surface 102 of the carrier 10 . The bonding pads 11p1 and 11p1' can be disposed on the electronic component 11.

Referring to FIG. 6C , the bonding pad 11p1' and the wire bonding pad 11p1'_f are connected by the bonding wire 11p1'_w.

Referring to FIG. 6D , the bonding pad 11p1 and the bonding pad 11p1' are connected through the bonding wire 11p1_w. In some embodiments, the operations of Figure 6D may be performed before the operations of Figure 6C. For example, the fabrication of the bonding wire 11p1_w may precede the fabrication of the bonding wire 11p1'_w.

Referring to FIG. 6E , the package 13 may be disposed in the through hole 10h to be disposed on the bonding wires 11p1_w and 11p1'_w, covering, contacting or surrounding at least a part thereof. In some embodiments, the manufacturing technology of the package 13 may include molding technology, such as transfer molding or compression molding.

Referring to FIG. 6F , a package body 14 may be disposed on the surface 102 of the carrier board 10 to encapsulate or cover the electronic component 11 . In some embodiments, the manufacturing technology of the package 14 may include molding technology, such as transfer molding or compression molding. In some embodiments, the operations in Figure 6F may be performed before the operations in Figure 6E. For example, the package 14 may be produced before the package 13 is produced.

One or a plurality of electrical contacts 12 may be disposed on the I/O terminal pads (such as ball pads) of the carrier board 10 . Electrical contacts 12 may be electrically connected to an underlying PCB (not shown) to provide electrical connections to carrier board 10, such as I/O connections. For example, electrical contact 12 may include or be electrically connected to a GND node, a VDD node, or a voltage node. In some embodiments, the fabrication operation of the electrical contacts 12 may be performed before the fabrication operation of the package body 13 . In some embodiments, the fabrication operation of the electrical contacts 12 may be performed before the fabrication operation of the package body 14 .

7A, 7B, and 7C are one or more preparation stages, illustrating the preparation method of the WBGA package according to some embodiments of the present disclosure. In order to better understand various aspects of the present disclosure, at least some of the figures have been simplified. In some embodiments, the WBGA package 5 in Figure 5 can be prepared by the following operations related to Figures 7A, 7B and 7C.

The operations in Figure 7A may be performed after the operations in Figure 6B. The electronic component 11 is disposed on the surface 102 of the carrier board 10 . Then, the package 14 can be disposed on the surface 102 of the carrier 10 to encapsulate or cover the electronic component 11 . The bonding pads 11p1 and 11p1' of the WBGA package 5 are surrounded by the package body 14.

In some embodiments, the package 14 can be disposed on the electronic component 11 , and then the electronic component 11 is disposed on the carrier 10 .

Referring to FIG. 7B , the bonding pad 11p1' and the wire bonding pad 11p1'_f are connected by the bonding wire 11p1'_w. The bonding pad 11p1 and the bonding pad 11p1' are connected by a bonding wire 11p1_w. The bonding wire 11p1_w may be produced before the bonding wire 11p1'_w is produced. Alternatively, the bonding wire 11p1'_w may be produced before the bonding wire 11p1_w.

Referring to FIG. 7C , the package body 13 may be disposed in the through hole 10h to be disposed on the bonding wires 11p1_w and 11p1'_w, covering, contacting or surrounding at least a part thereof. A portion of the package 14 may be disposed between the surface 111 of the electronic component 11 and the package 13 .

FIG. 8 is a flow chart illustrating a method 80 for manufacturing a WBGA package according to some embodiments of the present disclosure.

Step or operation S81 is to provide a carrier plate having a through hole extending between two opposite surfaces thereof.

For example, as shown in Figure 6A, a carrier board 10 is provided. The carrier 10 may have a surface 101 and a surface 102 opposite the surface 101 . In some embodiments, the carrier board 10 may include or define a through hole 10h penetrating or traversing the carrier board 10 . Via 10h may extend between surface 101 and surface 102. The carrier board 10 may include wire bonding pads 11p1_f and 11p1'_f.

Step or operation S82 is to dispose an electronic component on the carrier board, wherein the electronic component includes a plurality of bonding pads.

For example, as shown in FIG. 6B , the electronic component 11 is provided on the surface 102 of the carrier board 10 . The bonding pads 11p1 and 11p1' can be disposed on the electronic component 11.

Step or operation S83 is to electrically connect a bonding pad to a bonding pad on the carrier board through a bonding wire.

For example, as shown in FIG. 6C , the bonding pad 11p1' and the wire bonding pad 11p1'_f are connected by the bonding wire 11p1'_w.

Step or operation S84 is to electrically connect another bonding pad to the bonding pad through a bonding wire.

For example, as shown in FIG. 6D , the bonding pad 11p1 and the bonding pad 11p1' are connected by the bonding wire 11p1_w.

Step or operation S85 is to electrically connect the wire bonding pad to a node.

For example, as shown in FIG. 6F , one or more electrical contacts 12 may be disposed on I/O terminal pads (such as ball pads) of the carrier board 10 . Electrical contact 12 may include or be electrically connected to a GND node, a VDD node, or a voltage node.

Step or operation S86 is encapsulating the bond wire.

For example, as shown in FIG. 6E , the package 13 can be disposed in the through hole 10h to be disposed on the bonding wires 11p1_w and 11p1'_w, covering, contacting or surrounding at least a part thereof.

Step or operation S87 is to package the electronic component.

For example, as shown in FIG. 6F , a package body 14 can be provided on the surface 102 of the carrier board 10 to encapsulate or cover the electronic component 11 .

One aspect of the present disclosure provides a window ball grid array (WBGA) package. The WBGA package includes a carrier board having a first surface and a second surface opposite to the first surface of the carrier board. The carrier board has a through hole filled with a first package and extending between the first surface and the second surface of the carrier board. The WBGA package also includes an electronic component disposed on the second surface of the carrier board. The electronic component includes a first bonding pad and a second bonding pad. The WBGA package also includes a first bonding wire electrically connected between the first bonding pad and the second bonding pad.

Another aspect of the present disclosure provides a WBGA package. The WBGA package includes a carrier board having a first surface and a second surface opposite to the first surface of the carrier board. The carrier board has a through hole filled with a first package and extending between the first surface and the second surface of the carrier board. The WBGA package also includes an electronic component disposed on the second surface of the carrier board. The electronic component includes a first bonding pad and a second bonding pad electrically connected to a node.

Another aspect of the present disclosure provides a method of manufacturing a WBGA package. The preparation method includes providing a carrier plate having a first surface and a second surface opposite to the first surface of the carrier plate. The carrier board has a through hole extending between the first surface and the second surface of the carrier board. The preparation method also includes arranging an electronic component on the second surface of the carrier board. The electronic component includes a first bonding pad and a second bonding pad. The preparation method also includes electrically connecting the first bonding pad and the second bonding pad through a first bonding wire.

According to some embodiments of the present disclosure, bonding pads on the electronic component are used to electrically connect adjacent bonding pads to wire bonding pads on the carrier board. In other words, the bonding pad can be regarded as a relay point or springboard connecting adjacent bonding pads and wire bonding pads. Bonding pads allow electrical connections to be made via bonding wires.

By electrically connecting the bonding wires to the bonding pads, the circuit routing of the carrier board can be more flexible, the interconnections per unit area can be increased, and the spacing or intervals between adjacent bonding pads can be further reduced, thus miniaturizing the package size.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and may be substituted for many of the processes described above with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art will understand from the disclosure of this disclosure that existing or future developed processes, machines, manufacturing, etc. can be used in accordance with the disclosure to have the same function or achieve substantially the same results as the corresponding embodiments described herein. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patentable scope of this application.

1: Window ball grid array (WBGA) package 1B: Dashed box 3:WBGA package 4:WBGA package 5:WBGA package 10: Carrier board 10c: Core layer 10d1: Dielectric layer 10d2: Dielectric layer 10h:Through hole 10m: conductive wire 10v:Through hole 11: Electronic components 11g: Adhesive layer 11g': Adhesive layer 11p0: Bonding pad 11p0_f: Wire bonding pad 11p0'_f: Wire bonding pad 11p1: Bonding pad 11p1': Bonding pad 11p1_f: Wire bonding pad 11p1'_f: Wire bonding pad 11p1'_s: junction column 11p1'_s1: junction column 11p1'_s2: junction column 11p1_w: Bonding wire 11p1'_w: bonding wire 11p2: Bonding pad 11p2': Bonding pad 11p2_f: Wire bonding pad 11p2'_f: Wire bonding pad 11p3: Bonding pad 11p3': Bonding pad 11p3_f: Wire bonding pad 11p3'_f: Wire bonding pad 11p4: Bonding pad 11p4': Bonding pad 11p4_f: Wire bonding pad 11p4'_f: Wire bonding pad 12: Electrical contacts 13:Package 14:Package 30:Conductive layer 80:Preparation method 101:Surface 102:Surface 111:Surface 112:Surface 113:Surface 121: Electrical contacts 121_b:Terminal pad 122: Electrical contacts 122_b:Terminal pad 123: Electrical contacts 123_b:Terminal pad A-A': line CA: bonding pad d1: distance d2: distance NC: bonded pad S81: Steps S82: Steps S83: Steps S84: Steps S85: Steps S86: Steps S87: Steps

The disclosure content of this application can be more fully understood by referring to the embodiments and the patent scope combined with the drawings. The same element symbols in the drawings refer to the same elements. FIG. 1A is a cross-sectional view illustrating a window ball grid array (WBGA) package according to some embodiments of the present disclosure. FIG. 1B is an enlarged view illustrating a partial enlarged view of a WBGA package according to some embodiments of the present disclosure. FIG. 2A is a top view illustrating a WBGA package according to some embodiments of the present disclosure. FIG. 2B is a top view illustrating a WBGA package according to some embodiments of the present disclosure. FIG. 2C is a top view illustrating a WBGA package according to some embodiments of the present disclosure. FIG. 2D is a top view illustrating a WBGA package according to some embodiments of the present disclosure. FIG. 3 is a cross-sectional view illustrating a WBGA package according to some embodiments of the present disclosure. Figure 4 is a cross-sectional view illustrating a WBGA package according to some embodiments of the present disclosure. Figure 5 is a cross-sectional view illustrating a WBGA package according to some embodiments of the present disclosure. FIG. 6A illustrates one or more preparation stages, illustrating the preparation method of a WBGA package according to some embodiments of the present disclosure. FIG. 6B illustrates one or more preparation stages illustrating the preparation method of a WBGA package according to some embodiments of the present disclosure. FIG. 6C illustrates one or more preparation stages, illustrating the preparation method of the WBGA package according to some embodiments of the present disclosure. FIG. 6D is one or more preparation stages illustrating the preparation method of the WBGA package according to some embodiments of the present disclosure. FIG. 6E illustrates one or more preparation stages illustrating the preparation method of a WBGA package according to some embodiments of the present disclosure. FIG. 6F illustrates one or more preparation stages illustrating the preparation method of a WBGA package according to some embodiments of the present disclosure. FIG. 7A illustrates one or more preparation stages, illustrating a method of preparing a WBGA package according to some embodiments of the present disclosure. FIG. 7B illustrates one or more preparation stages illustrating the preparation method of a WBGA package according to some embodiments of the present disclosure. FIG. 7C illustrates one or more preparation stages illustrating the preparation method of a WBGA package according to some embodiments of the present disclosure. FIG. 8 is a flow chart illustrating a method of manufacturing a WBGA package according to some embodiments of the present disclosure.

1: Window ball grid array (WBGA) package 1B: Dashed box 10: Carrier board 10c: Core layer 10d1: Dielectric layer 10d2: Dielectric layer 10h:Through hole 10m: conductive wire 10v:Through hole 11: Electronic components 11g: Adhesive layer 11p1: Bonding pad 11p1': Bonding pad 11p1_f: Wire bonding pad 11p1'_f: Wire bonding pad 11p1_w: Bonding wire 11p1'_w: bonding wire 12: Electrical contacts 13:Package 14:Package 101:Surface 102:Surface 111:Surface 112:Surface 113:Surface d1: distance d2: distance

Claims (18)

A method for preparing a window ball grid array (WBGA) package, including: providing a carrier board having a first surface and a second surface opposite to the first surface of the carrier board, The carrier board has a through hole extending between the first surface and the second surface of the carrier board; an electronic component is disposed on the second surface of the carrier board, wherein the electronic component includes a first bonding pad and a second bonding pad; electrically connecting the first bonding pad and the second bonding pad through a first bonding wire; and connecting the second bonding pad and the carrier board through a second bonding wire. A first bonding pad on the first surface is electrically connected. The preparation method of claim 1 further includes: electrically connecting the first wire bonding pad to a power node or a ground node. The preparation method of claim 2 further includes: encapsulating the first bonding wire and the second bonding wire with a first package. The preparation method of claim 3 further includes: encapsulating the electronic component with a second package. The preparation method of claim 1, wherein the carrier board includes a first wire bonding pad on the first surface of the carrier board and a second wire bonding pad on the first surface of the carrier board, and the first The bonding pad is closer to the first wire bonding pad than the second wire bonding pad. The preparation method of claim 5, wherein the second wire bonding pad is electrically connected to a node, and the first wire bonding pad is disconnected from the node, and the node includes a power node or a ground node. The preparation method of claim 5, wherein the first wire bonding pad and the second wire bonding pad are separated by the through hole. The preparation method according to claim 5, further comprising: forming a third wire bonding pad adjacent to the first wire bonding pad; and forming a third wire bonding pad adjacent to the first wire bonding pad and with the third wire bonding pad. A fourth wire bonding pad is electrically connected; wherein the first wire bonding pad is at least partially surrounded by a conductive line connected between the third wire bonding pad and the fourth wire bonding pad. The preparation method of claim 5 further includes: forming a second bonding wire electrically connected between the second bonding pad and the second wire bonding pad. The preparation method of claim 9, wherein the second bonding wire extends through the through hole, and And the first bonding wire and the second bonding wire extend from the second bonding pad in opposite directions. The preparation method of claim 9, wherein the first bonding wire and the second bonding wire are packaged by the first package. The preparation method of claim 11, wherein the first bonding pad and the second bonding pad are partially surrounded by the first package. The preparation method of claim 11, wherein the first bonding pad and the second bonding pad are partially surrounded by the second package. A method for preparing a window ball grid array (WBGA) package, including: providing a carrier board having a first surface and a second surface opposite to the first surface of the carrier board, wherein the carrier board has A through hole is filled with a first package and extends between the first surface and the second surface of the carrier board; and an electronic component is provided on the second surface of the carrier board; wherein the electronic component includes and a first bonding pad and a second bonding pad electrically connected to a node; wherein the first bonding pad and the second bonding pad are electrically connected to a bonding pad on the first surface of the carrier board, And the wire bonding pad is electrically connected to the node through a conductive line of the carrier board. The preparation method according to claim 14, wherein the first bonding pad and the second bonding pad The pads are symmetrically arranged on an active surface of the electronic component, and the node includes a power node or a ground node. The preparation method of claim 14, wherein the second bonding pad is electrically connected to a first bonding wire and a second bonding wire. The preparation method of claim 16, wherein the first bonding line is located between the first surface and the second surface of the carrier board. The preparation method of claim 16, wherein the second bonding wire extends through the through hole, and the first bonding wire and the second bonding wire extend from the second bonding pad in opposite directions.