TWI825547B - Semiconductor device with re-fill layer and method for fabricating the same - Google Patents

Abstract

The present application discloses a semiconductor device with a re-fill layer and method for preparing the same. The semiconductor device includes a chip stack including a first base die; a first stacked die positioned on a front surface of the first base die; and a re-fill layer positioned on a sidewall of the stacked die. The re-fill layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, titanium oxide, aluminum oxide, or hafnium oxide.

Description

Semiconductor component with refill layer and preparation method thereof

This application claims the priority and benefits of U.S. Patent Application Nos. 17/497,754 and 17/500,026 (priority dates are "October 8, 2021" and "October 13, 2021"), which The contents of the US application are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device. In particular, it relates to a semiconductor device having a refill layer.

Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually becoming smaller to meet the increasing demand for computing power. However, during the downsizing process, different problems are added, and such problems continue to increase in number and complexity. Therefore, challenges remain in achieving improvements in quality, yield, performance and reliability, and in reducing complexity.

The above description of "prior art" only provides background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" does not constitute the prior art of the present disclosure. should not be used as any part of this case.

An embodiment of the present disclosure provides a semiconductor device including a wafer stack The stack includes a first base die; a first stacked die disposed on a front surface of the first base die; and a refill layer disposed on a side wall of the stacked die. The refill layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, titanium oxide, aluminum oxide or hafnium oxide.

In some embodiments, the refill layer has a thickness between about 50 Å and about 1000 Å.

In some embodiments, a width of the first base die is greater than a width of the stacked die.

In some embodiments, the semiconductor device further includes a first molding layer disposed on the refill layer and opposite the stacked die.

In some embodiments, the wafer stack further includes a passivation layer disposed on a rear surface of the first base die, and the front surface of the first base die is in contact with the rear surface of the first base die. The surfaces are arranged opposite each other.

In some embodiments, the wafer stack further includes a first connector disposed below the lower passivation layer and opposite to the first base die.

In some embodiments, the semiconductor device further includes a packaging substrate, wherein the die stack is disposed on the packaging substrate.

In some embodiments, the semiconductor component further includes a second connection member disposed under the packaging substrate.

In some embodiments, a width of the package substrate is greater than a width of the chip stack.

In some embodiments, the semiconductor device further includes a second molding layer disposed on the packaging substrate and covering the chip stack.

In some embodiments, the refill layer is also disposed horizontally on the front surface of the first base die.

Another embodiment of the present disclosure provides a semiconductor device including a chip stack including a first base die; a first stacked die disposed on a front surface of the first base die; and a refill layer , completely covering the stacked die and being disposed on the front surface of the first base die. The refill layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, titanium oxide, aluminum oxide or hafnium oxide.

In some embodiments, the wafer stack further includes a first molding layer that completely covers the refill layer.

Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a base wafer including a cutting portion; and bonding a first stacked die and a second stacked die through a hybrid bonding process. The die is bonded to a front surface of the base wafer, wherein the first stacked die and the second stacked die are disposed opposite to each other, and the cutting portion is interposed therebetween; a refill layer is conformally formed to cover The first stacked die and the second stacked die; forming a first molding layer to cover the refill layer and configured into an intermediate semiconductor component, the intermediate semiconductor component including the base wafer, the first stacked die , the second stacked die, the refill layer and the first molding layer; and cutting the intermediate semiconductor element along the cutting portion to separate the first stacked die, the second stacked die, the refill layer The layer, the first molding layer and the base wafer are separated, wherein after cutting, the base wafer is separated into a first base die and a second base die. The first base die, the first stacked die, the refill layer and the first molding layer are configured together into a first wafer stack.

In some embodiments, the refill layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, titanium oxide, aluminum oxide, or hafnium oxide.

In some embodiments, a process pressure of the hybrid bonding process ranges from about 100 MPa to about 150 MPa.

In some embodiments, a process temperature of the hybrid bonding process ranges from about 25°C to about 400°C.

In some embodiments, the first stacked die and the base wafer are bonded in a face-to-face configuration.

In some embodiments, the method of manufacturing a semiconductor device further includes, before bonding the first stacked die and the second stacked die to the front surface of the base wafer via the hybrid bonding process, in the A surface treatment is performed on the front surface of the base wafer. The surface treatment includes a wet chemical cleaning or a vapor phase heat treatment.

In some embodiments, the method of manufacturing a semiconductor device further includes bonding the wafer stack to a packaging substrate.

Due to the design of the semiconductor device of the present disclosure, the refill layer can compensate for hardness differences and fill cracks and seams of the stacked dies. Therefore, during cutting, its adverse effects are reduced or avoided. On the other hand, the cutting process does not need to be excessively optimized, so that the cost and process complexity of manufacturing the semiconductor device can be reduced.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

10:Preparation method

1A: Semiconductor components

1B:Semiconductor components

1C: Semiconductor components

101:Basic wafer

101BS: Back surface

101FS: Front surface

103:The first basic grain

105: The second basic grain

107: Base

109:Device components

111: Dielectric layer

113: Conductive characteristics

115: Through-base through hole

201:Stacked wafers

201BS:Back surface

201FS:Front surface

203:Base

205:Device components

207: Dielectric layer

209: Conductive characteristics

211:Through-substrate through hole

213: Passivation layer

215:Joint pad

301:Refill layer

301TS: Upper surface

401: First molding layer

401TS: Upper surface

403: Lower passivation layer

405: Lower joint pad

407: First connector

409: Second molding layer

501:Packaging substrate

503: Second connector

601: Carrier layer

603: Grain frame

CS1: Wafer stacking

CS2: Wafer stacking

ISD: Intermediate Semiconductor Device

S11: Steps

S13: Steps

S15: Steps

S17: Steps

S19: Steps

S21: Steps

S23: Steps

SD1: Stacked die

SD1B: Back surface

SD1F: Front surface

SD1S: side wall

SD2: Stacked die

SD2B: back surface

SD2F: front surface

SD2S: side wall

SD3: stacked die

SD3S: side wall

SD4: stacked die

SD4S: side wall

SD5: stacked die

SD5B: rear surface

SD5S: side wall

SD6: stacked die

SD6B: rear surface

SD6S: side wall

SL1: Cutting Department

SL2: Cutting Department

T1:Thickness

W1: Width

W2: Width

W3: Width

W4: Width

Z: direction

By referring to the embodiments and the patent scope together with the drawings, the disclosure content of the present application can be more fully understood. The same element symbols in the drawings refer to the same elements.

FIG. 1 is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

2 to 14 are schematic cross-sectional views illustrating a process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

15 to 16 are schematic cross-sectional views illustrating semiconductor devices according to some embodiments of the present disclosure.

Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, or may include an additional component formed between the first and second components. An embodiment such that the first and second components are not in direct contact. In addition, embodiments of the present disclosure may repeat reference numbers and/or letters in many examples. These repetitions are for simplicity and clarity and do not in themselves represent a specific relationship between the various embodiments and/or configurations discussed unless otherwise specified herein.

In addition, for ease of explanation, spaces such as "beneath", "below", "lower", "above", "upper", etc. may be used in this article. Relative terms are used to describe the relationship of one element or feature shown in the figures to another (other) element or feature. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may have its or otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It will be understood that when one component is formed on, connected to, and/or coupled to another component, it may include forming direct contact between those components. examples, and may also include embodiments in which additional components are formed between the components so that the components are not in direct contact.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not governed by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present progressive concept.

Unless otherwise specified in the content, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, Then terms such as "same", "equal", "planar", or "coplanar" as used in this article are not necessary means an exactly identical orientation, arrangement, position, shape, size, quantity, or other measurement, but it means a nearly identical orientation, arrangement, position, shape, size, within acceptable differences , quantity, or other measurement, and the acceptable differences may occur due to manufacturing processes, for example. The term "substantially" may be used herein to convey this meaning. For example, substantially the same, substantially equal, or substantially flat. planar), be exactly the same, equal, or flat, or they may be the same, equal, or flat within an acceptable difference, for example, said acceptable Variations can occur due to manufacturing processes.

In this disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a A semiconductor circuit (semiconductor circuit) and an electronic device (electronic device) are both included in the category of semiconductor components.

It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the opposite direction of the Z-direction arrow. .

It should be understood that the terms "forming", "formed" and "form" can mean and include any creating, building, patterning, planting. A method of implanting or depositing an element, a dopant or a material. Examples of formation methods may include atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion (diffusing), depositing (depositing), growing (growing), implantation (implantation), photolithography (photolithography), dry etching and wet etching, but are not limited thereto.

It should be understood that in the description of the present disclosure, functions or steps mentioned herein may occur in a different order than in the figures. For example, two diagrams shown in succession may actually execute at approximately the same time, or sometimes in reverse order, depending on the functionality involved. or steps.

FIG. 1 is a schematic flowchart illustrating a method 10 for manufacturing a semiconductor device 1A according to another embodiment of the present disclosure. 2 to 14 are cross-sectional schematic diagrams illustrating a process for preparing a semiconductor device 1A according to an embodiment of the present disclosure.

Please refer to FIGS. 1 and 2 . In step S11 , a base wafer 101 may be provided, and the base wafer 101 has a cutting part SL1 .

Referring to FIG. 2 , the base wafer 101 may include a substrate 107 , a plurality of device components 109 , a plurality of dielectric layers 111 , a plurality of conductive features 113 and a plurality of through-substrate vias 115 .

Please refer to FIG. 2. In some embodiments, the substrate 107 can be a bulk semiconductor substrate, which is completely composed of at least one semiconductor material; the bulk semiconductor substrate does not include any dielectric or isolation layer. Or conductive features. For example, the bulk semiconductor substrate may include an elemental semiconductor, a compound semiconductor, or a combination thereof. The elemental semiconductor is such as silicon or germanium. The compound semiconductor is such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, Indium arsenide, indium antimonide or other III-V compound semiconductors or II-VI compound semiconductors.

In some embodiments, the substrate 107 may include a semiconductor-on-insulator structure consisting, from bottom to top, of a handle substrate, an isolation layer, and an uppermost semiconductor material layer. The handling substrate and the uppermost semiconductor material layer may include the same materials as the aforementioned bulk semiconductor substrate. The isolation layer may be a crystalline or amorphous dielectric material, such as an oxide and/or nitride. For example, the isolation layer can be a dielectric oxide, such as silicon oxide. As another example, the isolation layer may be a dielectric nitride, such as silicon nitride or boron nitride. As yet another example, the isolation layer may include a stack of a dielectric oxide and a dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The isolation layer may have a thickness between approximately Between 10nm and approximately 200nm.

It should be understood that the term "about" modifies a quantity of an ingredient, component, or reactant of the present disclosure, which represents a numerical variation that may occur, for example This is done through typical measurements and liquid handling procedures used to create concentrates or solutions. Furthermore, variation can occur due to inadvertent errors in the measurement procedures applied to the manufacturing compositions or implementation of these methods or similar methods, differences in manufacturing, and sources. (source), or purity of ingredients. In one aspect, the term "about" means within 10% of the reported value. On the other hand, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

Referring to FIG. 2 , a plurality of device components 109 may be formed on a substrate 107 . Portions of device elements 109 may be formed in substrate 107 . The plurality of device elements 109 may be transistors, such as complementary metal-oxide semiconductor transistors, metal-oxide-semiconductor field-effect transistors, fin field transistors, etc. Effective transistors, the like, or combinations thereof.

Referring to FIG. 2 , a plurality of dielectric layers 111 may be formed on the substrate 107 and cover the plurality of device components 109 . In some embodiments, for example, the plurality of dielectric layers 111 may include silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorosilicate glass, or low dielectric constant dielectric materials. , the like, or combinations thereof. Low dielectric constant dielectric materials may have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the dielectric constant of The dielectric material may have a dielectric constant less than 2.0. The manufacturing technology of the plurality of dielectric layers 111 may include multiple deposition processes, such as chemical vapor deposition, plasma enhanced chemical vapor deposition or similar methods. Multiple planarization processes may be performed after the deposition processes to remove excess material and provide a generally flat surface for subsequent processing steps.

Referring to FIG. 2 , the plurality of conductive features 113 may include a plurality of interconnect layers, a plurality of conductive vias, and a plurality of conductive pads. The interconnection layers may be spaced apart from each other and may be horizontally disposed in the plurality of dielectric layers 111 along the direction Z. In this embodiment, the uppermost interconnect layers can be regarded as conductive pads. The conductive vias may connect adjacent interconnect layers, adjacent device elements 109 and interconnect layers, and adjacent conductive pads and interconnect layers along direction Z. In some embodiments, the conductive vias can improve heat dissipation and provide structural support. In some embodiments, for example, the plurality of conductive features 113 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal Nitride (eg titanium nitride), transition metal aluminide, or combinations thereof. During formation of dielectric layers 111 , conductive features 113 may be formed.

Referring to FIG. 2 , a plurality of through-substrate vias 115 may be formed in the substrate 107 , extending to the dielectric layers 111 , and electrically connected to the corresponding conductive features 113 .

It should be understood that in the description of the present disclosure, the numbers of the device elements 109 , the dielectric layers 111 , the conductive features 113 and the through-substrate vias 115 are for illustrative purposes only. The number of the aforementioned features may be greater or less than that shown in FIG. 2 .

In some embodiments, the plurality of device elements 109 , the plurality of conductive features 113 , and the plurality of through-substrate vias 115 may be configured together into functional units of the base wafer 101 . In the description of this disclosure, a functional unit is generally represented as a functionally associated circuit that has been separated into a distinct unit according to functional purposes. In some embodiments, the Functional units are often highly complex circuits such as processor cores, memory controllers or accelerator units. In some other embodiments, the complexity and functionality of a functional unit may be more complex or less complex.

Referring to FIG. 2 , the base wafer 101 may include a front surface 101FS and a back surface 101BS disposed opposite to each other. It should be understood that in the description of this disclosure, the term "front" surface is a technical term that implies the main surface of the structure forming device elements and conductive features. Similarly, the "back" surface of a structure is the principal surface relative to that surface. In the present disclosure, the front surface 101FS of the base wafer 101 may be the upper surface of the uppermost dielectric layer 111 . The back surface 101BS of the base wafer 101 may be the lower surface of the substrate 107 .

It should be understood that in the description of this disclosure, a surface of an element (or feature) at the highest vertical plane along dimension Z is referred to as an upper surface of the element (or feature). The surface of a component (or feature) at the lowest vertical plane along dimension Z is called the lower surface of the component (or feature).

Referring to FIG. 2 , a middle area of the base wafer 101 along the direction Z may be represented as a cutting portion SL1 . The cutting part SL1 can divide the base wafer 101 into a left area and a right area. After the cutting process along the cutting portion SL1, the left area of the base wafer 101 can be represented as a first base die 103, and the right area of the base wafer 101 can be represented as a second base die 105. The cutting process will be More details later. In some embodiments, the cutting portion SL1 may have a width between about 110 μm and about 220 μm.

Please refer to FIG. 1 and FIG. 3 to FIG. 8. In step S13, a plurality of stacked dies SD1, SD2, SD3, SD4, SD5, and SD6 may be bonded to the base wafer 101.

Referring to Figure 3, a stacked wafer 201 may be provided. In some embodiments, the heap The stacked wafer 201 may have a structure similar to the base wafer 101, but is not limited thereto. In some embodiments, the stacked wafer 201 may include a substrate 203 , a plurality of device components 205 , a plurality of dielectric layers 207 , a plurality of conductive features 209 , and a plurality of through-substrate vias 211 .

Please refer to FIG. 3. In some embodiments, the substrate 203 can be a bulk semiconductor substrate, which is entirely composed of at least one semiconductor material; the bulk semiconductor substrate does not include any dielectric, isolation layer or conductive layer. Characteristics. The fabrication technology of the bulk semiconductor substrate may be the same as that used for the substrate 107, and its description will not be repeated herein. In some embodiments, the substrate 203 may include a semiconductor-on-insulator structure, which is the same as the structure of the substrate 107 and its description will not be repeated herein.

Referring to FIG. 3 , a plurality of device components 205 may be formed on the substrate 203 . Portions of device elements 205 may be formed in substrate 203 . The plurality of device elements 205 may be transistors, such as complementary metal-oxide semiconductor transistors, metal-oxide-semiconductor field-effect transistors, fin field transistors, etc. Effective transistors, the like, or combinations thereof.

Referring to FIG. 3 , a plurality of dielectric layers 207 may be formed on the substrate 203 and cover the plurality of device components 205 . In some embodiments, for example, the plurality of dielectric layers 207 may include silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorosilicate glass, or low dielectric constant dielectric materials. , the like, or combinations thereof. Low dielectric constant dielectric materials may have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the dielectric material having a dielectric constant may have a dielectric constant less than 2.0. The manufacturing technology of the plurality of dielectric layers 207 may include multiple deposition processes, such as chemical vapor deposition, plasma enhanced chemical vapor deposition or similar methods. Multiple planarization processes may be performed after these deposition processes to remove excess material and provide a generally flat surface for subsequent processing steps.

Referring to FIG. 3 , the plurality of conductive features 209 may include a plurality of interconnect layers, a plurality of conductive vias, and a plurality of conductive pads. The interconnection layers may be spaced apart from each other and may be horizontally disposed in the plurality of dielectric layers 207 along the direction Z. In this embodiment, the uppermost interconnect layers can be regarded as conductive pads. The conductive vias may connect adjacent interconnect layers, adjacent device elements 205 and interconnect layers, and adjacent conductive pads and interconnect layers along direction Z. In some embodiments, the conductive vias can improve heat dissipation and provide structural support. In some embodiments, for example, the plurality of conductive features 209 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (eg, tantalum carbide, titanium carbide, tantalum magnesium carbide), metal Nitride (eg titanium nitride), transition metal aluminide, or combinations thereof. During formation of dielectric layer 207, conductive features 209 may be formed.

Referring to FIG. 3 , a plurality of through-substrate vias 211 may be formed in the substrate 203 , extending to the dielectric layers 207 , and electrically connected to the corresponding conductive features 209 .

It should be understood that in the description of the present disclosure, the numbers of device elements 205 , dielectric layers 207 , conductive features 209 and through-substrate vias 211 are for illustrative purposes only. The number of the aforementioned features may be greater or less than the number shown in FIG. 3 .

Referring to FIG. 3 , the stacked wafer 201 may include a front surface 201FS and a back surface 201BS disposed opposite to each other. In the present disclosure, the front surface 201FS of the stacked wafer 201 may be the upper surface of the uppermost dielectric layer 207 . The back surface 201BS of the stacked wafer 201 may be the lower surface of the substrate 203 .

In some embodiments, device elements 205 , conductive features 209 , and through-substrate vias 211 may be configured together to form multiple functional units of stacked wafer 201 .

Referring to FIG. 3 , a middle area of the stacked wafer 201 along the direction Z may be represented as a cutting portion SL2 . The cutting part SL2 can divide the stacked wafer 201 into a left area and a right area. After the cutting process along the cutting portion SL2, the left area of the stacked wafer 201 can be represented as a first stacked die SD1 (as shown in FIG. 6 below), and the right area of the stacked wafer 201 can be represented as a second stacked die. For die SD2 (as shown in Figure 6 below), the cutting process will be described in detail later. In some embodiments, the cutting portion SL2 may have a width between about 110 μm and about 220 μm.

Referring to FIG. 4 , the stacked wafer 201 can be turned over and the front surface 201FS of the stacked wafer 201 can be temporarily bonded to a carrier layer 601 . At this stage, the back surface 201BS of the stacked wafer 201 may face upward.

Referring to FIG. 5 , a passivation layer 213 may be formed on the back surface 201BS of the stacked wafer 201 . In some embodiments, the passivation layer 213 may include a polymer material, such as polybenzoxazole, polyimide, benzocyclobutene, and Ajinomoto to form a film. (ajinomoto buildup film), solder resist film (solder resist film) or the like. Polymeric materials (such as polyimide) can have some attractive characteristics, such as the ability to fill multiple openings with high aspect ratios, a relatively low dielectric constant (approximately 3.2), a simple deposition process, Reduction of sharp features or steps in underlying layers and high temperature tolerance after curing. Additionally, some photopolymer materials (such as photopolymers) can have all of the aforementioned properties and can be patterned like a photoresist mask and remain on the surface after patterning and etching, whereas photopolymers Material has been deposited on the surface as part of a passivation layer.

In some embodiments, for example, the manufacturing technology of the passivation layer 213 may include spin coating, lamination, deposition or similar methods. Deposition may include chemical vapor deposition, such as plasma enhanced chemical vapor deposition. The process temperature of plasma enhanced chemical vapor deposition can be Between about 350°C and about 450°C. The process pressure of plasma enhanced chemical vapor deposition can range from 2.0 Torr to about 2.8 Torr. The plasma enhanced chemical vapor deposition process duration may be between about 8 seconds and about 12 seconds.

Referring to FIG. 5 , a plurality of bonding pads 215 may be formed in the passivation layer 213 and may be electrically coupled to the corresponding through-substrate vias 211 . In some embodiments, a plurality of bonding pad openings (not shown in FIG. 5 ) may be formed in the passivation layer 213 , and a conductive material may be formed to fill the bonding pad openings, thereby forming a plurality of bonding pads 215 . The manufacturing technology of the pad opening may include a photolithography process followed by an etching process. In some embodiments, the etching process may be an anisotropic dry etching process using argon and tetrafluoromethane as etchants. The process temperature of the etching process may range from about 120°C to about 160°C. The process pressure of the etching process may range from about 0.3 Torr to about 0.4 Torr. The etching duration of the etching process may range from about 33 seconds to about 39 seconds. Alternatively, in some embodiments, the etching process may be an anisotropic dry etching process using helium and nitrogen trifluoride (nitrogen trifluoride) as etchants. The process temperature of the etching process may range from about 80°C to about 100°C. The process pressure of the etching process may range from about 1.2 Torr to about 1.3 Torr. The etching duration of the etching process may range from about 20 seconds to about 30 seconds.

In some embodiments, the pad openings may be sequentially filled with conductive material by sputtering or electroless plating. For example, when the pad opening is filled by sputtering using an aluminum-copper material as the source, the sputtering process temperature may be between about 100°C and about 400°C. The sputtering process pressure may range from approximately 1 mTorr to approximately 100 mTorr. As another example, the pad openings are filled by a plating process using a plating solution. The plating solution may include copper sulfate, copper methane sulfonate, copper gluconate, copper sulfamate, nitric acid Copper (copper nitrate), copper phosphate (copper phosphate) or copper chloride (copper chloride). The pH of the plating solution may be between about 2 and about 6, or between about 3 and about 5. The process temperature of the electroplating process can be maintained between about 40°C and about 75°C, or between about 50°C and about 70°C.

Referring to FIG. 6 , a separation process may be performed to cut the stacked wafer 201 along the cutting portion SL2. The separation process can be performed by a laser cutter or a saw blade. After the separation process, the stacked wafer 201 can be divided into stacked die SD1 and stacked die SD2. The stacked die SD1 may include a front surface SD1F and a back surface SD1B that are opposite to each other. In FIG. 6 , the front surface SD1F of the stacked die SD1 is the upper surface of the passivation layer 213 , and the rear surface SD1B of the stacked die SD1 is the lower surface of the lowermost dielectric layer 207 . Therefore, the stacked die SD2 may include a front surface SD2F and a back surface SD2B disposed opposite to each other. A plurality of stacked dies SD1, SD2 can be transformed from the carrier layer 601 into a die frame 603. It should be understood that after the separation process, tiny cracks and seams may occur on each sidewall SD1S, SD2S of stacked die SD1 and stacked die SD2.

Referring to FIG. 7 , the stacked die SD1 and the stacked die SD2 can be sequentially bonded to the base wafer 101 . The stacked die SD1 may be bonded to the base wafer 101 in a face-to-face configuration through a hybrid bonding process. The front surface SD1F of the stacked die SD1 may be bonded to the front surface 101FS of the base wafer 101 . In some embodiments, for example, the hybrid bonding process may be thermo-compression bonding, passivation-capping-layer assisted bonding, or surface activated bonding. . For example, the hybrid bonding process may include activating the exposed surfaces of the lowermost dielectric layer 207 and the uppermost dielectric layer 111 of the stacked die SD1 (eg, in a plasma process), and cleaning the dielectric layers 111 and 207 after activation. , activating the dielectric layer 111 The surface is in contact with the activated surface of dielectric layer 207 , and a thermal annealing process is performed to strengthen the bond between dielectric layer 111 and dielectric layer 207 .

In some embodiments, the process pressure of the hybrid bonding process may range from about 100 MPa to about 150 MPa. In some embodiments, the process temperature of the hybrid bonding process may range from approximately room temperature (eg, 25°C) to approximately 400°C. In some embodiments, surface treatments such as wet chemical cleaning and gas/vapor phase heat treatment may be used to lower the process temperature of the hybrid bonding process or shorten the time consumption of the hybrid bonding process.

In some embodiments, hybrid bonding processes may include dielectric-to-dielectric bonding, metal-to-metal bonding, and metal-to-dielectric bonding. The dielectric-to-dielectric bond may originate from the bond between the lowermost dielectric layer 207 of the stacked die SD1 and the uppermost dielectric layer 111 of the base wafer 101 . Metal-to-metal bonding may result from the bonding between the conductive pads of stacked die SD1 and the conductive pads of base wafer 101 . The metal-to-dielectric bond may originate from the bonding between the lowermost dielectric layer 207 of the stacked die SD1 and the conductive pads of the base wafer 101 and the uppermost dielectric layer 111 of the base wafer 101 and the stacked die. The bonding between the conductive pads of particle SD1.

In some embodiments, for example, when the lowermost dielectric layer 207 of the stacked die SD1 and the uppermost dielectric layer 111 of the base wafer 101 may include silicon oxide or silicon nitride, one of the dielectric layers 111 and 207 The bonding between them can be based on the hydrophilic bonding mechanism. Hydrophilic surface modification may be applied to dielectric layers 111 and 207 prior to bonding.

In some embodiments, when stacking the lowermost dielectric layer 207 of the die SD1 and the uppermost dielectric layer 111 of the base wafer 101, the stack includes a polymer adhesive, such as polyimide, phenylcyclobutene, polybenzo When using oxazole, the bonding between the dielectric layers 111 and 207 can be based on thermocompression bonding.

In some embodiments, after the bonding process, a thermal annealing process may be performed to strengthen the dielectric-to-dielectric bond and generate thermal expansion of the metal-to-metal bond to further further improve the joint quality.

Referring to FIG. 7 , the stacked die SD2 can be bonded to the base wafer 101 in a procedure similar to the stacked die SD1 , and its description will not be repeated herein. In this embodiment, stacked die SD1 is bonded to the left region of base wafer 101 . The stacked die SD2 is bonded to the right region of the base wafer 101 and is disposed away from the stacked die SD1.

Referring to FIG. 8 , the stacked dies SD3 , SD4 , SD5 , and SD6 can be provided in a procedure similar to the stacked dies SD1 and SD2 , and their description will not be repeated in the text. The stacked die SD3 can be bonded to the stacked die SD1 and the stacked die SD4 can be bonded to the stacked die SD2 respectively and correspondingly through a hybrid bonding process similar to that described in FIG. 7 , and will not be described again herein. . In some embodiments, stacked die SD3 and stacked die SD1 may be bonded in a face-to-back configuration. In some embodiments, stacked die SD3 and stacked die SD1 may be bonded in a back-to-back configuration. In some embodiments, a redistribution layer may be formed between stacked die SD3 and stacked die SD1 to electrically couple the conductive features of stacked die SD3 and stacked die SD1 . Stacked dies SD4, SD5, SD6 may be bonded in a procedure similar to stacked die SD3, and their description will not be repeated herein. In this embodiment, the uppermost stacked dies SD5 and SD6 may not include the through-substrate via holes.

In some embodiments, stacked die SD1 and stacked die SD3 may have the same layout and may include the same functional units. In some embodiments, stacked die SD1 and stacked die SD3 may have different layouts and may include different functional units.

It should be understood that in the description of the present disclosure, the number of stacked dies is for illustrative purposes only. The number of stacked dies may be greater or less than that shown in FIG. 8 .

Referring to Figures 1 and 9, in step S15, a refill layer 301 can be conformally formed to cover the negative number of stacked dies SD1, SD2, SD3, SD4, SD5, SD6 and the base Front surface 101FS of wafer 101 .

Referring to FIG. 9 , the refill layer 301 may be conformally formed on the front surface 101FS of the base wafer 101 and on each sidewall SD1S, SD2S, SD3S of the plurality of stacked dies SD1, SD2, SD3, SD4, SD5, and SD6. , SD4S, SD5S, SD6S and on each rear surface SD5B, SD6B of a plurality of stacked dies SD5, SD6. During cutting, the refill layer 301 can be used to fill the cracks and seams of the plurality of stacked dies SD1, SD2, SD3, SD4, SD5, and SD6. In some embodiments, the thickness T1 of the refill layer 301 may be between about 50 Å and about 1000 Å. For example, in some embodiments, refill layer 301 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, titanium oxide, aluminum oxide, hafnium oxide, or combinations thereof. For example, the fabrication technology of the refill layer 301 may include atomic layer deposition.

In general, atomic layer deposition is based on typically self-limiting reactants by depositing a single layer of material approximately one atomic (or molecule) per deposition cycle using sequential and staggered pulses of reactants. Deposition conditions and precursors are typically chosen to provide self-saturating reactants such that an absorbing layer of one reactant leaves a surface termination that is not produced by a gas phase reactant of the same reactant reaction. The substrate is sequentially contacted with a different reactant, which reacts with the aforementioned termination to continue to produce deposition. Therefore, each cycle of the interleaved pulses typically leaves no more than about a single layer of the desired material. However, during one or more cycles of atomic layer deposition, more than a single layer of material may be deposited.

In this embodiment, the refill layer 301 may include silicon nitride, and its fabrication technology may include atomic layer deposition. For example, the substrate surface on which the intended deposition is performed (such as the front surface 101FS of the base wafer 101, each sidewall SD1S, SD2S, SD3S, SD4S of the plurality of stacked dies SD1, SD2, SD3, SD4, SD5, SD6 , SD5S, SD6S and on each rear surface SD5B, SD6B of a plurality of stacked dies SD5, SD6) react with a first gas phase The first gas phase reactant includes a silicon precursor that is chemically adsorbed onto the substrate surface to form no more than a single layer of reactant species on the substrate surface. In some embodiments, each contact step may be repeated one or more times before proceeding to subsequent processing steps, ie, a subsequent contact step or removal/cleaning step.

In some embodiments, a silicon precursor may include a silicon halide source. In some embodiments, the first gas phase reactant may include a silicon halide source and may further include at least one of the following: silicon tetraiodide, silicon tetrabromide, silicon tetrabromide ( silicon tetrachloride), hexachlorodisilane, hexaiododisilane and octoiodotrisilane. In some embodiments, the silicon halide source may be preheated to provide sufficient gas phase pressure for delivery. For example, the silicon halide source may be preheated to between about 90°C and about 125°C, or to about 100°C.

In some embodiments, contacting (or exposing) the substrate surface to a silicon halide source may include pulsing a silicon precursor on the substrate surface for a time interval of between about 0.5 seconds to about 30 seconds, or between Between about 0.5 seconds and about 10.0 seconds, or between about 0.5 seconds and about 5.0 seconds. Furthermore, during the pulse, the flow rate of the silicon halide source may be less than 2000 sccm, or less than 1000 sccm, or less than 500 sccm, or less than 250 sccm, or even less than 100 sccm.

Excess silicon halide sources and reactant by-products, if any, can be removed from the substrate surface, for example by purging an inert gas. In some embodiments, atomic layer deposition may include a purge cycle in which the substrate surface is purged for a time period of less than approximately 5.0 seconds. Excess silicon halide sources and any reactant by-products can be aided in removal by a vacuum created by a pump system.

Next, the base surface is contacted with a second gas phase reactant. The second gas phase The reactants include a nitrogen source. In some embodiments, the second gas phase reactant may include at least one of the following: ammonia, hydrazine, or alkyl-hydrazine. Alkyl hydrazine can be represented as a derivative of hydrazine, which can include an alkyl (alkyl) functional group, and can also include additional functional groups. Non-limiting exemplary embodiments of an alkyl hydrazine can include tert. Butylhydrazine (tertbutylhydrazine), methylhydrazine (methylhydrazine) or dimethylhydrazine (dimethylhydrazine).

In some embodiments, contacting (or exposing) the substrate surface to a nitrogen source may include the nitrogen source generating a pulse on the substrate surface for a time interval of between about 0.5 seconds to about 30 seconds, or between about 0.5 seconds to approximately 10.0 seconds, or between approximately 0.5 seconds to approximately 5.0 seconds. During the pulse, the flow rate of the nitrogen source may be less than 4000 sccm, or less than 2000 sccm, or less than 1000 sccm, or even less than 250 sccm.

Excess second gas phase reactants and reactant by-products, if any, may be removed from the substrate surface, for example, by a purge gas pulse and/or a vacuum generated by a pump system. Preferably, the purge gas is any inert gas, such as argon, nitrogen or helium, but is not limited thereto.

In some embodiments, atomic layer deposition can be performed at a reaction chamber pressure less than approximately 50 Torr, a reaction chamber pressure less than 25 Torr, or even a reaction chamber pressure less than 5 Torr.

In some embodiments, once refill layer 301 is deposited, refill layer 301 may be exposed to a plasma in order to improve the material properties of refill layer 301 . In some embodiments, the plasma may be configured as a capacitively coupled plasma source, an inductively coupled plasma source, or a remote plasma source. In some embodiments, the source gas generated from the plasma may include one or more of nitrogen, helium, hydrogen, and argon. In some embodiments, supplying plasma source gas energy The power may be greater than about 150W, or greater than about 300W, or greater than about 600W, or even greater than about 900W. In some embodiments, the pressure at which refill layer 301 is exposed to the plasma may be less than about 4 Torr, less than about 2 Torr, or may even be less than 1 Torr. In some embodiments, the duration of exposure of refill layer 301 to the plasma may be less than about 300 seconds, less than about 150 seconds, or even less than about 90 seconds.

Please refer to FIGS. 1, 10 and 11. In step S17, a first molding layer 401 may be formed on the refill layer 301.

Referring to FIG. 10 , the first molding layer 401 may be formed on the refill layer 301 to completely cover the refill layer 301 , the front surface 101FS of the base wafer 101 and the plurality of stacked dies SD1, SD2, SD3, SD4, SD5, SD6. It should be understood that the gaps between stacked dies SD1, SD3, SD5 and stacked dies SD2, SD4, SD6 may be completely filled by the first molding layer 401. In some embodiments, the first molding layer 401 may include a molding compound such as polybenzoxazole, polyimide, benzocyclobutene, epoxy laminate ( epoxy laminate) or ammonium bifluoride. The manufacturing technology of the first molding layer 401 may include compression molding, transfer molding, liquid encapsulant molding or other molding. For example, a molding compound can be dispensed in liquid form. Next, a curing process is performed to solidify the molding compound. The formation of the molding compound may overflow the intermediate semiconductor element as shown in FIG. 10 so that the molding compound can completely cover the refill layer 301 and the plurality of stacked dies SD1, SD2, SD3, SD4, SD5, SD6.

Referring to FIG. 11 , a thinning process may be performed to reduce a thickness of the substrate 203 so as to reduce the heights of the plurality of stacked dies SD5 and SD6. This thinning process allows for modification Good heat dissipation and provides a low component profile. In some embodiments, the plurality of stacked dies SD5, SD6 may be thinned to a thickness of between about 0.5 μm and about 10 μm. Thinning processes can be accomplished using mechanical abrasion, grinding or similar methods, or chemical removal such as a wet etch.

In some embodiments, a thinning stop layer (not shown) may be implanted in the substrate 203 of the plurality of stacked dies SD5, SD6 for thinning stop control. The thinning stop layer may be a dopant layer or an epitaxial growth layer having a thickness of between about 0.2 μm and about 10 μm. The thickness of the thinned stop layer can be selected so that it is thick enough to terminate the thinning process depending on the etch selectivity used. For example, if the etching selectivity used is approximately 1:100, the thinning stop layer may have a thickness ranging from approximately 0.2 μm to approximately 5 μm. Multiple sizes are available for thinning the stop layer based on process configuration.

Referring to FIGS. 1 and 12 , in step S19 , a plurality of first connectors 407 may be formed to electrically couple to the plurality of device components 109 of the base wafer 101 .

Referring to Figure 12, the intermediate semiconductor device ISD as described in Figure 11 can be flipped. A lower passivation layer 403 may be formed on the back surface 101BS of the base wafer 101 . In some embodiments, the lower passivation layer 403 may include a polymer material, such as polybenzoxazole, polyimide, benzocyclobutene, or ajinomoto. buildup film, solder resist film or similar. Polymeric materials (such as polyimide) can have some attractive characteristics, such as the ability to fill multiple openings with high aspect ratios, a relatively low dielectric constant (approximately 3.2), a simple deposition process, Reduction of sharp features or steps in underlying layers and high temperature tolerance after curing. Additionally, some photopolymer materials (such as photopolymers) can have all of the aforementioned properties and can be patterned like a photoresist. The mask can remain on the surface after patterning and etching, and the photopolymer material has been deposited on the surface as part of a passivation layer.

In some embodiments, for example, the manufacturing technology of the lower passivation layer 403 may include spin coating, lamination, deposition or similar methods. Deposition may include chemical vapor deposition, such as plasma enhanced chemical vapor deposition. The plasma enhanced chemical vapor deposition process temperature may be between about 350°C and about 450°C. The process pressure of plasma enhanced chemical vapor deposition can range from 2.0 Torr to about 2.8 Torr. The plasma enhanced chemical vapor deposition process duration may be between about 8 seconds and about 12 seconds.

Referring to FIG. 12 , a plurality of lower bonding pads 405 may be formed in the lower passivation layer 403 and may be electrically coupled to the corresponding through-substrate vias 115 . In some embodiments, a plurality of bonding pad openings (not shown in FIG. 12 ) may be formed in the lower passivation layer 403 , and a conductive material may be formed to fill the bonding pad openings, thereby forming the lower passivation layer 403 . The manufacturing technology of the pad opening may include a photolithography process followed by an etching process. In some embodiments, the etching process may be an anisotropic dry etching process using argon and tetrafluoromethane as etchants. The process temperature of the etching process may range from about 120°C to about 160°C. The process pressure of the etching process may range from about 0.3 Torr to about 0.4 Torr. The etching duration of the etching process may range from about 33 seconds to about 39 seconds. Alternatively, in some embodiments, the etching process may be an anisotropic dry etching process using helium and nitrogen trifluoride (nitrogen trifluoride) as etchants. The process temperature of the etching process may range from about 80°C to about 100°C. The process pressure of the etching process may range from about 1.2 Torr to about 1.3 Torr. The etching duration of the etching process may range from about 20 seconds to about 30 seconds.

In some embodiments, the pad openings may be sequentially filled with conductive material by sputtering or electroless plating. For example, when the pad opening uses an aluminum-copper material as the source When filling by sputtering, the sputtering process temperature may be between about 100°C and about 400°C. The sputtering process pressure may range from approximately 1 mTorr to approximately 100 mTorr. As another example, the pad openings are filled by a plating process using a plating solution. The plating solution may include copper sulfate, copper methane sulfonate, copper gluconate, copper sulfamate, copper nitrate, copper phosphate (copper phosphate) or copper chloride (copper chloride). The pH of the plating solution may be between about 2 and about 6, or between about 3 and about 5. The process temperature of the electroplating process can be maintained between about 40°C and about 75°C, or between about 50°C and about 70°C.

Referring to FIG. 12 , a plurality of first connections 407 may be formed on the lower passivation layer 403 and on a plurality of lower bonding pads 405 . The plurality of first connecting members 407 may be electrically connected to the plurality of lower bonding pads 405 respectively and correspondingly. In some embodiments, the plurality of first connectors 407 may include a conductive material with low resistivity, such as tin, lead, silver, copper, nickel, bismuth or alloys thereof, and its manufacturing technology may include an appropriate process. , such as evaporation, plating or ball drop.

In some embodiments, the plurality of first connectors 407 may be solder joints. The solder joints may include a material such as tin, or other suitable materials such as silver or copper. In one embodiment where the solder joints are tin solder joints, the fabrication technique of the solder joints may include initially forming a layer via evaporation, electroplating, printing, solder transfer or ball placement. Tin to a thickness of between approximately 10 μm and approximately 100 μm. Once the layer of tin has been formed on the lower passivation layer 403, a reflow process can be performed to shape the solder joints into the desired shape.

In some embodiments, the plurality of first connectors 407 may be cylindrical bumps, For example, the stud bumps include copper. The pillar bumps can be formed directly on the back surface 101BS of the base wafer 101 without the need for multiple contact pads, multiple lower bump metals or the like, thereby also reducing the cost and process complexity of the semiconductor device 1A. This may allow for an increase in the density of the stud bumps. For example, in some embodiments, a critical dimension (eg, pitch) of a stud bump may be less than approximately 5 μm, and the stud bump may have a height less than approximately 10 μm. Fabrication techniques for the pillar bumps may include using any suitable method, such as depositing a seed layer, selectively forming a bump metal, using a mask to define a shape of the pillar bumps, electrochemical Plating the stud bumps in the mask, and then removing the mask and any undesired portions of the seed layer. The stud bumps can be used to electrically connect the semiconductor device 1A to other packaging components, such as a fan-out redistribution layer, packaging substrates, interposers, printing Circuit boards and the like.

Referring to FIGS. 1 and 13 , in step S21 , a separation process may be performed along the cutting portion SL1 to form a plurality of chip stacks CS1 and CS2 .

Referring to FIG. 13 , a separation process may be performed to cut the base wafer 101 along the cutting portion SL2 . During the separation process, the first molding layer 401 may also fill the gaps between the stacked dies SD1, SD3, SD5 and the stacked dies SD2, SD4, SD6. The manufacturing technology of the separation process may include a laser cutter or a saw blade. After the separation process, the base wafer 101 can be divided into a first base die 103 and a second base die 105 . In some embodiments, the width W1 of the first base die 103 may be greater than the width W2 of the stacked die SD1.

Referring to FIG. 13 , the first base die 103 , a plurality of stacked dies SD1 , SD3 , SD5 , the remaining refill layer 301 and the remaining first molding layer 401 are configured together to form a chip stack CS1 . The second basic die 105, multiple stacked die SD2, SD4, SD6, remaining The refill layer 301 and the remaining first molding layer 401 are configured together to form a wafer stack CS2.

Conventionally, the separation process includes cutting materials with distinct hardness (eg, soft first mold layer 401 and hard base wafer 101) so that multiple process parameters may be difficult to optimize. Additionally, stresses during cutting of materials with greater hardness can cause cracks and seams to propagate across stacked dies SD1, SD2, SD3, SD4, SD5, SD6. Therefore, the structural stability and reliability of the semiconductor device 1A may be affected.

On the contrary, the refill layer 301 can compensate for the difference in hardness and fill the cracks and seams of the plurality of stacked dies SD1, SD2, SD3, SD4, SD5, and SD6. Therefore, adverse effects during the separation process can be reduced or avoided. In other words, the separation process does not need to be over-optimized so as to reduce the complexity of the manufacturing process of the semiconductor device 1A.

Referring to FIGS. 1 and 14 , in step S23 , the plurality of chip stacks CS1 and CS2 may be respectively and correspondingly bonded to the plurality of packaging substrates 501 , and a plurality of second connectors 503 may be formed under the plurality of packaging substrates 501 .

Referring to FIG. 14 , the chip stack CS1 may be bonded to a packaging substrate 501 via a first connector 407 . In some embodiments, the width W3 of the package substrate 501 may be greater than the width W4 of the die stack CS1. A plurality of second connections 503 may be formed under the packaging substrate 501 and electrically coupled to the first connections 407 via a plurality of conductive features formed in the packaging substrate 501 (not shown for clarity). In some embodiments, the plurality of second connectors 503 may be controlled collapse chip connection (C4) bumps, and their manufacturing technology includes a C4 process.

Referring to FIG. 14, a second molding layer 409 may be formed on the packaging substrate 501 to completely cover the chip stack CS1. In some embodiments, second molding layer 409 may include a mold Plastic compounds such as polybenzoxazole, polyimide, benzocyclobutene, epoxy laminate or ammonium bifluoride. The manufacturing technology of the second molding layer 409 may include compression molding, transfer molding, liquid encapsulant molding, or other molding. For example, a molding compound can be dispensed in liquid form. Next, a curing process is performed to solidify the molding compound. The molding compound may be formed overflowing the packaging substrate 501 so that the molding compound may completely cover the die stack CS1. A planarization process, such as mechanical grinding, chemical mechanical grinding, or other etch-back techniques, can be applied to remove excess portions of the molding compound and provide a generally flat surface.

15 to 16 are schematic cross-sectional views illustrating semiconductor devices 1B and 1C according to some embodiments of the present disclosure.

Referring to FIG. 15 , the semiconductor device 1B may have a structure similar to that described in FIG. 14 . Elements in FIG. 15 that are the same as or similar to those in FIG. 14 have been labeled with similar element numbers, and repeated descriptions thereof have been omitted.

In the semiconductor device 1B, the refill layer 301 may also cover the rear surface SD5B of the stacked die SD5. A portion of the second molding layer 409 may be disposed on the refill layer 301 . The upper surface 401TS of the first molding layer 401 may be substantially coplanar with the upper surface 301TS of the refill layer 301 .

Referring to FIG. 16 , the semiconductor device 1C may have a structure similar to that described in FIG. 14 . Elements in FIG. 16 that are the same as or similar to those in FIG. 14 have been labeled with similar element numbers, and repeated descriptions thereof have been omitted.

In the semiconductor device 1C, the refill layer 301 may also cover the rear surface SD5B of the stacked die SD5. The second molding layer 409 may completely cover the first molding layer 401 . Second molding layer 409 does not contact the refill layer 301 or the base 203 of the stacked die SD5.

An embodiment of the present disclosure provides a semiconductor device, including a chip stack including a first base die; a first stacked die disposed on a front surface of the first base die; and a refill layer, disposed on one side wall of the stacked die. The refill layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, titanium oxide, aluminum oxide or hafnium oxide.

Another embodiment of the present disclosure provides a semiconductor device including a chip stack including a first base die; a first stacked die disposed on a front surface of the first base die; and a refill layer , completely covering the stacked die and being disposed on the front surface of the first base die. The refill layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, titanium oxide, aluminum oxide or hafnium oxide.

Yet another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a base wafer including a cutting portion; and bonding a first stacked die and a second stacked die through a hybrid bonding process. The die is bonded to a front surface of the base wafer, wherein the first stacked die and the second stacked die are disposed opposite to each other, and the cutting portion is interposed therebetween; a refill layer is conformally formed to cover The first stacked die and the second stacked die; forming a first molding layer to cover the refill layer and configured into an intermediate semiconductor component, the intermediate semiconductor component including the base wafer, the first stacked die , the second stacked die, the refill layer and the first molding layer; and cutting the intermediate semiconductor element along the cutting portion to separate the first stacked die, the second stacked die, the refill layer The layer, the first molding layer and the base wafer are separated, wherein after cutting, the base wafer is separated into a first base die and a second base die. The first base die, the first stacked die, the refill layer and the first molding layer are configured together into a first wafer stack.

Due to the design of the semiconductor device of the present disclosure, the refill layer 301 can compensate for the hardness difference and fill the cracks and seams of the stacked dies SD1, SD2, SD3, SD4, SD5, and SD6. Therefore, during cutting, its adverse effects are reduced or avoided. On the other hand, the cutting process does not need to be excessively optimized, so that the cost and process complexity of manufacturing the semiconductor device 1A can also be reduced.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

1A: Semiconductor components 101BS: Back surface 101FS: Front surface 103:The first basic grain 105: The second basic grain 107: Base 109:Device components 111: Dielectric layer 113: Conductive characteristics 203:Base 205:Device components 207:Dielectric layer 209: Conductive characteristics 211:Through-substrate through hole 213: Passivation layer 215:Joint pad 301:Refill layer 401: First molding layer 403: Lower passivation layer 405: Lower joint pad 407: First connector 409: Second molding layer 501:Packaging substrate 503: Second connector CS1: Wafer stacking SD1: Stacked die SD1S: side wall SD3: stacked die SD5: stacked die W3: Width W4: Width Z: direction

Claims (20)

A semiconductor component including: A wafer stack includes: a first basic grain; a first stacked die disposed on a front surface of the first base die; and A refill layer is provided on one side wall of the stacked grain; The refill layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, titanium oxide, aluminum oxide or hafnium oxide. The semiconductor device of claim 1, wherein the refill layer has a thickness ranging from about 50Å to about 1000Å. The semiconductor device of claim 2, wherein a width of the first base die is greater than a width of the stacked die. The semiconductor device according to claim 3, further comprising a first molding layer disposed on the refill layer and opposite to the stacked die. The semiconductor device of claim 4, wherein the chip stack further includes a passivation layer disposed on a rear surface of the first base die, and the front surface of the first base die is in contact with the first base die. The rear surfaces of the grains are arranged opposite each other. The semiconductor device of claim 5, wherein the chip stack further includes a first connection member disposed below the lower passivation layer and opposite to the first base die. The semiconductor device according to claim 6, further comprising a packaging substrate, wherein the chip stack is disposed on the packaging substrate. The semiconductor device according to claim 7, further comprising a second connection member disposed below the packaging substrate. The semiconductor device of claim 8, wherein a width of the packaging substrate is greater than a width of the chip stack. The semiconductor device according to claim 9, further comprising a second molding layer disposed on the packaging substrate and covering the chip stack. The semiconductor device of claim 10, wherein the refill layer is also horizontally disposed on the front surface of the first base die. A semiconductor component including: A wafer stack includes: a first basic grain; a first stacked die disposed on a front surface of the first base die; and a refill layer completely covering the stacked die and disposed on the front surface of the first base die; The refill layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, titanium oxide, aluminum oxide or hafnium oxide. The semiconductor device of claim 12, wherein the wafer stack further includes a first molding layer that completely covers the refill layer. A method for preparing semiconductor components, including: Provide a base wafer, the base wafer including a cutting part; bonding a first stacked die and a second stacked die to a front surface of the base wafer via a hybrid bonding process, wherein the first stacked die and the second stacked die are disposed opposite to each other, and the cutting part is inserted therebetween; Conformally forming a refill layer to cover the first stacked die and the second stacked die; A first molding layer is formed to cover the refill layer and configured to form an intermediate semiconductor element, the intermediate semiconductor element including the base wafer, the first stacked die, the second stacked die, the refill layer and the first molding layer; and The intermediate semiconductor element is cut along the cutting portion to separate the first stacked die from the second stacked die, the refill layer, the first molding layer, and the base wafer, wherein after cutting , the basic wafer is divided into a first basic die and a second basic die; The first base die, the first stacked die, the refill layer and the first molding layer are configured together to form a first wafer stack. The method of manufacturing a semiconductor device according to claim 14, wherein the refill layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, titanium oxide, aluminum oxide or hafnium oxide. The method of manufacturing a semiconductor device as claimed in claim 15, wherein a process pressure of the hybrid bonding process is between about 100 MPa and about 150 MPa. The method of manufacturing a semiconductor device as claimed in claim 15, wherein a process temperature of the hybrid bonding process is between about 25°C and about 400°C. The method of manufacturing a semiconductor device according to claim 15, wherein the first stacked die and the base wafer are bonded in a face-to-face configuration. The method of manufacturing a semiconductor device according to claim 15, further comprising: before bonding the first stacked die and the second stacked die to the front surface of the base wafer through the hybrid bonding process, Perform a surface treatment on the front surface of the base wafer; The surface treatment includes a wet chemical cleaning or a vapor phase heat treatment. The method of manufacturing a semiconductor device according to claim 15, further comprising bonding the wafer stack to a packaging substrate.