TWI823479B - Thin-film chip resistor-capacitor and method of fabricating the same - Google Patents
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Abstract
Description
本發明是有關於一種電阻電容元件,且特別是指一種薄膜晶片電阻電容及其製作方法。 The present invention relates to a resistor and capacitor element, and in particular to a thin film chip resistor and capacitor and a manufacturing method thereof.
常見的電阻電容元件為利用電阻與電容做串聯或並聯設計或者藉由低溫陶瓷共燒製程形成電阻電容耦合電器而達成。在習知電阻電容元件的設計上,為了達到電路的小型化,通常電阻與電容的尺寸設計空間會大幅受到限制,導致難以達到高阻值與高容值,且也會因為尺寸過小而導致可耐功率與散熱效果降低。另一方面,低溫陶瓷共燒製程容易受到共燒時各自元件的熱物理性質的影像而導致生產品質不佳。 Common resistive and capacitive components are achieved by using resistors and capacitors in series or parallel designs, or by forming resistive and capacitive coupling devices through a low-temperature ceramic co-firing process. In the design of conventional resistor and capacitor components, in order to achieve circuit miniaturization, the size design space of resistors and capacitors is usually greatly restricted, making it difficult to achieve high resistance and capacitance values, and also causing failure due to the small size. The power resistance and heat dissipation effect are reduced. On the other hand, the low-temperature ceramic co-firing process is easily affected by the thermophysical properties of the respective components during co-firing, resulting in poor production quality.
本發明提出一種薄膜晶片電阻電容及其製作方法,其透過在電阻層或基材的上方製作額外的薄膜電容層,並藉由端電極耦接電阻層和薄膜電容層而形成電阻電容元件, 可在不犧牲電阻值和電容值的前提下,同時達成晶片薄化與微型化等效果。 The present invention proposes a thin film chip resistor and capacitor and a manufacturing method thereof. The resistor and capacitor element is formed by forming an additional thin film capacitor layer on top of the resistor layer or substrate, and coupling the resistor layer and the thin film capacitor layer through terminal electrodes. Effects such as chip thinning and miniaturization can be achieved simultaneously without sacrificing resistance and capacitance values.
本發明之一方面是指一種薄膜晶片電阻電容,其包含基材、電阻層、第一介質層、第一薄膜電容層、第一端電極和第二端電極。電阻層設置於基材上。第一介質層設置於電阻層上。第一薄膜電容層設置於該第一介質層上,其包含互為實體分離的第一電容電極和第二電容電極。第一端電極設置於基材的第一側邊上且耦接電阻層和第一電容電極。第二端電極設置於基材之相對於第一側邊的第二側邊上且耦接電阻層和第二電容電極。 One aspect of the present invention refers to a thin film chip resistor capacitor, which includes a substrate, a resistive layer, a first dielectric layer, a first thin film capacitor layer, a first terminal electrode and a second terminal electrode. The resistance layer is arranged on the base material. The first dielectric layer is disposed on the resistive layer. The first thin film capacitor layer is disposed on the first dielectric layer and includes a first capacitor electrode and a second capacitor electrode that are physically separated from each other. The first terminal electrode is disposed on the first side of the substrate and couples the resistive layer and the first capacitive electrode. The second terminal electrode is disposed on the second side of the substrate relative to the first side and is coupled to the resistance layer and the second capacitance electrode.
依據本發明的一或多個實施例,上述第一電容電極和上述第二電容電極為梳狀電極,且上述第一電容電極的電極分支和上述第二電容電極的電極分支為交替設置。 According to one or more embodiments of the present invention, the first capacitor electrode and the second capacitor electrode are comb-shaped electrodes, and the electrode branches of the first capacitor electrode and the electrode branches of the second capacitor electrode are alternately arranged.
依據本發明的一或多個實施例,上述薄膜晶片電阻電容更包含第二介質層,其設置於上述第一薄膜電容層上且覆蓋上述第一電容電極的電極分支和上述第二電容電極的電極分支。 According to one or more embodiments of the present invention, the thin film chip resistor capacitor further includes a second dielectric layer disposed on the first thin film capacitor layer and covering the electrode branches of the first capacitor electrode and the second capacitor electrode. Electrode branches.
依據本發明的一或多個實施例,上述薄膜晶片電阻電容更包含第二薄膜電容層,其設置於上述基材之相對於上述電阻層的另一側上,且其包含互為實體分離且分別耦接上述第一端電極和上述第二端電極的第三電容電極和第四電容電極。 According to one or more embodiments of the present invention, the thin film chip resistor capacitor further includes a second thin film capacitor layer, which is disposed on the other side of the base material relative to the resistive layer, and includes a second thin film capacitor layer that is physically separated from each other and The third capacitor electrode and the fourth capacitor electrode are respectively coupled to the first terminal electrode and the second terminal electrode.
依據本發明的一或多個實施例,上述第三電容電極和上述第四電容電極為梳狀電極,且上述第三電容電極的 電極分支和上述第四電容電極的電極分支為交替設置。 According to one or more embodiments of the present invention, the third capacitor electrode and the fourth capacitor electrode are comb-shaped electrodes, and the third capacitor electrode The electrode branches and the electrode branches of the fourth capacitor electrode are arranged alternately.
依據本發明的一或多個實施例,上述薄膜晶片電阻電容更包含第三介質層,其設置於上述第二薄膜電容層上且覆蓋上述第三電容電極的電極分支和上述第四電容電極的電極分支。 According to one or more embodiments of the present invention, the thin film chip resistor capacitor further includes a third dielectric layer disposed on the second thin film capacitor layer and covering the electrode branches of the third capacitor electrode and the fourth capacitor electrode. Electrode branches.
本發明另一方面是指一種製作薄膜晶片電阻電容的方法,其包含:提供基材;在基材上形成電阻層;在電阻層上形成第一介質層;在第一介質層上形成第一薄膜電容層,此第一薄膜電容層包含互為實體分離的第一電容電極和第二電容電極;在基材的第一側邊上形成耦接電阻層和第一電容電極的第一端電極;以及在基材之相對於第一側邊的第二側邊上形成耦接電阻層和第二電容電極的第二端電極。 Another aspect of the present invention refers to a method for manufacturing thin film chip resistors and capacitors, which includes: providing a base material; forming a resistance layer on the base material; forming a first dielectric layer on the resistance layer; forming a first dielectric layer on the first dielectric layer. Thin film capacitor layer, this first thin film capacitor layer includes a first capacitor electrode and a second capacitor electrode that are physically separated from each other; a first terminal electrode coupling the resistance layer and the first capacitor electrode is formed on the first side of the substrate ; And forming a second terminal electrode coupling the resistive layer and the second capacitive electrode on the second side of the substrate relative to the first side.
依據本發明的一或多個實施例,上述方法更包含在上述第一薄膜電容層上形成第二介質層,此第二介質層覆蓋上述第一電容電極的電極分支和上述第二電容電極的電極分支。 According to one or more embodiments of the present invention, the above method further includes forming a second dielectric layer on the above-mentioned first thin film capacitor layer, and the second dielectric layer covers the electrode branches of the above-mentioned first capacitor electrode and the above-mentioned second capacitor electrode. Electrode branches.
依據本發明的一或多個實施例,上述方法更包含在上述基材之相對於上述電阻層的另一側上形成第二薄膜電容層,此第二薄膜電容層包含互為實體分離且分別耦接上述第一端電極和上述第二端電極的第三電容電極和第四電容電極。 According to one or more embodiments of the present invention, the above method further includes forming a second thin film capacitor layer on the other side of the above substrate relative to the above resistive layer. The second thin film capacitor layer includes entities that are physically separated from each other and are respectively Third capacitor electrodes and fourth capacitor electrodes coupled to the first terminal electrode and the second terminal electrode.
依據本發明的一或多個實施例,上述方法更包含在上述第二薄膜電容層上形成第三介質層,此第三介質層覆 蓋上述第三電容電極的電極分支和上述第四電容電極的電極分支。 According to one or more embodiments of the present invention, the above method further includes forming a third dielectric layer on the above second film capacitor layer, and the third dielectric layer covers Cover the electrode branches of the above-mentioned third capacitor electrode and the electrode branches of the above-mentioned fourth capacitor electrode.
100:薄膜晶片電阻電容 100:Thin film chip resistor and capacitor
102:基材 102:Substrate
104:電阻層 104:Resistance layer
106A,106B:下電極 106A, 106B: Lower electrode
108:第一介質層 108: First dielectric layer
110A,110B:端電極 110A, 110B: terminal electrode
112A,112B:第一上電極 112A, 112B: first upper electrode
114:第二介質層 114: Second dielectric layer
116A1,116B1:第二上電極 116A1, 116B1: second upper electrode
116A2,116B2:電極分支 116A2, 116B2: Electrode branch
118:保護層 118:Protective layer
122A,122B:側電極 122A, 122B: Side electrode
200:薄膜晶片電阻電容 200: Thin film chip resistors and capacitors
202:基材 202:Substrate
204:電阻層 204:Resistance layer
206A1,206B1:下電極 206A1, 206B1: lower electrode
206A2,206B2:下電極分支 206A2, 206B2: Lower electrode branch
208:第一介質層 208: First dielectric layer
210A,210B:端電極 210A, 210B: terminal electrode
212A,212B:第一上電極 212A, 212B: first upper electrode
214:第二介質層 214: Second dielectric layer
216A1,216B1:第二上電極 216A1, 216B1: second upper electrode
216A2,216B2:上電極分支 216A2, 216B2: Upper electrode branch
218:保護層 218:Protective layer
222A,222B:側電極 222A, 222B: Side electrode
224:第三介質層 224:Third dielectric layer
C,C1,C2:電容 C, C1, C2: capacitor
CA,CB:電容電極 CA, CB: capacitive electrode
CAa,CBa:電極分支 CAa,CBa:electrode branches
R:電阻 R: Resistor
T1:第一端 T1: first end
T2:第二端 T2: Second end
為了更完整了解實施例及其優點,現參照結合所附圖式所做之下列描述,其中:[圖1]為依據本發明實施例之薄膜晶片電阻電容的剖視圖;[圖2]為[圖1]之薄膜晶片電阻電容的等效電路圖;[圖3]為[圖2]之電容的平面結構的一示例;[圖4]為依據本發明另一實施例之薄膜晶片電阻電容的剖視圖;[圖5]為[圖4]之薄膜晶片電阻電容的等效電路圖;以及[圖6A]至[圖6F]為製作[圖4]之薄膜晶片電阻電容的各階段剖視圖。 For a more complete understanding of the embodiments and their advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein: [Fig. 1] is a cross-sectional view of a thin film chip resistor and capacitor according to an embodiment of the present invention; [Fig. 2] is [Fig. 1] The equivalent circuit diagram of the thin film chip resistor and capacitor; [Fig. 3] is an example of the planar structure of the capacitor of [Fig. 2]; [Fig. 4] is a cross-sectional view of the thin film chip resistor and capacitor according to another embodiment of the present invention; [Fig. 5] is an equivalent circuit diagram of the thin film chip resistor and capacitor of [Fig. 4]; and [Fig. 6A] to [Fig. 6F] are cross-sectional views of each stage of manufacturing the thin film chip resistor and capacitor of [Fig. 4].
以下仔細討論本揭露的實施例。然而,可以理解的是,實施例提供許多可應用的概念,其可實施於各式各樣的特定內容中。所討論、揭示之實施例僅供說明,並非用以限定本揭露之範圍。 Embodiments of the present disclosure are discussed in detail below. It is to be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The embodiments discussed and disclosed are for illustration only and are not intended to limit the scope of the present disclosure.
在本文中所使用的用語僅是為了描述特定實施例,非用以限制申請專利範圍。除非另有限制,否則單數形式的「一」或「該」用語也可用來表示複數形式。 The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the scope of the patent application. Unless otherwise restricted, the singular form "a" or "the" may also be used to denote the plural form.
可被理解的是,雖然在本文可使用「第一」、「第二」...等用語來描述各種訊號、元件和/或零件,但此些用語不應限制此些訊號、元件和/或零件。此些用語僅用以區別一訊號、元件和/或零件與另一訊號、元件和/或零件。 It will be understood that although terms such as "first", "second"... may be used herein to describe various signals, components and/or parts, these terms should not limit these signals, components and/or parts. or parts. These terms are only used to distinguish one signal, component and/or part from another signal, component and/or part.
空間相對性用語的使用是為了說明元件在使用或操作時的不同方位,而不只限於圖式所繪示的方向。元件也可以其他方式定向(旋轉90度或在其他方向),而在此使用的空間相對性描述也可以相同方式解讀。 The use of spatially relative terms is to describe the different orientations of components during use or operation, and is not limited to the orientation depicted in the drawings. The components may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted in the same manner.
為了簡化和明確說明,本文可能會在各種實施例中重複使用元件符號和/或字母,但這並不表示所討論的各種實施例及/或配置之間有因果關係。此外,在圖式描述中,相似元件可具有與先前圖式的名稱和標號相似的名稱和標號。後續圖式利用不同文脈或不同功能的元件時,此元件可具有不同的高位數字,以代表不同圖號(例如,圖1的1xx和圖4的2xx)。分配予各元件的特定標號僅用以幫助說明,而不意欲暗示任何結構或功能上的限制。 For simplicity and clarity, element symbols and/or letters may be repeated in various embodiments herein, but this does not imply a causal relationship between the various embodiments and/or configurations discussed. Furthermore, in the description of the figures, similar elements may have names and numbers similar to those of previous figures. When subsequent drawings use components with different contexts or different functions, the components may have different high-digit numbers to represent different drawing numbers (for example, 1xx in Figure 1 and 2xx in Figure 4). The specific reference numerals assigned to various components are merely to aid in description and are not intended to imply any structural or functional limitations.
圖1為依據本發明實施例之薄膜晶片電阻電容100的剖視圖。薄膜晶片電阻電容100包含基材102、電阻層104、下電極106A、106B、第一介質層108、第一上電極112A、112B、第二介質層114、第二上電極116A1、116B1、電極分支116A2、116B2、保護層118和側電極122A、122B。基材102可以是例如氧化鋁基材、陶瓷基材或其他合適的絕緣基材。電阻層104和下電極106A、106B分別設置於基材102的上側、左下側和
右下側,其中電阻層104為薄膜合金箔片,其可包含例如銀銅合金、鎳鉻銅合金、鎳鉻矽合金、錳銅合金、鎳銅合金和/或其他具類似特性的合金材料,而下電極106A、106B可包含例如銅、銀和/或其他合適的導電金屬材料。
FIG. 1 is a cross-sectional view of a thin film chip resistor and
第一介質層108和第一上電極112A、112B設置於電阻層104上。第一介質層108可包含例如樹脂、環氧樹脂、苯並環丁烯(Benzocyclobutene;BCB)、聚四氟乙烯(Polytetrafluoroethylene;PTFE)、聚醯亞胺(Polyimide;PI)、五氧化二鉭(Ta2O5)、氮化鉭(TaN)、二氧化鈦(TiO2)或其他合適的介面絕緣材料。第一上電極112A、112B分別位於第一介質層108的左右兩側,且可包含例如銅、銀和/或其他合適的導電金屬材料。
The
第二介質層114、第二上電極116A1、116B1和電極分支116A2、116B2設置於第一介質層108和第一上電極112A、112B上。第二介質層114覆蓋電極分支116A2、116B2,且也可包含例如樹脂、環氧樹脂、苯並環丁烯、聚四氟乙烯、聚醯亞胺、五氧化二鉭、氮化鉭、二氧化鈦或其他合適的介面絕緣材料。第二上電極116A1、116B1分別位於第二介質層114的左右兩側,且分別接觸第一上電極112A、112B。電極分支116A2、116B2均位於第二上電極116A1、116B1之間,且分別耦接第二上電極116A1、116B1。此外,第二上電極116A1和電極分支116A2的組成與第二上電極116B1和電極分支
116B2的組成分別為兩相對的電容電極。由於此些電容電極為實體分離,且第二上電極116A1、116B1和電極分支116A2、116B2彼此之間具有由第二介質層114填滿的間隔,故第二上電極116A1和電極分支116A2可與第二上電極116B1和電極分支116B2互相作用而構成薄膜電容層。同樣地,第二上電極116A1、116B1和電極分支116A2、116B2也可包含例如銅、銀和/或其他合適的導電金屬材料。
The
保護層118設置於第二介質層114、第二上電極116A1、116B1和電極分支116A2、116B2上,且覆蓋第二介質層114和電極分支116A2、116B2,以更進一步保護電極分支116A2、116B2和電阻層104等下方元件。保護層118可包含樹脂、環氧樹脂、油墨、苯並環丁烯、聚醯亞胺、防焊光阻和/或其他合適材料。
The
側電極122A延伸設置於下電極106A、基材102的左側邊、電阻層104的左側邊、第一上電極112A的左側邊和第二上電極116A1上,且耦接電阻層104、第二上電極116A1和電極分支116A2。側電極122B延伸設置於下電極106B、基材102的右側邊、電阻層104的右側邊、第一上電極112B的右側邊和第二上電極116B1上,且耦接電阻層104、第二上電極116B1和電極分支116B2。具體而言,側電極122A的一端設置於第二上電極116A1上且覆蓋第二上電極116A1和保護層118的一部分,並依序沿著第一上電極112A、電阻層104和基
材102的左側邊而延伸至下電極106A,使得其另一端覆蓋下電極106A。相似地,側電極122B的一端設置於第二上電極116B1上且覆蓋第二上電極116B1和保護層118的一部分,並依序沿著第一上電極112B、電阻層104和基材102的右側邊而延伸至下電極106B,使得其另一端覆蓋下電極106B。側電極122A、122B也可包含例如銅、銀和/或其他合適的導電金屬材料。在一些實施例中,側電極122A、122B的外側可再鍍上例如錫、鎳等金屬薄膜層。
The
在本實施例中,下電極106A、第一上電極112A、第二上電極116A1和側電極122A構成端電極110A,且下電極106B、第一上電極112B、第二上電極116B1和側電極122B構成端電極110B。端電極110A、110B分別設置於基材102的兩對向側邊,且用以作為耦接外部電路的接點。
In this embodiment, the
薄膜晶片電阻電容100相當於並聯電阻-電容電路。圖2為圖1之薄膜晶片電阻電容100的等效電路圖。圖2所示之等效電路圖包含彼此並聯的電阻R和電容C以及分別耦接電阻R和電容C相對兩側的第一端T1和第二端T2,其中電阻R對應電阻層104,電容C對應第二上電極116A1、116B1和電極分支116A2、116B2,而第一端T1和第二端T2分別對應端電極110A、110B。
The thin film
圖3為圖2之電容C的平面結構的一示例。電容C包含相對的兩電容電極CA、CB,其中電容電極CA具 有多個電極分支CAa,而電容電極CB具有多個電極分支CBa,且電極分支CAa、CBa彼此交錯排列。電容電極CA、CB均為梳狀,且電極分支CAa、CBa可分別對應圖1之電極分支116A2、116B2。圖1繪示之梳狀電極和圖3繪示之電極分支CAa、CBa僅為示例,其個數可依設計需求調整。 FIG. 3 is an example of the planar structure of the capacitor C in FIG. 2 . The capacitor C includes two opposite capacitor electrodes CA and CB, in which the capacitor electrode CA has There are multiple electrode branches CAa, and the capacitive electrode CB has multiple electrode branches CBa, and the electrode branches CAa and CBa are staggered with each other. The capacitor electrodes CA and CB are both comb-shaped, and the electrode branches CAa and CBa can respectively correspond to the electrode branches 116A2 and 116B2 in Figure 1 . The comb-shaped electrodes shown in Figure 1 and the electrode branches CAa and CBa shown in Figure 3 are only examples, and their numbers can be adjusted according to design requirements.
圖4為依據本發明另一實施例之薄膜晶片電阻電容200的剖視圖。薄膜晶片電阻電容200包含基材202、電阻層204、下電極206A1、206B1、下電極分支206A2、206B2、第一介質層208、第一上電極212A、212B、第二介質層214、第二上電極216A1、216B1、上電極分支216A2、216B2、保護層218、側電極222A、222B和第三介質層224。相較於圖1之薄膜晶片電阻電容100,在圖4之薄膜晶片電阻電容200中,基材202的下方另具有下電極分支206A2、206B2和第三介質層224,其中下電極分支206A2、206B2分別耦接下電極206A1、206B1,而第三介質層224覆蓋下電極分支206A2、206B2。第三介質層224也可包含例如樹脂、環氧樹脂、苯並環丁烯、聚四氟乙烯、聚醯亞胺、五氧化二鉭、氮化鉭、二氧化鈦或其他合適的介面絕緣材料。下電極分支206A2、206B2均位於下電極206A1、206B1之間,且分別耦接下電極206A1、206B1。此外,下電極206A1和下電極分支206A2的組成與下電極206B1和下電極分支206B2的組成分別為兩相對的電容電極。由於此些電容
電極為實體分離,且下電極206A1、206B1和下電極分支206A2、206B2彼此之間具有由第三介質層224填滿的間隔,故下電極206A1和下電極分支206A2可與下電極206B1和下電極分支206B2互相作用而構成薄膜電容層。下電極206A1和下電極分支206A2之組合與下電極206B1和下電極分支206B2之組合也可分別具有如圖3所示之電容電極CA、CB的梳狀結構,其中下電極分支206A2、下電極分支206B2分別對應電極分支CAa、CBa。同樣地,下電極分支206A2、206B2也可包含例如銅、銀和/或其他合適的導電金屬材料。
FIG. 4 is a cross-sectional view of a thin film chip resistor and
基材202、電阻層204、下電極206A1、206B1、第一介質層208、端電極210A、210B、第一上電極212A、212B、第二介質層214、第二上電極216A1、216B1、上電極分支216A2、216B2、保護層218和側電極222A、222B可分別與圖1之基材102、電阻層104、下電極106A、106B、第一介質層108、端電極110A、110B、第一上電極112A、112B、第二介質層114、第二上電極116A1、116B1、電極分支116A2、116B2、保護層118和側電極122A、122B相同或相似,故相關說明請參照先前段落,在此不重複敘述。
薄膜晶片電阻電容200相當於並聯電阻-電容電路。圖5為圖4之薄膜晶片電阻電容200的等效電路圖。圖5所示之等效電路圖包含彼此並聯的電阻R和電容C1、C2以及分別耦接電阻R和電容C1、C2相對兩側的第一
端T1和第二端T2,其中電阻R對應電阻層204,電容C1對應第二上電極216A1、216B1和上電極分支216A2、216B2,電容C2對應下電極206A1、206B1和下電極分支206A2、206B2,而第一端T1和第二端T2分別對應端電極210A、210B。由於薄膜晶片電阻電容200的上下兩側均具有薄膜電容層的設計,故可進一步增加其電容值。
The thin film
圖6A至圖6F為製作圖4之薄膜晶片電阻電容200的各階段剖視圖。首先,如圖6A所示,提供基材202,並在基材202上形成電阻層204。電阻層204可依據其材料種類,藉由貼合、印刷或例如濺鍍等物理氣相沉積的方式來形成於基材202上。
6A to 6F are cross-sectional views of various stages of manufacturing the thin film chip resistor and
接著,如圖6B所示,在電阻層204上形成第一上電極212A、212B,且在基材202之相對於電阻層204的一側上形成下電極206A1、206B1和下電極分支206A2、206B2。下電極206A1、206B1、下電極分支206A2、206B2和第一上電極212A、212B可由下列方式形成。首先,使用例如濺鍍或薄膜貼合方式在基材202上和在電阻層204上分別形成導電層,接著再以黃光微影和蝕刻等製程對形成的導電層進行圖案化以移除不需要的部分,接著再進行電鍍製程,如此便形成下電極206A1、206B1、下電極分支206A2、206B2和第一上電極212A、212B。黃光微影和蝕刻等製程可在各處進行不同厚度材料的去除,使得下電極分支206A2、206B2的厚度小於下
電極206A1、206B1的厚度。在其他實施例中,下電極206A1、206B1、下電極分支206A2、206B2和第一上電極212A、212B可藉由印刷方式形成。
Next, as shown in FIG. 6B , first
之後,如圖6C所示,在電阻層204之未被第一上電極212A、212B覆蓋的部分上形成第一介質層208,且在基材202之未被下電極206A1、206B1覆蓋的部分上形成第三介質層224。第一介質層208和第三介質層224可依據其材料藉由例如塗佈、光阻乾膜壓合或印刷技術形成。形成的第一介質層208的頂部可與第一上電極212A、212B的頂部共平面,且形成的第三介質層224的頂部可與下電極206A1、206B1的頂部共平面。
After that, as shown in FIG. 6C , the
接著,如圖6D所示,在第一介質層208和第一上電極212A、212B上形成第二上電極216A1、216B1和上電極分支216A2、216B2,且接著在第二上電極216A1、216B1之間形成覆蓋上電極分支216A2、216B2的第二介質層214。第二上電極216A1、216B1、上電極分支216A2、216B2和第二介質層214可由下列方式形成。首先,使用例如濺鍍或薄膜貼合方式在第一介質層208和第一上電極212A、212B上形成導電層,接著再以黃光微影和蝕刻等製程對形成的導電層進行圖案化以移除不需要的部分,接著再進行電鍍製程,如此便形成第二上電極216A1、216B1和上電極分支216A2、216B2。黃光微影和蝕刻等製程可在各處進行不同厚度材料的去除,使得上電極分支216A2、216B2的厚度小於
第二上電極216A1、216B1的厚度。在其他實施例中,第二上電極216A1、216B1和上電極分支216A2、216B2可藉由印刷方式形成。第二介質層214可依據其材料藉由例如塗佈、光阻乾膜壓合或印刷技術形成。形成的第二介質層214的頂部可低於或等高於第二上電極216A1、216B1的頂部,且可高於或等高於上電極分支216A2、216B2的頂部。
Next, as shown in FIG. 6D , second upper electrodes 216A1 and 216B1 and upper electrode branches 216A2 and 216B2 are formed on the
之後,如圖6E所示,在第二介質層214和第二上電極216A1、216B1上形成保護層218。形成的保護層218覆蓋第二介質層214、上電極分支216A2、216B2和部分的第二上電極216A1、216B1。保護層218可依據其材料藉由例如塗佈、光阻乾膜壓合或印刷技術形成。
Afterwards, as shown in FIG. 6E , a
接著,如圖6F所示,在基材202、電阻層204、下電極206A1、第一上電極212A和第二上電極216A1的左側邊形成側電極222A,且在基材202、電阻層204、下電極206B1、第一上電極212B和第二上電極216B1的右側邊形成側電極222B。側電極222A、222B可藉由濺鍍方式分別形成於基材202和電阻層204的左右兩側且向上下兩側延伸至保護層218和第三介質層224並覆蓋第二上電極216A1、216B1和下電極206A1、206B1。在一些實施例中,可在側電極222A、222B的外側再鍍上例如錫、鎳等金屬薄膜層。
Next, as shown in FIG. 6F , a
圖1之薄膜晶片電阻電容100也可以相似於上述段落結合圖6A至圖6F繪示內容製作。由於薄膜晶片電阻
電容100的電容電極僅在基材102的單側,故不需在基材102之相對於電阻層104的另一側上形成電極分支和介質層;其餘各元件的製作步驟可與圖6A至圖6F繪示內容相同,故在此不重複說明。
The thin film chip resistor and
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.
100:薄膜晶片電阻電容 100:Thin film chip resistor and capacitor
102:基材 102:Substrate
104:電阻層 104:Resistance layer
106A,106B:下電極 106A, 106B: Lower electrode
108:第一介質層 108: First dielectric layer
110A,110B:端電極 110A, 110B: terminal electrode
112A,112B:第一上電極 112A, 112B: first upper electrode
114:第二介質層 114: Second dielectric layer
116A1,116B1:第二上電極 116A1, 116B1: second upper electrode
116A2,116B2:電極分支 116A2, 116B2: Electrode branch
118:保護層 118:Protective layer
122A,122B:側電極 122A, 122B: Side electrode
Claims (10)
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CN105070504A (en) * | 2015-07-22 | 2015-11-18 | 广东欧珀移动通信有限公司 | Resistor-capacitor integrated device |
CN106340387A (en) * | 2016-09-30 | 2017-01-18 | 广东风华高新科技股份有限公司 | Chip type composite component and preparation method thereof |
CN110060868A (en) * | 2015-12-28 | 2019-07-26 | 三星电机株式会社 | Dielectric combination and multilayer ceramic capacitor comprising the dielectric combination |
TW202013401A (en) * | 2018-09-21 | 2020-04-01 | 矽品精密工業股份有限公司 | Line circuit capacitance structure |
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CN105070504A (en) * | 2015-07-22 | 2015-11-18 | 广东欧珀移动通信有限公司 | Resistor-capacitor integrated device |
CN110060868A (en) * | 2015-12-28 | 2019-07-26 | 三星电机株式会社 | Dielectric combination and multilayer ceramic capacitor comprising the dielectric combination |
CN106340387A (en) * | 2016-09-30 | 2017-01-18 | 广东风华高新科技股份有限公司 | Chip type composite component and preparation method thereof |
TW202013401A (en) * | 2018-09-21 | 2020-04-01 | 矽品精密工業股份有限公司 | Line circuit capacitance structure |
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