TWI822337B - Semiconductor structure and fabrication method thereof - Google Patents

Abstract

A semiconductor structure includes a first inter-metal dielectric layer disposed above a substrate and a first wire layer disposed in the first inter-metal dielectric layer. A second inter-metal dielectric layer is disposed on the first inter-metal dielectric layer, and a thin film resistor is disposed in the second inter-metal dielectric layer. A first via is located directly above the first wire layer and extends downward from the top surface of the second inter-metal dielectric layer by a first depth. A second via passes through the thin film resistor and extends downward from the top surface of the second inter-metal dielectric layer by a second depth, where the second depth is greater than or equal to the first depth. There is no patterned portion directly below a vertically projected area of the thin film resistor.

Description

Semiconductor structures and manufacturing methods

The present disclosure relates to semiconductor manufacturing techniques, and in particular to semiconductor structures including thin film resistors and methods of manufacturing the same.

In many analog circuits, such as active filters, resistor string digital-to-analog converters, bandgap reference circuits, instrument amplifiers, etc., thin film resistors are usually integrated. Thin film resistors have a low temperature coefficient of resistance ( temperature coefficient of resistance (TCR), has become an important component in analog circuits.

Thin film resistors are formed by depositing thin film resistive materials on a substrate and subjecting the thin film resistive materials to a patterning process. However, since the thin film resistor is integrated into the semiconductor device, the electrical properties of the thin film resistor are easily affected by various semiconductor processes and various components in the semiconductor device. The electrical properties of the thin film resistor will affect the performance of the analog circuit. Have a great impact. Therefore, how to integrate thin film resistors into semiconductor devices and maintain the electrical properties of the thin film resistors is an issue that requires urgent research.

In view of this, the present disclosure proposes a semiconductor structure and a manufacturing method thereof. The structure contains a thin film resistor with no patterned areas, such as etch stop layers, metal layers, semiconductor layers, or combinations thereof, directly below the vertical projected area of the thin film resistor, within the intermetallic dielectric layer to improve the flatness of the thin film resistor. degree, thereby achieving the effect of reducing the resistance value mismatch of the thin film resistor and improving the resistance value stability of the thin film resistor, so that the electrical properties of the thin film resistor integrated in the semiconductor device can comply with the integrated circuit requirements.

According to an embodiment of the present disclosure, a semiconductor structure is provided, including a substrate, a first inter-metal dielectric layer, a first conductive line layer, a second inter-metal dielectric layer, a thin film resistor, a first via hole and a second via hole. . The first inter-metal dielectric layer is disposed above the substrate, the first conductor layer is disposed in the first inter-metal dielectric layer, the second inter-metal dielectric layer is disposed on the first inter-metal dielectric layer, and the thin film resistor is disposed on In the second inter-metal dielectric layer, the first via hole is located directly above the first conductor layer and extends downward from the top surface of the second inter-metal dielectric layer to a first depth, the second via hole passes through the thin film resistor, and A second depth extends downwardly from the top surface of the second inter-metal dielectric layer, wherein the second depth is greater than or equal to the first depth and there is no patterned area directly below the vertically projected area of the thin film resistor.

According to an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, including the following steps: providing a substrate; forming a first conductive layer above the substrate; depositing a first inter-metal dielectric layer to cover the first conductive layer; Forming a thin film resistor on an inter-metal dielectric layer; depositing a second inter-metal dielectric layer to cover the thin film resistor; forming a first hole directly above the first conductor layer, and forming a second hole through the thin film resistor, The first hole and the second hole are formed by the same etching process; a first via hole is formed in the first hole, and a second via hole is formed in the second hole.

In order to make the features of the present disclosure clear and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

100, 200: Semiconductor structure

101: Base

103:Transistor

105: Doped area

107: Gate

108: Via hole

109: Interlayer dielectric layer

110: First inter-metal dielectric layer

111: First wire layer

113: Silicon oxide layer

115:Thin film resistor

117:Anti-reflective layer

119: Etch stop layer

120: Second inter-metal dielectric layer

121: Second wire layer

130:Vertical projection area

131: First via hole

132: Second via hole

140:Patterned photoresist layer

141:First opening

142:Second opening

151:The first hole

152:Second hole

T1: first depth

T2: Second depth

In order to make the following easier to understand, the drawings and their detailed text descriptions may be referred to simultaneously when reading this disclosure. Through the specific embodiments in this article and with reference to the corresponding drawings, the specific embodiments of the present disclosure are explained in detail, and the working principles of the specific embodiments of the present disclosure are explained. In addition, features in the drawings may not be drawn to actual scale for the sake of clarity, and therefore the dimensions of some features in some drawings may be intentionally exaggerated or reduced.

FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present disclosure.

FIGS. 2 , 3 and 4 are schematic cross-sectional views of some stages of a manufacturing method of a semiconductor structure according to an embodiment of the present disclosure.

FIG. 5 is a bar graph of resistance values of thin film resistors according to some embodiments of the present disclosure.

FIG. 6 is a graph of resistance value mismatch of thin film resistors according to some embodiments of the present disclosure.

FIG. 7 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure.

The present disclosure provides several different embodiments that can be used to implement different features of the disclosure. To simplify explanation, examples of specific components and arrangements are also described in this disclosure. These examples are provided for illustrative purposes only and are not intended to be limiting in any way. For example, the following description of "the first feature is formed on or above the second feature" may mean "the first feature is in direct contact with the second feature" or "the first feature is in direct contact with the second feature". "There are other features between the features", so that the first feature and the second feature are not in direct contact. Additionally, various embodiments in the present disclosure may use repeated reference symbols and/or textual notations. These repeated reference symbols and notations are used to make the description more concise and clear, but are not used to indicate the correlation between different embodiments and/or configurations.

In addition, for the space-related descriptive words mentioned in this disclosure, such as: "under", "low", "lower", "above", "above", "upper", "top" "," bottom" and similar words, for convenience In the description, its usage is to describe the relative relationship between one element or feature and another (or more) elements or features in the drawings. In addition to the orientations shown in the drawings, these spatially related terms are also used to describe possible orientations of the semiconductor device during use and operation. As the semiconductor device is oriented differently (rotated 90 degrees or other orientations), the spatially related description used to describe its orientation should be interpreted in a similar manner.

Although this disclosure uses terms such as first, second, third, etc. to describe various elements, components, regions, layers, and/or sections, it should be understood that these elements, components, regions, layers, and/or blocks should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and/or block from another element, component, region, layer, and/or block, and do not themselves imply or represent the element. There is no previous serial number, nor does it represent the order of arrangement of one component with another component, or the order of the manufacturing method. Therefore, a first element, component, region, layer, or block discussed below may also be termed a second element, component, region, layer, or block without departing from the scope of the specific embodiments of the disclosure. Of.

The terms "about" or "substantially" used in this disclosure generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range, or Within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, even without specifically stating "approximately" or "substantially", the meaning of "approximately" or "substantially" may still be implied.

The terms "coupling", "coupling" and "electrical connection" mentioned in this disclosure include any direct and indirect electrical connection means. For example, if a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connections.

Although the invention of the present disclosure is described below through specific embodiments, the inventive principles of the present disclosure can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, Certain details have been omitted which are within the scope of the knowledge of a person of ordinary skill in the art.

The present disclosure relates to semiconductor structures and methods of fabricating the same. Embodiments of the present disclosure do not provide patterned areas, such as etch stops, directly below the vertical projection area of thin film resistors included in the semiconductor structure, at least within the inter-metal dielectric layer. layer, metal layer, semiconductor layer or a combination of the above, thereby improving the flatness of the thin film resistor, reducing the resistance value mismatch of the thin film resistor, and improving the resistance value stability of the thin film resistor. , so that the electrical properties of thin film resistors integrated in semiconductor devices can meet the requirements of integrated circuits.

In addition, according to embodiments of the present disclosure, a via electrically coupled to the thin film resistor and another via electrically coupled to the conductive layer located below the thin film resistor can be manufactured simultaneously without adding a photomask. quantity and other processes to achieve the effect of saving manufacturing costs.

Figure 1 is a schematic cross-sectional view of a semiconductor structure 100 according to an embodiment of the present disclosure. The semiconductor structure 100 includes a substrate 101, such as a semiconductor substrate or other suitable substrate. In some embodiments, a plurality of elements may be formed in the substrate 101. a transistor 103 and/or other electronic components. Transistor 103 may include doped regions 105, such as source/drain regions, formed in substrate 101, and gate 107, such as a polysilicon gate, formed on substrate 101. In addition, an inter-layer dielectric layer (ILD) 109 is formed on the substrate 101 to cover the gate 107 and the surface of the substrate 101. The composition of the inter-layer dielectric layer 109 may be silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric material. A via 108 is formed in the interlayer dielectric layer 109 . The via 108 may be made of tungsten, aluminum, copper or other conductive materials. The via 108 is electrically coupled to the gate 107 . After that, a first conductor layer 111 is formed on the interlayer dielectric layer 109. The first conductor layer 111 can also be called a first metal layer, which is a part of the interconnection structure. The composition of the first conductor layer 111 can be aluminum or copper. or other suitable conductive metal materials, the via holes 108 in the interlayer dielectric layer 109 are electrically coupled to the first conductive layer 111 .

Still referring to Figure 1, a first metal interlayer dielectric layer is formed on the interlayer dielectric layer 109. (inter-metal dielectric layer, IMD) 110 to cover the first conductor layer 111. In some embodiments, the composition of the first inter-metal dielectric layer 110 is, for example, fluorosilicate glass (FSG), which can be deposited through a deposition process, such as plasma enhanced chemical vapor deposition. The first inter-metal dielectric layer 110 is formed by a PECVD) process and/or a high-density plasma chemical vapor deposition (HDPCVD) process. In one embodiment, in order to improve the surface flatness of the first inter-metal dielectric layer 110, a chemical mechanical planarization (CMP) process may be performed after depositing the first inter-metal dielectric layer 110. In another embodiment, a low pressure chemical vapor deposition (LPCVD) process may be used to form the silicon-containing oxide layer 113 on the first inter-metal dielectric layer 110, such as a silicon-rich oxide layer ( silicon-rich oxide (SRO) to repair the surface of the CMP-processed first inter-metal dielectric layer 110 , which facilitates the subsequent formation of the thin-film resistor 115 on the first inter-metal dielectric layer 110 .

Continuing to refer to FIG. 1 , a thin film resistor 115 and an anti-reflective layer 117 are formed on the first inter-metal dielectric layer 110 (or on the silicon-containing oxide layer 113 ). In some embodiments, the composition of the thin film resistor 115 may be silicon chromium (SiCr), nickel chromium (NiCr); or alloy derivatives of silicon chromium (SiCr), such as silicon chromium carbide (SiCCr), silicon chromium oxide (CrSiO ), silicon chromium nitride (CrSiN), silicon chromium doped with carbon and oxygen (SiCrCO); or alloy derivatives of nickel chromium (NiCr), such as carbon and oxygen doped nickel chromium (NiCrCO), aluminum nickel chromium ( AlNiCr), titanium nickel chromium (TiNiCr); other resistance materials, such as tantalum nitride (TaN), titanium nitride (TiN), tantalum silicide (Ta ₂ Si), titanium silicide (SiTi ₂ ); or other suitable Metal materials, such as tungsten (W), molybdenum (Mo), gold (Au), silver (Ag), etc. The thickness of the thin film resistor 115 is typically less than 1 micrometer (μm), for example, about 50 Å to 5000 Å, depending on the electrical requirements of the thin film resistor 115 and the location in which the thin film resistor 115 is integrated. The thickness of the thin film resistor 115 is determined by the size of the semiconductor device. In addition, the resistance value of the thin film resistor 115 is determined by its thickness, width and length, and the thickness, width and length can be adjusted according to the resistance value of the thin film resistor 115 required by the integrated circuit. The composition of the anti-reflective layer 117 is, for example, silicon oxynitride (SiON). The anti-reflective layer 117 on the thin film resistor 115 facilitates the photolithography process of forming the thin film resistor 115, making the pattern and size of the thin film resistor 115 more precise. for precision.

Continuing to refer to FIG. 1 , in this implementation, a second inter-metal dielectric layer 120 is formed on the first inter-metal dielectric layer 110 and the silicon-containing oxide layer 113 to cover the thin film resistor 115 and the anti-reflection layer 117 , the composition of the second inter-metal dielectric layer 120 is, for example, silicon oxide. In addition, according to the embodiment of the present disclosure, the semiconductor structure 100 is provided with a first via 131 directly above the first conductive line layer 111, and is also provided with a second via 132 penetrating the thin film resistor 115. The via hole 131 extends downwardly from the top surface of the second inter-metal dielectric layer 120 to a first depth T1. The first via hole 131 passes through the second inter-metal dielectric layer 120, the silicon-containing oxide layer 113 and part of the first The inter-metal dielectric layer 110 reaches the top surface of the first conductive layer 111. In some embodiments, an etching stop layer can be formed on the top surface of the first conductive layer 111, and the bottom surface of the first via hole 131 can be contact etched. The top surface of the stop layer may be located in the etch stop layer. The second via hole 132 extends downwardly from the top surface of the second inter-metal dielectric layer 120 to a second depth T2. According to some embodiments of the present disclosure, the second depth T2 may be greater than or equal to 1 to 1.5 times the first depth T1. Since in the embodiment of the present disclosure, there is no patterned area directly below the vertical projection area of the thin film resistor 115, compared with the etching of the hole to form the first via hole 131, the first conductive line layer 111 and the etching thereon will be affected. The etching stop layer blocks, and the etching of the hole forming the second via hole 132 is not blocked by the patterned block. Therefore, the second depth T2 of the second via hole 132 can be greater than or equal to the first depth of the first via hole 131 1 to 1.5 times that of T1.

In some embodiments, the second depth T2 can be adjusted to the first depth by controlling the parameters of the etching process for forming the first via hole 131 and the second via hole 132 , such as controlling the usage amount of etchant and the etching time. T1 is substantially the same. As shown in FIG. 1 , the bottom surface of the first via hole 131 and the bottom surface of the second via hole 132 may be at the same level, and the second via hole 132 passes through the second inter-metal dielectric layer 120 , the anti-reflection layer 117, the thin film resistor 115, the silicon-containing oxide layer 113 and part of the first inter-metal dielectric layer 110, reach the first inter-metal dielectric layer 110, so that the bottom surface of the second via hole 132 is A first inter-metal dielectric layer 110 surrounds. In other embodiments, the second depth T2 is greater than the first depth T1, the bottom surface of the first via hole 131 and the bottom surface of the second via hole 132 are not at the same level, and the second via hole 132 is not at the same level. The through hole 132 passes through the second inter-metal dielectric layer 120, the anti-reflection layer 117, the thin film resistor 115, the silicon-containing oxide layer 113, the first inter-metal dielectric layer 110 and part of the inter-layer dielectric layer 109, to reach In the interlayer dielectric layer 109 , the bottom surface of the second via hole 132 is surrounded by the interlayer dielectric layer 109 .

Furthermore, according to embodiments of the present disclosure, within the vertically projected area 130 of the thin film resistor 115, at least within the first intermetal dielectric layer 110 directly below the thin film resistor 115, there are no patterned areas, such as no etching. The stop layer, the metal layer (such as the first conductor layer 111 or other metal patterns), the semiconductor layer (such as the polysilicon pattern) or a combination of the above improves the flatness of the thin film resistor 115 to improve the electrical properties of the thin film resistor 115 Performance, such as improving resistance value stability and reducing resistance value mismatch. In some embodiments, in the vertically projected area 130 of the thin film resistor 115, there are no patterned areas in the interlayer dielectric layer 109 directly below the thin film resistor 115, such as no etch stop layer, metal layer ( For example, other wires and/or electrodes), semiconductor layers (such as polysilicon patterns), gates 107 or a combination thereof, the flatness of the thin film resistor 115 is improved to enhance the electrical performance of the thin film resistor 115 . In other embodiments, the interlayer dielectric layer 109 directly below the thin film resistor 115 within the vertically projected area 130 of the thin film resistor 115 may have patterned areas, such as an etch stop layer, a metal layer (eg, a conductive line, and a metal layer). /or electrode), semiconductor layer (such as polysilicon pattern), gate 107, etc., but because at least the first inter-metal dielectric layer 110 is separated between the interlayer dielectric layer 109 and the thin film resistor 115, and these patterned areas The blocks will be covered by the interlayer dielectric layer 109, so the flatness of the thin film resistor 115 is less affected by the patterned blocks in the interlayer dielectric layer 109, so that the electrical properties of the thin film resistor 115 will not be greatly affected.

Still referring to FIG. 1 , a second conductive layer 121 is formed on the top surface of the second inter-metal dielectric layer 120 , and the first via hole 131 is electrically connected to the second conductive layer 121 and the first conductive layer 111 . The hole 132 is electrically connected to the second conductive line layer 121 and the thin film resistor 115, and the bottom surface of the second via hole 132 is not electrically coupled to the first conductive line layer 111 and other conductive layers.

FIGS. 2 , 3 and 4 are schematic cross-sectional views of some stages of a manufacturing method of a semiconductor structure according to an embodiment of the present disclosure. Referring to Figure 2, first a substrate 101 is provided, such as a semiconductor A substrate, in which a plurality of transistors 103 and/or other electronic components may be formed. The transistors 103 may include doped regions 105 formed in the substrate 101 , such as source/drain regions, and formed on the substrate 101 The gate 107 is, for example, a polycrystalline silicon gate. An interlayer dielectric layer (ILD) 109 is formed on the substrate 101 to cover the gate 107 and the surface of the substrate 101 , and a via hole 108 is formed in the interlayer dielectric layer 109 . The hole of the via hole 108 can be formed in the interlayer dielectric layer 109 through photolithography and etching processes. In some embodiments, an etch stop layer can be formed on the gate 107 so that the etching of the hole stops on the etch stop layer. Conductive material is then deposited to fill the holes to form vias 108 . After that, a first conductor layer 111 is formed on the interlayer dielectric layer 109. The first conductor layer 111 can also be called a first metal layer, which is a part of the interconnection structure. The first conductive layer 111 may be formed through deposition, photolithography, and etching processes, and the via hole 108 in the interlayer dielectric layer 109 is electrically coupled to the gate 107 and the first conductive layer 111 .

Still referring to FIG. 2 , after that, a first metal interlayer dielectric layer 110 is deposited on the interlayer dielectric layer 109 to cover the first conductive line layer 111 , which may be through a plasma enhanced chemical vapor deposition (PECVD) process and/or high The first inter-metal dielectric layer 110 is formed through a density plasma chemical vapor deposition (HDPCVD) process. In addition, in one embodiment, in order to improve the surface flatness of the first inter-metal dielectric layer 110 , a chemical mechanical planarization (CMP) process may be performed after depositing the first inter-metal dielectric layer 110 . In another embodiment, a silicon-containing oxide layer 113 may be formed on the first inter-metal dielectric layer 110 using a low-pressure chemical vapor deposition (LPCVD) process to repair the CMP-processed first inter-metal dielectric layer. 110, which facilitates the subsequent formation of the thin film resistor 115 on the first inter-metal dielectric layer 110.

Still referring to FIG. 2 , a thin film resistor material layer is deposited on the first inter-metal dielectric layer 110 and the silicon-containing oxide layer 113 by using a physical vapor deposition (PVD) process, such as sputtering (sputter). A process is used to deposit a thin film resistive material layer, and then another sputtering process is used to deposit an anti-reflective material layer on the thin film resistive material layer, and then the anti-reflective material layer and the thin film resistive material layer are patterned together through photolithography and etching processes. To form the thin film resistor 115 and the anti-reflection layer 117. Forming the anti-reflective material layer on the thin film resistor material layer facilitates the photolithography process of the thin film resistor material layer, making the formed The pattern and dimensions of the resulting thin film resistor 115 are more precise. Afterwards, a second inter-metal dielectric layer 120 is formed on the first inter-metal dielectric layer 110 and the silicon-containing oxide layer 113 to cover the thin film resistor 115 and the anti-reflection layer 117 . The second inter-metal dielectric layer 120 can be deposited using a plasma enhanced chemical vapor deposition (PECVD) process, and an annealing process is performed after the deposition process to make the material of the second inter-metal dielectric layer 120 denser. As shown in Figure 2, according to an embodiment of the present disclosure, a patterned photoresist layer 140 is formed on the second inter-metal dielectric layer 120, which has a first opening 141 corresponding to directly above the first conductive layer 111. and a second opening 142 corresponding to directly above the thin film resistor 115 .

Then, referring to FIG. 3 , the patterned photoresist layer 140 in FIG. 2 is used as an etching mask, and an etching process, such as a dry etching or wet etching process, is used. The etching gas or etchant passes through the first part of the patterned photoresist layer 140 . The opening 141 forms a first hole 151 in the second inter-metal dielectric layer 120, the silicon-containing oxide layer 113 and the first inter-metal dielectric layer 110, which is located directly above the first conductive layer 111 and has a first depth. T1, while the etching gas or etchant passes through the second opening 142 of the patterned photoresist layer 140, the second inter-metal dielectric layer 120, the anti-reflective layer 117, the thin film resistor 115, the silicon-containing oxide layer 113 and the first A second hole 152 is formed in the inter-metal dielectric layer 110 and passes through the thin film resistor 115 and has a second depth T2. In some embodiments, as shown in FIG. 3 , the bottom surface of the second hole 152 and the bottom surface of the first hole 151 are at the same level, that is, the second depth T2 may be substantially equal to the first depth T1 . In other embodiments, the bottom surface of the second hole 152 may be lower than the bottom surface of the first hole 151 , that is, the second depth T2 may be greater than or equal to 1 to 1.5 times of the first depth T1 , depending on the formation of the first hole. 151 and the etching process parameters of the second hole 152, as well as the materials of each stacked layer in the vertical projection area 130 (as shown in FIG. 1) of the thin film resistor 115.

After that, referring to Figure 4, a physical vapor deposition (PVD) process can be used to form a diffusion barrier layer (conformally) on the inner walls of the first hole 151 and the second hole 152. The material of the diffusion barrier layer is, for example, titanium (Ti), titanium nitride (TiN), a combination of the above, or other suitable barrier materials. Then, another physical vapor deposition (PVD) process is used to deposit a conductive material to fill the first holes 151 and the second holes 152, and to be deposited on the top surface of the second inter-metal dielectric layer 120. On the surface, the composition of the conductive material is, for example, tungsten (W), copper (Cu) or aluminum (Al). After that, a chemical mechanical planarization (CMP) process is used to remove the conductive material outside the first hole 151 and the second hole 152 to form the first via hole 131 and the second via hole 132 at the same time, and the top of the first via hole 131 is The surface and the top surface of the second via hole 132 are on the same plane. Then, a second conductor layer 121 as shown in FIG. 1 is formed on the second inter-metal dielectric layer 120 to complete the semiconductor structure 100 .

According to embodiments of the present disclosure, the second via hole 132 and the first via hole 131 may be formed simultaneously through the same photolithography process and the same etching process, as well as the same deposition process and the same chemical mechanical planarization (CMP) process. Therefore, the second via hole 132 and the first via hole 131 can be formed simultaneously without increasing the number of photomasks and the related photolithography process, etching process, deposition process and chemical mechanical planarization process, thereby achieving the effect of saving process costs. , and the second via hole 132 and the first via hole 131 may have the same material, such as the same diffusion barrier layer and the same filling conductive material. In addition, since the dielectric layer directly under the thin film resistor 115, such as the first inter-metal dielectric layer 110, does not have an etching stop layer, a metal layer (such as the first conductive line layer 111 or other metal patterns), a semiconductor layer (such as polycrystalline silicon), pattern) and other patterned blocks, and can also control the etching process parameters (such as the amount of etchant used, etching time, etc.) to form the first hole 151 and the second hole 152, so the second depth T2 of the second via hole 132 can Greater than or equal to 1 to 1.5 times the first depth T1 of the first via hole 131 , and both the first via hole 131 and the second via hole 132 can achieve their respective required electrical connection functions, wherein the first via hole 131 can Electrically coupled to the first conductive layer 111 and the second conductive layer 121, the second via hole 132 can be electrically coupled to the thin film resistor 115 and the second conductive layer 121, and the bottom surface of the second via hole 132 can be made of the first metal The interlayer dielectric layer 110 or the interlayer dielectric layer 109 surrounds without being electrically coupled to other conductive layers.

Figure 5 is a histogram of the film resistance value Rs (ohms/square, Ω/□) of the film resistor of some embodiments of the present disclosure, in which Embodiment 1: M1 L1*0% is the value shown in Figure 1 There is no overlap between the first conductor layer 111 and the thin film resistor 115 in the vertical projection direction (such as the Z direction); Example 2: M1 L1*30% is the degree of overlap between the first conductive layer 111 and the thin film resistor in the vertical projection direction. 30%, for example The overlapping area of the first conductive layer and the thin film resistor accounts for 30% of the thin film resistor; Example 3: M1 L1*50% is the overlap degree of the first conductive layer and the thin film resistor in the vertical projection direction, which is 50%, for example The overlapping area of the first conductive layer and the thin film resistor accounts for 50% of the thin film resistor; Example 4: M1 L1*100% is the overlap degree of the first conductive layer and the thin film resistor in the vertical projection direction, which is 100%, for example The overlapping area of the first conductor layer and the thin film resistor accounts for 100% of the thin film resistor. It can be seen from the data in Figure 5 that the higher the degree of overlap between the first conductor layer 111 and the thin film resistor 115, the lower the thin film resistance value Rs of the thin film resistor 115, which means that the target resistance value of the thin film resistor 115 must be maintained. , it is necessary that the first conductor layer 111 and the thin film resistor 115 do not overlap at all in the vertical projection direction.

Figure 6 is a graph showing resistance value mismatch (mismatch) of thin film resistors of some embodiments of the present disclosure, which are various sizes of Embodiment 1: M1 L1*0% and Embodiment 3: M1 L1*50% respectively. The resistance value mismatch percentage (%‧μm) of the thin film resistor, where the horizontal axis is the width/length (unit: μm) of the thin film resistor of different sizes. For example, the width/length of the thin film resistor are respectively 2.5/4, 2.5/8, 2.5/12.5, 2.5/50, 2.5/100, 4/10, 4/50, 10/50, 10/100, the resistance value mismatch percentage indicates that they were manufactured under the same conditions The degree to which the film resistance values Rs of multiple film resistors match each other. The higher the mismatch percentage, the more film resistance values Rs of the film resistors manufactured under the same conditions are inconsistent with the film resistance values Rs of other film resistors. . It can be seen from the data in Figure 6 that the resistance value mismatch percentage of the thin film resistors of various sizes in Example 1: M1 L1*0% is lower than that of the thin film resistors of various sizes in Example 3: M1 L1*50%. The resistance value mismatch percentage of the resistor, which means that the first conductor layer 111 and the thin film resistor 115 have no overlap at all in the vertical projection direction can improve the resistance value matching of the thin film resistor to meet the requirements of the thin film resistor in integrated circuits. Electrical requirements of the application. In addition, it can be seen from the data in Figure 6 that when the width of the thin film resistor is the same but the length is longer, the resistance value mismatch percentage decreases as the length increases. Therefore, when integrating small-sized resistors in semiconductor devices When it comes to thin film resistors, it is more necessary to improve the resistance value mismatch of the thin film resistors through embodiments of the present disclosure, so as to facilitate the application of small-sized thin film resistors in integrated circuits.

FIG. 7 is a schematic cross-sectional view of a semiconductor structure 200 according to another embodiment of the present disclosure. The difference between the semiconductor structure 200 in FIG. 7 and the semiconductor structure 100 in FIG. 1 is that the thin film resistor 115 included in the semiconductor structure 200 is formed on There is an etch stop layer 119 and an anti-reflective layer 117, and the etch stop layer 119 and the anti-reflective layer 117 have patterned areas corresponding to the positions of the second via holes 132, and cover the second metal interlayer interlayer above the thin film resistor 115. The top surface of the electrical layer 120 is uneven, and the top surface of a portion of the second inter-metal dielectric layer 120 located squarely on the etching stop layer 119 and the anti-reflective layer 117 is higher than the top surface of other portions. In addition, the second via hole 132 of the semiconductor structure 200 passes through the second inter-metal dielectric layer 120 and the anti-reflection layer 117 , and the bottom surface of the second via hole 132 stops on the top surface of the etching stop layer 119 or is located on the etching stop layer 119 , without passing through the thin film resistor 115 into the first inter-metal dielectric layer 110 , the thin film resistor 115 is directly formed on the top surface of the first inter-metal dielectric layer 110 . The thin film resistance value (Rs) of the semiconductor structure 200 is approximately 1070+/-32Ω/□, and the thin film resistance value (Rs) of the semiconductor structure 100 is approximately 1001+/-30Ω/□. Therefore, the resistance of the thin film resistor of the semiconductor structure 100 is The value is relatively stable, and compared with the fluctuation of the thin film resistance value of the semiconductor structure 200, the fluctuation degree can be improved by about 6%. In addition, the mismatch percentage of the sheet resistance value of the semiconductor structure 200 is 0.116%·μm, while the mismatch percentage of the sheet resistance value of the semiconductor structure 100 is 0.065%·μm. Therefore, the resistance mismatch degree of the semiconductor structure 100 is low. Compared with the resistance value mismatch of the semiconductor structure 200, the resistance value mismatch can be improved by about 50%.

According to some embodiments of the present disclosure, no patterned areas, such as etch stop layers, metal layers, semiconductor layers, or combinations of the foregoing, are provided directly below the vertically projected area of the thin film resistor, at least within the inter-metal dielectric layer. Moreover, the conductor layer located in the intermetallic dielectric layer below the thin film resistor will not overlap with the thin film resistor in the vertical projection direction, thereby improving the flatness of the thin film resistor and reducing the resistance value mismatch of the thin film resistor. degree, and the effect of improving the stability of the resistance value of the thin film resistor, so that the electrical properties of the thin film resistor integrated in the semiconductor device can meet the requirements of the integrated circuit.

Furthermore, according to embodiments of the present disclosure, a via hole electrically coupled to the thin film resistor, and Another via electrically coupled to the conductive layer in the intermetal dielectric layer below the thin film resistor can be fabricated simultaneously through the same photolithography process and the same etching process, as well as the same deposition process and the same planarization process. , so there is no need to increase the number of photomasks and other process steps, which can achieve the effect of saving manufacturing costs.

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the patentable scope of the present invention shall fall within the scope of the present invention.

100:Semiconductor Structure

101: Base

103:Transistor

105: Doped area

107: Gate

108: Via hole

109: Interlayer dielectric layer

110: First inter-metal dielectric layer

111: First wire layer

113: Silicon oxide layer

115:Thin film resistor

117:Anti-reflective layer

120: Second inter-metal dielectric layer

121: Second wire layer

130:Vertical projection area

131: First via hole

132: Second via hole

T1: first depth

T2: Second depth

Claims (10)

A semiconductor structure, including: a substrate; a first inter-metal dielectric layer disposed above the substrate; a first conductor layer disposed in the first inter-metal dielectric layer; a second inter-metal dielectric layer , disposed on the first inter-metal dielectric layer; a thin film resistor, disposed in the second inter-metal dielectric layer; a silicon-containing oxide layer, disposed on the first inter-metal dielectric layer and the second Between the inter-metal dielectric layers; a first via hole located directly above the first conductor layer and extending downward from a top surface of the second inter-metal layer dielectric layer to a first depth; and a second via hole , through the thin film resistor, extending downward from the top surface of the second inter-metal dielectric layer to a second depth, wherein the second depth is greater than or equal to the first depth, and in the vertical projection of the thin film resistor There is no patterned area directly below the area. The semiconductor structure of claim 1, wherein the second depth is greater than or equal to 1 to 1.5 times the first depth. The semiconductor structure of claim 1, wherein the patterned area includes an etching stop layer, a metal layer, a semiconductor layer or a combination of the foregoing. The semiconductor structure of claim 1, further comprising a second conductive layer disposed above the first conductive layer, wherein the first via hole is electrically connected to the first conductive layer and the second conductive layer, and the third conductive layer Two via holes are electrically connected to the thin film resistor and the second conductive layer. The semiconductor structure of claim 1, wherein the bottom surface of the first via hole and the bottom surface of the second via hole are at the same level. The semiconductor structure of claim 1, wherein the silicon-containing oxide layer is disposed between the first inter-metal dielectric layer and the thin film resistor. The semiconductor structure of claim 6, further comprising: an anti-reflection layer disposed on the thin film resistor; and an interlayer dielectric layer disposed under the first inter-metal dielectric layer, wherein the second conductive The hole passes through the anti-reflection layer and the silicon-containing oxide layer, and the bottom surface of the second via hole is located in the first inter-metal dielectric layer or the inter-layer dielectric layer. A manufacturing method including a semiconductor structure, including: providing a substrate; forming a first conductor layer above the substrate; depositing a first inter-metal layer dielectric layer to cover the first conductor layer; Forming a thin film resistor on the electrical layer; depositing a second intermetallic dielectric layer to cover the thin film resistor; forming a silicon-containing oxide layer located on the first intermetallic dielectric layer and the second intermetallic dielectric layer between layers; forming a first hole directly above the first conductor layer, and forming a second hole through the thin film resistor, wherein the first hole and the second hole are formed by the same etching process; and A first via hole is formed in the first hole, and a second via hole is formed in the second hole. The method of manufacturing a semiconductor structure as claimed in claim 8, wherein the first hole extends downward from a top surface of the second inter-metal layer dielectric layer to a first depth, and the second hole extends downward from the second inter-metal layer dielectric layer. A top surface of the electrical layer extends downward to a second depth, and the second depth is greater than or equal to 1 to 1.5 times the first depth. The method of manufacturing a semiconductor structure as described in claim 8, wherein the first via hole and the second via hole are formed simultaneously by the same deposition process and the same chemical mechanical planarization process.

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