TWI821198B - Integrated circuit, non-transitory computer readable medium and computing system - Google Patents

Abstract

An integrated circuit (IC) including a first synchronous circuit configured to operate in synchronization with a clock signal is provided. The first synchronous circuit includes a selector including a first input terminal configured to receive a first input signal, a second input terminal configured to receive a second input signal, and a third input terminal configured to receive a scan enable signal indicating one of a scan test mode and a function operation mode and a latch unit configured to operate as a flip-flop outputting a first output signal corresponding to the first input signal in the scan test mode and to operate as a latch outputting a second output signal corresponding to the second input signal in the function operation mode.

Description

Integrated circuits, non-transitory computer-readable media and computing systems [Cross-reference to related applications]

This application claims Korean Patent Application No. 10-2017-0104520, which was filed with the Korean Intellectual Property Office on August 18, 2017, and Korean Patent Application No. 10-2017-0104520, which was filed with the Korean Intellectual Property Office on March 22, 2018. No. 10-2018-0033490, the full disclosure content of the Korean patent application is incorporated into this case for reference.

Exemplary embodiments of the inventive concept relate to a non-transitory computer-readable medium storing a library of standard cells, an integrated circuit (IC) including a synchronous circuit, and a computing system for designing the IC. For example, at least some exemplary embodiments relate to a non-transitory computer-readable medium storing a standard cell library including standard cells corresponding to a synchronization circuit, an IC including the synchronization circuit, and a design IC computing system.

Due to the integration of semiconductor wafers, testing the semiconductor wafers may consume time and resources. Design for testability (DFT) technology is widely used to maintain the quality of semiconductor wafers and improve test efficiency.

Exemplary embodiments of the inventive concept provide a non-transitory computer readable medium storing a library of standard cells including standard cells corresponding to synchronization circuits operating as flip-flops or latches depending on the mode, a medium including An integrated circuit (IC) of the synchronous circuit and a computing system for designing the IC.

According to an exemplary embodiment of the inventive concept, an IC is provided, the IC including a first synchronization circuit configured to operate in synchronization with a clock signal, the first synchronization circuit including: a selector, It includes a first input terminal, a second input terminal and a third input terminal, the first input terminal is configured to receive a first input signal, the second input terminal is configured to receive a second input signal, and the third input terminal is configured to receive a second input signal. three input terminals configured to receive a scan enable signal instructing the first synchronization circuit to operate in one of a scan test mode and a functional operation mode; and a reconfigurable latch configured selectively switching between operating as a flip-flop in the scan test mode and operating as a latch in the functional mode of operation such that the reconfigurable latch in the scan test mode The latch outputs a first output signal corresponding to the first input signal and the reconfigurable latch outputs a second output signal corresponding to the second input signal in the functional mode of operation.

According to another exemplary embodiment of the inventive concept, there is provided a non-transitory computer-readable medium storing a standard cell library, the standard cell library including information on a plurality of standard cells, the standard cells The library, when executed by the processor, configures the processor to: design an integrated circuit, the integrated circuit including synchronization with a clock signal An operational synchronization circuit including a reconfigurable latch configured to operate as a flip-flop in a scan test mode and as a latch in a functional mode of operation in response to a scan enable signal Selectively switching between operations such that the reconfigurable latch outputs a first output signal corresponding to a first input signal in the scan test mode and the reconfigurable latch in the functional operation mode The configured latch outputs a second output signal corresponding to the second input signal.

According to another exemplary embodiment of the inventive concept, a computing system is provided, the computing system comprising: a storage device configured to store a standard cell library, the standard cell library including information on a plurality of standard cells. , the plurality of standard cells including a plurality of flip-flop latch cells and a plurality of flip-flop cells; and a processor configured to design an integrated circuit (IC), the integrated circuit including A scan test circuit of a plurality of synchronization circuits configured to operate in synchronization with a clock signal such that at least one of the plurality of synchronization circuits includes a reconfigurable latch using the A plurality of standard cells are formed, the reconfigurable latch is configured to operate as a flip-flop in a scan test mode in response to a scan enable signal having a first logic level and in response to a scan enable signal having a second logic level. level of the scan enable signal to operate as a latch in a functional operating mode.

10, 10A: Integrated circuit (IC)

100: Synchronous circuit

100_1, 100_1', 100_1a, 100_1b: first synchronization circuit

100_2: Second synchronization circuit

100_3: The third synchronization circuit

110:Multiplexer

120, 120': Main latch

130, 130', 130a: slave latch

200_1: Combinational logic circuit/first combinational logic circuit

200_2: Combinational logic circuit/second combinational logic circuit

1000:Computing systems/IC design systems

1100: Processor

1200:Memory

1210:Synthesis module

1220: Placement and routing (P&R) module

1230: Static timing analysis (STA) module

1300: Input/output (I/O) device

1400:Storage device

1410: Standard cell library

1411: Flip-flop cell group

1413:Latch cell group

1415: Flip-flop latch cell group

1500:Bus

a:Scan test mode

b: Functional operation mode

C01, C02, C03, C04, C05, C06, C07: Examples

CLK: clock signal

ck: internal clock signal

ckn: inverted clock signal

D: Second terminal/data input signal

inv1, inv2: inverter

IS1: the first internal signal

IS2: Second internal signal

PI1: Scan input signal

PI2: data input signal

PO1, SO: Scan output signal

PO2, Q: data output signal

R01, R02, R03, R04: columns

S10, S20, S110, S111, S113, S115, S117, S120, S121, S123, S125, S127, S130, S210, S220: Operation

SE: Scan for Enablement Signals

SI: First terminal/scan input signal

SW: switch

Exemplary embodiments of the inventive concept will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram illustrating an IC including a synchronization circuit according to an exemplary embodiment.

2 is a block diagram illustrating a first synchronization circuit according to an exemplary embodiment.

3A and 3B are logic diagrams according to an exemplary embodiment of each of the master latches and slave latches included in the first synchronization circuit shown in FIG. 2 .

4 is a block diagram illustrating a first synchronization circuit according to an exemplary embodiment.

FIG. 5 is a logic diagram according to an exemplary embodiment of each of the master latches and slave latches included in the first synchronization circuit shown in FIG. 4 .

6 is a block diagram illustrating a first synchronization circuit according to an exemplary embodiment.

7 is a block diagram illustrating a computing system for designing an IC according to an exemplary embodiment.

Figure 8 shows a schematic layout of an IC according to an exemplary embodiment.

9 is a diagram illustrating a cell library according to an exemplary embodiment.

FIG. 10 is a flowchart illustrating a method of designing an IC according to an exemplary embodiment.

FIG. 11 is a flowchart illustrating an exemplary embodiment of operation S110 shown in FIG. 10 .

FIG. 12 is a flowchart illustrating an exemplary embodiment of operation S120 shown in FIG. 10 .

13 is a flowchart for explaining a method of manufacturing an IC according to an exemplary embodiment.

Hereinafter, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating an integrated circuit (IC) 10 including a synchronization circuit according to an exemplary embodiment.

Referring to FIG. 1 , IC 10 may include a plurality of synchronization circuits 100 . The plurality of synchronization circuits 100 may form a sequential circuit and may form a scan chain operating as a scan test circuit.

The plurality of synchronization circuits 100 may each include a first terminal SI and a second terminal D. The first terminal SI receives a scan input signal, and the second terminal D receives a data input signal. In addition, each of the plurality of synchronization circuits 100 may output a scan output signal SO based on the scan input signal and may output a data output signal Q based on the data input signal.

For example, multiple combinational logic circuits such as the first combinational logic circuit 200_1 and the second combinational logic circuit 200_2 may each be implemented as a synchronous circuit or an asynchronous circuit. The plurality of combinational logic circuits 200_1 and 200_2 may process data signals input to the plurality of combinational logic circuits 200_1 and 200_2 and may output results obtained by the processing.

The first synchronization circuit 100_1 may provide the scan input signal PI1 as the scan output signal SO in synchronization with the clock signal CLK in a scan test mode (for example, a mode in which the scan enable signal SE has a logic high level), and in the functional operation mode (For example, a mode in which the scan enable signal SE has a logic low level), the first synchronization circuit 100_1 may provide the data input signal PI2 as the data output signal Q.

The first combinational logic circuit 200_1 can perform an arithmetic operation on the data output signal Q of the first synchronization circuit 100_1 to provide the data input signal D of the second synchronization circuit 100_2. In addition, the second synchronization circuit 100_2 can receive the scan output signal SO of the first synchronization circuit 100_1 as the scan input signal SI. In addition, the second synchronization circuit 100_2 can operate in a functional operation mode or a scan test mode based on the scan enable signal SE and the clock signal CLK.

The second combinational logic circuit 200_2 can perform an arithmetic operation on the data output signal Q of the second synchronization circuit 100_2 to provide the data input signal D of the third synchronization circuit 100_3. In addition, the third synchronization circuit 100_3 can receive the scan output signal SO of the second synchronization circuit 100_2 as the scan input signal SI. In addition, the third synchronization circuit 100_3 can operate in a functional operation mode or a scan test mode based on the scan enable signal SE and the clock signal CLK. The third synchronization circuit 100_3 can output the data output signal PO2 in the functional operation mode, and in the scan test mode, the third synchronization circuit 100_3 can output the scan output signal PO1.

In the drawings, an example is shown in which three synchronous circuits constitute a sequential circuit, but the IC 10 according to the exemplary embodiment of the present invention is not limited thereto. The number of synchronization circuits included in IC 10 may vary.

At least one of the plurality of synchronization circuits 100 may be implemented as one of the synchronization circuits shown in FIGS. 2 to 6 . At least one of the plurality of synchronization circuits 100 may operate as a latch in a functional operating mode and as a flip-flop in a scan test mode. Therefore, in the at least one synchronization circuit, the operating speed in functional operation is increased and the power consumption is reduced, and furthermore, an additional hold buffer can be omitted in scan test operation. Therefore, the total area of the IC 10 is reduced, and the power consumption of the IC 10 is reduced.

FIG. 2 is a block diagram showing the first synchronization circuit 100_1 according to an exemplary embodiment. The first synchronization circuit 100_1 shown in Figure 2 may be included in the IC 10 shown in Figure 1 At least one of the plurality of synchronization circuits 100 included, and for example, may be the first synchronization circuit 100_1, but is not limited thereto. The scan input signal SI shown in FIG. 2 may be the scan input signal PI1 shown in FIG. 1 , and the data input signal D shown in FIG. 2 may be the data input signal PI2 shown in FIG. 1 .

Referring to FIG. 2 , the first synchronization circuit 100_1 may include a multiplexer 110 , a master latch 120 and a slave latch 130 . The first synchronization circuit 100_1 may operate as a flip-flop or a latch based on the operation mode.

The multiplexer 110 can receive the data input signal D and the scan input signal SI, and based on the operation mode, the multiplexer 110 can select a signal from the data input signal D and the scan input signal SI to provide the signal obtained by the selection. The first internal signal IS1. The multiplexer 110 can provide the data input signal D as the first internal signal IS1 in the functional operation mode b of transmitting data, and in the scan test mode a of performing the test operation, the multiplexer 110 can provide the scan input signal SI as the third internal signal IS1. An internal signal IS1. Multiplexer 110 may be referred to as a mux, scan mux, or selector.

The multiplexer 110 may include a first input terminal, a second input terminal and a third input terminal. The first input terminal receives the scan input signal SI, the second input terminal receives the data input signal D, and the third input terminal The terminal receives the scan enable signal SE.

In an exemplary embodiment, the operation mode may be determined based on the logic bits of the scan enable signal SE received by the first synchronization circuit 100_1. For example, if the scan enable signal SE has a first logic level (for example, a logic high level), it can be implemented Scan test mode a, and if the scan enable signal SE has a second logic level (eg, a logic low level), functional operation mode b can be implemented. However, the first synchronization circuit 100_1 according to the exemplary embodiment of the present invention is not limited to this. In other exemplary embodiments, if the scan enable signal SE has a second logic level, the scan test mode a can be implemented, and if the scan enable signal SE has a first logic level, the functional operation mode b can be implemented .

The main latch 120 may latch the first internal signal IS1 output from the multiplexer 110 based on the clock signal CLK to output the second internal signal IS2. The slave latch 130 may latch the second internal signal IS2 output from the master latch 120 based on an inversion clock signal obtained by performing an inversion operation on the clock signal CLK.

In the scan test mode a, the multiplexer 110 may provide the scan input signal SI to the main latch 120 . The first internal signal IS1 may be the scan input signal SI. The master latch 120 can latch the scan input signal SI, and the slave latch 130 can latch the second internal signal IS2 to output the scan output signal SO.

In scan test mode a, both the master latch 120 and the slave latch 130 can operate to form a flip-flop. The master latch 120 and the slave latch 130 may perform a scanning operation of latching the scan input signal SI to provide the scan output signal SO.

The scan output signal SO may be provided as a scan input signal of a next synchronization circuit connected to the first synchronization circuit 100_1 (for example, the second synchronization circuit 100_2 shown in FIG. 1 ), and the next synchronization circuit may be in the scan test mode. In a, operations similar to those of the first synchronization circuit 100_1 are performed.

On the other hand, in the functional operation mode b, the multiplexer 110 may provide the data input signal D to the main latch 120 . The first internal signal IS1 may be the data input signal D. The main latch 120 can perform the function of latching the data input signal D to provide the data output signal Q. In functional operating mode b, slave latch 130 may not be used.

The first synchronization circuit 100_1 according to an exemplary embodiment may output the scan output signal SO and the data output signal Q through different nodes. The scan output signal SO can be output from the latch 130 , and the data output signal Q can be output from the latch 120 . Therefore, in the scan test mode a, the first synchronization circuit 100_1 can operate as a flip-flop in which both the master latch 120 and the slave latch 130 operate. On the other hand, in the functional operation mode b, since the slave latch 130 does not operate, the first synchronization circuit 100_1 can operate as a latch.

In the case where the synchronization circuit operates as a latch, the delay time is shorter than that in the flip-flop case, and the power consumption is less than that in the flip-flop case, whereby when the functional operation mode is implemented The situation described is efficient. However, if the synchronization circuit is also intended to operate as a latch when the scan test mode is executed, an additional separate holding buffer may be required between the synchronization circuit and another synchronization circuit to enable the The scan shift operation is performed stably, which may increase the area of the IC and the power consumption of the IC.

In contrast, since the first synchronization circuit 100_1 according to the exemplary embodiment operates as a latch in the functional operation mode b and operates as a flip-flop in the scan test mode a, the operation speed in the functional operation is improved and Power consumption reduction low, and in scan test operations, an additional hold buffer may not be needed. Therefore, the total area of the IC is reduced, and further, the power consumption of the IC is reduced.

In an exemplary embodiment, slave latch 130 may include a plurality of transistors each having a threshold voltage that is higher than a threshold voltage of a plurality of transistors included in master latch 120 . The slave latches 130 may be implemented using transistors each having a high threshold voltage, and therefore, in scan test mode a, the leakage current of the slave latches 130 is reduced, and includes the master latch The operating speed of the flip-flop of the latch 120 and the slave latch 130 is reduced. Therefore, the problem of hold time violation in scan test mode a is solved.

3A and 3B are logic diagrams according to an exemplary embodiment of each of the master latches and slave latches included in the first synchronization circuit 100_1 shown in FIG. 2 .

Referring to FIG. 3A , the first synchronization circuit 100_1 may include a multiplexer 110 , a master latch 120 and a slave latch 130 . In an exemplary embodiment, the multiplexer 110 may include three NAND gates and one inverter. However, this is only an example, and the multiplexer 110 may be implemented in various types.

The master latch 120 and the slave latch 130 may each include two transmission gates and three inverters. Logic gates may be connected to each other as shown in Figure 3A. However, the master latch 120 and the slave latch 130 shown in FIG. 3A are examples, and exemplary embodiments of the present invention are not limited thereto. The number of transmission gates and inverters included in each of master latch 120 and slave latch 130 may vary based on design.

The first synchronization circuit 100_1 may include a plurality of inverters inv1 and inv2 that respectively generate an inverted clock signal chn and an internal clock signal ck based on the clock signal CLK received from the outside. . The plurality of inverters inv1 and inv2 are shown as being disposed outside the master latch 120 and the slave latch 130 , but are not limited thereto. In other exemplary embodiments, the plurality of inverters inv1 and inv2 may be included in at least one of the master latch 120 and the slave latch 130 .

The main latch 120 may enable the latch for a high level. Therefore, the master latch 120 can transparently output the data input signal D output from the multiplexer 110 as the data output signal Q during the logic high period, which is the internal clock signal ck. Empowerment cycle.

The master latch 120 and the slave latch 130 may form a flip-flop, and the flip-flop may operate as a negative edge flip-flop. Therefore, the slave latch 130 can output the scan output signal SO at the negative edge of the internal clock signal ck or the positive edge of the inverted clock signal ckn.

Referring to FIG. 3B , the master latch 120 ′ and the slave latch 130 ′ may each include two transmission gates and three inverters. Logic gates may be connected to each other as shown in Figure 3B. However, the master latch 120' and the slave latch 130' shown in FIG. 3B are examples, and exemplary embodiments of the present invention are not limited thereto.

The first synchronization circuit 100_1' may include a plurality of inverters inv1 and inv2. The plurality of inverters inv1 and inv2 respectively generate an inverted clock signal ckn and an internal clock signal based on the clock signal CLK received from the outside. ck. The plurality of inverters inv1 and inv2 are shown to be disposed outside the master latch 120' and the slave latch 130', but are not Not limited to this. In other embodiments, the plurality of inverters inv1 and inv2 may be included in at least one of the master latch 120' and the slave latch 130'.

The main latch 120' may activate the latch for a low level. The master latch 120' can transparently output the data input signal D output from the multiplexer 110 as the data output signal Q during the deactivation period (ie, the logic low period) of the internal clock signal ck.

The master latch 120' and the slave latch 130' may form a flip-flop, and the flip-flop may operate as a positive edge flip-flop. Therefore, the slave latch 130' can output the scan output signal SO at the positive edge of the internal clock signal ck (ie, the negative edge of the inverted clock signal ckn).

FIG. 4 is a block diagram showing the first synchronization circuit 100_1a according to an exemplary embodiment. The first synchronization circuit 100_1a shown in FIG. 4 may be at least one of the plurality of synchronization circuits 100 included in the IC 10 shown in FIG. 1, and for example, may be the first synchronization circuit 100_1, but not only Limited to this. In FIG. 4 , the same elements as those shown in FIG. 2 will not be described again.

Referring to FIG. 4 , the first synchronization circuit 100_1a may include a multiplexer 110, a master latch 120, and a slave latch 130a. The first synchronization circuit 100_1a may operate as a flip-flop in the scan test mode a, and in the functional operation mode b, the first synchronization circuit 100_1a may operate as a latch.

The slave latch 130a may latch the second internal signal IS2 output from the master latch 120 based on an inverted clock signal obtained by performing an inverting operation on the clock signal CLK. At this time, the slave latch 130a can receive the scan enable signal SE, and in response to the scan enable signal SE, the slave latch 130a can determine whether to execute the slave latch 130a latch operation. The slave latch 130a may perform the latch operation in the scan test mode a, and in the functional operation mode b, the slave latch 130a may not perform the latch operation.

For example, if the scan enable signal SE has a first logic level (eg, a logic high level), the slave latch 130a can perform a latch operation, and if the scan enable signal SE has a second logic level (eg, a logic high level) For example, if the logic level is low), then the slave latch 130a may not perform the latch operation.

In an exemplary embodiment, slave latch 130a may include a plurality of transistors each having a threshold voltage that is higher than a threshold voltage of a plurality of transistors included in master latch 120 . The slave latches 130a can be implemented using transistors each having a high threshold voltage, and therefore, in the scan test mode a, the leakage current of the slave latches 130a is reduced, and the operation speed of the first synchronization circuit 100_1a reduce. Therefore, the problem of hold time violation in scan test mode a is solved.

In the functional operation mode b, since only the master latch 120 is used, the slave latch 130a may not perform a latch operation, and therefore, the power consumption of the first synchronization circuit 100_1a is reduced. In addition, the slave latch 130a does not operate, and therefore, even when the threshold voltages of the transistors included in the slave latch 130a are respectively high, the operation speed of the first synchronization circuit 100_1a does not decrease.

FIG. 5 is a logic diagram according to an exemplary embodiment of each of the master latches and slave latches included in the first synchronization circuit shown in FIG. 4 . In FIG. 5 , the same elements as those shown in FIG. 3A will not be described again.

Referring to FIG. 5 , the first synchronous circuit 100_1a can operate as a positive-edge flip-flop in the scan test mode, and in the functional operation mode, the first synchronous circuit 100_1a Can operate as a low level enable latch.

In an exemplary embodiment, slave latch 130a may include two transfer gates, two inverters, and one NAND gate. Logic gates can be connected to each other as shown in Figure 5. However, the master latch 120 and the slave latch 130a shown in FIG. 5 are examples, and exemplary embodiments of the present invention are not limited thereto.

The NAND gate can perform an NAND operation on the scan enable signal SE output by the autonomous latch 120 and the second internal signal IS2. For example, if the scan enable signal SE has a logic low level (functional operation mode), the scan output signal SO can be fixed to a logic high level regardless of the data input signal D and the clock signal CLK. That is, in the functional operation mode, the scan output signal SO can be fixed to a logic high level. Therefore, the power consumption of the slave latch 130a is reduced.

An exemplary embodiment is an NAND operation of the NAND gate performed in a process in which the slave latch 130a controls whether to perform a latch operation on the second internal signal IS2 based on the scan enable signal SE. The slave latch 130a may include a NOR gate instead of an NOR gate, and the NOR gate may receive the inverted signal of the scan enable signal SE and the second internal signal IS2 to perform the NOR operation. For example, if the scan enable signal SE has a logic low level (functional operation mode), the scan output signal SO can be fixed to a logic high level regardless of the data input signal D and the clock signal CLK.

In the slave latch 130a of the first synchronization circuit 100_1a according to an exemplary embodiment of the present invention, input of the second internal signal IS2 output from the master latch 120 may be blocked based on the scan enable signal SE, and may be implemented in various ways. block input 2. Operation of internal signal IS2.

In FIG. 5 , an example is shown in which the master latch 120 is a high-level enable latch and the master latch 120 and the slave latch 130 a constitute a negative-edge flip-flop, but according to an exemplary embodiment of the present invention The first synchronization circuit 100_1a is not limited to this. Even in the case where the master latch 120 is a low-level enable latch and the master latch 120 and the slave latch 130a form a positive-edge flip-flop, the slave latch 130a can also be activated based on the scan enable signal. SE is configured to block input of the second internal signal IS2 in the slave latch 130a.

The first synchronization circuit 100_1a according to an exemplary embodiment of the present invention is not limited to one in which the latch operation of the slave latch 130a in the functional operation mode is controlled by blocking the input of the second internal signal IS2 output from the master latch 120 example of. In other exemplary embodiments, the first synchronization circuit 100_1a may be configured to block the clock signal CLK received from the slave latch 130a in response to the scan enable signal SE. For example, the slave latch 130a may be configured such that if the scan enable signal SE has a logic low level (functional operation mode), the internal clock signal ck and the inverted clock signal are not input to the transmission gate.

FIG. 6 is a block diagram showing the first synchronization circuit 100_1b according to an exemplary embodiment. The first synchronization circuit 100_1b shown in FIG. 6 may be at least one of the plurality of synchronization circuits 100 included in the IC 10 shown in FIG. 1, and for example, may be the first synchronization circuit 100_1, but not only Limited to this. In FIG. 6 , the same elements as those shown in FIG. 2 will not be described again.

Referring to FIG. 6 , the first synchronization circuit 100_1b may include a multiplexer 110, a master Latch 120, slave latch 130 and switch SW. The first synchronization circuit 100_1b may operate as a flip-flop in the scan test mode a, and in the functional operation mode b, the first synchronization circuit 100_1b may operate as a latch.

In response to the scan enable signal SE, the switch SW blocks the clock signal CLK from being input to the slave latch 130 . Therefore, whether to perform the latch operation of the slave latch 130 can be determined based on the scan enable signal SE. The switch SW can be implemented in various types.

For example, if the scan enable signal SE has a first logic level (eg, a logic high level), the clock signal CLK may be input to the slave latch 130 , and if the scan enable signal SE has a second logic level level (eg, a logic low level), the clock signal CLK may not be input to the slave latch 130 . Therefore, the slave latch 130 may perform the latch operation in the scan test mode a, and the slave latch 130 may not perform the latch operation in the functional operation mode b.

In FIG. 6 , a configuration in which the clock signal CLK is blocked from being input from outside the latch 130 to the inside of the slave latch 130 is illustrated, but the first synchronization circuit 100_1b according to the embodiment of the present invention is not limited to this. The first synchronization circuit 100_1b may further include a switch SW that blocks the second internal signal IS2 from being input from outside the slave latch 130 to the slave latch 130 . For example, the switch may be configured such that if the scan enable signal SE has a logic high level (scan test mode a), the second internal signal IS2 is input to the slave latch 130, and if the scan enable signal SE SE has a logic low level (functional operation mode b), then the second internal signal IS2 is not input to the slave latch 130 .

In functional operating mode b, since only the master latch 120 is used, the slave latch The latch 130 may not perform the latch operation, and therefore, the power consumption of the first synchronization circuit 100_1b is reduced. In addition, the slave latch 130 does not operate, and therefore, even when the threshold voltages of the transistors included in the slave latch 130 are respectively high, the operation speed of the first synchronization circuit 100_1b does not decrease.

7 is a block diagram illustrating a computing system 1000 for designing an IC according to an exemplary embodiment.

Referring to FIG. 7 , a computing system 1000 for designing an IC (hereinafter referred to as an IC design system) may include a processor 1100 , a memory 1200 , an input/output (I/O) device 1300 , a storage device 1400 and a bus 1500. In an exemplary embodiment, IC design system 1000 may be implemented using an integrated device, and thus, may be an IC design device. The IC design system 1000 may be provided as a dedicated device for designing ICs of semiconductor devices, but may be a computer driving various simulation tools or design tools.

The computing system 1000 can design the IC 10 shown in Figure 1, and therefore the design includes one of the first synchronization circuits 100_1, 100_1', 100_1a and 100_1b shown in Figures 2, 3A, 3B, 4, 5 and 6. the IC of the person.

The processor 1100 may include processing circuitry including, but not limited to, a processor, a central processing unit (CPU), a controller, an arithmetic logic unit (ALU), a digital signal processor , microcomputer, field programmable gate array (field programmable gate array, FPGA), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), system-on-chip (SoC), Programmable logic unit, microprocessor, or any other device capable of performing operations in a predefined manner.

The processor 1100 may be configured as a special purpose computer by layout design or execution of computer-readable instructions stored in the memory 1200 to perform at least one of various operations for designing an IC.

The processor 1100 can communicate with the memory 1200, the I/O device 1300, and the storage device 1400 through the bus 1500. The processor 1100 can drive the synthesis module 1210, the placement and routing (P&R) module 1220, and the static timing analysis (static timing analysis (STA) module 1230) loaded into the memory 1200, This is used to implement the operation of designing IC. The operation of the processor 1100 to execute the code stored in each of the modules will be described below with reference to FIG. 10 .

The memory 1200 can store the synthesis module 1210, the P&R module 1220 and the STA module 1230. The synthesis module 1210, the P&R module 1220 and the STA module 1230 can be loaded from the storage device 1400 into the memory 1200.

Synthesis module 1210 may be a program that includes a plurality of instructions for performing logic synthesis operations and design for test (DFT) logic insertion operations. P&R module 1220 may be a program that includes a plurality of instructions for performing P&R operations. STA module 1230 may be a program that includes a plurality of instructions for performing STA operations.

The memory 1200 may be a volatile memory, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), or it may be non-volatile. Memory, such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), resistive random access memory (resistive random access memory) memory (ReRAM), ferroelectric random access memory (ferroelectric random access memory (FRAM)) or reverse or flash memory.

I/O device 1300 may control user input and output via user interface devices. For example, the I/O device 1300 may include one or more input devices such as a keyboard, a mouse device, and a touch pad and may receive input data that defines the IC. For example, I/O device 1300 may include output devices such as a display and speakers and may display placement results, routing results, STA results, etc.

The storage device 1400 can store various data associated with the synthesis module 1210, the P&R module 1220, and the STA module 1230. The storage device 1400 may include a memory card (for example, a multimedia card (MMC), an embedded multi-media card (eMMC), a secure digital (SD) card, a micro SD card, etc.), a solid-state Drive (solid state drive, SSD), hard disk drive (hard disk drive, HDD) and/or similar devices.

Figure 8 shows a schematic layout of IC 10A according to an exemplary embodiment. In FIG. 8, elements included in IC 10A may not be to scale for ease of illustration and may be exaggerated or reduced for clarity of illustration.

Referring to Figure 8, IC 10A may include instances of standard cells C01 through C07. Instances corresponding to the same standard cell may have the same layout, and instances corresponding to different standard cells may have different layouts. Instances C01 to C07 can be Classify and place in multiple columns R01 to R04. The instances C01 to C07 may each have a length H (i.e., a height) defined in a direction perpendicular to the plurality of columns R01 to R04 extending in the R01 to R04 have the same length (ie, width) or different lengths (ie, width) in the parallel direction (ie, X direction). The plurality of columns R01 to R04 in which instances C01 to C07 are classified may each have a height that matches the minimum height of a standard cell.

At least one of the instances C01 to C07 of the standard cells placed in the IC 10A may be a synchronization circuit and may be the first synchronization circuit 100_1 shown in FIGS. 2, 3A, 3B, 4, 5, and 6 One of , 100_1', 100_1a and 100_1b.

The standard cells included in the IC 10A may be selected from a standard cell library containing information about a plurality of standard cells based on physical characteristics of the standard cells, such as functional and timing characteristics, and by placing the selected The following example of a standard cell can be used to generate the layout of IC 10A. The standard cell library may contain information about various standard cells (for example, functional information and timing information about the standard cells and topological information about the layout). A standard cell library according to an exemplary embodiment may include a flip-flop cell group, a latch cell group, and a flip-flop latch cell group. The standard cell library will be explained below with reference to FIG. 9 .

Figure 9 is a diagram illustrating a standard cell library 1410 according to an exemplary embodiment. The standard cell library 1410 is stored in the storage device 1400 shown in FIG. 7 .

Referring to FIG. 9 , the standard cell library 1410 may include information on characteristics of a plurality of standard cells having different characteristics. For example, the standard cell library 1410 may include information about power characteristics, timing characteristics, or shape characteristics of standard cells.

The standard cell library 1410 may include a flip-flop cell group 1411, a latch cell group 1413, and a flip-flop latch cell group 1415. The flip-flop cell group 1411 may include information about flip-flop standard cells having different characteristics, and the latch cell group 1413 may include information about latch standard cells having different characteristics.

Flip-flop cell group 1411 may include information about standard cells of synchronization devices that operate as flip-flops regardless of mode, and latch cell group 1413 may include information about standard cells that operate as latches regardless of mode. Information about the standard cells of the operating synchronization device.

Flip-flop latch cell group 1415 may contain information about standard cells of synchronization devices that operate as flip-flops or latches, depending on the mode. For example, the flip-flop latch cell group 1415 may include cells related to the first synchronization circuits 100_1, 100_1', 100_1a, and 100_1b shown in FIG. 2, FIG. 3A, FIG. 3B, FIG. 4, FIG. 5, and FIG. 6. information.

According to an exemplary embodiment, a computing system that designs an IC may generate layout information for the IC with reference to the standard cell library 1410 .

FIG. 10 is a flowchart illustrating a method of designing an IC according to an exemplary embodiment. FIG. 11 is a flowchart illustrating an exemplary embodiment of operation S110 shown in FIG. 10 . FIG. 12 is a flowchart illustrating an exemplary embodiment of operation S120 shown in FIG. 10 .

Referring to FIGS. 7 and 10 , a method of designing an IC may correspond to a process of designing a layout of the IC and may be performed using a tool for designing the IC. In this case, use Tools for designing ICs may be software modules or programs that include a plurality of instructions executed by a processor and may be stored in a computer-readable storage medium. Therefore, the method of designing the IC may be referred to as a computer-implemented method for designing the IC. The method of designing an IC shown in FIG. 10 can be performed by the computing system 1000 shown in FIG. 7 . The IC designed by the design method can be the IC 10 shown in Figure 1, and therefore can include the first synchronization circuits 100_1, 100_1', 100_1a shown in Figures 2, 3A, 3B, 4, 5 and 6 and one of 100_1b.

Referring to FIGS. 7 and 10 , in operation S110 , the processor 1100 may use the synthesis module 1210 to perform a synthesis operation. "Synthesis" may be the operation of converting input data of an IC into hardware including logic gates to generate a netlist and may be referred to as "logic synthesis." The input data may be of an abstract type corresponding to the operation of the IC (eg, data defined in a register transfer level (RTL)). A netlist can be generated from the RTL code using a standard cell library, and the netlist can be a gate level netlist. In embodiments, the RTL code may be provided as an input file to a synthesis tool, and the netlist may be provided as an output file from the synthesis tool. The netlist may include a plurality of standard cells and information about connection relationships of the standard cells.

Referring to FIG. 11, in performing the synthesis operation, the processor 1100 may perform operations S111 to S117.

In operation S111, the processor 1100 may execute the synthesis module 1210 to select a plurality of standard cells respectively corresponding to a plurality of synchronization circuits constituting the scan test circuit. At this time, the processor 1100 can execute the code included in the synthesis module 1210 to The plurality of standard cells are selected based on the input data and the standard cell library 1410 shown in FIG. 9 .

In a functional mode of operation, the processor 1100 may select a flip-flop latch cell for a timing path in which sufficient timing margin is maintained (eg, a situation in which the maintaining timing margin is equal to or greater than a certain value). That is, based on the standard cell library 1410 shown in FIG. 9, the processor 1100 can select and place the flip-flop latch cell in a situation where the holding time is non-critical in the functional operating mode.

In an exemplary embodiment, in operation S113, the processor 1100 may determine whether a flip-flop cell of the selected standard cell is included in a timing path in which the timing margin is maintained to be equal to or greater than a specific value in the functional operation mode. .

In operation S115, the processor 1100 may replace the flip-flops included in the timing path in which the timing margin is equal to or greater than a specific value with the flip-flop latch cells based on the standard cell library 1410 shown in FIG. organ cells. The processor 1100 may determine when the hold-up margin of the flip-flop cell in the functional mode of operation is equal to or greater than the length of the enable period when the replaced flip-flop latch cell operates as a latch. The hold slack is equal to or greater than a specific value and the hold time can be determined to be non-critical.

In an exemplary embodiment, the processor 1100 may execute the synthesis module 1210 to optimally select a flip-flop cell, and may then replace the flip-flop latch cell therein to maintain timing margin in a functional mode of operation. Flip-flop cells selected for adequate timing paths.

If a timing path in which the slack is equal to or greater than a specific value is maintained If the flip-flop cell is not included, the processor 1100 may select the flip-flop cell as is.

In the case of replacing the flip-flop cell with the flip-flop latch cell, the processor 1100 may reconnect the standard cells constituting the scan test circuit based on the polarity of the clock signal in operation S117. The synthesis module 1210 can insert DFT logic into the IC, which is used to connect multiple synchronization circuits that constitute the scan test circuit.

In an exemplary embodiment, a clock signal applied to a flip-flop latch cell after substitution in scan test mode may be relative to a clock signal applied to a flip-flop cell prior to substitution. Has reverse phase. That is, the polarity of the clock signal applied to the inverter latch cell may be opposite to the polarity of the clock signal applied to the flip-flop cell.

For example, the first synchronization circuits 100_1 and 100_1a shown in FIG. 3A and FIG. 5 can operate as high-level enable latches in the functional operation mode and can operate as negative-edge flip-flops in the scan test mode, and therefore, The polarity in the functional operating mode can be reversed from the polarity in the scan test mode. Therefore, in the case where the flip-flop cell is replaced by a flip-flop latch cell corresponding to each of the first synchronization circuits 100_1 and 100_1a shown in FIGS. 3A and 5 , the flip-flop The latch cell can be reconnected to other standard cells that make up the scan test circuit based on the polarity of the clock signal. This description can be applied to the flip-flop latch cell corresponding to the first synchronization circuit 100_1' shown in FIG. 3B.

Referring to FIGS. 7 and 10 , in operation S120 , by using the P&R module 1220 , the processor 1100 may place and route standard cells defining the IC and may generate layout data of the IC. For example, the layout data may be based on a graphic design system (graphic design system, GDS)II information. In an exemplary embodiment, the netlist may be provided as an input file to the P&R module 1220 and the layout data may be output as an output file from the P&R module 1220 .

Referring to FIG. 12, in the process of performing placement and routing operations, the processor 1100 may perform operations S121 to S127.

In operation S121, the processor 1100 may execute the execution code included in the P&R module 1220 to place a standard cell defining the scan test circuit and may route a net included in the placed standard cell.

In operation S123, the processor 1100 may determine whether the flip-flop cell of the selected standard cell is included in a timing path in which the timing margin is maintained to be equal to or greater than a specific value in the functional operation mode.

In operation S125, the processor 1100 may replace the flip-flops included in the timing path in which the timing margin is equal to or greater than a specific value with the flip-flop latch cells based on the standard cell library 1410 shown in FIG. organ cells. That is, the processor 1100 may execute the P&R module 1220 to replace the flip-flop cells in which the hold time is not critical in the functional operation mode with the flip-flop latch cells based on the standard cell library 1410 shown in FIG. 9 Yuan.

In operation S127, when replacing the flip-flop cell with the flip-flop latch cell, the processor 1100 may re-route the standard cell based on the polarity of the clock signal.

When a flip-flop cell is not included in a timing path in which timing margin is maintained equal to or greater than a specific value, the processor 1100 may place the flip-flop cell as-is without replacing the flip-flop cell and may route all flip-flop cells. The standard cell to place.

When routing is complete, processor 1100 may generate layout information for the IC.

Referring again to FIG. 7 and FIG. 10 , in operation S130 , by using the STA module 1230 , the processor 1100 can perform an STA operation on the layout data.

In operation S130, the processor 1100 may execute the code included in the STA module 1230 to determine whether timing is violated. "Timing analysis" can mean an operation of determining whether the timing paths included in the IC satisfy timing constraints (timing constraints), and selecting the timing critical path of the IC or one of them from the timing paths based on the result of the determination. A timing path in which the total time delay from input (i.e., starting point) to output (i.e., end point) exceeds the timing requirements (timing requirements). Timing constraints may include setup timing constraint conditions and hold timing constraint conditions.

When it is determined that timing is not violated, the design operation may end. On the other hand, when it is determined that the timing is violated, the processor 1100 may perform operation S120 again.

Based on the timing analysis determination, the processor 1100 may execute the P&R module 1220 to replace at least some of the flip-flop cells with flip-flop latch cells or to replace at least some of the flip-flop latch cells with flip-flop cells. Yuan. For example, processor 1100 may execute P&R module 1220 and, therefore, flip-flop cells may be replaced with flip-flop latch cells in timing paths where sufficient timing margin is maintained. On the other hand, when the holding timing margin is insufficient, the processor 1100 may execute the P&R module 1220 to replace the flip-flop latch cells with flip-flop cells. In addition, in the re-executed operation S120, after replacing the standard cell, the standard cell may be connected to the scan test circuit again based on the polarity of the clock signal.

13 is a flowchart for explaining a method of manufacturing an IC according to an exemplary embodiment.

Referring to FIG. 13 , the method of manufacturing an IC can be divided into an operation S10 of designing the IC and an operation S20 of manufacturing the IC. The operation S20 of manufacturing the IC may be an operation of manufacturing a semiconductor device based on the IC using layout data generated in the operation S10 of designing the IC and may be performed by a semiconductor processing module. The IC manufactured by the manufacturing method may be the IC 10 shown in Figure 1, and therefore may include the first synchronization circuits 100_1, 100_1', 100_1a shown in Figures 2, 3A, 3B, 4, 5 and 6 and one of 100_1b.

In operation S210, a mask may be generated based on the layout data. First, optical proximity correction (OPC) can be performed based on the layout data. In this case, OPC may represent a process that changes the layout by reflecting errors based on the optical proximity effect. The layout obtained by the changes can then be used to create masks based on the OPC results. In this case, the mask can be made using a layout in which OPC is reflected (eg, GDS II in which OPC is reflected).

In operation S220, the mask may be used to manufacture a semiconductor device in which the IC is implemented. Semiconductor devices with ICs implemented therein can be manufactured by performing various semiconductor processes on a semiconductor substrate such as a wafer using multiple masks. For example, a process using a mask may represent a patterning process using a lithography process. The desired pattern can be formed on the semiconductor substrate or material layer through a patterning process. In this case, the semiconductor process can include Including deposition process, etching process, ion process, cleaning process, etc. In addition, the semiconductor process may include a packaging process of mounting a semiconductor device on a printed circuit board (PCB) and sealing the semiconductor device using a sealant, and may also include a testing process of testing the semiconductor device or package. .

While exemplary embodiments of the inventive concept have been particularly shown and described with reference to some exemplary embodiments thereof, it will be understood that various modifications may be made thereto without departing from the spirit and scope of the following claims. Changes in form and detail.

100_1‧‧‧First synchronization circuit

110‧‧‧Multiplexer

120‧‧‧Main latch

130‧‧‧from latch

a‧‧‧Scan test mode

b‧‧‧Functional operation mode

CLK‧‧‧clock signal

D‧‧‧Second terminal/data input signal

IS1‧‧‧First internal signal

IS2‧‧‧Second internal signal

Q‧‧‧Data output signal

SE‧‧‧Scanning Enablement Signal

SI‧‧‧First terminal/scan input signal

SO‧‧‧Scan output signal

Claims (24)

An integrated circuit (IC) includes: a first synchronous circuit configured to operate synchronously with a clock signal, the first synchronous circuit including: a selector including a first input terminal, a second input terminal and a third input terminals, the first input terminal is configured to receive a first input signal, the second input terminal is configured to receive a second input signal, and the third input terminal is configured to receive a scan enable signal, the The scan enable signal instructs the first synchronization circuit to operate in one of a scan test mode and a functional operation mode; and the reconfigurable latch is configured to operate as a flip-flop in the scan test mode. Selectively switching between operating as a latch in the functional operating mode, such that the reconfigurable latch outputs a first signal corresponding to the first input signal in the scan test mode. output signal and in the functional mode of operation the reconfigurable latch outputs a second output signal corresponding to the second input signal. The integrated circuit as claimed in claim 1, wherein the reconfigurable latch includes: a first node configured to output the first output signal; and a second node configured to output the second output signal. The integrated circuit of claim 1, wherein the selector is configured to select the first scan enable signal in response to the scan enable signal. One of an input signal and the second input signal is output as a first internal signal, and the reconfigurable latch includes a master latch configured to latch based on the clock signal. latching the first internal signal to output a second internal signal; and a slave latch configured to latch the second internal signal based on the clock signal. The integrated circuit as claimed in claim 3, wherein the slave latch is configured to receive the scan enable signal, and the slave latch is configured to operate based on the scan enable signal. Selectively latching the second internal signal. The integrated circuit as claimed in claim 4, wherein in the functional operation mode, the integrated circuit is configured to block the input of the second internal signal to the slave latch. The integrated circuit as described in claim 4, wherein in the functional operation mode, the integrated circuit is configured to block the input of the clock signal to the slave latch. The integrated circuit as described in claim 3 of the patent application, wherein the master latch and the slave latch each include a plurality of transistors, and one of the plurality of transistors of the slave latch The threshold voltage of each of the plurality of transistors of the main latch is higher than the threshold voltage of each of the plurality of transistors of the main latch. The integrated circuit as described in claim 3 of the patent application, wherein in the scan test mode, the slave latch is configured to output the first an output signal, and in the functional mode of operation, the master latch is configured to output the second output signal. The integrated circuit of claim 1, wherein the flip-flop is a negative-edge flip-flop, and the reconfigurable latch includes a high-level enable latch. The integrated circuit of claim 1, wherein the flip-flop is a positive-edge flip-flop, and the reconfigurable latch includes a low-level enable latch. The integrated circuit as described in item 1 of the patent application further includes: a second synchronization circuit configured to: switch between the scan test mode and the functional operation mode based on the scan enable signal. , based on a third input signal, a third output signal is output in synchronization with the clock signal in the scan test mode, the third input signal is the first output signal output from the first synchronization circuit , and based on the received fourth input signal, output a fourth output signal in the functional operation mode. A non-transitory computer-readable medium storing a library of standard cells that contains information about a plurality of standard cells that, when executed by a processor, configures the processor Integrated circuit: Designing an integrated circuit through a synthesis module executed by a processor. The integrated circuit including a synchronization circuit operating in synchronization with the clock signal, the synchronization circuit including: a reconfigurable latch configured to operate as a flip-flop in a scan test mode and in a functional operation in response to a scan enable signal Selectively switching between operating as a latch in the scan test mode such that the reconfigurable latch outputs a first output signal corresponding to a first input signal and operates in the function The reconfigurable latch in the mode outputs a second output signal corresponding to the second input signal. The non-transitory computer-readable medium of claim 12, wherein the synchronization circuit includes a selector configured to select the first input in response to the scan enable signal. One of the signal and the second input signal is output as a first internal signal, and the reconfigurable latch includes a master latch configured to latch the clock signal based on the clock signal. The first internal signal is used to output a second internal signal; and the slave latch is configured to latch the second internal signal based on the clock signal. The non-transitory computer-readable medium as described in claim 13 of the patent application, wherein the standard cell library, when executed by the processor, further configures the processor to convert the integrated circuit design The integrated circuit further includes: a switching element configured to block the input of the clock signal to the slave latch based on the scan enable signal. The non-transitory computer-readable medium as described in claim 13 of the patent application, wherein the standard cell library, when executed by the processor, further configures the processor to convert the integrated circuit design The method is such that: in the scan test mode, the first output signal is output from the slave latch, and in the functional operation mode, the second output signal is output from the master latch. The non-transitory computer-readable medium as described in claim 13 of the patent application, wherein the standard cell library, when executed by the processor, further configures the processor to convert the integrated circuit design This enables the main latch to activate the latch at a high level. The non-transitory computer-readable medium as described in claim 13 of the patent application, wherein the standard cell library, when executed by the processor, further configures the processor to convert the integrated circuit design This causes the main latch to activate the latch for a low level. A computing system includes: a storage device configured to store a standard cell library, the standard cell library including information about a plurality of standard cells, the plurality of standard cells including a plurality of flip-flop latches. a cell and a plurality of flip-flop cells; and a processor configured to execute a synthesis module to design an integrated circuit (IC), the integrated circuit including a scan test circuit having a plurality of synchronization circuits, the plurality of A synchronization circuit is configured to operate in synchronization with the clock signal, so that one of the plurality of synchronization circuits At least one includes: a reconfigurable latch formed using the plurality of standard cells, the reconfigurable latch configured to respond to a scan enable signal having a first logic level. Operates as a flip-flop in the scan test mode and operates as a latch in the functional operation mode in response to the scan enable signal having a second logic level. The computing system of claim 18, wherein the processor is configured to design the standard cells by selecting standard cells respectively corresponding to the plurality of synchronous circuits based on input data and the standard cell library. The integrated circuit, such that the processor is configured to replace the flip-flop latch cell with a first flip-flop latch cell in the plurality of flip-flop latch cells to maintain a timing margin equal to or greater than a specified value. The first flip-flop cell among the plurality of flip-flop cells included in the timing path. The computing system of claim 19, wherein the processor is configured to design the integrated circuit such that in the scan test mode, the input to the flip-flop toggle is The polarity of the clock signal of the reconfigurable latch formed by the first flip-flop latch cell in the latch cell is the same as that input to the plurality of flip-flop latch cells using the plurality of flip-flop latch cells. The polarity of the clock signal of the reconfigurable latch formed by the first flip-flop cell in the cell is opposite. The computing system of claim 18, wherein the processor is configured to design the integrated circuit in the following manner: based on input data and the standard cell library selection, respectively, with the plurality of The standard cell corresponding to the synchronous circuit, Placing and routing the selected standard cells to generate layout data for the integrated circuit and replacing the second flip-flop latch cell with a second flip-flop latch cell in the plurality of flip-flop latch cells. A second flip-flop cell of the plurality of flip-flop cells included in a timing path in which a timing margin is maintained greater than or equal to a specific value in the functional operating mode. The computing system of claim 21, wherein the processor is configured to based on the second flip-flop latch cell input to the plurality of flip-flop latch cells. The clock signal of the cell is re-routed to the selected standard cell. The computing system of claim 18, wherein the processor is configured to design the integrated circuit in the following manner: based on input data and the standard cell library selection, respectively, with the plurality of Synchronizing the standard cells corresponding to the circuit, placing and routing the selected standard cells to generate layout data of the integrated circuit, performing a timing analysis operation on the layout data, and based on the results of the timing analysis operation, Replacing the plurality of flip-flop latch cells in the selected standard cells that violate timing in the functional operating mode with a third flip-flop cell in the plurality of flip-flop cells The third flip-flop latch cell in the element. The computing system as described in item 23 of the patent application, wherein the The processor is configured to reroute the selected criterion based on the clock signal input to the third flip-flop latch cell of the plurality of flip-flop latch cells. cells.