TWI819441B - Package substrate, chip package and integrated circuit chip - Google Patents

Abstract

A packaging substrate has a substrate surface and a chip area located on the substrate surface. The packaging substrate includes a plurality of circuit layers, a plurality of conductive holes, and a plurality of byte area rows. The circuit layers are sequentially spaced below the substrate surface. Each of the circuit layers has multiple traces. Each of the conductive vias is connected to at least two of the circuit layers. The byte area rows are arranged in sequence from the edge of the chip area toward the center of the chip area. Each of the byte area rows includes a plurality of byte areas arranged in a row, each of the byte areas includes multiple pads, and the pads are formed by the circuit layer closest to the substrate surface. The pads of the byte regions of the byte region row closer to the edge of the chip region extend from directly under the chip region through the traces of the circuit layer closer to the substrate surface directly below the outside of the wafer area.

Description

Packaging substrates, chip packages and integrated circuit chips

The present invention relates to a packaging substrate, and in particular to a packaging substrate, a chip package using the packaging substrate, and a corresponding integrated circuit chip mounted on the packaging substrate.

In the field of integrated circuit (IC) design, Double Data Rate Synchronous Dynamic Random Access Memory (DDR) is an IC chip (Chip). Multiple byte blocks to which multiple channels (Channels) for DDR belong are usually arranged on the active surface of the IC chip. Therefore, when the number of these byte area rows increases, it is necessary to optimize the arrangement of these byte area rows on the active surface of the IC chip to improve the area utilization of the IC chip.

The invention provides a packaging substrate for mounting integrated circuit chips to improve the area utilization of the integrated circuit chips.

The invention provides a chip package for packaging integrated circuit chips to improve the area utilization of the integrated circuit chips.

The invention provides an integrated circuit chip to improve the area utilization rate of the integrated circuit chip.

The packaging substrate of the present invention is suitable for mounting an integrated circuit chip in a flip-chip bonding manner, and has a substrate surface and a chip area located on the substrate surface. The packaging substrate includes multiple circuit layers, multiple conductive vias and multiple bit arrays. These circuit layers are arranged at intervals below the substrate surface. Each of these wiring layers has multiple traces. Each of the conductive vias connects at least two of the circuit layers. These bit group rows are arranged side by side in sequence from the edge of the chip area toward the center of the chip area. Each of these byte area rows includes a plurality of byte areas arranged in a row. Each of these byte areas includes a plurality of pads, and these pads are formed by the circuit layer closest to the substrate surface. . The pads of the bit group areas of the bit group area rows closer to the edge of the chip area extend from just below the chip area to just below outside the chip area through the traces of the circuit layer closer to the substrate surface.

The chip package of the present invention includes the above-mentioned packaging substrate and an integrated circuit chip. The integrated circuit chip is mounted on the chip area of the packaging substrate through flip-chip bonding.

The integrated circuit chip of the present invention is suitable for being mounted on the chip area of the above-mentioned packaging substrate by flip-chip bonding.

Based on the above, in the present invention, the pads of the bit group areas of the bit group area rows closer to the edge of the chip area extend from directly below the chip area through the traces of the circuit layer closer to the substrate surface. to just below outside the wafer area. Therefore, the number of side-by-side rows of byte blocks can be increased.

Please refer to FIGS. 1A and 1B . In this embodiment, the chip package 50 includes a chip 52 (ie, an integrated circuit chip 52 ) and a packaging substrate 100 . The chip 52 is suitable for being mounted on the packaging substrate 100 in a flip-chip bonding manner. Specifically, the chip 52 has an active surface 52a and a plurality of chip pads 52b located on the active surface 52a, and the package substrate 100 has a substrate surface 100a, a chip area 100b located on the substrate surface 100a and a chip area 100b located on the substrate surface 100a. A plurality of pads p in area 100b (also seen as pads p in FIG. 2). The die pads 52b of the die 52 may be mounted to the pads p located in the die area 100b via a plurality of conductive bumps 54. In this embodiment, the signal distribution of the pads p located in the projected area below the chip 52 is in a mirror image relationship with the chip pads 52b on the active surface 52a of the chip 52.

Please refer to FIG. 1B and FIG. 2 to FIG. 7 . In this embodiment, the packaging substrate 100 of FIG. 1B includes a plurality of circuit layers 110 (also visible in the circuit layers 100 (L1-L9) of FIG. 3 ) and a plurality of conductive vias. 120 (conductive via). Figures 5, 6 and 7 are schematic plan views of the first circuit layer 110 (L1), the second circuit layer 110 (L2) and the fourth circuit layer 110 (L4) of Figure 3 respectively. These circuit layers 110 are arranged at intervals below the substrate surface 100a. Each of these circuit layers 110 has a plurality of traces t (as shown in FIG. 2 and also seen in FIGS. 6 and 7 ). Each of the conductive vias 120 connects at least two of the circuit layers 110 . In other words, any two of the circuit layers 110 can be electrically connected to each other via the conductive vias 120 .

In this embodiment, under the application of DDR or similar parallel signals, the packaging substrate 100 includes a plurality of byte banks. In FIG. 2 , three byte area rows r1 , r2 , and r3 are taken as an example, and in FIGS. 3 to 7 , four byte area rows r1 , r2 , r3 , and r4 are used as an example. FIG. 2 is a partial top view near the bottom side of the chip area 100b of the packaging substrate 100, which is composed of a plurality of circuit layers 110. As can be seen from FIG. 2, on an orthographic projection plane, these bit group areas are arranged r1, r2, r3 are arranged side by side in sequence from the edge of the wafer area 100b toward the center of the wafer area 100b. The side-by-side arrangement mentioned here means that these byte block rows r1, r2, and r3 are arranged adjacently in sequence in such a manner that their length directions are parallel to each other. In other words, these byte area rows r1, r2, and r3 are all arranged in the first direction (for example: Y direction). Therefore, the edge length in the second direction (eg, X direction) can be reduced, and the edge length corresponding to the second direction (eg, X direction) of the wafer 52 can also be reduced. Each of these byte area rows r1, r2, r3 (eg r1 or r2 or r3) includes a plurality of byte areas B arranged in a row. In other words, in the second direction (for example: X direction), these byte blocks B arranged in the same row form the same byte block row (for example, r1 or r2 or r3), which supports signal transmission of the same channel. In addition, corresponding to each bit group row of the chip 52, the chip pads 52b are arranged in the same manner as each other, or in a mirror image arrangement. For example: the chip pads 52b constituting the bit group row r1 and the chip pads 52b constituting the bit group row r2 are arranged in the same manner. Alternatively, the chip pads 52b constituting the bit group row r1 and the chip pads 52b constituting the bit group row r2 are arranged in a mirror image relationship along a line of symmetry.

In order to simplify the diagram, in Figure 2, the number of these byte areas B in the same byte area row is two as an example. In Figures 4 to 7, these bits in the same byte area row are The number of tuple areas B is four, but is not limited to these numbers. Each of these byte areas B includes a plurality of pads p (ie, the pads p connected to the conductive bumps 54 in FIG. 1B ). The pads p can be arranged in parallel (as shown in Figure 2) or staggered (not shown). These pads p are composed of the circuit layer 110 closest to the substrate surface 100a (ie, the circuit layer 110 (L1) in FIG. 3).

In this embodiment, the pads p of the bit group areas B closer to the bit group area row r at the edge of the chip area 100b pass through the traces t of the circuit layer 110 closer to the substrate surface 100a from the chip area. Directly below 100b extends to directly below outside the wafer area 100b. For example: as shown in the second circuit layer 110 (L2) of FIG. 6, the pads p of the bit group areas B of the bit group area row r1 close to the edge of the chip area 100b pass through the circuit layer close to the substrate surface 100a. These traces t2 of 110 (L2) extend from directly below the wafer area 100b to directly below outside the wafer area 100b. On the other hand, the pads p of the bit group areas B in the bit group area row r that are farther away from the edge of the chip area 100b pass through the traces t of the circuit layer 110 that are farther away from the substrate surface 100a from the chip area 100b. Directly below extends to directly below outside the wafer area 100b. For example: as shown in the fourth circuit layer 110 (L4) of FIG. 7, the pads p of the bit group areas B of the bit group area row r2 far away from the edge of the chip area 100b pass through the circuit layer far away from the substrate surface 100a. These traces t4 of 110 (L4) extend from directly below the wafer area 100b to directly below outside the wafer area 100b.

In this embodiment, under the application of DDR or similar parallel signals, these circuit layers 100 include a circuit layer for signal transmission and a circuit layer for providing power/ground, and conductive vias 120 are electrically connected between the two circuit layers. connection. Moreover, the line layers (L2, L4, L6, and L8) mainly with signal transmission functions can be located respectively in the two line layers (L1 and L3, L3 and L5, L5 and L7, or L7 and L9) mainly with power/ground functions. ) between. In an embodiment not shown, the circuit layers (L2, L4, L6 and L8) mainly with power/ground functions can be respectively located in the two circuit layers (L1 and L3, L3 and L5) mainly with signal transmission functions. , L5 and L7 or L7 and L9). It can be seen from FIG. 3 to FIG. 7 that in this embodiment, it is assumed that there are four byte area rows r1, r2, r3, and r4 in the first direction (for example: the Y direction in FIG. 2) from the area close to the wafer area 100b. The edges are gradually arranged away from the chip area 100. The pads p in these bit group area rows r1, r2, r3, and r4 will respectively pass through these of the circuit layer 110 (L2, L4, L6, L8) of the substrate surface 100a. The trace t extends from directly below the chip area 100b to directly below the outside of the chip area 100b, with the circuit layer 110 (L2), the circuit layer 110 (L4), the circuit layer 110 (L6), and the circuit layer 110 (L8) gradually moving away from each other. Substrate surface 100a. Although the figure only shows the circuit layer 110 (L2) and the circuit layer 110 (L4), it can be inferred that the byte area r3 will also configure wiring on the circuit layer 110 (L6) to transmit the signal from the chip area 100b. Directly below extends to directly below outside the chip area 100b, which is not shown in the drawing. In addition, the byte area row r4 will be configured with traces on the circuit layer 110 (L8) to extend the signal from directly below the chip area 100b to directly below the chip area 100b, which is also not shown in the figure.

It can be seen from the above that compared with the known technology that arranges multiple byte areas r in succession in the X direction of the chip or packaging substrate, the present invention arranges the multiple byte areas r with their length directions parallel to each other. are arranged adjacently in sequence, which can reduce the edge length of the chip or packaging substrate in the X direction. In addition, the multiple byte rows r of the present invention are continuously arranged along the Y direction of the chip or the packaging substrate with their widths, so the multiple byte rows will not cause edges in the Y direction of the chip or the packaging substrate. Too long issue. In particular, the plurality of wafer pads 52b on the active surface 52a of the wafer 52, the corresponding bit group area rows r1, r2, r3, r4 are arranged side by side in sequence from the edge of the wafer area 100b toward the center of the wafer area 100b. , therefore, the edge length of the wafer 52 in the second direction (for example, the X direction) can be reduced.

Please refer to Figure 2 again. In this embodiment, Pmin represents the minimum distance between two pads (bumps) p. W represents the width of the function unit (ie, byte area B). H represents the height of the functional unit (ie, byte area B). D represents the outer diameter of the pad p (bump 54). G represents the spacing between two (bump 54) pads p on adjacent edges of the functional unit (ie, the two byte areas B). T1 represents the width of the signal trace t in the chip area 100b. S1 represents the spacing between two signal traces t. T2 represents the width of the signal trace t outside the chip area 100b. Lmax represents the maximum length of the signal trace t in the chip area 100b. n1 represents the number of signal traces t between two (bump 54) pads p. n2 represents the number of signal traces t between two functional units (ie, byte area B).

In this embodiment, Pmin = n1T1 + (n1+1)S1 + D. In other words, the minimum distance Pmin between two adjacent pads p of one of the byte areas B belonging to a single byte area row (for example: r1 in Figure 2) is equal to the minimum distance Pmin between the two adjacent pads p located in these phases. The number n1 of these traces t between adjacent pads p is multiplied by the width T1 of the portion of trace t directly below the die area 100b, the number n1 of these traces t between these adjacent pads p plus one and then multiplied by Take the sum of the spacing S1 of these traces t and the outer diameter D of any one of these pads p.

In this embodiment, G = n2T1 + (n2+1)S1 + D. In other words, the minimum distance between two adjacent byte areas B belonging to a single byte area row (for example: r3 in Figure 2) is equal to the distance between these adjacent byte areas B. The number n2 of these traces t is multiplied by the width of the part of the trace t directly below the chip area 100b, the number n2 of these traces t between the adjacent bit group regions B is multiplied by one, and then multiplied by the width of the traces The sum of the spacing t and the outer diameter D of any one of these pads p.

In this embodiment, S1 ≧ 2×T1. In other words, the spacing S1 between two adjacent traces t is greater than or equal to twice the line width T1 of the traces t in the chip area 100b.

In this embodiment, the thinner trace t-impedance (trace impedance) of T1 is equal to the thicker trace t-impedance of T2 ± 30%. In other words, the impedance of the portion directly below each of these thinner traces t within the die area 100b is 0.7 to 1.3 times the impedance of the portion directly below the thicker trace t outside the die area 100b. The trace impedance inside and outside the die area is related to the trace width.

In this embodiment, Lmax is greater than 2 millimeters (mm). In other words, taking r3 in FIG. 2 as an example, the distance directly below each of these traces t in the chip area 100b is greater than 2 mm.

In this embodiment, G is greater than Pmin. In other words, one of the pads p belonging to one of the byte areas B of a single byte area row (for example: r3 of FIG. 2) is the same as one of the pads p belonging to the same single byte area row (for example: r3 of FIG. 2). r3) The distance between the nearest adjacent pads p of the byte areas B is greater than the distance between the closest ones of the pads p of the byte areas B belonging to a single byte area row (for example: r3 in Figure 2). The minimum distance Pmin between two adjacent pads p.

In this embodiment, W≦4×Pmin. In other words, each of these byte areas B is located within the byte area B, and the width of the byte area B is less than or equal to the width between two adjacent pads p of the byte area B. Four times the minimum spacing Pmin.

In this embodiment, the traces t connected to the pads p of the bit group rows farther away from the edge of the chip area 100b (for example: r2, r3, r4 relative to r1) are on the substrate surface 100a. The orthographic projection of the pads p of the bit group area rows (for example: r1) closer to the edge of the chip area 100b overlaps with the orthographic projection of the pads p on the substrate surface 100a. In some embodiments, the orthographic projections of the traces t connected to the pads p of different bit group regions on the substrate surface 100a do not completely overlap.

Please refer to FIG. 8 . In this embodiment, the packaging substrate 100 includes a plurality of byte area rows r1 , r2 , and r3 . These byte area rows r1, r2, and r3 are arranged side by side in sequence from an edge of the chip area 100b toward the center of the chip area 100b. In addition, the packaging substrate 100 further includes a plurality of byte area rows r4, r5, and r6. These byte area rows r4, r5, and r6 are arranged side by side in sequence from the other edge of the chip area 100b toward the center of the chip area 100b. Compared with the known technology that arranges multiple byte areas r in succession in the X direction of the chip or packaging substrate, the present invention arranges the multiple byte areas r in sequence in such a way that their length directions are parallel to each other. Arranged adjacently, this can reduce the edge length of the chip or packaging substrate in the X direction. In addition, the multiple byte rows r of the present invention are continuously arranged along the Y direction of the chip or the packaging substrate with their widths, so the multiple byte rows will not cause edges in the Y direction of the chip or the packaging substrate. Too long issue.

Please refer to FIG. 9 . In this embodiment, the packaging substrate 100 includes a plurality of byte area rows r1 , r2 , r3 , and r4 . These byte area rows r1, r2, r3, and r4 are arranged side by side in sequence from an edge of the chip area 100b toward the center of the chip area 100b. In addition, the packaging substrate 100 further includes a plurality of byte area rows r5, r6, r7, and r8. These byte area rows r5, r6, r7, and r8 are arranged side by side in sequence from the other edge of the chip area 100b toward the center of the chip area 100b. Compared with the known technology that arranges multiple byte areas r in succession in the X direction of the chip or packaging substrate, the present invention arranges the multiple byte areas r in sequence in such a way that their length directions are parallel to each other. Arranged adjacently, this can reduce the edge length of the chip or packaging substrate in the X direction. In addition, the multiple byte rows r of the present invention are continuously arranged along the Y direction of the chip or the packaging substrate with their widths, so the multiple byte rows will not cause edges in the Y direction of the chip or the packaging substrate. Too long issue.

To sum up, in the present invention, in addition to the arrangement of multiple byte area rows, the pads of the bit area rows closer to the edge of the chip area are connected via the closer These traces of the circuit layer on the substrate surface extend from directly below the chip area to directly below outside the chip area. Therefore, the number of side-by-side bit group rows can be increased, and the required length of the edge of the active surface of the chip can be reduced, thereby improving the area utilization of the integrated circuit chip and preventing the chip from being too large.

50: Chip package 52:wafer 52a: Active side 52b:wafer pad 54: Conductive bumps 100:Package substrate 100a:Substrate surface 100b: Chip area 110: Line layer 120: Conductive channel B: Byte area p:pad r1, r2, r3, r3, r5, r6, r7, r8: Byte area arrangement (r) t, t2, t4: wiring D:Outer diameter G: spacing H: height Pmin: minimum spacing Lmax: maximum length S1: spacing T1: Width T2: Width W: Width

1A and 1B are respectively a top view and a side view of a chip package according to an embodiment of the present invention. FIG. 2 is a partial top view of the package substrate of FIG. 1A near the bottom side of the chip area. FIG. 3 is a schematic perspective view of multiple byte areas and multiple circuit layers of the packaging substrate of FIG. 1A . FIG. 4 is a schematic plan view of multiple byte areas of FIG. 3 . FIG. 5 is a schematic plan view of the first circuit layer 100 (L1) of FIG. 3 . FIG. 6 is a schematic plan view of the second circuit layer 100 (L2) of FIG. 3 . FIG. 7 is a schematic plan view of the fourth circuit layer 100 (L4) of FIG. 3 . FIG. 8 is a top view of a chip package according to another embodiment of the present invention. FIG. 9 is a top view of a chip package according to yet another embodiment of the present invention.

100b: Chip area

B: Byte area

p:pad

r1, r2, r3: Byte area arrangement

t: trace

D:Outer diameter

G: spacing

H: height

Pmin: minimum spacing

Lmax: maximum length

S1: spacing

T1:width

T2:Width

W: Width

Claims (25)

A packaging substrate is suitable for mounting an integrated circuit chip in a flip-chip bonding manner, and has a substrate surface and a chip area located on the substrate surface. The packaging substrate includes: A plurality of circuit layers are arranged at intervals below the substrate surface in sequence, wherein each of the circuit layers has a plurality of traces; A plurality of conductive vias, each of the conductive vias connecting at least two of the circuit layers; and A plurality of byte area rows are arranged side by side in sequence from the edge of the chip area toward the center of the chip area, wherein each of the byte area rows includes a plurality of byte areas arranged in a row. Each of the bit areas includes a plurality of pads, the pads are composed of the circuit layer closest to the substrate surface, and the bits of the bit area rows closer to the edge of the chip area The pads in the group area extend from directly below the chip area to directly below outside the chip area through the traces of the circuit layer closer to the substrate surface. The package substrate according to claim 1, wherein the distance between two adjacent ones of the traces is greater than or equal to twice the line width of the traces. The packaging substrate as claimed in claim 1, wherein the impedance of the portion of each of the traces directly below the chip area is 0.7 to 1.3 of the impedance of the portion of the trace directly below the chip area. times. The packaging substrate of claim 1, wherein the distance between each of the traces directly below the chip area is greater than 2 mm. The packaging substrate of claim 1, wherein the minimum distance between two adjacent pads of one of the byte regions belonging to a single byte region row is equal to the distance between the adjacent pads. The number of the traces between the pads is multiplied by the width of the part of the trace directly under the chip area, the number of the traces between the adjacent pads is multiplied by one and multiplied by the width of the traces. The distance between the lines and the sum of the outer diameter of any one of the pads. The packaging substrate as claimed in claim 1, wherein the minimum distance between two adjacent byte areas belonging to a single byte area row is equal to the distance between the adjacent byte areas. The number of the traces is multiplied by the width of the part of the trace directly under the chip area, the number of the traces between the adjacent bit groups plus one, multiplied by the spacing of the traces. , the sum of the outer diameter of any one of the pads. The packaging substrate of claim 1, wherein one of the pads belonging to one of the byte areas of a single byte area row and the bit cells belonging to the same single byte area row The distance between the most adjacent pads of the group area is greater than the minimum distance between two adjacent pads of one of the bit areas belonging to a single bit area row. The package substrate as claimed in claim 1, wherein each of the byte areas is located within a byte area, and the width of the byte area is less than or equal to the phase of the pads of the byte area. Four times the minimum distance between adjacent two. A chip package including: A packaging substrate has a substrate surface and a chip area located on the substrate surface. The packaging substrate includes: A plurality of circuit layers are arranged at intervals below the substrate surface in sequence, wherein each of the circuit layers has a plurality of traces; A plurality of conductive vias, each of the conductive vias connecting at least two of the circuit layers; and A plurality of byte area rows are arranged side by side in sequence from the edge of the chip area toward the center of the chip area, wherein each of the byte area rows includes a plurality of byte areas arranged in a row. Each of the bit areas includes a plurality of pads, the pads are composed of the circuit layer closest to the substrate surface, and the bits of the bit area rows closer to the edge of the chip area The pads in the group area extend from directly below the chip area to directly below outside the chip area through the traces of the circuit layer closer to the substrate surface; and An integrated circuit chip is mounted on the chip area of the packaging substrate in a flip-chip bonding manner. The chip package as claimed in claim 9, wherein the distance between two adjacent ones of the traces is greater than or equal to twice the line width of the traces. The chip package of claim 9, wherein the impedance of the portion of each of the traces directly below the chip area is 0.7 to 0.7 to the impedance of the portion of the trace directly below the chip area. 1.3 times. The chip package of claim 9, wherein the distance between each of the traces directly below the chip area is greater than 2 mm. The chip package of claim 9, wherein the minimum distance between two adjacent pads of one of the byte regions belonging to a single byte region row is equal to the distance between the adjacent pads of the byte regions. The number of traces between adjacent pads is multiplied by the width of the portion of the trace directly below the chip area, the number of traces between adjacent pads plus one is multiplied by the The spacing of the traces and the sum of the outer diameters of any of the pads. The chip package of claim 9, wherein the minimum distance between two adjacent byte areas belonging to a single byte area row is equal to the distance between the adjacent byte areas. The number of the traces is multiplied by the width of the part of the trace directly below the chip area, the number of the traces between the adjacent bit group areas plus one, multiplied by the width of the traces spacing, and the sum of the outer diameters of any of the pads. The chip package of claim 9, wherein one of the pads belonging to one of the byte regions of a single byte region and the bits belonging to the same single byte region are The distance between the most adjacent pads of the tuple area is greater than the minimum distance between two adjacent pads of one of the byte areas belonging to a single byte area row. . The chip package of claim 9, wherein each of the byte regions is located within a byte region, and the width of the byte region is less than or equal to the width of the pads of the byte region. Four times the minimum distance between two adjacent ones. An integrated circuit chip is suitable for being mounted in a chip area of a packaging substrate in a flip-chip bonding manner. The chip area is located on a substrate surface of the packaging substrate. The packaging substrate includes: A plurality of circuit layers are arranged at intervals below the substrate surface in sequence, wherein each of the circuit layers has a plurality of traces; A plurality of conductive vias, each of the conductive vias connecting at least two of the circuit layers; and A plurality of byte area rows are arranged side by side in sequence from the edge of the chip area toward the center of the chip area, wherein each of the byte area rows includes a plurality of byte areas arranged in a row. Each of the bit areas includes a plurality of pads, the pads are composed of the circuit layer closest to the substrate surface, and the bits of the bit area rows closer to the edge of the chip area The pads in the group area extend from directly below the chip area to directly below outside the chip area through the traces of the circuit layer closer to the substrate surface. The integrated circuit chip of claim 17, wherein the chip has an active surface and a plurality of chip pads located on the active surface, and the packaging substrate has a plurality of contact pads located in the chip area, and the chip pads The signal distribution of the pads, which are respectively mounted to the pads through a plurality of conductive bumps and located in the projection area below the chip, is in a mirror image relationship with the chip pads on the active surface of the chip. The integrated circuit chip of claim 17, wherein the distance between adjacent two of the traces is greater than or equal to twice the line width of the traces. The integrated circuit chip as claimed in claim 17, wherein the impedance of the portion directly below each of the traces within the chip area is 0.7 of the impedance of the portion of the trace directly below the chip area outside the chip area. to 1.3 times. The integrated circuit chip of claim 17, wherein the distance between each of the traces directly below the chip area is greater than 2 mm. The integrated circuit chip of claim 17, wherein the minimum spacing between two adjacent pads of one of the byte areas belonging to a single byte area row is equal to the distance between the pads located in the byte area row. The number of traces between adjacent pads is multiplied by the width of the portion of the trace directly below the chip area, the number of traces between adjacent pads plus one is multiplied by the The total distance between the traces and the outer diameter of any one of the pads. The integrated circuit chip of claim 17, wherein the minimum distance between two adjacent byte areas belonging to a single byte area row is equal to the distance between the adjacent byte areas. The number of the traces between the traces is multiplied by the width of the part of the trace directly below the chip area, the number of the traces between the adjacent bit group regions is multiplied by one and then multiplied by the width of the traces spacing and the sum of the outer diameters of any one of the pads. The integrated circuit chip of claim 17, wherein one of the pads belonging to one of the byte regions of a single byte region row and the pads belonging to the same single byte region row The distance between the nearest adjacent pads of the byte area is greater than the minimum distance between two adjacent pads of one of the byte areas belonging to a single byte area row. spacing. The integrated circuit chip of claim 17, wherein each of the byte areas is located within a byte area, and the width of the byte area is less than or equal to the pads of the byte area. Four times the minimum distance between two adjacent ones.

Images