TWI818528B - Control device and control method thereof - Google Patents

Abstract

A control device configured to drive a display device including a first channel and a second channel includes a first output device, a second output device, a first delay generator, a second delay generator, a first multiplexer, and a second multiplexer. The first output device outputs first transfer data according to an enable signal. A second output device outputs second transfer data according to the enable signal. The first delay generator counts a first delay time to generate a first trigger signal according to the enable signal. The second delay generator counts a second delay time to generate a second trigger signal according to the enable signal. The first multiplexer provides the first transfer data to the first channel according to the first trigger signal. The second multiplexer provides the second transfer data to the second channel according to the second trigger signal.

Description

Control device and control method thereof

The present invention relates to a control device and a control method for a display device, and in particular to a control device and a control method for time-dividing display units of different channels to reduce resistance voltage drop.

The driving of the backlight panel can be realized by various interface signals. Bi-phase Mark Code (BMC) is a signal interface for driving the backlight panel. In backlight drive systems of different sizes, the resistance voltage drop (IR drop) of the supply voltage of the display device will affect the overall power consumption and the clarity of the screen. Therefore, it is necessary to optimize the control method of the backlight panel to reduce the voltage drop of the supply voltage of the display device.

The present invention hereby proposes a control device and a control method for time-sharing the display units of different channels of the display device to reduce the voltage drop of the supply voltage of the display device, by staggering the time when different channels of different display devices receive the preamble and Adjust the bit width ratio of logic 0 and logic 1 to reduce the number of display units that are turned on at the same time. number, thereby reducing the degree of voltage drop in the supply voltage of the display device.

In view of this, the present invention proposes a control device for driving a display device, wherein the display device includes a first channel and a second channel. The above control device includes a first output device, a second output device, a first delay generator, a second delay generator, a first multiplexer and a second multiplexer. The above-mentioned first output device outputs a first transfer data according to the enable signal. The above-mentioned second output device outputs a second transfer data according to the above-mentioned enable signal. The first delay generator counts a first delay time according to the enable signal to generate a first trigger signal. The second delay generator counts a second delay time according to the enable signal to generate a second trigger signal. The first multiplexer provides the first transfer data to the first channel according to the first trigger signal. The second multiplexer provides the second transfer data to the second channel according to the second trigger signal.

According to an embodiment of the present invention, each of the first delay generator and the second delay generator includes a counter, a register and a comparator. The counter counts a first time or a second time according to the enable signal and a clock signal. The above-mentioned register is used to store the above-mentioned first delay time or the above-mentioned second delay time. The comparator compares the first time and the first delay time to generate the first trigger signal, or compares the second time and the second delay time to generate the second trigger signal. When the first time is equal to the first delay time, the comparator generates the first trigger signal. When the second time is equal to the second delay time, the comparator generates the second trigger signal.

According to an embodiment of the present invention, the first delay time and the second delay time are different.

According to an embodiment of the present invention, the above-mentioned first output device and the One of the second output devices further includes a bit width controller, a bit time adjuster and a data generator. The above-mentioned bit width controller generates a control signal according to the bit width ratio. The above-mentioned bit time adjuster generates an adjustment signal according to a clock signal, the above-mentioned enable signal and the above-mentioned control signal. The above-mentioned data generator converts an input data into a transfer data according to the above-mentioned enable signal and the above-mentioned adjustment signal. The transfer data includes at least one first logic bit and at least one second logic bit, wherein the ratio of the bit width of the first logic bit and the bit width of the second logic bit is the bit width. Compare.

According to an embodiment of the present invention, the bit width ratio of the first transfer data and the bit width ratio of the second transfer data are different.

The present invention further provides a control method for driving a display device, wherein the display device includes a first channel and a second channel. The above control method includes outputting a first transfer data and a second transfer data according to the enable signal; counting a first delay time and a second delay time according to the enable signal to respectively generate a first trigger signal and a second trigger signal; providing the first transfer data to the first channel according to the first trigger signal; and providing the second transfer data to the second channel according to the second trigger signal.

According to an embodiment of the present invention, the step of counting the first delay time and the second delay time according to the enable signal to generate the first trigger signal and the second trigger signal respectively further includes using a register. , store the above-mentioned first delay time and the above-mentioned second delay time; count a first time and a second time according to the above-mentioned enable signal and a clock signal; when the above-mentioned first time is equal to the above-mentioned first delay time, generate the above-mentioned first trigger signal; and when the above-mentioned second time is equal to the above-mentioned second delay time, the above-mentioned second trigger signal is generated.

According to an embodiment of the present invention, the first delay time is different from the second delay time.

According to an embodiment of the present invention, the step of outputting the first transfer data and the second transfer data according to the enable signal further includes generating a first control signal according to a first element width ratio; according to a second The bit width ratio generates a second control signal; according to a clock signal, the above-mentioned enable signal and the above-mentioned first control signal, a first adjustment signal is generated; according to the above-mentioned clock signal, the above-mentioned enable signal and the above-mentioned second control signal signal to generate a second adjustment signal; convert a first input data into the first transfer data according to the enable signal and the first control signal; and convert a first input data into the first transfer data according to the enable signal and the second control signal. The second input data is converted into the above-mentioned second transfer data.

According to an embodiment of the present invention, the first transfer data includes at least one first logical bit and at least one second logical bit, wherein the bit width of the first logical bit of the first transfer data and the above-mentioned third logical bit are The ratio of the bit widths of the two logical bits is the above-mentioned first bit width ratio, wherein the above-mentioned second transfer data includes at least one first logical bit and at least one second logical bit, wherein the above-mentioned second transfer data The ratio of the bit width of the first logic bit to the bit width of the second logic bit is the second bit width ratio.

10:Display device

100:Control device

111: First output device

112: Second output device

11N: Nth output device

121: First delay generator

122: Second delay generator

12N: Nth delay generator

131:First multiplexer

132: Second multiplexer

13N:Nth multiplexer

210,700: Transfer data

220: Delayed transfer of data

300: Delay generator

310: Counter

320: Temporary register

330: Comparator

400:Output device

410: Bit width controller

420:Bit time adjuster

430:Data generator

800,1000:Output device

810,900: Preamble generator

820: Function code generator

920: Preamble value register

930:Bit counter

940: Preamble shift register

950: Bit number comparator

1010: Function code generator

1011: Function code number register

1012: Function code register

1013: Function code counter

1014: Function code shift register

1015: Function code number comparator

1020: Lookup table register

1030: Lookup table comparator

1040: Width counter

1050: Bit width comparator

1060:Bit generator

1200:Control method

SC: control signal

SAD: adjust signal

TM: established time

CLK: clock signal

PRE: preamble

FNC: function code

DTC: data code

CC: command code

CC1: first command code

CC2: Second command code

CC3: third command code

CC4: fourth command code

D1: first data

D2: Second data

DM: Mth data

EOP: end of packet

Idle: idle state

P1: number of bits

P2: Number of function codes

PV: established value

ENPRE: preamble enable signal

ENFC: function code enable signal

CV1: first count value

CV2: second count value

SFT1: first shift signal

SFT2: second shift signal

BTC: bit code

BMC: bidirectional marking code

CH1: first channel

CH2: Second channel

CHN: Channel N

CNT: counting signal

HBP: half bit pulse

FBP: full bit pulse

LUT: lookup table

DI: input data

DI1: first input data

DI2: Second input data

DIN: Nth input data

DT: transfer data

DT1: first transfer data

DT2: Second transfer data

DTN: Nth transfer data

EN: enable signal

DLY: delay time

DLY1: first delay time

DLY2: second delay time

DLYN: Nth delay time

TR: trigger signal

TR1: first trigger signal

TR2: second trigger signal

TRN: Nth trigger signal

DDT1: first delayed transfer data

DDT2: Second delayed transfer data

DDTN: Nth delayed transfer data

DL: Default logic level

S1210~S1230: step process

Figure 1 is a block diagram showing a control device according to an embodiment of the present invention; Figures 2A-2B are schematic diagrams showing data transfer according to an embodiment of the present invention; Figure 3 is a block diagram showing a delay generator according to an embodiment of the present invention; Figure 4 is a block diagram showing an output device according to an embodiment of the present invention; Figure 5 is a block diagram showing a delay generator according to an embodiment of the present invention. A diagram showing the relationship between input data and converted data according to an embodiment of the present invention; Figures 6A-6B show waveform diagrams of converted data according to an embodiment of the present invention; Figure 7 shows a waveform diagram according to another embodiment of the present invention. A schematic diagram of transferring data according to one embodiment; Figure 8 shows a block diagram of an output device according to another embodiment of the present invention; Figure 9 shows a pre-processor according to one embodiment of the present invention. A block diagram of a code generator; Figure 10 is a block diagram of an output device according to another embodiment of the present invention; Figure 11 is a block diagram of a bit code and a bi-phase signal according to an embodiment of the present invention. A relationship diagram of tag codes; and Figure 12 is a flow chart showing a control method according to an embodiment of the present invention.

The following description is an embodiment of the present invention. The purpose is to illustrate the general principles of the present invention and should not be regarded as a limitation of the present invention. The scope of the present invention shall be determined by the scope of the patent application.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions , layers, and/or sections should not be limited by these terms, and these terms are only used to distinguish between different elements, components, regions, layers, and/or sections. Therefore, as discussed below a first element, component, region, layer, And/or a portion could be termed a second element, component, region, layer, and/or portion without departing from the teachings of some embodiments of the present disclosure.

It is worth noting that the following disclosure may provide multiple embodiments or examples for practicing different features of the present invention. The specific component examples and arrangements described below are only used to briefly illustrate the spirit of the present invention and are not intended to limit the scope of the present invention. In addition, the following description may reuse the same component symbols or words in multiple examples. However, the purpose of repeated use is only to provide a simplified and clear description, and is not intended to limit the relationship between multiple embodiments and/or configurations discussed below. In addition, the following description of one feature being connected to, coupled to, and/or formed on another feature may actually include multiple different embodiments, including the features being in direct contact, or including other additional features. features are formed between such features, etc., such that the features are not in direct contact.

Figure 1 is a block diagram showing a control device according to an embodiment of the present invention. As shown in FIG. 1 , the control device 100 is coupled to the display device 10 , where the display device 10 includes a first channel CH1 , a second channel CH2 , . . . and an Nth channel CHN. According to some embodiments of the present invention, the first channel CH1, the second channel CH2, ... and the N-th channel CHN each include at least one display unit.

The control device 100 includes a first output device 111, a second output device 112, ..., an N-th output device 11N, a first delay generator 121, a second delay generator 122, ..., an N-th delay generator 12N. , the first multiplexer 131, the second multiplexer 132, ... and the Nth multiplexer 13N.

The first output device 111, the second output device 112, ... and the N-th output device 11N respectively convert the first input data DI1, the second input data DI2, ... and the N-th input data according to the enable signal EN. DINs are converted into first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN. The first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N respectively count the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time according to the enable signal EN. Delay time DLYN, and generate the first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN correspondingly.

According to an embodiment of the present invention, the first multiplexer 131, the second multiplexer 132, ... and the N-th multiplexer 13N respectively operate according to the first trigger signal TR1, the second trigger signal TR2,... and the Nth trigger signal TRN, and provide the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN to the corresponding first channel CH1, the second channel CH2,... and the Nth transfer data The channel CHN is the first delayed transfer data DDT1, the second delayed transfer data DDT2, ... and the Nth delayed transfer data DDTN.

According to another embodiment of the present invention, when the first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N have not yet counted the first delay time DLY1, the second delay time DLY2, . ..and the Nth delay time DLYN, the corresponding first trigger signal TR1, second trigger signal TR2,...and Nth trigger signal TRN are not generated.

In other words, after the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN are respectively delayed by the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN, Then provided to the corresponding first channel CH1, second channel CH2, ... and Nth channel CHN.

According to an embodiment of the present invention, when any one of the first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N has not counted to the first delay time DLY1, the second delay time DLY2,...and the Nth delay time When DLYN, the first multiplexer 131, the second multiplexer 132, ... and the N-th multiplexer 13N provide the preset logic level DL to the first channel CH1, the second channel CH2,... .and the corresponding one of the Nth channel CHN. According to an embodiment of the present invention, the preset logic level DL may be a high logic level. According to another embodiment of the present invention, the preset logic level DL may be a low logic level.

According to an embodiment of the present invention, the first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N are different from each other, and the first delay time DLY1, the second delay time DLY2, ... .and the Nth delay time DLYN are different from each other.

According to another embodiment of the present invention, at least two of the first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N are the same, and the first delay time DLY1, the second delay generator 12N are the same. At least two of the delay times DLY2, ... and the Nth delay time DLYN are the same. In other words, the first predetermined number of output devices share the first delay time generated by the first delay generator, and the second predetermined number of output devices share the second delay time generated by the second delay generator. This is for explanation and explanation only as shown in Figure 1 and is not limited thereto in any way.

Figures 2A-2B are schematic diagrams showing data transfer according to an embodiment of the present invention. As shown in Figure 2A, the transfer data 210 includes the preamble PRE, the first data D1, the second data D2, ..., the Mth data DM and the end of the packet EOP. According to an embodiment of the present invention, the transfer data 210 corresponds to the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN in Figure 1.

The preamble PRE is used to initialize the display unit of the first channel CH1, the second channel CH2, ... and the Nth channel CHN of the display device 10 in Figure 1. The first data D1, the second data D2, ...and the Mth data DM is used to transmit control The control data of the corresponding display unit. The end of packet EOP is used to indicate the end of transmission.

According to an embodiment of the present invention, before the preamble PRE and after the end of the packet EOP, the transfer data 210 is in the idle state Idle. As shown in the embodiment of FIGS. 2A-2B, the transfer data 210 in the idle state is at a high logic level. According to another embodiment of the present invention, the transfer data 210 in the idle state may also be at a low logic level.

According to an embodiment of the present invention, when the idle state Idle is at a high logic level and the transfer data 210 is transmitted with the least significant bit (Least Significant Bit, LSB) first, the preamble PRE is 0xAA to facilitate generating the most Number of logical conversions. According to another embodiment of the present invention, when the idle state Idle is at a high logic level and the transfer data 210 is transmitted with the most significant bit (Most Significant Bit, MSB) first, the preamble PRE is 0x55 to facilitate generation of Maximum number of logical transformations.

According to another embodiment of the present invention, when the idle state Idle is at a low logic level and the transfer data 210 is transmitted with the least significant bit (Least Significant Bit, LSB) first, the preamble PRE is 0x55. According to another embodiment of the present invention, when the idle state Idle is at a low logic level and the transfer data 210 is transmitted with the most significant bit (Most Significant Bit, MSB) first, the preamble PRE is 0xAA.

As shown in FIG. 2B , the delay transfer data 220 further includes the delay time DLY compared to the transfer data 210 . According to an embodiment of the present invention, the delayed transfer data 220 corresponds to the first delayed transfer data DDT1, the second delayed transfer data DDT2, ... and the Nth delayed transfer data DDTN in Figure 1, where the delay time DLY corresponds to To the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN in Figure 1. In other words, the delayed transfer data 220 is delayed by the delay time DLY from the transfer data 210 before starting to provide the preamble PRE.

In other words, as shown in the embodiment shown in Figure 1, the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN are delayed by the first delay time DLY1 and the second delay time DLY2 respectively. ,... and the Nth delay time DLYN (corresponding to the delayed transfer data 220 in Figure 2B), and then provide the corresponding preamble PRE to the corresponding first channel CH1, second channel CH2,... and Channel N CHN.

FIG. 3 is a block diagram of a delay generator according to an embodiment of the present invention. As shown in FIG. 3 , the delay generator 300 includes a counter 310 , a register 320 and a comparator 330 . The counter 310 counts the predetermined time TM according to the enable signal EN and the clock signal CLK. The register 320 is used to store the delay time DLY. The comparator 330 is used to compare the predetermined time TM and the delay time DLY. According to an embodiment of the present invention, when the predetermined time TM is equal to the delay time DLY, the comparator 330 generates the trigger signal TR.

According to an embodiment of the present invention, the delay generator 300 corresponds to any one of the first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N in Figure 1. As shown in FIGS. 1 and 3 , the first delay generator 121 , the second delay generator 122 , ... and the counter 310 of the N-th delay generator 12N count according to the enable signal EN and the clock signal CLK. Set timeTM. When the predetermined time TM counted by the first delay generator 121 is equal to the first delay time DLY1, the first delay generator 121 generates the first trigger signal TR1; when the predetermined time TM counted by the second delay generator 122 is equal to the second During the delay time DLY2, the second delay generator 122 generates the second trigger signal TR2, and so on.

According to another embodiment of the present invention, the register 320 in Figure 3 is used to store the first delay time DLY1, the second delay time DLY2, ... and the first delay time DLY1 in Figure 1. Nth delay time DLYN. When the predetermined time TM counted by the counter 310 is equal to the first delay time DLY1, the comparator 330 generates the first trigger signal TR1; when the predetermined time TM counted by the counter 310 is equal to the second delay time DLY2, the comparator 330 generates the second trigger signal TR1. Trigger signal TR2, and so on.

Figure 4 is a block diagram showing an output device according to an embodiment of the present invention. As shown in FIG. 4 , the output device 400 includes a bit width controller 410 , a bit time adjuster 420 and a data generator 430 .

The bit width controller 410 generates the control signal SC according to the bit width ratio Q. The bit time adjuster 420 generates the adjustment signal SAD according to the clock signal CLK, the enable signal EN and the control signal SC. The data generator 430 converts the input data DI into transfer data DT according to the enable signal EN and the adjustment signal SAD.

According to an embodiment of the present invention, the bit width ratio Q is a ratio of the bit width of the first logic bit and the bit width of the second logic bit. According to an embodiment of the present invention, the first logic bit is logic 0, and the second logic bit is logic 1. According to some embodiments of the present invention, the output device 400 corresponds to any one of the first output device 111, the second output device 112, ... and the N-th output device 11N in Figure 1.

Figure 5 is a diagram showing the relationship between input data and converted data according to an embodiment of the present invention. According to an embodiment of the present invention, the input data DI in Figure 5 corresponds to the input data DI in Figure 4 and the first input data DI1, second input data DI2, ... and the Nth input data in Figure 1 DIN, the conversion data DT corresponds to the conversion data DT in Figure 4 and the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN.

As shown in Figure 5, the input data DI is between logical 0 and logical 1. combination. When the input data DI is logic 0, the conversion data DT is not converted. When the input data DI is logic 1, the transition data DT transitions when the input data DI transitions from logic 0 to logic 1, and transitions again at half cycle. According to an embodiment of the present invention, the conversion data DT is a Bi-phase Mark Code (BMC).

Figures 6A-6B are waveform diagrams showing converted data according to an embodiment of the present invention. As shown in Figure 6A, when the bit width ratio Q is 1, the bit width ratio representing logic 0 and logic 1 of the converted data DT is 1:1. Therefore, the bit width of logic 0 of the conversion data DT is the same as the bit width of logic 1.

As shown in Figure 6B, when the bit width ratio Q is 1.6, the bit width of the logic 0 representing the converted data DT is 1.6 times the bit width of the logic 1. In other words, the bit width of logic 0 of the conversion data DT is greater than the bit width of logic 1.

As shown in Figures 6A-6B, the bit width of logic 1 is fixed, and the bit width ratio Q is used to adjust the bit width of logic 0. According to an embodiment of the present invention, the bit width ratio Q is greater than 1 and less than 2. According to other embodiments of the present invention, the bit width of logic 0 can also be fixed, and the bit width ratio Q is used to adjust the bit width of logic 1.

Returning to Figure 1, due to at least two mutually different first delay times DLY1, second delay times DLY2, ... and Nth delay time DLYN, the first channel CH1, the second channel CH2, ... and the Nth delay time DLYN The conduction time of the display unit on the N channel CHN can be staggered. In addition, the bit width ratio Q of the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN is not 1, so that the conversion time of different transfer data is different. Therefore, the conduction time of different display units can be further staggered, thereby reducing the voltage drop caused by the supply voltage of the display device. Spend.

Figure 7 is a schematic diagram showing data transfer according to another embodiment of the present invention. As shown in Figure 7, the transfer data 700 includes preamble code PRE, function code FNC, data code DTC and packet end EOP. Comparing the transfer data 700 with the transfer data 210 in Figure 2A, the transfer data 700 further includes the function code FNC.

According to an embodiment of the present invention, the transfer data 700 corresponds to any one of the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN in Figure 1. The preamble PRE is used to initialize the display unit of the first channel CH1, the second channel CH2, ... or the Nth channel CHN of the display device 10 in Figure 1.

The function code FNC includes a first instruction code CC1, a second instruction code CC2, a third instruction code CC3 and a fourth instruction code CC4. According to an embodiment of the present invention, the first command code CC1, the second command code CC2, the third command code CC3 and the fourth command code CC4 are used to set the synchronization format of the control device 100 and the display device 10.

The data code DTC includes the first data D1, the second data D2, ... and the M-th data DM, where the first data D1, the second data D2, ... and the M-th data DM are used to transmit and control the corresponding display unit. control information. The end of packet EOP is used to indicate the end of transmission.

According to an embodiment of the present invention, before the preamble PRE and after the end of the packet EOP, the transfer data 700 is in the idle state Idle. As shown in the embodiment of Figure 7, the transfer data 700 is at a high logic level in the idle state. According to another embodiment of the present invention, the transfer data 700 may also be at a low logic level in the idle state.

Figure 8 is a block diagram showing an output device according to another embodiment of the present invention. As shown in Figure 8, the output device 800 includes a preamble generator 810 and function code generator 820. According to an embodiment of the present invention, the output device 800 corresponds to the first output device 111, the second output device 112, ... and the N-th output device 11N in Figure 1.

The preamble generator 810 is used to generate the preamble code PRE, and the function code generator 820 is used to generate the function code FNC. The output device 800 converts the input data DI into the data code DTC, and sequentially outputs the preamble code PRE, function code FNC, data code DTC and packet end EOP as transfer data DT. According to an embodiment of the present invention, the function code FNC, the data code DTC and the end of the packet EOP are biphase marking codes.

According to an embodiment of the present invention, the input data DI in Figure 8 corresponds to one of the first input data DI1, the second input data DI2, ... and the Nth input data DIN in Figure 1, Figure 8 The transfer data DT corresponds to one of the first transfer data DT1, the second transfer data DT2, ... and the Nth transfer data DTN in Figure 1. How the preamble code PRE, function code FNC and data code DTC are generated will be explained in detail below.

Figure 9 is a block diagram of a preamble generator according to an embodiment of the present invention. As shown in Figure 9, the preamble generator 900 includes a preamble bit number register 910, a preamble value register 920, a bit counter 930, a preamble shift register 940 and a bit Arion comparator 950.

The preamble bit number register 910 is used to store the bit number P1 of the preamble PRE, and the preamble value register 920 is used to store a predetermined value PV. According to some embodiments of the present invention, the preamble value register 920 stores a predetermined value PV corresponding to the number of bits P1. The bit counter 930 counts according to the enable signal EN and the preamble enable signal ENPRE to generate the first count value CV1 and the first shift signal SFT1. According to an embodiment of the present invention, the enable signal EN is equivalent to the enable signal EN in Figure 1 Signal EN.

According to an embodiment of the present invention, when the idle state Idle is at a high logic level and the preamble shift register 940 outputs the least significant bit (Least Significant Bit, LSB) first, the predetermined value PV is 0xAA, To facilitate the maximum number of logical transformations. According to another embodiment of the present invention, when the idle state Idle is at a high logic level and the preamble shift register 940 outputs the most significant bit (Most Significant Bit, MSB) first, the predetermined value PV is 0x55 , in order to produce the maximum number of logical transformations.

According to another embodiment of the present invention, when the idle state Idle is at a low logic level and the preamble shift register 940 outputs the least significant bit (Least Significant Bit, LSB) first, the predetermined value PV is 0x55 . According to another embodiment of the present invention, when the idle state Idle is at a low logic level and the preamble shift register 940 outputs the most significant bit (Most Significant Bit, MSB) first, the predetermined value PV is 0xAA. .

According to other embodiments of the present invention, the predetermined value PV can also be other values. Here, only 0x55 and 0xAA are used for illustration and explanation, and are not limited thereto in any form.

The preamble shift register 940 shifts the predetermined value PV according to the first shift signal SFT1 and outputs it as the preamble PRE. The bit number comparator 950 compares the first count value CV1 with the bit number P1 to generate the preamble enable signal ENPRE.

When the first count value CV1 is not greater than the number of bits P1, the preamble enable signal ENPRE is at the first logic level, enabling the preamble bit counter 930 to continue counting. When the first count value CV1 is greater than the bit number P1, the preamble enable signal ENPRE is at the second logic level and the disabled preamble bit counter 930 stops counting.

For example, assume that the bit number P1 is 32, which means that the preamble PRE shown in Figure 7 has 32 bits. The bit counter 930 starts counting according to the enable signal EN and outputs the first count value CV1 and the first shift signal SFT1. The bit number comparator 950 compares the first count value CV1 with the bit number P1.

When the first count value CV1 is not greater than the bit number P1, the bit number comparator 950 uses the preamble enable signal ENPRE to control the bit counter 930 to continue counting. The preamble shift register 940 outputs the most significant bit or the least significant bit of the predetermined value PV stored in the preamble value register 920 according to the first shift signal SFT1 generated by the bit counter 930 is the preamble PRE.

When the first count value CV1 is greater than the number of bits P1 (in this embodiment, the first count value CV1 is 33 and the number of bits P1 is 32), the bit number comparator 950 uses the preamble enable signal ENPRE controls the bit counter 930 to stop counting.

According to an embodiment of the present invention, since the preamble value register 920 stores the predetermined value PV corresponding to the number of bits P1, after the output of each bit of the preamble value register 920 is completed, the preamble shift The bit register 940 then stops outputting the preamble PRE. According to another embodiment of the present invention, when the bit counter 930 stops counting according to the preamble enable signal ENPRE, the bit counter 930 stops generating the first shift signal SFT1 at the same time.

Figure 10 is a block diagram showing an output device according to an embodiment of the present invention. As shown in FIG. 10 , the output device 1000 includes a function code generator 1010 , a lookup table register 1020 and a lookup table comparator 1030 . According to some embodiments of the present invention, the output device 1000 combined with the preamble generator 900 in Figure 9 corresponds to the output device 800 in Figure 8 and the first output device 111 and the second output device 112 in Figure 1. ..and one of the N-th output devices 11N.

As shown in Figure 10, the function code generator 1010 includes a function code number register 1011, a function code register 1012, a function code counter 1013, a function code shift register 1014 and a function code number comparator 1015. The function code number register 1011 is used to store the function code number P2, and the function code register 1012 is used to store the instruction code CC of the function code number P2.

As shown in the embodiment of Figure 7, the function code FNC includes 4 instruction codes, which means that the number of function codes P2 is 4. In addition, the function code register 1012 is used to store the first command code CC1, the second command code CC2, the third command code CC3 and the fourth command code CC4 in sequence. According to some embodiments of the present invention, when the function code FNC includes Y instruction codes, the function code number P2 stored in the function code number register 1011 is Y, and the function code register 1012 stores Y function codes in sequence.

Returning to Figure 10, the function code counter 1013 starts counting according to the preamble enable signal ENPRE generated by the bit number comparator 950 in Figure 9 to generate the second count value CV2 and the second shift signal SFT2. . The function code shift register 1014 sequentially outputs the command code CC stored in the function code register 1014 according to the second shift signal SFT2. The function code number comparator 1015 compares the second count value CV2 and the function code number P2 to generate the function code enable signal ENFC.

As shown in the embodiment of Figure 7, when the second count value CV2 is 1, the function code shift register 1014 outputs the first instruction code CC1; when the second count value CV2 is 2, the function code shift The temporary register 1014 outputs the second command code CC2, and so on.

As shown in Figure 10, the lookup table register 1020 is used to store the lookup table LUT. The lookup table comparator 1030 converts the instruction code CC and/or the input data DI into the corresponding bit code BTC according to the function code enable signal ENFC and the lookup table LUT.

According to an embodiment of the present invention, when the second count value CV2 is not greater than the function code number P2, the lookup table comparator 1030 operates in the first state according to the function code enable signal ENFC to convert the instruction code CC into the corresponding The bitcode of BTC.

According to another embodiment of the present invention, when the second count value CV2 is greater than the function code number P2, the lookup table comparator 1030 operates in the second state according to the function code enable signal ENFC to convert the input data DI into the corresponding The bitcode of BTC.

As shown in FIG. 10 , the output device 1000 further includes a width counter 1040 , a bit width comparator 1050 and a bit generator 1060 . The width counter 1040 generates the count signal CNT according to the clock signal CLK. The bit width comparator 1050 generates the half-bit pulse HBP and the full-bit pulse FBP according to the count signal CNT, and the bit generator 1060 converts the bit code BTC into a bidirectional mark code BMC.

According to an embodiment of the present invention, when the bit code BTC is logic 1, the bi-phase mark code BMC is switched once every half cycle, and when the bit code BTC is logic 0, the bi-phase mark code BMC is switched. Switch once every cycle. According to another embodiment of the present invention, when the bit code BTC is logic 0, the bi-phase mark code BMC is switched once every half cycle. When the bit code BTC is logic 1, the bi-phase mark code BMC is switched. Switch once every cycle.

As shown in the output device 800 in Figure 8, the preamble generator 900 in Figure 9, and the output device 1000 in Figure 10, the preamble generator 900 outputs the preamble PRE according to the enable signal EN. When the preamble PRE output is completed, the preamble enable signal ENPRE is used to enable the preamble generator 900 to output the function code FNC. When the output of the function code FNC is completed, the preamble generator 900 outputs the input data DI as the data code DTC according to the function code enable signal ENFC, where the function code FNC and the data code DTC are bi-phase mark codes BMC.

According to an embodiment of the present invention, when the transmission of the data code DTC is completed, the preamble generator 900 further outputs the end-of-packet EOP, where the end-of-packet EOP is the biphase mark code BMC. In other words, except for the preamble PRE, the function code FNC, data code DTC and packet end EOP of the transfer data DT output by the output device 800 are all biphase mark codes BMC.

Returning to Figure 10, when the designer provides a wrong function code lookup table or wants to change the design, he can modify the command code CC stored in the function code register 1012 and the lookup table LUT stored in the lookup table register 1020. That meets the requirements. In addition, the user can also modify the function code number P2 stored in the function code number register 1011, the instruction code CC stored in the function code register 1012, and the lookup table LUT stored in the lookup table register 1020, and Meet various needs.

FIG. 11 is a diagram showing the relationship between bit codes and bi-phase tag codes according to an embodiment of the present invention. According to an embodiment of the present invention, the bit code BTC in Figure 11 corresponds to the bit code BTC in Figure 10, and the bi-phase mark code BMC corresponds to the bi-phase mark code BMC in Figure 5.

As shown in Figure 11, the bit code BTC is a combination of logical 0 and logical 1. When the bit code BTC is logic 0, the bi-phase mark code BMC is converted once per cycle. When the bit code BTC is logic 1, the bi-phase mark code BMC switches every half cycle.

According to another embodiment of the present invention, when the bit code BTC is logic 0, the bi-phase mark code BMC is switched once every half cycle. When the bit code BTC is logic 1, the bi-phase mark code BMC is switched. Switch once every cycle. The embodiment shown in Figure 6 is for illustration and explanation and is not limited in any way.

Figure 12 shows a control method according to an embodiment of the present invention. Flowchart of the method. The following description of the control method 1200 in Figure 12 will be combined with the control device 100 in Figure 1 to facilitate detailed explanation.

First, according to the enable signal EN, the first output device 111, the second output device 112, ... and the N-th multiplexer 13N in Figure 1 are used to generate the first transfer data DT1, the second transfer data DT2,... ..and the Nth transfer data DTN (step S1210).

As shown in the embodiment of FIG. 4, according to the adjustment signal SAD, the data generator 430 is used to convert the first input data DI1, the second input data DI2, ... and the Nth input data DIN into the first transfer data DT1 respectively. , the second transfer data DT2,... and the Nth transfer data DTN, wherein any one of the first transfer data DT1, the second transfer data DT2,... and the Nth transfer data DTN is one of logic 0 and logic 1. The bit width ratio is the bit width ratio Q.

Then, according to the enable signal EN, the first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N in Figure 1 are used to count the first delay time DLY1, the second delay time DLY2, ... and the Nth delay time DLYN, to generate the first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN respectively (step S1220).

As shown in the embodiment of Figure 3, the predetermined time TM is counted, and when the predetermined time TM is equal to the delay time DLY (corresponding to the first delay time DLY1, the second delay time DLY2, ... and the Nth delay of Figure 1 At time DLYN), a trigger signal TR (corresponding to the first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN in Figure 1) is generated.

Returning to Figure 12, according to the first trigger signal TR1, the second trigger signal TR2, ... and the Nth trigger signal TRN, the first multiplexer 131, the second multiplexer The processors 132, ... and the N-th multiplexer 13N respectively provide the first transfer data DT1, the second transfer data DT2,... and the N-th transfer data DTN to the corresponding first channel CH1 of the display device 10. , the second channel CH2, ... and the Nth channel CHN (step S1230).

As shown in the embodiment of FIG. 1, since the first delay generator 121, the second delay generator 122, ... and the Nth delay generator 12N are used to count the first delay time DLY1, the second delay time DLY2, ...and the Nth delay time DLYN to generate the first trigger signal TR1, the second trigger signal TR2,...and the Nth trigger signal TRN correspondingly, so the first multiplexer 131, the second multiplexer 132,... ...and the N-th multiplexer 13N respectively delay the first delay time DLY1, the second delay time DLY2, ... and the N-th delay time DLYN before transferring the first transfer data DT1, the second transfer data DT2,... ..and the Nth transfer data DTN is provided to the first channel CH1, the second channel CH2,...and the Nth channel CHN.

The present invention hereby proposes a control device and a control method for time-sharing the display units of different channels of the display device to reduce the voltage drop of the supply voltage of the display device, by staggering the time when different channels of different display devices receive the preamble and The bit width ratio of logic 0 and logic 1 is adjusted to reduce the number of display cells that are turned on at the same time, thereby reducing the degree of voltage drop in the supply voltage of the display device.

Although the embodiments and their advantages of the present disclosure have been disclosed above, it should be understood that anyone with ordinary skill in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the relevant technical field can learn from some implementations of the present disclosure. Examples of revealing content include understanding the current or future development of Processes, machines, fabrications, compositions of matter, devices, methods and steps that can perform substantially the same functions or obtain substantially the same results in the embodiments described herein may be used according to some embodiments of the present disclosure. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each claimed patent scope constitutes an individual embodiment, and the protection scope of the present disclosure also includes the combination of each claimed patent scope and embodiments.

10:Display device

100:Control device

111: First output device

112: Second output device

11N: Nth output device

121: First delay generator

122: Second delay generator

12N: Nth delay generator

131:First multiplexer

132: Second multiplexer

13N:Nth multiplexer

CH1: first channel

CH2: Second channel

CHN: Channel N

DI1: first input data

DI2: Second input data

DIN: Nth input data

DT1: first transfer data

DT2: Second transfer data

DTN: Nth transfer data

EN: enable signal

DLY1: first delay time

DLY2: second delay time

DLYN: Nth delay time

TR1: first trigger signal

TR2: second trigger signal

TRN: Nth trigger signal

DDT1: first delayed transfer data

DDT2: Second delayed transfer data

DDTN: Nth delayed transfer data

DL: Default logic level

Claims (10)

A control device used to drive a display device, wherein the display device includes a first channel and a second channel, including: a first output device that outputs a first transfer data according to an enable signal; a second output A device, according to the above-mentioned enable signal, outputs a second transfer data; a first delay generator, according to the above-mentioned enable signal, counts a first delay time to generate a first trigger signal; a second delay generator, Count a second delay time to generate a second trigger signal based on the enable signal; a first multiplexer provides the first transfer data to the first channel based on the first trigger signal; and a first multiplexer provides the first transfer data to the first channel based on the first trigger signal; The second multiplexer provides the second transfer data to the second channel according to the second trigger signal. The control device of claim 1, wherein each of the first delay generator and the second delay generator includes: a counter that counts a first time or a clock signal based on the enable signal and a clock signal. a second time; a register for storing the first delay time or the second delay time; and a comparator for comparing the first time with the first delay time to generate the first trigger signal, or comparing The second time and the second delay time generate the second trigger signal, wherein when the first time is equal to the first delay time, the comparator generates the first trigger signal, wherein when the second time When equal to the second delay time, the comparator generates the second trigger signal. The control device of claim 1, wherein the first delay time and the second delay time are different. The control device of claim 1, wherein one of the above-mentioned first output device and the above-mentioned second output device further includes: a pixel width controller that generates a control signal according to a pixel width ratio; a pixel time adjustment A device that generates an adjustment signal based on a clock signal, the above-mentioned enable signal and the above-mentioned control signal; and a data generator that converts an input data into a transfer data based on the above-mentioned enable signal and the above-mentioned adjustment signal, wherein the above-mentioned transfer data It includes at least one first logic bit and at least one second logic bit, wherein the ratio of the bit width of the first logic bit and the bit width of the second logic bit is the bit width ratio. The control device of claim 4, wherein the bit width ratio of the first transfer data and the bit width ratio of the second transfer data are different. A control method for driving a display device, wherein the display device includes a first channel and a second channel, wherein the control method includes: outputting a first transfer data and a second transfer data according to an enable signal; According to the above-mentioned enable signal, a first delay time and a second delay time are counted to generate a first trigger signal and a second trigger signal respectively; according to the above-mentioned first trigger signal, the above-mentioned first transfer data is provided to the above-mentioned first channel; and The second transfer data is provided to the second channel according to the second trigger signal. As in claim 6, the control method, wherein the step of counting the first delay time and the second delay time according to the enable signal to generate the first trigger signal and the second trigger signal respectively further includes: using a temporary The register stores the first delay time and the second delay time; counts a first time and a second time according to the enable signal and a clock signal; when the first time is equal to the first delay time , generate the above-mentioned first trigger signal; and when the above-mentioned second time is equal to the above-mentioned second delay time, generate the above-mentioned second trigger signal. As in the control method of claim 6, the first delay time is different from the second delay time. As claimed in claim 6, the control method, wherein the step of outputting the first transfer data and the second transfer data according to the enable signal further includes: generating a first control signal according to a first element width ratio; The second bit width ratio generates a second control signal; a first adjustment signal is generated according to a clock signal, the enable signal and the first control signal; and a first adjustment signal is generated according to the clock signal, the enable signal and the first control signal. Two control signals generate a second adjustment signal; convert a first input data into the first transfer data according to the above-mentioned enable signal and the above-mentioned first control signal; and According to the above enable signal and the above second control signal, a second input data is converted into the above second transfer data. The control method of claim 9, wherein the first transfer data includes at least one first logical bit and at least one second logical bit, wherein the bit width of the first logical bit of the first transfer data and the above-mentioned The ratio of the bit width of the second logic bit is the above-mentioned first bit width ratio, wherein the above-mentioned second transfer data includes at least one first logic bit and at least one second logic bit, wherein the above-mentioned second transfer data The ratio of the bit width of the first logic bit to the bit width of the second logic bit is the second bit width ratio.

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