TWI817856B - Method of forming conductive vias - Google Patents

Abstract

A method of forming conductive vias includes: patterning a mask layer on a semiconductor device which includes a first area and a second area; performing a first etching process through the mask layer to form a first opening with a first depth in the first area and a second opening with the first depth in the second area; performing a second etching process through the mask layer to extend the first opening and the second opening to a second depth and a third depth respectively, the second depth and the third depth are different; performing a third etching process through the mask layer to extend the first opening and the second opening to a fourth depth, the first opening and the second opening exposed a bottom metal layer; and depositing a conductive material in the first opening and the second opening.

Description

Methods of forming conductive vias

The present disclosure relates to a method of forming conductive vias.

In the process of manufacturing semiconductors, various electrical connection structures are usually designed according to circuit requirements to connect various electronic components. Conductive vias and connection pads are two common electrical connection structures. An adhesive layer is provided between the electrical connection structures to assist in their connection. However, if too many electrical connection structures are provided, the conductivity of the semiconductor element will be affected due to the increase in the number of adhesive layers.

Therefore, how to propose a method of forming conductive vias that can solve the above problems is one of the problems that the industry is currently eager to invest in research and development resources to solve.

In view of this, one aspect of the present disclosure is to provide a method of forming conductive vias that can effectively solve the above problems.

Some embodiments of the present disclosure relate to a method of forming a conductive via, including: patterning a mask layer above a semiconductor device, the semiconductor device including a first region and a second region; performing a first etching process through the mask layer to respectively A first opening and a second opening with a first depth are formed on the first area and the second area, wherein the first opening exposes the first metal layer; a second etching process is performed through the mask layer to extend the first opening to the two depths, and extending the second opening to a third depth, wherein the second depth is different from the third depth; performing a third etching process through the mask layer to extend the first opening and the second opening to a fourth depth, and the first opening and the second opening exposing the bottom metal layer; and depositing conductive material in the first opening and the second opening.

In some embodiments, the step of performing the second etching process through the mask layer includes penetrating the first metal layer and the second metal layer below the first metal layer through the first opening.

In some embodiments, performing the second etching process through the mask layer causes the first opening to expose the oxide layer located under the first metal layer.

In some embodiments, performing the third etching process through the mask layer causes the first opening and the second opening to extend into the bottom metal layer but not through the bottom metal layer.

In some embodiments, the second depth is greater than the third depth.

In some embodiments, the step of depositing the conductive material includes: conformally forming an adhesive layer on a plurality of sidewalls and a plurality of bottom surfaces of the first opening and the second opening; and depositing a filling layer on the first opening and the second opening. in the mouth.

In some embodiments, the adhesive layer and the first metal layer are made of the same material.

In some embodiments, a method of forming a conductive via further includes performing a mechanical grinding process and removing portions of the conductive material.

In some embodiments, the first etching process and the third etching process use the same first etching gas. The second etching process uses a second etching gas different from the first etching gas.

In some embodiments, the first etching gas and the second etching gas have different etching speeds for the first metal layer.

In summary, in the methods for forming conductive vias in some embodiments of the present disclosure, the conductive vias formed in the first opening and the second opening by the method of forming the conductive vias can reduce the number of semiconductor components. The connection pad structure is used to solve the problem of excessive connection electrical structures reducing the conductivity of semiconductor components. In addition, by forming the conductive via holes in the first opening and the second opening, the process steps of making separate connection pads can be omitted, thereby improving the process efficiency of the semiconductor device.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, the following description where a first feature is formed on or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be Embodiments are formed between a first feature and a second feature such that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference symbols and/or letters in various instances. This repetition is for simplicity and clarity and does not in itself represent a relationship between the various embodiments and/or configurations discussed.

In addition, for simplicity of description, spatially relative terms such as "below", "below", "lower", "above", "upper" and similar terms may be used herein. Describe the relationship of one element or feature to another (additional) element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, "about," "approximately," "approximately" or "substantially" generally means falling within twenty percent, within ten percent, or within one hundred percent of a given value or range. Out of five. Numerical quantities given herein are approximations, meaning that terms such as "about," "approximately," "approximately" or "substantially" may be inferred when not expressly stated otherwise.

FIG. 1 is a flowchart of a method M1 of forming a conductive via according to some embodiments of the present disclosure. Please refer to picture 1. Some embodiments of the present disclosure are related to a method M1 for forming a conductive via, including: patterning a mask layer over a semiconductor element, and the semiconductor element includes a first region and a second region (step S110); performing the step S110 through the mask layer. An etching process to form a first opening and a second opening with a first depth in the first region and the second region respectively, wherein the first opening exposes the first metal layer (step S120); perform the second opening through the mask layer An etching process is performed to extend the first opening to a second depth, and the second opening is extended to a third depth, where the second depth is different from the third depth (step S130); a third etching process is performed through the mask layer to extend the first opening and the second opening reaches a fourth depth, and the first opening and the second opening expose the bottom metal layer (step S140); and a conductive material is deposited in the first opening and the second opening (step S150).

FIG. 2A is a top view of the semiconductor device 110 during one stage of the method M1 for forming conductive vias according to some embodiments of the present disclosure. The conductive via forming method M1 will make it possible to create a plurality of conductive vias in different areas of the semiconductor element 110 . Specifically, the semiconductor device 110 includes a first region 120 and a second region 130 . For example, in the embodiment of FIG. 2A , the first area 120 is an array area, and the second area 130 is a peripheral area. The first opening 122 and the second opening 132 are located in the first area 120 and the second area 130 respectively. In this embodiment, the first region 120 also includes the bit lines 150 and the capacitor array 300 shown in FIG. 2C (only the connection pads 330 of the capacitor array 300 are shown in FIG. 2A). In FIG. 2A , the first opening 122 passes through part of the bit line 150 and connects the first region 120 and other electrical components (not shown) located below the first region 120 . The second opening 132 is not in contact with the bit line 150 and is connected to other electrical components (not shown) located above and below the bit line 150 . Next, the structure of the semiconductor device 110 will be described with respect to cross-sectional side views drawn along different lines B-B', C-C' and D-D'.

Figure 2B is a cross-sectional side view of the semiconductor device 110 along line B-B' in Figure 2A. The line A-A' marked in Figure 2B corresponds to the top view position of Figure 2A. Please refer to Figure 2A and Figure 2B. In FIG. 2B, the semiconductor device 110 includes a first oxide layer 140, a bit line 150, a second oxide layer 160 and a bottom metal layer 170 stacked in sequence. Bit line 150 extends only in first area 120 . In some embodiments, the materials of the first oxide layer 140 and the second oxide layer 160 include SiO2. In the example of FIG. 2B , the bottom metal layer 170 is a plurality of connection pads buried in the second oxide layer 160 . In some embodiments, the material of bottom metal layer 170 includes tungsten (W). The bit line 150 is formed by sequentially stacking a nitride layer 152, an isolation oxide layer 154, a first metal layer 156 and a second metal layer 158. The hydrogen (H) atoms generated during the growth of the nitride layer 152 in the bit line 150 may drill down into the capacitor array 300 and affect the performance of the capacitor array 300 . Therefore, the bit line 150 has an isolation oxide layer 154 to increase the distance between the nitride layer 152 and the capacitor array 300 . On the other hand, in some embodiments, the material of the first metal layer 156 includes TiN, and the material of the second metal layer 158 includes W. The first metal layer 156 will help improve the adhesion between the second metal layer 158 and other materials. sex. It should be noted that the number of bit lines 150 shown in Figure 2B is only exemplary. In other embodiments, the number of bit lines 150 can be adjusted according to requirements. The first opening 122 sequentially passes through the first oxide layer 140 , the nitride layer 152 , the isolation oxide layer 154 , the first metal layer 156 , the second metal layer 158 and the second oxide layer 160 , and is electrically connected to the bottom metal layer 170 connection. The second opening 132 passes through the first oxide layer 140 and the second oxide layer 160 in sequence, and is electrically connected to the bottom metal layer 170 . The first opening 122 and the second opening 132 are filled with the conductive material 180 .

FIG. 2C is a cross-sectional side view of the semiconductor device 110 along line CC' in FIG. 2A. The line A-A' marked in Figure 2C corresponds to the top view position of Figure 2A. Please refer to Figure 2A and Figure 2C. In FIG. 2C , the capacitor array 300 and the word line 400 of the semiconductor device 110 are shown. The capacitor array 300 includes a plurality of capacitors 310 , a plurality of transistors 320 and a plurality of connection pads 330 . In this embodiment, the capacitor 310 is hexagonally densely packed in the semiconductor device 110 . Each capacitor 310 is electrically connected to a source/drain of a transistor 320 , and the other source/drain of the transistor 320 is electrically connected to the connection pad 330 . The gate of the transistor 320 is electrically connected to the word line 400 . Each of the plurality of connection pads 330 is electrically connected to one bit line 150 . It should be noted that this figure only shows a second opening 132 passing through the first oxide layer 140 and the second oxide layer 160 from the right side of Figure 2C and being electrically connected to the bottom metal layer 170 .

Figure 2D is a cross-sectional side view of the semiconductor device 110 along line D-D' in Figure 2A. The line A-A' marked in Figure 2D corresponds to the top view position of Figure 2A. Please refer to Figure 2A and Figure 2D. In Figure 2D, the electrical connection between the bit line 150 of the semiconductor device 110, the capacitor array 300 and the first opening 122 is shown. In this embodiment, the signal with the capacitor array 300 is electrically transmitted to the first opening 122 through the bit line 150 . It should be noted that although the first opening 122 penetrates the semiconductor device 110 and is electrically connected to the bottom metal layer 170 in FIG. 2D, the first opening 122 mainly electrically transmits the signal of the capacitor array 300 to the bottom metal layer 170. In other words, the portion of the first opening 122 located above the bit line 150 is not used for transmitting signals of the capacitor array 300 .

It should be noted that the conductive via holes formed in the first opening 122 and the second opening 132 by the method M1 can reduce the connection pad structure in the semiconductor device 110 . Specifically, a layer of adhesive material is used on the connection pad structure to assist in connecting the connection pad structure to other layers. However, if too many connection pad structures are used, the conductivity of the semiconductor device 110 will be reduced due to an increase in the adhesive material layer. Therefore, forming conductive vias through method M1 can solve the problem of excessive connection pad structures reducing the conductivity of the semiconductor device 110 . In addition, by method M1 in The conductive vias formed by the first opening 122 and the second opening 132 can eliminate the process steps of making separate connection pads, thereby improving the process efficiency of the semiconductor device 110 . Next, the method M1 for forming a conductive via hole will be described step by step on how to form the first opening 122 and the second opening 132 in the first region 120 and the second region 130 of the semiconductor device 110 respectively.

FIG. 3A is a cross-sectional side view of the semiconductor device 110 during one stage of the method M1 of forming a conductive via according to some embodiments of the present disclosure. The cross-sectional side view illustrated in Figure 3A is a cross-sectional side view along line B-B' in Figure 2A. In addition, Figures 3B to 3H shown subsequently are also cross-sectional side views along line B-B' in Figure 2A. Please refer to Figure 1, Figure 2A and Figure 3A. Before step S110 is performed, the semiconductor device 110 includes a first oxide layer 140, a bit line 150, a second oxide layer 160 and a bottom metal layer 170 stacked sequentially from top to bottom. In step S110, the mask layer 200 is formed on the semiconductor element 110 and then patterned. In some embodiments, the patterned mask layer 200 may be implemented by alternately performing multiple lithography processes and etching processes. It is noted that the openings 210 on the patterned mask layer 200 will be aligned with the location of the bottom metal layer 170 .

3B is a cross-sectional side view of the semiconductor device 110 at another stage of the method M1 for forming conductive vias according to some embodiments of the present disclosure. Please refer to Figure 1, Figure 2A and Figure 3B. In step S120 , the first etching process is simultaneously performed on the first region 120 and the second region 130 of the semiconductor device 110 . The first etching process forms a first opening 122 with a first depth D1 in the first region 120 and a second opening 132 with a first depth D1 in the second region 130 respectively. In some embodiments, the first etching process is an anisotropic gas etching process using a first etching gas. The first etching gas has a high selective etching rate for specific materials. For example, in the example of FIG. 3B , the first etching gas has a high selective etching rate for oxides and nitrides. In other words, the first etching process will have a high etching rate for oxides and nitrides, but will have a low etching rate or no etching for other materials, such as metal materials.

Please continue to refer to Figure 1, Figure 2A and Figure 3B. Specifically, the first etching process sequentially etches the first oxide layer 140 , the nitride layer 152 and the isolation oxide layer 154 from top to bottom in the first region 120 . On the other hand, the first etching process will simultaneously etch the first oxide layer 140 in the second region 130 . When the bottom surface of the first opening 122 exposes the first metal layer 156, the first etching process is stopped. It should be noted that the time to end the first etching process is determined by the time when the bottom surface of the first opening 122 exposes the first metal layer 156 . In the example of FIG. 2B , when the first etching process is completed, the second opening 132 only extends in the first oxide layer 140 .

3C is a cross-sectional side view of the semiconductor device 110 at another stage of the method M1 for forming conductive vias according to some embodiments of the present disclosure. Please refer to Figure 1, Figure 2A and Figure 3C. In step S130 , the second etching process is simultaneously performed on the first region 120 and the second region 130 of the semiconductor device 110 . The second etching process respectively forms the first opening 122 with the second depth D2 in the first region 120 and the second opening 132 with the third depth D3 in the second region 130, and the second depth D2 is different from the third depth. D3. In some embodiments, the second depth D2 is greater than the third depth D3. In some embodiments, the second etching process is an anisotropic gas etching process using a second etching gas, and the second etching gas is different from the first etching gas. The second etching gas has a high selective etching rate for specific materials. For example, in the example of FIG. 3C , the second etching gas has a high selective etching rate for metal materials. In other words, the first etching gas and the second etching gas have different etching speeds for the first metal layer 156 and the second metal layer 158 . The second etching process will have a higher etching rate for metal materials, but will have a lower etching rate or no etching for other materials, such as oxides and nitrides.

Please continue to refer to Figure 1, Figure 2A and Figure 3C. Step S130 further includes: penetrating the first metal layer and the second metal layer located below the first metal layer through the first opening (step S132 ). Step S130 causes the first opening 122 to expose the oxide layer (eg, the second oxide layer 160 ) located under the first metal layer 156 . Specifically, in step S132, the first metal layer 156 and the second metal layer 158 in the first region 120 are sequentially etched in the second etching process. Subsequently, the first opening 122 exposes the second oxide layer 160 . Meanwhile, in the second region 130 , since the second etching process only has a high selective etching rate for metal materials, the depth of the second opening 132 does not change significantly like the depth of the first opening 122 . In some embodiments, the third depth D3 of the second opening 132 is almost equal to the first depth D1 , and the bottom surface of the second opening 132 still only extends in the first oxide layer 140 .

Figure 3D is a cross-sectional side view of the semiconductor device 110 at another stage of the method M1 for forming conductive vias according to some embodiments of the present disclosure. Please refer to Figure 1, Figure 2A and Figure 3D. In step S140 , the third etching process is simultaneously performed on the first region 120 and the second region 130 of the semiconductor device 110 . The third etching process forms the first opening 122 and the second opening 132 with the fourth depth D4 in the first region 120 and the second region 130 respectively. In some embodiments, the third etching process is an anisotropic gas etching process. In some embodiments, the first etching process and the third etching process use the same first etching gas. Therefore, the third etching process will have a higher etching rate for oxides and nitrides. When the third etching process starts to be performed, etching starts from the second oxide layer 160 in the first opening 122 of the first region 120 , and etching starts from the first oxide layer 140 in the second opening 132 of the second region 130 .

Please continue to refer to Figure 1, Figure 2A and Figure 3D. Step S140 causes the first opening 122 and the second opening 132 to extend into the bottom metal layer 170 but not through the bottom metal layer 170 . Specifically, the third etching process will perform over-etching after the bottom surfaces of the first opening 122 and the second opening 132 expose the bottom metal layer 170 . The purpose of performing over-etching is to remove the second oxide layer 160 remaining on the bottom metal layer 170 to ensure the electrical connection between the bottom metal layer 170 and the subsequently filled conductive material 180 (as shown in Figure 2B) It is not affected by the remaining second oxide layer 160 . However, since the third etching process has a low selective etching rate for metal materials, the bottom metal layer 170 will not be etched through. Specifically, the third etching process will form the groove 172 on the bottom metal layer 170 exposed on the bottom surfaces of the first opening 122 and the second opening 132 . Finally, both the first opening 122 and the second opening 132 will have a fourth depth D4.

3E is a cross-sectional side view of the semiconductor device 110 at another stage of the method M1 for forming conductive vias according to some embodiments of the present disclosure. Please refer to Figure 1, Figure 2A and Figure 3E. Mask layer 200 is removed. Specifically, the mask layer 200 may be removed through multiple wet etching processes or other suitable processes. After the mask layer 200 is removed, the surface of the first oxide layer 140 is exposed.

FIG. 3F is a cross-sectional side view of the semiconductor device 110 at another stage of the method M1 for forming conductive vias according to some embodiments of the present disclosure. Please refer to Figure 1, Figure 2A and Figure 3F. In step S150 , the conductive material 180 is deposited in the first opening 122 and the second opening 132 . In some embodiments, the conductive material 180 includes an adhesive layer 182 and a filling layer 184 . In some embodiments, the adhesive layer 182 and the first metal layer 156 are made of the same material, such as TiN. The filling layer 184 and the second metal layer 158 are made of the same material, such as W. The adhesive layer 182 will help improve the adhesion between the filling layer 184 and other materials.

Please continue to refer to Figure 1, Figure 2A and Figure 3F. Step S150 further includes: conformally forming an adhesive layer on a plurality of side walls and a plurality of bottom surfaces of the first opening and the second opening (step S152). In some embodiments, step S152 can be performed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), atomic layer epitaxy (ALD), or other suitable methods. The deposition process conformally forms the adhesive layer 182 on the plurality of sidewalls and bottom surfaces of the first opening 122 and the second opening 132 . Specifically, the adhesion layer 182 will cover the surfaces of the first oxide layer 140 , the nitride layer 152 , the isolation oxide layer 154 , the first metal layer 156 , the second metal layer 158 , the second oxide layer 160 and the bottom metal layer 170 .

3G is a cross-sectional side view of the semiconductor device 110 at another stage of the method M1 for forming conductive vias according to some embodiments of the present disclosure. Please refer to Figure 1, Figure 2A and Figure 3G. Step S150 further includes: depositing a filling layer in the first opening and the second opening (step S154). Specifically, the deposition process is performed on the first region 120 and the second region 130 simultaneously. In some embodiments, step S154 can be performed by physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable methods. A deposition process deposits the filling layer 184 in the first opening 122 and the second opening 132 . It should be noted that the filling layer 184 filled in the first opening 122 and the second opening 132 will only directly contact the adhesive layer 182 . On the other hand, the filling layer 184 in step S154 will also be deposited on the surface of the first oxide layer 140 .

3H is a cross-sectional side view of the semiconductor device 110 at another stage of the method M1 for forming conductive vias according to some embodiments of the present disclosure. Please refer to Figure 1, Figure 2A and Figure 3H. The method M1 of forming the conductive via further includes performing a mechanical polishing process, such as a chemical-mechanical planarization (CMP) process and removing the conductive material portion (step S160). Specifically, the CMP process is performed on the first region 120 and the second region 130 simultaneously to remove part of the conductive material 180 deposited on the first oxide layer 140 . After step S160, the surface of the semiconductor device 110 will expose the first oxide layer 140, the adhesion layer 182 and the filling layer 184.

From the above detailed description of the specific embodiments of the present disclosure, it can be clearly seen that in the method of forming a conductive via hole in some embodiments of the present disclosure, the first opening and the second opening are formed by the method of forming the conductive via hole. The formed conductive via holes can reduce the connection pad structure in the semiconductor element to solve the problem of excessive connection electrical structures reducing the conductivity of the semiconductor element. In addition, by forming the conductive via holes in the first opening and the second opening, the process steps of making separate connection pads can be omitted, thereby improving the process efficiency of the semiconductor device.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the disclosure, and they can make various changes, substitutions and substitutions herein without departing from the spirit and scope of the disclosure.

110:Semiconductor components 120:First area 122:First opening 130:Second area 132:Second opening 140: First oxide layer 150: bit line 152:Nitride layer 154:Isolation oxide layer 156: First metal layer 158: Second metal layer 160: Second oxide layer 170: Bottom metal layer 172: Groove 180: Conductive materials 182:Adhesive layer 184:Filling layer 200:Mask layer 210:Open your mouth 300:Capacitor array 310: Capacitor 320: Transistor 330:Connection pad 400: character line D1: first depth D2: Second depth D3: The third depth D4: fourth depth A-A’, B-B’, C-C’, D-D’: lines M1:Method S110, S120, S130, S132, S140, S150, S152, S154, S160: Steps

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a flowchart of a method of forming conductive vias according to some embodiments of the present disclosure.

FIG. 2A is a top view of a semiconductor device during one stage of a method of forming conductive vias in accordance with some embodiments of the present disclosure. Figure 2B is a cross-sectional side view of the semiconductor device along line B-B' in Figure 2A. Figure 2C is a cross-sectional side view of the semiconductor device shown along line C-C' in Figure 2A. Figure 2D is a cross-sectional side view of the semiconductor device along line D-D' in Figure 2A. 3A is a cross-sectional side view of a semiconductor device during one stage of a method of forming conductive vias in accordance with some embodiments of the present disclosure. 3B is a cross-sectional side view of a semiconductor device at another stage of a method of forming conductive vias in accordance with some embodiments of the present disclosure. 3C is a cross-sectional side view of a semiconductor device at another stage of a method of forming conductive vias in accordance with some embodiments of the present disclosure. Figure 3D is a cross-sectional side view of a semiconductor device at another stage of a method of forming conductive vias in accordance with some embodiments of the present disclosure. 3E is a cross-sectional side view of a semiconductor device at another stage of a method of forming conductive vias in accordance with some embodiments of the present disclosure. 3F is a cross-sectional side view of a semiconductor device at another stage of a method of forming conductive vias in accordance with some embodiments of the present disclosure. 3G is a cross-sectional side view of a semiconductor device at another stage of a method of forming conductive vias in accordance with some embodiments of the present disclosure. 3H is a cross-sectional side view of a semiconductor device at another stage of a method of forming conductive vias in accordance with some embodiments of the present disclosure.

Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

M1:Method

S110, S120, S130, S140, S150: steps

Claims (10)

A method of forming conductive vias, comprising: Patterning a mask layer over a semiconductor device, the semiconductor device including a first region and a second region; A first etching process is performed through the mask layer to form a first opening and a second opening with a first depth on the first region and the second region respectively, wherein the first opening exposes a first opening. a metal layer; Performing a second etching process through the mask layer to extend the first opening to a second depth, and extending the second opening to a third depth, wherein the second depth is different from the third depth; Performing a third etching process through the mask layer to extend the first opening and the second opening to a fourth depth and expose a bottom metal layer; and A conductive material is deposited in the first opening and the second opening. As in the method of forming a conductive via as described in claim 1, the step of performing the second etching process through the mask layer includes: The first opening penetrates the first metal layer and a second metal layer located below the first metal layer. The method of forming a conductive via as claimed in claim 1, wherein the step of performing the second etching process through the mask layer causes the first opening to expose an oxide layer underneath the first metal layer. The method of forming a conductive via as claimed in claim 1, wherein the step of performing the third etching process through the mask layer causes the first opening and the second opening to extend into the bottom metal layer, but not through this bottom metal layer. The method of forming a conductive via as claimed in claim 1, wherein the second depth is greater than the third depth. As for the method of forming a conductive via as described in claim 1, the step of depositing the conductive material includes: Conformally forming an adhesive layer on the side walls and bottom surfaces of the first opening and the second opening; and A filling layer is deposited in the first opening and the second opening. The method of forming a conductive via as claimed in claim 6, wherein the adhesive layer and the first metal layer are made of the same material. The method of forming a conductive via as described in claim 1 further includes: A mechanical grinding process is performed to remove a portion of the conductive material. The method of forming a conductive via as claimed in claim 1, wherein the first etching process and the third etching process use the same first etching gas, and the second etching process uses a different gas than the first etching gas. a second etching gas. The method of forming a conductive via as claimed in claim 9, wherein the first etching gas and the second etching gas have different etching speeds for the first metal layer.

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