TWI817444B - Semiconductor device with protection layer - Google Patents

Abstract

The present application discloses a semiconductor device. The semiconductor device includes a substrate; and a first gate stack positioned on the substrate and including: a first gate dielectric layer positioned on the substrate; a first gate protection layer positioned on the first gate dielectric layer and including titanium silicon nitride; a first work function layer positioned on the first gate protection layer; and a first gate filler layer positioned on the first work function layer.

Description

Semiconductor components with protective layer

This application claims priority to U.S. Patent Application Nos. 17/667,667 and 17/667,813 (that is, the priority date is "February 9, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device. In particular, it relates to a semiconductor component having a protective layer.

Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually becoming smaller to meet the increasing demand for computing power. However, during the downsizing process, different problems are added, and such problems continue to increase in number and complexity. Therefore, challenges remain in achieving improvements in quality, yield, performance and reliability, and in reducing complexity.

The above description of "prior art" only provides background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" does not constitute the prior art of the present disclosure. should not be used as any part of this case.

An embodiment of the present disclosure provides a semiconductor device, including a substrate; and a first gate stack disposed on the substrate and including: a first gate dielectric layer disposed on On the substrate; a first gate protection layer, which is disposed on the first gate dielectric layer and includes titanium silicon nitride; a first work function layer, which is disposed on the first gate protection layer; and a first A gate filling layer is provided on the first work function layer.

Another embodiment of the present disclosure provides a semiconductor device, including a substrate including an array area or a surrounding area surrounding the array area; a word line structure disposed in the array area; and a first A gate stack is disposed on the surrounding area and includes: a first gate dielectric layer disposed on the surrounding area; a first gate protection layer disposed on the first gate dielectric layer and including nitrogen titanium silicon; a first work function layer disposed on the first gate protection layer; and a first gate filling layer disposed on the first work function layer.

Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate including an array region and a surrounding region, the surrounding region surrounding the array region; forming a word line trench in the array region; Conformally forming a layer of first isolation material in the word line trench and on the substrate; Conformally forming a layer of protective material on the layer of first isolation material formed on the surrounding area; Conformally forming A layer of first work function material is formed on the layer of protective material; a layer of first barrier material is conformally formed on the layer of first isolation material and on the layer of first work function material; and a layer of filling material is formed on the layer of first work function material. on a barrier material; and patterning the layer of first isolation material, the layer of protection material, the layer of first work function material, the layer of first barrier material and the layer of filling material to form a first gate stack A word line structure is formed on the surrounding area and in the array area; wherein the protective material includes silicon titanium nitride.

Due to the design of the semiconductor device of the present disclosure, the first gate protection layer including titanium silicon nitride can have a low resistivity and excellent barrier properties, and is stable under heating. Therefore, the first gate stack including the first gate protection layer including titanium silicon nitride may have excellent characteristics. Therefore, the performance of the semiconductor device can be improved.

The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

1A: Semiconductor components

1B:Semiconductor components

1C: Semiconductor components

1D: Semiconductor components

1E: Semiconductor components

1F: Semiconductor components

1G: Semiconductor components

1H: Semiconductor components

10:Preparation method

100: First gate stack

101: First gate dielectric layer

103: First gate protection layer

105: First work function layer

105-1: Lower work function layer

105-3:Add work function layer

107: First gate barrier layer

109: First gate filling layer

111: First gate cover layer

113: First impurity region

115: First gap sub-layer

117:Interface layer

119:Adjustment layer

121:Dipole layer

123: Functional layer

200: Second gate stack

201: Second gate dielectric layer

203: Second gate protection layer

205: Second work function layer

207: Second gate barrier layer

209: Second gate filling layer

211: Second gate cover layer

213: Second impurity region

215: Second gap sub-layer

301: Base

303:Insulation layer

305: First active zone

307: Second active zone

309:Array active area

400: Character line structure

401: Character line isolation layer

403: Character line barrier layer

405: Character line conductive layer

407: Character line cover layer

407-1: Lower part

407-3: Upper part

409: Word line impurity area

501:The first isolation material

503: Protective materials

505: First work function material

507: Second work function material

509: First barrier material

511:Filling material

513: Hard mask material

515: Hard mask layer

601: First mask layer

603: Second mask layer

605: The third mask layer

AA: array area

PA:surrounding area

S11: Steps

S13: Steps

S15: Steps

S17: Steps

S19: Steps

S21: Steps

T1:Thickness

T2:Thickness

TR1: word line trench

Z: direction

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is understood that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

3 to 8 are schematic cross-sectional views illustrating portions of a semiconductor according to some embodiments of the present disclosure.

FIG. 9 is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

10 to 23 are schematic cross-sectional views illustrating a process of manufacturing a semiconductor device according to an embodiment of the present disclosure.

Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, descriptions in which the first component is formed on the second component may include embodiments in which the first and second components are in direct contact, or may include additional components formed between the first and second components. space so that the first and second components do not come into direct contact. In addition, embodiments of the present disclosure may repeat reference numbers and/or letters in many examples. These repetitions are for simplicity and clarity and do not in themselves represent a specific relationship between the various embodiments and/or configurations discussed unless otherwise specified herein.

In addition, for ease of explanation, spaces such as "beneath", "below", "lower", "above", "upper", etc. may be used in this article. Relative terms are used to describe the relationship of one element or feature shown in the figures to another (other) element or feature. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It will be understood that when one component is formed on, connected to, and/or coupled to another component, it may include forming direct contact between those components. examples, and may also include embodiments in which additional components are formed between the components so that the components are not in direct contact.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not governed by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present progressive concept.

Unless otherwise indicated in the content, it shall mean orientation, layout, location, shapes, sizes, and quantity. (amounts), or other measurements (measures), as used in this article such as "same (same)", "equal (equal)", "planar (planar)", or "total" Terms such as "coplanar" do not necessarily mean an exact identical orientation, layout, location, shape, size, quantity, or other measurement, but they do mean, within acceptable differences, that Substantially identical orientation, layout, location, shape, size, quantity, or other measurements, and acceptable differences may occur due to, for example, manufacturing processes. The term "substantially" may be used herein to convey this meaning. For example, as substantially the same, substantially equal, or substantially planar, as exactly the same, equal, or planar, or It may be the same, equal, or flat within acceptable differences that may occur due to the manufacturing process, for example.

In this disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a A semiconductor circuit (semiconductor circuit) and an electronic device (electronic device) are both included in the category of semiconductor components.

It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the opposite direction of the Z-direction arrow. .

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device 1A according to an embodiment of the present disclosure.

Referring to Figure 1, the semiconductor device 1A may include a substrate 301, an insulating layer 303. A first gate stack 100, a first gate capping layer 111, a plurality of first impurity regions 113, a first gap sub-layer 115, a second gate stack 200, and a second gate cap. The capping layer 211, a plurality of second impurity regions 213, a second gap sub-layer 215, a word line structure 400 and a plurality of word line impurity regions 409.

Referring to FIG. 1 , the substrate 301 may include an array area AA and a surrounding area PA. In a top view (not shown), the surrounding area PA may surround the array area AA. In some embodiments, the substrate 301 may be a block-shaped semiconductor substrate that is entirely composed of at least one semiconductor material. For example, the bulk semiconductor substrate may include an elemental semiconductor, a compound semiconductor, or a combination thereof. The elemental semiconductor is such as silicon or germanium. The compound semiconductor is such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, or phosphide. Indium, indium arsenide, indium antimonide or other III-V compound semiconductors or II-VI compound semiconductors.

In some embodiments, the substrate 301 may include a semiconductor-on-insulator structure composed from bottom to top of a handling substrate, an insulating layer, and an uppermost semiconductor material layer. The handling substrate and the uppermost semiconductor material layer may comprise the same material as the aforementioned bulk semiconductor substrate. The insulating layer may be a crystalline or amorphous dielectric material, such as an oxide and/or nitride. For example, the insulator can be a dielectric oxide, such as silicon oxide. As another example, the insulator may be a dielectric nitride such as silicon nitride or boron nitride. As yet another example, the insulating layer may be a stack of a dielectric oxide and a dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulating layer may have a thickness ranging from about 10 nm to about 200 nm.

It should be understood that the term "about" modifies a quantity of an ingredient, component, or reactant of the present disclosure, which represents a numerical variation that may occur, for example Generally speaking, it is based on typical measurements and liquid handling Liquid handling procedures are used to make concentrates or solutions. Furthermore, variation can occur due to inadvertent errors in the measurement procedures applied to the manufacturing compositions or implementation of these methods or similar methods, differences in manufacturing, and sources. (source), or purity of ingredients. In one aspect, the term "about" means within 10% of the reported value. On the other hand, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

Referring to FIG. 1 , the insulating layer 303 may be disposed in the array area AA and the surrounding area PA of the substrate 301 . For example, the insulating layer 303 may include an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or fluorine-doped silicate. The insulating layer 303 may define a first active area 305 and a second active area 307 in the peripheral area PA, and define an array active area 309 in the array area AA. In some embodiments, the second active area 307 may be disposed adjacent the first active area 305 . In some embodiments, the first active area 305 and the second active area 307 may be separated from each other.

It should be understood that the first active region 305 may include a portion of the substrate 301 and a space above and below the portion of the substrate 301 . Describing a component as being disposed on the first active area 305 means that the component is disposed on an upper surface of that part of the substrate 301 . Describing a component as being disposed in the first active region 305 means that the component is disposed in that portion of the substrate 301 ; however, an upper surface of the component may be flush with the upper surface of that portion of the substrate 301 . Describing a component as being disposed above (or on) the first active region means that the component is disposed above the upper surface of that portion of substrate 301 . Accordingly, the second active area 307 and the array active area 309 may respectively and correspondingly include other parts of the substrate 301 and multiple spaces above the other parts of the substrate 301 .

Referring to FIG. 1 , the first gate stack 100 may be disposed in the first active region 305 on the top, and may include a first gate dielectric layer 101, a first gate protection layer 103, a first work function layer 105, a first gate barrier layer 107 and a first gate filling layer 109 .

Referring to FIG. 1 , the first gate dielectric layer 101 may be disposed on the first active region 305 . In some embodiments, the thickness T1 of the first gate dielectric layer 101 may range from about 0.5 nm to about 5.0 nm. Preferably, the thickness T1 of the first gate dielectric layer 101 may range from about 0.5 nm to about 2.5 nm. In some embodiments, for example, first gate dielectric layer 101 may include an isolation material having a dielectric constant of about 4.0 or greater (unless otherwise noted, Otherwise all dielectric constants mentioned in the text are relative to a vacuum). For example, the isolation material having a dielectric constant of about 4.0 or greater may include hafnium oxide, zirconium hafnium oxide, lanthanum hafnium oxide, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium oxide, aluminum oxide, Silicon aluminum, titanium oxide, tantalum pentoxide, lanthanum oxide, lanthanum silicon oxide, strontium titanate, lanthanum aluminate, yttrium oxide, lead zirconium titanate, barium titanate , barium strontium titanate, barium zirconate or mixtures thereof. Alternatively, in another embodiment, the isolation material may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or the like.

Referring to FIG. 1 , the first gate protection layer 103 may be disposed on the first gate dielectric layer 101 . The first gate protection layer 103 may include titanium silicon nitride. The first gate protection layer 103 may have a low resistivity and excellent barrier properties, and be stable under heating. Therefore, the first gate stack 100 including the first gate protection layer 103 including titanium silicon nitride may have excellent characteristics. In some embodiments, the resistivity of the first gate protection layer 103 may be approximately 500 μΩ. cm to about 5000μΩ. cm. In some embodiments, the titanium content in the first gate protection layer 103 may be approximately 10 to 40 atomic percent. The silicon content in the first gate protection layer 103 may be approximately 10 to 40 atomic percent. In the first gate protection layer 103 The nitrogen content in may be approximately 25 to 47 atomic percent.

Please refer to FIG. 1 , the first work function layer 105 may be disposed on the first gate protection layer 103 . In some embodiments, the thickness of first work function layer 105 may be between about 10 Å and about 200 Å. Preferably, the thickness of the first work function layer 105 may be between about 10 Å and about 100 Å. In some embodiments, for example, the first work function layer 105 may include aluminum, silver, titanium, titanium nitride, titanium aluminum, titanium carbide aluminum, titanium nitride aluminum, Titanium silicon aluminum, tantalum nitride, tantalum carbide, silicon tantalum nitride, manganese, zirconium or tungsten nitride.

Referring to FIG. 1 , the first gate barrier layer 107 may be disposed on the first work function layer 105 . In some embodiments, for example, the first gate barrier layer 107 may be titanium nitride or a titanium/titanium nitride double layer.

Referring to FIG. 1 , the first gate filling layer 109 may be disposed on the first gate barrier layer 107 . In some embodiments, first gate fill layer 109 may include tungsten or aluminum, for example.

Referring to FIG. 1 , the first gate capping layer 111 may be disposed on the first gate filling layer 109 . In some embodiments, for example, the first gate capping layer 111 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or fluorine-doped silicate.

It should be understood that in the description of the present disclosure, silicon oxynitride represents a substance that includes silicon, nitrogen and oxygen, wherein a proportion of oxygen is greater than a proportion of nitrogen. Silicon nitride oxide represents a substance that contains silicon, oxygen and nitrogen, in which a proportion of nitrogen is greater than a proportion of oxygen.

Referring to FIG. 1 , a plurality of first impurity regions 113 may be disposed in the first active region 305 and adjacent to both ends of the first gate dielectric layer 101 . The plurality of first impurity regions 113 may have a first electrical type (eg, n-type or p-type). In some embodiments, the plurality of first impurity regions 113 may include p-type dopants, such as boron, aluminum, gallium, and indium. In some embodiments, the plurality of first impurity regions 113 may include n-type dopants, such as antimony, arsenic, and phosphorus. In some embodiments, the doping concentration of the plurality of first impurity regions 113 may range from about 1E19 atoms/cm ³ to about 1E21 atoms/cm ³ .

Referring to FIG. 1 , the first gap sublayer 115 may be disposed on the sidewall of the first gate stack 100 . In some embodiments, for example, the first interstitial layer 115 may include silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride. In some embodiments, the first spacer sub-layer 115 may include the same material as the first gate capping layer 111 .

Referring to FIG. 1 , the second gate stack 200 may be disposed on the second active region 307 and may include a second gate dielectric layer 201 , a second gate protection layer 203 , and a second work function layer 205 , a second gate barrier layer 207 and a second gate filling layer 209.

Referring to FIG. 1 , the second gate dielectric layer 201 may be disposed on the second active region 307 . In some embodiments, the thickness T2 of the second gate dielectric layer 201 may range from approximately 0.5 nm to approximately 5.0 nm. Preferably, the thickness T2 of the second gate dielectric layer 201 may range from about 0.5 nm to about 2.5 nm. In some embodiments, the thickness T2 of the second gate dielectric layer 201 and the thickness T1 of the first gate dielectric layer 101 may be substantially the same. In some embodiments, the thickness T2 of the second gate dielectric layer 201 is different from the thickness T1 of the first gate dielectric layer 101 . In some embodiments, the second gate dielectric layer 201 may include the same material as the first gate dielectric layer 101 . In some embodiments, for example, the second gate dielectric layer 201 may include an isolation material having a dielectric constant of approximately 4.0 or greater.

Referring to FIG. 1 , the second gate protection layer 203 may be disposed on the second gate dielectric layer 201 . The second gate protection layer 203 may include titanium silicon nitride. The second gate protection layer 203 may have a low resistivity and excellent barrier properties, and be stable under heating. Therefore, the package The second gate stack 200 including the second gate protection layer 203 including titanium silicon nitride may have excellent characteristics. In some embodiments, the resistivity of the second gate protection layer 203 may be approximately 500 μΩ. cm to about 5000μΩ. cm. In some embodiments, the titanium content in the second gate protection layer 203 may be approximately 10 to 40 atomic percent. The silicon content in the second gate protection layer 203 may be approximately 10 to 40 atomic percent. The nitrogen content in the second gate protection layer 203 may be approximately 25 to 47 atomic percent.

Referring to FIG. 1 , the second work function layer 205 may be disposed on the second gate protection layer 203 . In some embodiments, the thickness of the second work function layer 205 may be between about 10 Å and about 200 Å. Preferably, the thickness of the second work function layer 205 may be between about 10 Å and about 100 Å. In some embodiments, the thickness of the second work function layer 205 and the thickness of the first work function layer 105 may be substantially the same. In some embodiments, the thickness of second work function layer 205 may be different from the thickness of first work function layer 105 . In some embodiments, for example, the second work function layer 205 may include aluminum, silver, titanium, titanium nitride, titanium aluminum, titanium carbide aluminum, titanium nitride aluminum, Titanium silicon aluminum, tantalum nitride, tantalum carbide, silicon tantalum nitride, manganese, zirconium or tungsten nitride.

Referring to FIG. 1 , the second gate barrier layer 207 may be disposed on the second work function layer 205 . In some embodiments, the second gate barrier layer 207 may include the same material as the first gate barrier layer 107 . In some embodiments, for example, the second gate barrier layer 207 may be titanium nitride or a titanium/titanium nitride double layer.

Referring to FIG. 1 , the second gate filling layer 209 may be disposed on the second gate barrier layer 207 . In some embodiments, the second gate filling layer 209 may include the same material as the first gate filling layer 109 . In some embodiments, the second gate filling layer 209 may include tungsten or aluminum, for example.

Referring to FIG. 1 , the second gate capping layer 211 may be disposed on the second gate filling layer 209 . In some embodiments, the second gate capping layer 211 may include the same material as the first gate capping layer 111 . In some embodiments, for example, the second gate capping layer 211 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or fluorine-doped silicate.

Referring to FIG. 1 , a plurality of second impurity regions 213 may be disposed in the second active region 307 and adjacent to the second gate dielectric layer 201 . In some embodiments, the plurality of second impurity regions 213 may have the same electrical type as the plurality of first impurity regions 113 . In some embodiments, the electrical types of the plurality of second impurity regions 213 and the electrical types of the plurality of first impurity regions 113 may be different. In some embodiments, the plurality of second impurity regions 213 may include p-type dopants, such as boron, aluminum, gallium, and indium. In some embodiments, the plurality of second impurity regions 213 may include n-type dopants, such as antimony, arsenic, and phosphorus. In some embodiments, the doping concentration of the plurality of second impurity regions 213 may range from about 1E19 atoms/cm ³ to about 1E21 atoms/cm ³ .

Referring to FIG. 1 , the second gap sublayer 215 may be disposed on the sidewall of the second gate stack 200 . In some embodiments, second gap sub-layer 215 may include the same material as first gap sub-layer 115 . In some embodiments, for example, the second interstitial layer 215 may include silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride. In some embodiments, the second spacer sub-layer 215 may include the same material as the second gate capping layer 211 .

Referring to FIG. 1 , the word line structure 400 may be disposed in the array active area 309 . The word line structure 400 may include a word line isolation layer 401, a word line barrier layer 403, a word line conductive layer 405, and a word line capping layer 407.

Referring to FIG. 1 , the word line isolation layer 401 can be disposed inwardly in the array active area 309 . The word line isolation layer 401 may have a U-shaped cross-sectional profile. Having a U-shaped profile avoids corner effects. In some embodiments, for example, the word line isolation layer 401 may include an isolation material. The isolation material has a dielectric constant of approximately 4.0 or greater. Alternatively, in another embodiment, the isolation material may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or the like.

Referring to FIG. 1 , the word line barrier layer 403 may be disposed on the word line isolation layer 401 . The word line barrier layer 403 may have a U-shaped cross-sectional profile. In some embodiments, word line barrier layer 403 may include the same material as first gate barrier layer 107 . In some embodiments, for example, the word line barrier layer 403 may be titanium nitride or a titanium/titanium nitride double layer.

Referring to FIG. 1 , the word line conductive layer 405 may be disposed on the word line barrier layer 403 . In some embodiments, word line conductive layer 405 may include the same material as first gate filling layer 109 . In some embodiments, word line conductive layer 405 may include tungsten or aluminum, for example. In some embodiments, for example, the word line conductive layer 405 may include a conductive material, such as doped polysilicon, silicon germanium, metal, metal alloy, metal silicide, metal nitride, metal carbide, or combinations thereof of multiple layers. The metal can be aluminum, copper, tungsten or cobalt. The metal silicide may be nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide or the like.

Referring to FIG. 1 , the word line cap layer 407 can be disposed on the word line isolation layer 401 , the word line barrier layer 403 and the word line conductive layer 405 . The upper surface of the word line capping layer 407 and the upper surface of the substrate 301 may be substantially coplanar. In some embodiments, for example, the word line capping layer 407 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or fluorine-doped silicate.

Referring to FIG. 1 , a plurality of word line impurity regions 409 may be disposed in the array active region 309 and adjacent to the word line structure 400 . In some embodiments, word line impurity regions 409 may include p-type dopants such as boron, aluminum, gallium, and indium. In some embodiments, word line impurity regions 409 may include n-type dopants such as antimony, arsenic, and phosphorus. In some embodiments, the doping concentration of the word line impurity regions 409 may range from about 1E19 atoms/cm ³ to about 1E21 atoms/cm ³ .

FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device 1B according to another embodiment of the present disclosure.

Referring to FIG. 2 , the semiconductor device 1B may have a structure similar to that described in FIG. 1 . Elements in FIG. 2 that are the same as or similar to those in FIG. 1 have been labeled with similar element numbers, and repeated description thereof has been omitted.

In the semiconductor device 1B, the word line capping layer 407 may include a lower portion 407-1 and an upper portion 407-3. The lower part 407-1 may be disposed on the word line isolation layer 401, the word line barrier layer 403, and the word line conductive layer 405. The upper part 407-3 can be provided on the lower part 407-1. The upper surface of the upper part 407-3 and the upper surface of the base 301 may be substantially coplanar. Lower portion 407-1 may include an isolation material having a dielectric constant of approximately 4.0 or greater. The upper portion 407-3 may include a low dielectric constant material such as silicon oxide or the like. The upper portion 407-3 containing a low dielectric constant material can reduce the electric field on the surface above the substrate 301; therefore, leakage current can be reduced.

3 to 8 are schematic cross-sectional views illustrating some parts of semiconductors 1C, 1D, 1E, 1F, 1G, and 1H according to some embodiments of the present disclosure.

Referring to FIG. 3 , the semiconductor device 1C may have a structure similar to that described in FIG. 1 . Elements in FIG. 3 that are the same as or similar to those in FIG. 1 have been labeled with similar element numbers, and repeated descriptions thereof have been omitted.

In the semiconductor device 1C, the first work function layer 105 may include a lower work function layer 105-1 and an upper work function layer 105-3. The lower work function layer 105-1 may be disposed on the first gate protection layer 103. The upper work function layer 105-3 can be disposed between the lower work function layer 105-1 and the first gate barrier. between layers 107.

For example, the lower work function layer 105-1 may include aluminum, silver, titanium, titanium nitride, titanium aluminum, titanium carbide aluminum, titanium nitride aluminum, titanium silicide silicon aluminum), tantalum nitride, tantalum carbide, silicon tantalum nitride, manganese, zirconium or tungsten nitride. For example, the upper work function layer 105-3 may include titanium nitride, tantalum nitride, tantalum carbide, tungsten nitride, or ruthenium.

Referring to FIG. 4 , the semiconductor device 1D may have a structure similar to that described in FIG. 1 . Elements in FIG. 4 that are the same as or similar to those in FIG. 1 have been labeled with similar element numbers, and repeated descriptions thereof have been omitted.

In the semiconductor device 1D, an interface layer 117 may be disposed between the substrate 301 and the first gate dielectric layer 101 . In some embodiments, the thickness of interface layer 117 may be between about 5 Å and about 20 Å. Interface layer 117 may include a chemical oxide of substrate 301, such as silicon oxide. The interface layer 117 can facilitate the formation of the first gate dielectric layer 101 .

Referring to FIG. 5 , the semiconductor device 1E may have a structure similar to that described in FIG. 1 . Elements in FIG. 5 that are the same as or similar to those in FIG. 1 have been labeled with similar element numbers, and repeated descriptions thereof have been omitted.

In the semiconductor device 1E, an adjustment layer 119 may be disposed between the first gate protection layer 103 and the first work function layer 105 . In some embodiments, the adjustment layer 119 may include a material or an alloy including lanthanide nitride. The adjustment layer 119 can be used to fine-tune the threshold voltage of the first gate stack 100 .

Referring to FIG. 6 , the semiconductor device 1F may have a structure similar to that described in FIG. 1 . Elements in FIG. 6 that are the same as or similar to those in FIG. 1 have been labeled with similar element numbers, and repeated description thereof has been omitted.

In the semiconductor device 1F, a dipole layer 121 may be disposed between the substrate 301 and the first gate dielectric layer 101 . In some embodiments, dipole layer 121 may have a thickness less than 2 nm. The dipole layer 121 can replace multiple defects in the first gate dielectric layer 101 and improve the mobility and reliability of the first gate dielectric layer 101 . The dipole layer 121 may include a material including one or more of the following: lutetium oxide, lutetium silicon oxide, yttrium oxide, yttrium silicon oxide , lanthanum oxide, lanthanum silicon oxide, barium oxide, barium silicon oxide, strontium oxide, strontium silicon oxide, oxide Aluminum oxide, aluminum silicon oxide, titanium oxide, titanium silicon oxide, hafnium oxide, hafnium silicon oxide, zirconium oxide ( zirconium oxide), zirconium silicon oxide, tantalum oxide, tantalum silicon oxide, scandium oxide, scandium silicon oxide, magnesium oxide ) and magnesium silicon oxide.

Referring to FIG. 7 , the semiconductor device 1G may have a structure similar to that described in FIG. 1 . Elements in FIG. 7 that are the same as or similar to those in FIG. 1 have been labeled with similar element numbers, and repeated description thereof has been omitted.

In the semiconductor device 1G, a functional layer 123 may be disposed between the first gate dielectric layer 101 and the first gate protection layer 103 . In some embodiments, functional layer 123 may have a thickness between about 10 Å and about 15 Å. In some embodiments, functional layer 123 may include titanium nitride or tantalum nitride, for example. The functional layer 123 can protect the first gate dielectric layer 101 from damage during subsequent semiconductor processes. In some embodiments, for example For example, the functional layer 123 may include titanium and titanium silicide. The functional layer 123 can also reduce the resistivity of the first gate protection layer 103 . Therefore, the characteristics of the first gate stack 100 can be improved. As a result, the performance of the semiconductor device 1G can be improved.

Referring to FIG. 8 , the semiconductor device 1H may have a structure similar to that described in FIG. 1 . Elements in FIG. 8 that are the same as or similar to those in FIG. 1 have been labeled with similar element numbers, and repeated description thereof has been omitted.

In the semiconductor device 1H, the interface layer 117 may be provided on the substrate 301. The dipole layer 121 may be disposed between the first gate dielectric layer 101 and the interface layer 117 . The functional layer 123 may be disposed between the first gate dielectric layer 101 and the first gate protection layer 103 . The adjustment layer 119 may be disposed between the first work function layer 105 and the first gate protection layer 103 .

It should be understood that the terms "forming", "formed" and "form" can mean and include any creating, building, patterning, planting. A method of implanting or depositing an element, a dopant or a material. Examples of formation methods may include atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion (diffusing), depositing (depositing), growing (growing), implantation (implantation), photolithography (photolithography), dry etching and wet etching, but are not limited thereto.

It should be understood that in the description of the present disclosure, functions or steps mentioned herein may occur in a different order than in the figures. For example, two diagrams shown in succession may actually be executed at approximately the same time, or sometimes in the reverse order, depending on the functions or steps involved.

FIG. 9 is a schematic flowchart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. 10 to 23 are schematic cross-sectional views illustrating a process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure.

Referring to FIGS. 9 and 10 , in step S11 , a substrate 301 including an array area AA and a surrounding area PA may be provided, and an insulating layer 303 may be formed in the substrate 301 .

Referring to FIG. 10 , the surrounding area PA may surround the array area AA. A series of deposition processes may be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 301 . A photolithography process may be performed to define the location of the insulating layer 303 . After the lithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a plurality of trenches passing through the pad oxide layer, the pad nitride layer, and the substrate 301 . An isolation material may be deposited into the trenches, and a planarization process, such as chemical mechanical polishing, may then be performed to remove more than the fill material until substrate 301 is exposed and insulating layer 303 is formed. For example, the isolation material may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or fluorine-doped silicate. The insulating layer 303 may define a first active area 305 and a second active area 307 in the peripheral area PA, and define an array active area 309 in the array area AA.

Referring to FIGS. 9 and 11 , in step S13 , a word line trench TR1 may be formed in the array area AA, and a layer of first isolation material 501 may be conformally formed in the word line trench TR1 and on the substrate 301 superior.

Referring to FIG. 11, a photolithography process may be performed to define the position of the word line trench TR1 in the array area AA. After the lithography process, an etching process, such as an anisotropic dry etching process, may be performed to remove a portion of the substrate 301 and form the word line trench TR1. For example, the layer of first isolation material 501 may be conformally formed in the word line trench TR1 and on the substrate 301 by chemical vapor deposition, atomic layer deposition, or other applicable deposition processes. For example, the first isolation material 501 may include hafnium oxide, zirconium hafnium oxide, lanthanum hafnium oxide, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium oxide, aluminum oxide, silicon aluminum oxide, titanium oxide, dioxide pentoxide Tantalum pentoxide, lanthanum oxide, lanthanum silicon oxide, strontium titanate, lanthanum aluminate, yttrium oxide, gallium(III) trioxide, gadolinium gallium oxide, lead zirconate titanate zirconium titanate), barium titanate, barium strontium titanate (barium strontium titanate), barium zirconate (barium zirconate) or mixtures thereof.

Please refer to Figures 9, 12 and 13. In step S15, a layer of protective material 503 may be conformally formed on the layer of first isolation material 501, and the layer of first isolation material 501 is formed on the surrounding area PA, and A layer of first work function material 505 and a layer of second work function material 507 may be conformally formed on the layer of protective material 503 .

Referring to FIG. 12, a first mask layer 601 can be formed to cover the array area AA. For example, the first mask layer 601 may be silicon nitride. The protective material 503 may be titanium silicon nitride.

In some embodiments, the manufacturing technology of the layer of protective material 503 may include a thermal chemical vapor deposition process. During the thermal chemical vapor deposition process, a titanium-containing gas, a silicon-containing gas and a nitrogen-containing gas may be introduced into the layer of first isolation material 501 on the surrounding area PA to form a silicon titanium nitride film ( For example, this layer of protective material 503). For example, the titanium-containing gas may be tetraxydimethylaminotitanium (TDMAT) or tetraxydiethylaminotitanium (TDEAT). For example, the silicon-containing gas may be SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiH ₄ or Si2H ₆ . For example, the nitrogen-containing gas can be ammonia or monomethylhydrazine. The flow rate of the titanium-containing gas may be between about 5 standard cubic centimeters per minute (sccm) and about 50 sccm. The flow rate of the silicon-containing gas may be between about 5 sccm and about 500 sccm. The flow rate of nitrogen-containing gas may be between about 50 sccm and about 500 sccm. The process pressure of the thermal chemical vapor deposition process may range from about 0.3 Torr to about 5 Torr. The process temperature may range from about 400°C to about 650°C.

Alternatively, in some embodiments, the manufacturing technique of the layer of protective material 503 may include a plasma chemical vapor deposition process. For example, the gases used to generate the plasma can be hydrogen and argon. The frequency of the plasma RF power may be 13.56MHz. The RF power of the plasma can range from about 200W to about 800W. The flow rate of titanium-containing gas (eg, TiCl ₄ ) may be between about 1 sccm and about 10 sccm. The flow rate of the silicon-containing gas (eg, SiH ₄ ) may be between approximately 0.1 sccm and approximately 10 sccm. The flow rate of nitrogen-containing gas (N ₂ ) may range from about 30 sccm to about 500 sccm. The flow rate of hydrogen may be between approximately 100 and 3000 sccm. The flow rate of argon can be between approximately 100 and 2000 sccm. The process pressure of the plasma chemical vapor deposition process may range from about 0.5 Torr to about 5 Torr. The process temperature may be between about 350°C and about 450°C.

Alternatively, in some embodiments, a layer of titanium nitride and a layer of silicon nitride may be formed sequentially on the layer of first isolation material 501, and the layer of first isolation material 501 is formed on the surrounding area PA. An annealing process may be performed to convert the layer of titanium nitride and the layer of silicon nitride into a titanium silicon nitride film (eg, the layer of protective material 503 ).

Referring to FIG. 13 , in some embodiments, the layer of first work function material 505 and the layer of second work function material 507 may be formed separately. In some embodiments, the layer of first work function material 505 and the layer of second work function material 507 may include the same material and may be formed simultaneously. For example, the first work function material 505 and the second work function material 507 can be aluminum, silver, titanium, titanium nitride, titanium aluminum, titanium carbide aluminum, titanium nitride aluminum. , titanium silicon aluminum, Tantalum nitride, tantalum carbide, silicon tantalum nitride, manganese, zirconium or tungsten nitride. For example, the manufacturing technology of the layer of first work function material 505 and the layer of second work function material 507 may include atomic layer deposition, plasma vapor deposition, chemical vapor deposition or other applicable deposition processes.

Referring to FIGS. 9 , 14 and 15 , in step S17 , a layer of first barrier material 509 may be conformally formed on the layer of first isolation material 501 , on the layer of first work function material 505 and on the layer of first work function material 505 . The layer of second work function material 507 can be formed on the layer of first barrier material 509 , and a layer of filling material 511 can be formed on the layer of first barrier material 509 .

Referring to Figure 14, the first mask layer 601 can be removed. Next, the layer of first barrier material 509 may be conformally formed on the layer of first work function material 505, on the layer of second work function material 507, and on the layer of first isolation material 501, and the A layer of first isolation material 501 is formed in array area AA. For example, the manufacturing technology of the layer of first barrier material 509 may include chemical vapor deposition, atomic layer deposition, physical vapor deposition or other applicable deposition processes. The first barrier material 509 may be titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof.

Referring to FIG. 15 , the layer of filling material 511 may be formed on the layer of first barrier material 509 . For example, the manufacturing technology of the layer of filling material 511 may include physical vapor deposition, chemical vapor deposition, sputtering or other applicable deposition processes. For example, the filling material 511 may be tungsten, aluminum, doped polycrystalline silicon, silicon germanium, metal, metal alloy, metal silicide, metal nitride or metal carbide. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially flat surface for subsequent processing steps.

Please refer to Figure 9 and Figures 16 to 19. In step S19, the layer of first isolation material 501, the layer of protective material 503, the layer of first work function material 505, the layer of second work function material 507, can be patterned. The layer of first barrier material 509 and the layer of filling material 511 form a first gate stack 100 and a second gate stack 200 on the surrounding area PA.

Referring to FIG. 16 , a layer of hard mask material 513 may be formed on the layer of filling material 511 . A planarization process, such as chemical mechanical polishing, may be performed to provide a generally flat surface for subsequent processing steps. A second hard mask layer 603 may be formed on the layer of hard mask material 513. The second hard mask layer 603 may include patterns of the first gate stack 100 and the second gate stack 200 . It should be understood that the array area AA may be covered by the second hard mask layer 603 .

Referring to FIG. 17 , an etching process, such as an anisotropic dry etching process, may be performed to transfer the patterns of the first gate stack 100 and the second gate stack 200 to the hard mask layer 515 (also represented as pattern on the hard mask layer 515).

Referring to FIG. 18 , the patterned hard mask layer 515 can be used as a mask to perform an etching process to remove the first isolation material 501 , the protective material 503 , the first work function material 505 , and the second work function material 507 , the first barrier material 509 and some portions of the filling material 511 .

After the etching process, the layer of first isolation material 501 formed on the surrounding area PA can be converted into a first gate dielectric layer 101 and a second gate dielectric layer 201 . This layer of protective material 503 can be converted into a first gate protective layer 103 and a second gate protective layer 203 . This layer of first work function material 505 may be converted into first work function layer 105 . This layer of second work function material 507 can be converted into a second work function layer 205 . The layer of first barrier material 509 formed on the surrounding area PA can be converted into the first gate barrier layer 107 and the second gate barrier layer 207 . The layer of filling material 511 formed on the surrounding area PA can be converted into a first gate filling layer 109 and a second gate filling layer 209 .

Referring to FIG. 18 , the first gate dielectric layer 101 , the first gate protection layer 103 , the first work function layer 105 , the first gate barrier layer 107 and the first gate filling layer 109 may be configured to form a first Gate stack 100. The second gate dielectric layer 201, the second gate protection layer 203, the second work function layer 205, the second gate barrier layer 207 and the second gate filling layer 209 may be configured to form a second gate. Stack 200.

Referring to FIG. 19 , an implantation process may be performed to form a plurality of first impurity regions 113 and a plurality of second impurity regions 213 . The dopants in the implantation process may include p-type impurities (dopants) or n-type impurities (dopants). P-type impurities can be added to an intrinsic semiconductor to create multiple valence electron defects. In a silicon-containing substrate, examples of p-type dopants or impurities include, but are not limited to, boron, aluminum, gallium, and indium. n-type impurities can be added to an intrinsic semiconductor to contribute free electrons to the intrinsic semiconductor. In a silicon-containing substrate, examples of n-type dopants or impurities include, but are not limited to, antimony, arsenic, and phosphorus. In some embodiments, the doping concentration of the plurality of first impurity regions 113 and the plurality of second impurity regions 213 may range from about 1E19 atoms/cm ³ to about 1E21 atoms/cm ³ . After the implantation process, the plurality of first impurity regions 113 and the plurality of second impurity regions 213 may have an electrical type, such as n-type or p-type. In some embodiments, the manufacturing technology of the plurality of first impurity regions 113 and the plurality of second impurity regions 213 may include two different implant processes.

Please refer to FIG. 1 and FIG. 20 to FIG. 23. In step S21, a word line structure 400 may be formed in the array area AA.

Referring to FIG. 20 , a third mask layer 605 can be formed to cover the surrounding area PA. A recess process may be performed to remove portions of the first isolation material 501, the first barrier material 509, and the filling material 511 in the array area AA. After the recessing process, the layer of first isolation material 501 can be converted into a word line isolation layer 401 in the word line trench TR1. This layer of first barrier material 509 can be converted into a word line barrier layer 403 in word line trench TR1. This layer of fill material 511 may be converted into word line conductive layer 405 in word line trench TR1.

Referring to FIG. 21, a word line capping layer 407 may be formed to completely fill the word line trench TR1. Word line isolation layer 401, word line barrier layer 403, word line conductive layer 405 and so on Together with the word line capping layer 407, the word line structure 400 is configured.

Referring to FIG. 22, an implantation process may be performed to form a plurality of word line impurity regions 409. The dopants in the implantation process may include p-type impurities (dopants) or n-type impurities (dopants). In some embodiments, the word line impurity regions 409 have a doping concentration between about 1E19 atoms/cm ³ and about 1E21 atoms/cm ³ . After the implantation process, the plurality of word line impurity regions 409 may have an electrical type, such as N-type or p-type.

Referring to Figure 23, the third mask layer 605 can be removed. Next, a layer of spacer material (not shown) may be conformally formed on the substrate 301 to cover the first gate stack 100 and the second gate stack 200 . For example, the spacer material may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride or fluorine-doped silicate. An etching process, such as an anisotropic dry etching process, may be performed to remove a portion of the spacer material and simultaneously form the first gate capping layer 111 , the first spacer sublayer 115 , and the second gate capping layer. 211 and the second gap sub-layer 215.

An embodiment of the present disclosure provides a semiconductor device, including a substrate; and a first gate stack disposed on the substrate and including: a first gate dielectric layer disposed on the substrate; a first gate stack An extremely protective layer, which is disposed on the first gate dielectric layer and includes silicon titanium nitride; a first work function layer, which is disposed on the first gate protective layer; and a first gate filling layer, which is disposed on on the first work function layer.

Another embodiment of the present disclosure provides a semiconductor device, including a substrate including an array area or a surrounding area surrounding the array area; a word line structure disposed in the array area; and a first A gate stack is disposed on the surrounding area and includes: a first gate dielectric layer disposed on the surrounding area; a first gate protection layer disposed on the first gate dielectric layer and including nitrogen titanium silicon; a first work function layer disposed on the first gate protection layer; and a first gate filling layer disposed on the first work function layer.

Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate including an array region and a surrounding region, the surrounding region surrounding the array region; forming a word line trench in the array region; Conformally forming a layer of first isolation material in the word line trench and on the substrate; Conformally forming a layer of protective material on the layer of first isolation material formed on the surrounding area; Conformally forming A layer of first work function material is formed on the layer of protective material; a layer of first barrier material is conformally formed on the layer of first isolation material and on the layer of first work function material; and a layer of filling material is formed on the layer of first work function material. on a barrier material; and patterning the layer of first isolation material, the layer of protection material, the layer of first work function material, the layer of first barrier material and the layer of filling material to form a first gate stack A word line structure is formed on the surrounding area and in the array area; wherein the protective material includes titanium silicon nitride.

Due to the design of the semiconductor device of the present disclosure, the first gate protection layer 103 including titanium silicon nitride can have a low resistivity and excellent barrier properties, and is stable under heating. Therefore, the first gate stack 100 including the first gate protection layer 103 including titanium silicon nitride may have excellent characteristics. Therefore, the performance of the semiconductor device 1A can be improved.

Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, these processes, Machinery, manufacturing, material composition, means, methods, or steps are included in the patent scope of this application.

1A: Semiconductor components 100: First gate stack 101: First gate dielectric layer 103: First gate protection layer 105: First work function layer 107: First gate barrier layer 109: First gate filling layer 111: First gate cover layer 113: First impurity region 115: First gap sub-layer 200: Second gate stack 201: Second gate dielectric layer 203: Second gate protection layer 205: Second work function layer 207: Second gate barrier layer 209: Second gate filling layer 211: Second gate cover layer 213: Second impurity region 215: Second gap sub-layer 301: Base 303:Insulation layer 305: First active zone 307: Second active zone 309:Array active area 400: Character line structure 401: Character line isolation layer 403: Character line barrier layer 405: Character line conductive layer 407: Character line cover layer 409: Word line impurity area AA: array area PA:surrounding area T1:Thickness T2:Thickness Z: direction

Claims (14)

A semiconductor device includes: a substrate including an array region and a surrounding region; and a first gate stack disposed on the substrate and including: a first gate dielectric layer disposed on the substrate; A first gate protection layer is provided on the first gate dielectric layer and includes silicon titanium nitride; a first work function layer is provided on the first gate protection layer; a first gate filling layer, disposed on the first work function layer; and a word line structure disposed in the array area; wherein the word line structure includes: a word line isolation layer disposed inward in the array area; a word line structure disposed inwardly in the array area; A character line conductive layer is disposed on the character line isolation layer; and a character line cover layer is disposed on the character line isolation layer and the character line conductive layer. The semiconductor device of claim 1, wherein the surrounding area surrounds the array area, and the first gate stack is disposed on the surrounding area. The semiconductor device according to claim 2, further comprising a first gate barrier layer disposed between the first work function layer and the first gate filling layer; wherein the first gate barrier layer includes Titanium nitride or titanium/titanium nitride double layer. The semiconductor device according to claim 3, further comprising a first gate capping layer disposed on the first gate filling layer; wherein the first gate capping layer includes silicon oxide, silicon nitride, nitrogen Silicon oxide, silicon nitride oxide or fluorine-doped silicate. The semiconductor device according to claim 4, further comprising an insulating layer disposed in the surrounding area of the substrate and defining a first active area and a second active area, the second active area being adjacent to the first active area. area; wherein the first gate stack is disposed on the first active area. The semiconductor device according to claim 5, further comprising a plurality of first impurity regions disposed in the first active region and adjacent to the first gate dielectric layer. The semiconductor device according to claim 6, further comprising a second gate stack disposed on the second active region and including: a second gate dielectric layer disposed on the second active region; a second a gate protection layer disposed on the second gate dielectric layer and including silicon titanium nitride; a second work function layer disposed on the second gate protection layer; and a second gate filling layer, disposed on the second work function layer. The semiconductor device of claim 7, wherein a thickness of the first gate dielectric layer is substantially the same as a thickness of the second gate dielectric layer. The semiconductor device according to claim 8, wherein the first work function layer and the second work function layer include aluminum, silver, titanium, titanium nitride, titanium aluminum, titanium carbide aluminum, aluminum nitride Titanium nitride aluminum, titanium silicon aluminum, tantalum nitride, tantalum carbide, silicon tantalum nitride, manganese, zirconium or tungsten nitride. The semiconductor device of claim 8, wherein the first work function layer and the second work function layer include different materials. The semiconductor device according to claim 9, further comprising a plurality of second impurity regions disposed in the second active region and adjacent to the second gate dielectric layer. The semiconductor device of claim 11, wherein an electrical type of the plurality of first impurity regions is the same as an electrical type of the plurality of second impurity regions. The semiconductor device of claim 11, wherein an electrical type of the plurality of first impurity regions is different from an electrical type of the plurality of second impurity regions. The semiconductor device according to claim 1, wherein the word line cover layer includes a lower part and an upper part, the lower part is disposed on the word line isolation layer and the word line conductive layer, and the upper part is disposed on the lower part on; wherein the lower part includes an isolation material having a dielectric constant of approximately 4.0 or greater; wherein the upper part includes a low dielectric constant material.