TWI803281B - Semiconductor device with protection layer and method for fabricating the same - Google Patents

Abstract

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including an array area and a peripheral area surrounding the array area; a word line structure positioned in the array area; and a first gate stack positioned on the peripheral area and including: a first gate dielectric layer positioned on the peripheral area; a first gate protection layer positioned on the first gate dielectric layer and including titanium silicon nitride; a first work function layer positioned on the first gate protection layer; and a first gate filler layer positioned on the first work function layer.

Description

Semiconductor element with protective layer and preparation method thereof

This application claims priority to US Patent Application Nos. 17/667,667 and 17/667,813 (ie, the priority date is "February 9, 2022"), the contents of which are incorporated herein by reference in their entirety.

The disclosure relates to a semiconductor element and a method for manufacturing the semiconductor element. In particular, it relates to a semiconductor element with a protective layer and a method for preparing the semiconductor element with the protective layer.

Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually reduced to meet the increasing demand for computing power. However, during the process of shrinking dimensions, different problems are added, and such problems continue to increase in number and complexity. Therefore, challenges remain in achieving improved quality, yield, performance and reliability, and reduced complexity.

The above "prior art" description only provides background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" is It should not be part of this case.

An embodiment of the present disclosure provides a semiconductor device, including a substrate; and a first gate stack disposed on the substrate and including: a first gate dielectric layer disposed on the substrate; a first gate stack An electrode protection layer disposed on the first gate dielectric layer includes silicon nitride titanium; a first work function layer disposed on the first gate protection layer; and a first gate filling layer disposed on the on the first work function layer.

Another embodiment of the present disclosure provides a semiconductor device, including a base, including an array area and a surrounding area, the surrounding area surrounds the array area; a word line structure is disposed in the array area; and a first A gate stack, disposed on the surrounding area and including: a first gate dielectric layer, disposed on the surrounding area; a first gate protection layer, disposed on the first gate dielectric layer and comprising silicon titanium nitride; a first work function layer disposed on the first gate protection layer; and a first gate filling layer disposed on the first work function layer.

Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, including an array region and a peripheral region, the peripheral region surrounding the array region; forming a word line trench in the array region; Conformally forming a layer of first isolation material in the word line trench and on the substrate; conformally forming a layer of protective material on the layer of first isolation material formed on the surrounding area; conformally forming a layer of first work function material on the layer of protective material; conformally forming a layer of first barrier material on the layer of first isolation material and on the layer of first work function material; forming a layer of filler material on the layer of first on a barrier material; and patterning the layer of first isolation material, the layer of protection material, the layer of first work function material, the layer of first barrier material and the layer of filling material to form a first gate stack A word line structure is formed on the surrounding area and in the array area; wherein the protection material includes titanium silicon nitride.

Due to the design of the semiconductor device disclosed in the present disclosure, the first gate protective layer comprising titanium silicon nitride can have a low resistivity and an excellent barrier characteristic, and is stable. Therefore, the first gate stack including the first gate protection layer including titanium silicon nitride can have excellent characteristics. Therefore, the performance of the semiconductor device can be improved.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

1A: Semiconductor components

1B: Semiconductor components

1C: Semiconductor components

1D: Semiconductor components

1E: Semiconductor components

1F: Semiconductor components

1G: Semiconductor components

1H: Semiconductor components

10: Preparation method

100: first gate stack

101: The first gate dielectric layer

103: The first gate protection layer

105: The first work function layer

105-1: Lower work function layer

105-3: Upper work function layer

107: The first gate barrier layer

109: The first gate filling layer

111: the first gate cover layer

113: the first impurity region

115: The first gap sublayer

117: interface layer

119: Adjustment Layers

121: dipole layer

123: Functional layer

200: second gate stack

201: second gate dielectric layer

203: Second gate protection layer

205: Second work function layer

207: The second gate barrier layer

209: Second gate filling layer

211: second gate cover layer

213: the second impurity region

215: Second gap sublayer

301: Base

303: insulation layer

305: The first active zone

307: The second active area

309: Array active area

400: character line structure

401: word line isolation layer

403: word line barrier layer

405: word line conductive layer

407:Character line cover layer

407-1: lower part

407-3: upper part

409: Word line impurity area

501: The first isolation material

503: Protective material

505: First work function materials

507:Second work function material

509: The first barrier material

511: filling material

513: Hard mask material

515: Hard mask layer

601: The first mask layer

603: The second mask layer

605: The third mask layer

AA: array area

PA: Peripheral Area

S11: step

S13: step

S15: step

S17: step

S19: step

S21: step

T1: Thickness

T2: Thickness

TR1: word line groove

Z: Direction

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be understood that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure.

3 to 8 are schematic cross-sectional views illustrating some parts of semiconductors according to some embodiments of the present disclosure.

FIG. 9 is a schematic flow diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

10 to 23 are schematic cross-sectional views illustrating a process for manufacturing a semiconductor device according to an embodiment of the present disclosure.

Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Certainly, these embodiments are only for illustration, and are not intended to limit the scope of the present disclosure. for example In other words, in the description that the first part is formed on the second part, it may include the embodiment in which the first and second parts are formed in direct contact, and may also include an additional part formed between the first and second parts, so that the first An embodiment in which the first and second parts are not in direct contact. In addition, embodiments of the present disclosure may repeat reference numerals and/or letters in many instances. These repetitions are for the purpose of simplicity and clarity and, unless otherwise indicated in the context, do not in themselves imply a specific relationship between the various embodiments and/or configurations discussed.

Additionally, for ease of description, spaces such as "beneath", "below", "lower", "above", "upper" may be used herein Relative relationship terms are used to describe the relationship of one element or feature to another (other) element or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be at other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It should be understood that when forming a component on, connected to, and/or coupled to another component, it may include implementations where these components are formed in direct contact. Examples, and may also include embodiments in which additional components are formed between these components such that the components do not come into direct contact.

It will be understood that although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not constrained by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the presently advanced concepts.

Unless the context indicates otherwise, when referring to orientation, layout, location, shapes, sizes, amounts, or other measures, Then terms such as "same", "equal", "planar", or "coplanar" as used herein are not necessarily Means an exact identical orientation, arrangement, position, shape, size, quantity, or other measurement, but it is meant to include, within acceptable variance, nearly identical orientation, arrangement, position, shape, size , quantity, or other measure, and for example, the acceptable variance may occur due to manufacturing processes (manufacturing processes). The term "substantially" may be used herein to express this meaning. For example, as substantially the same, substantially equal, or substantially planar, as being exactly the same, equal, or planar, or Yes, they may be the same, equal, or flat within acceptable variances that may occur, for example, due to manufacturing processes.

In this disclosure, a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a Both a semiconductor circuit and an electronic device are included in the category of semiconductor devices.

It should be understood that in the description of the present disclosure, above (or above (up)) corresponds to the direction of the Z-direction arrow, and below (or below (down)) corresponds to the relative direction of the Z-direction arrow .

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure 1A.

Please refer to FIG. 1 , the semiconductor device 1A may include a substrate 301, an insulating layer 303, a first gate stack 100, a first gate capping layer 111, a plurality of first impurity regions 113, and a first spacer. layer 115, a second gate stack 200, a second gate cap layer 211, a plurality of second impurity regions 213, a second gap sublayer 215, a word line structure 400 and a plurality of word line impurities District 409.

Please refer to FIG. 1 , the substrate 301 may include an array area AA and a peripheral area PA. In a top view (not shown), the surrounding area PA may surround the array area AA. In some embodiments, the substrate 301 may be a monolithic semiconductor substrate completely composed of at least one semiconductor material. For example, the bulk semiconductor substrate may comprise an elemental semiconductor such as silicon or germanium, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, phosphide, or a combination thereof. Indium, indium arsenide, indium antimonide or other III-V compound semiconductors or II-VI compound semiconductors.

In some embodiments, the substrate 301 may include a semiconductor-on-insulator structure composed from bottom to top of a handle substrate, an insulating layer, and an uppermost layer of semiconductor material. The handle substrate and the uppermost layer of semiconductor material may comprise the same materials as described above for the bulk semiconductor substrate. The insulating layer can be a crystalline or amorphous dielectric material, such as an oxide and/or nitride. For example, the insulator can be a dielectric oxide such as silicon oxide. As another example, the insulator may be a dielectric nitride such as silicon nitride or boron nitride. As another example, the insulating layer may be a stack of a dielectric oxide and a dielectric nitride, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulating layer may have a thickness between about 10 nm and about 200 nm.

It should be understood that the term "about" modifies ingredients, parts A quantity (quantity) of a piece, or a reactant (reactant) of the present disclosure, which represents a variation (variation) in a numerical quantity that can occur, for example, which is obtained through typical measurement and liquid handling procedures (liquid handling procedures) ), and the liquid handling process is used to make concentrates or solutions. Furthermore, variations may arise from inadvertent errors in measurement procedures applied to the manufacture of compositions or in the implementation of the methods or the like, differences in manufacture, source (source), or the purity of ingredients (purity). In one aspect, the term "about" means within 10% of the reported value. On the other hand, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

Please refer to FIG. 1 , the insulating layer 303 may be disposed in the array area AA and the surrounding area PA of the substrate 301 . For example, the insulating layer 303 may include an isolation material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride or fluorine-doped silicate. The insulating layer 303 can define a first active area 305 and a second active area 307 in the peripheral area PA, and define an array active area 309 in the array area AA. In some embodiments, the second active region 307 may be disposed adjacent to the first active region 305 . In some embodiments, the first active region 305 and the second active region 307 can be separated from each other.

It should be understood that the first active region 305 may include a portion of the substrate 301 and a space above and below the portion of the substrate 301 . It is described that a device is disposed on the first active region 305 , which means that the device is disposed on an upper surface of the portion of the substrate 301 . It is described that a device is disposed in the first active region 305 , which means that the device is disposed in the portion of the substrate 301 ; however, an upper surface of the device may be flush with the upper surface of the portion of the substrate 301 . It is described that an element is disposed on (or on) the first active region, which means that the element is disposed on the upper surface of the portion of the substrate 301 . Accordingly, the second active area 307 and the array active area 309 can be respectively and correspond to Including other parts of the base 301 and a plurality of spaces above the other parts of the base 301 .

Referring to FIG. 1, the first gate stack 100 can be disposed on the first active region 305, and can include a first gate dielectric layer 101, a first gate protection layer 103, and a first work function layer 105. , a first gate barrier layer 107 and a first gate filling layer 109 .

Referring to FIG. 1 , the first gate dielectric layer 101 may be disposed on the first active region 305 . In some embodiments, the thickness T1 of the first gate dielectric layer 101 may be between about 0.5 nm and about 5.0 nm. Preferably, the thickness T1 of the first gate dielectric layer 101 may be between about 0.5 nm and about 2.5 nm. In some embodiments, for example, the first gate dielectric layer 101 may include an isolation material having a dielectric constant of approximately 4.0 or greater (unless otherwise noted, Otherwise all dielectric constants mentioned in the text are relative to a vacuum). For example, the isolation material having a dielectric constant of about 4.0 or greater may include hafnium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, zirconium oxide, aluminum oxide, hafnium oxide Silicon aluminum, titanium oxide, tantalum pentoxide, lanthanum oxide, lanthanum silicon oxide, strontium titanate, lanthanum aluminate, yttrium oxide, lead zirconium titanate, barium titanate , barium strontium titanate, barium zirconate or mixtures thereof. Alternatively, in another embodiment, the isolation material may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride or the like.

Referring to FIG. 1 , the first gate protection layer 103 may be disposed on the first gate dielectric layer 101 . The first gate protection layer 103 may include titanium silicon nitride. The first gate protection layer 103 can have a low resistivity and an excellent barrier property, and is stable under heating. Therefore, the first gate stack 100 including the first gate protection layer 103 including titanium silicon nitride can have excellent characteristics. In some embodiments, the resistivity of the first gate protection layer 103 may be between about 500μΩ. cm to about 5000μΩ. between cm. In some embodiments, in the first gate protection layer The titanium content in 103 may be approximately 10 to 40 atomic percent. The silicon content in the first gate protection layer 103 may be about 10 to 40 atomic percent. The nitrogen content in the first gate protection layer 103 may be about 25 to 47 atomic percent.

Referring to FIG. 1 , the first work function layer 105 may be disposed on the first gate protection layer 103 . In some embodiments, the thickness of the first work function layer 105 may be between about 10 Å and about 200 Å. Preferably, the thickness of the first work function layer 105 may be between about 10 Å and about 100 Å. In some embodiments, for example, the first work function layer 105 may include aluminum, silver, titanium, titanium nitride, titanium aluminum, titanium carbide aluminum, titanium nitride aluminum, Titanium silicon aluminum, tantalum nitride, tantalum carbide, tantalum silicon nitride, manganese, zirconium or tungsten nitride.

Referring to FIG. 1 , the first gate barrier layer 107 may be disposed on the first work function layer 105 . In some embodiments, for example, the first gate barrier layer 107 can be titanium nitride or a titanium/titanium nitride double layer.

Referring to FIG. 1 , the first gate filling layer 109 may be disposed on the first gate barrier layer 107 . In some embodiments, for example, the first gate-fill layer 109 may include tungsten or aluminum.

Referring to FIG. 1 , the first gate capping layer 111 may be disposed on the first gate filling layer 109 . In some embodiments, for example, the first gate capping layer 111 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride or fluorine-doped silicate.

It should be understood that in the description of the present disclosure, silicon oxynitride refers to a substance including silicon, nitrogen and oxygen, wherein a proportion of oxygen is greater than a proportion of nitrogen. Silicon oxynitride refers to a substance comprising silicon, oxygen and nitrogen, wherein a proportion of nitrogen is greater than a proportion of oxygen.

Referring to FIG. 1 , a plurality of first impurity regions 113 may be disposed in the first active region 305 and adjacent to both ends of the first gate dielectric layer 101 . The plurality of first impurity regions 113 can have a first electrical type (eg, n-type or p-type). In some embodiments, the plurality of first impurity regions 113 may include p-type dopants such as boron, aluminum, gallium and indium. In some embodiments, the plurality of first impurity regions 113 may include n-type dopants such as antimony, arsenic and phosphorus. In some embodiments, the doping concentration of the plurality of first impurity regions 113 may be between about 1E19 atoms/cm ³ and about 1E21 atoms/cm ³ .

Referring to FIG. 1 , the first gap sublayer 115 may be disposed on the sidewall of the first gate stack 100 . In some embodiments, for example, the first gap sublayer 115 may include silicon oxide, silicon nitride, silicon oxynitride or silicon oxynitride. In some embodiments, the first gap sublayer 115 may include the same material as the first gate cap layer 111 .

Referring to FIG. 1, the second gate stack 200 can be disposed on the second active region 307, and can include a second gate dielectric layer 201, a second gate protection layer 203, and a second work function layer 205. , a second gate barrier layer 207 and a second gate filling layer 209 .

Referring to FIG. 1 , the second gate dielectric layer 201 may be disposed on the second active region 307 . In some embodiments, the thickness T2 of the second gate dielectric layer 201 may be between about 0.5 nm and about 5.0 nm. Preferably, the thickness T2 of the second gate dielectric layer 201 may be between about 0.5 nm and about 2.5 nm. In some embodiments, the thickness T2 of the second gate dielectric layer 201 and the thickness T1 of the first gate dielectric layer 101 may be substantially the same. In some embodiments, the thickness T2 of the second gate dielectric layer 201 is different from the thickness T1 of the first gate dielectric layer 101 . In some embodiments, the second gate dielectric layer 201 may include the same material as the first gate dielectric layer 101 . In some embodiments, for example, the second gate dielectric layer 201 may include an isolation material having a dielectric constant of approximately 4.0 or greater.

Please refer to FIG. 1, the second gate protection layer 203 can be disposed on the second gate dielectric layer 201 on. The second gate protection layer 203 may include titanium silicon nitride. The second gate protection layer 203 can have a low resistivity and an excellent barrier property, and is stable under heating. Therefore, the second gate stack 200 including the second gate protection layer 203 including titanium silicon nitride can have excellent characteristics. In some embodiments, the resistivity of the second gate protection layer 203 may be between about 500μΩ. cm to about 5000μΩ. between cm. In some embodiments, the titanium content in the second gate protection layer 203 may be about 10 to 40 atomic percent. The silicon content in the second gate protection layer 203 may be about 10 to 40 atomic percent. The nitrogen content in the second gate protection layer 203 may be about 25 to 47 atomic percent.

Referring to FIG. 1 , the second work function layer 205 may be disposed on the second gate protection layer 203 . In some embodiments, the thickness of the second work function layer 205 may be between about 10 Å to about 200 Å. Preferably, the thickness of the second work function layer 205 may be between about 10 Å to about 100 Å. In some embodiments, the thickness of the second work function layer 205 and the thickness of the first work function layer 105 may be substantially the same. In some embodiments, the thickness of the second work function layer 205 may be different from the thickness of the first work function layer 105 . In some embodiments, for example, the second work function layer 205 may include aluminum, silver, titanium, titanium nitride, titanium aluminum, titanium carbide aluminum, titanium nitride aluminum, Titanium silicon aluminum, tantalum nitride, tantalum carbide, tantalum silicon nitride, manganese, zirconium or tungsten nitride.

Referring to FIG. 1 , the second gate barrier layer 207 may be disposed on the second work function layer 205 . In some embodiments, the second gate barrier layer 207 may include the same material as the first gate barrier layer 107 . In some embodiments, for example, the second gate barrier layer 207 can be titanium nitride or a titanium/titanium nitride double layer.

Referring to FIG. 1 , the second gate filling layer 209 may be disposed on the second gate barrier layer 207 . In some embodiments, the second gate filling layer 209 may include 109 of the same material. In some embodiments, the second gate-fill layer 209 may include tungsten or aluminum, for example.

Referring to FIG. 1 , the second gate capping layer 211 may be disposed on the second gate filling layer 209 . In some embodiments, the second gate capping layer 211 may include the same material as the first gate capping layer 111 . In some embodiments, for example, the second gate cap layer 211 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride or fluorine-doped silicate.

Referring to FIG. 1 , a plurality of second impurity regions 213 may be disposed in the second active region 307 and adjacent to the second gate dielectric layer 201 . In some embodiments, the plurality of second impurity regions 213 may have the same electrical type as the plurality of first impurity regions 113 . In some embodiments, the electrical type of the plurality of second impurity regions 213 may be different from the electrical type of the plurality of first impurity regions 113 . In some embodiments, the plurality of second impurity regions 213 may include p-type dopants such as boron, aluminum, gallium and indium. In some embodiments, the plurality of second impurity regions 213 may include n-type dopants such as antimony, arsenic and phosphorus. In some embodiments, the doping concentration of the plurality of second impurity regions 213 may be between about 1E19 atoms/cm ³ and about 1E21 atoms/cm ³ .

Referring to FIG. 1 , the second gap sublayer 215 may be disposed on the sidewall of the second gate stack 200 . In some embodiments, the second gap sublayer 215 may comprise the same material as the first gap sublayer 115 . In some embodiments, for example, the second gap sublayer 215 may include silicon oxide, silicon nitride, silicon oxynitride or silicon oxynitride. In some embodiments, the second gap sublayer 215 may include the same material as the second gate cap layer 211 .

Referring to FIG. 1 , the word line structure 400 can be disposed in the array active area 309 . The word line structure 400 may include a word line isolation layer 401 , a word line barrier layer 403 , a word line conductive layer 405 and a word line capping layer 407 .

Please refer to FIG. 1, the word line isolation layer 401 can be set inwardly in the active area of the array 309 in. The word line isolation layer 401 may have a U-shaped profile. Has a U-shaped profile to avoid corner effects. In some embodiments, for example, the word line isolation layer 401 may include an isolation material having a dielectric constant of about 4.0 or greater. Alternatively, in another embodiment, the isolation material may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride or the like.

Referring to FIG. 1 , the word line barrier layer 403 can be disposed on the word line isolation layer 401 . The word line barrier layer 403 may have a U-shaped profile. In some embodiments, the word line barrier layer 403 may include the same material as the first gate barrier layer 107 . In some embodiments, for example, the word line barrier layer 403 can be titanium nitride or a titanium/titanium nitride double layer.

Referring to FIG. 1 , the word line conductive layer 405 can be disposed on the word line barrier layer 403 . In some embodiments, the word line conductive layer 405 may include the same material as the first gate filling layer 109 . In some embodiments, word line conductive layer 405 may include tungsten or aluminum, for example. In some embodiments, for example, the word line conductive layer 405 may include a conductive material, such as doped polysilicon, silicon germanium, metal, metal alloy, metal silicide, metal nitride, metal carbide, or a combination thereof. of multiple layers. The metal can be aluminum, copper, tungsten or cobalt. The metal silicide may be nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like.

Referring to FIG. 1 , the word line capping layer 407 may be disposed on the word line isolation layer 401 , the word line barrier layer 403 and the word line conductive layer 405 . The upper surface of the word line capping layer 407 and the upper surface of the substrate 301 may be substantially coplanar. In some embodiments, for example, the word line capping layer 407 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or fluorine-doped silicate.

Please refer to FIG. 1 , a plurality of word line impurity regions 409 may be disposed in the array active region 309 and adjacent to the word line structure 400 . In some embodiments, the plurality of word line impurity regions 409 may include p-type dopants such as boron, aluminum, gallium and indium. In some embodiments, the plurality of word line impurity regions 409 may include n-type dopants such as antimony, arsenic, and phosphorus. In some embodiments, the doping concentration of the plurality of word line impurity regions 409 may be between about 1E19 atoms/cm ³ and about 1E21 atoms/cm ³ .

FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device 1B according to another embodiment of the present disclosure.

Please refer to FIG. 2 , the semiconductor device 1B may have a structure similar to that described in FIG. 1 . Components in FIG. 2 that are the same as or similar to those in FIG. 1 have been labeled with similar component numbers, and repeated descriptions thereof have been omitted.

In the semiconductor device 1B, the word line capping layer 407 may include a lower portion 407-1 and an upper portion 407-3. The lower part 407 - 1 can be disposed on the word line isolation layer 401 , the word line barrier layer 403 and the word line conductive layer 405 . The upper portion 407-3 may be disposed on the lower portion 407-1. The upper surface of the upper part 407 - 3 and the upper surface of the base 301 may be substantially coplanar. The lower portion 407-1 may include an isolation material having a dielectric constant of approximately 4.0 or greater. The upper portion 407-3 may comprise a low dielectric constant material such as silicon oxide or the like. The upper portion 407-3 comprising a low dielectric constant material can reduce the electric field on the upper surface of the substrate 301; thus, leakage current can be reduced.

3 to 8 are schematic cross-sectional views illustrating some parts of semiconductors 1C, 1D, 1E, 1F, 1G, and 1H according to some embodiments of the present disclosure.

Please refer to FIG. 3 , the semiconductor device 1C may have a structure similar to that described in FIG. 1 . Components in FIG. 3 that are the same as or similar to those in FIG. 1 have been labeled with similar component numbers, and repeated descriptions thereof have been omitted.

In the semiconductor element 1C, the first work function layer 105 may include the following work function layer 105-1 and an upper work function layer 105-3. The lower work function layer 105 - 1 may be disposed on the first gate protection layer 103 . The upper work function layer 105 - 3 may be disposed between the lower work function layer 105 - 1 and the first gate barrier layer 107 .

For example, the lower work function layer 105-1 may include aluminum, silver, titanium, titanium nitride, titanium aluminum, titanium carbide aluminum, titanium nitride aluminum, titanium aluminum silicide silicon aluminum), tantalum nitride, tantalum carbide, silicon tantalum nitride, manganese, zirconium or tungsten nitride. For example, the upper work function layer 105-3 may include titanium nitride, tantalum nitride, tantalum carbide, tungsten nitride or ruthenium.

Please refer to FIG. 4 , the semiconductor device 1D may have a structure similar to that described in FIG. 1 . Components in FIG. 4 that are the same as or similar to those in FIG. 1 have been labeled with similar component numbers, and repeated descriptions thereof have been omitted.

In the semiconductor device 1D, an interfacial layer 117 can be disposed between the substrate 301 and the first gate dielectric layer 101 . In some embodiments, the interfacial layer 117 may have a thickness between about 5 Å and about 20 Å. The interface layer 117 may comprise a chemical oxide of the substrate 301, such as silicon oxide. The interfacial layer 117 can facilitate the formation of the first gate dielectric layer 101 .

Please refer to FIG. 5 , the semiconductor device 1E may have a structure similar to that described in FIG. 1 . Components in FIG. 5 that are the same as or similar to those in FIG. 1 have been labeled with similar component numbers, and repeated descriptions thereof have been omitted.

In the semiconductor device 1E, an adjustment layer 119 can be disposed between the first gate protection layer 103 and the first work function layer 105 . In some embodiments, the adjustment layer 119 may include a material or an alloy including lanthanide nitride. The adjustment layer 119 can be used to fine-tune the threshold voltage of the first gate stack 100 .

Please refer to FIG. 6, the semiconductor element 1F may have a structure similar to that described in FIG. structure. Components in FIG. 6 that are the same as or similar to those in FIG. 1 have been labeled with similar component numbers, and repeated descriptions thereof have been omitted.

In the semiconductor device 1F, a dipole layer 121 may be disposed between the substrate 301 and the first gate dielectric layer 101 . In some embodiments, the dipole layer 121 may have a thickness less than 2 nm. The dipole layer 121 can replace defects in the first gate dielectric layer 101 and improve the mobility and reliability of the first gate dielectric layer 101 . The dipole layer 121 may comprise a material, which includes one or more of the following: lutetium oxide, lutetium silicon oxide, yttrium oxide, yttrium silicon oxide , lanthanum oxide, lanthanum silicon oxide, barium oxide, barium silicon oxide, strontium oxide, strontium silicon oxide, Aluminum oxide, aluminum silicon oxide, titanium oxide, titanium silicon oxide, hafnium oxide, hafnium silicon oxide, zirconium oxide ( zirconium oxide), zirconium silicon oxide, tantalum oxide, tantalum silicon oxide, scandium oxide, scandium silicon oxide, magnesium oxide ) and magnesium silicon oxide.

Please refer to FIG. 7 , the semiconductor device 1G may have a structure similar to that described in FIG. 1 . Components in FIG. 7 that are the same as or similar to those in FIG. 1 have been labeled with similar component numbers, and repeated descriptions thereof have been omitted.

In the semiconductor device 1G, a functional layer 123 may be disposed between the first gate dielectric layer 101 and the first gate protection layer 103 . In some embodiments, the functional layer 123 may have a thickness ranging from about 10 Å to about 15 Å. In some embodiments, for example That is, the functional layer 123 may include titanium nitride or tantalum nitride. The functional layer 123 can protect the first gate dielectric layer 101 from being damaged during subsequent semiconductor manufacturing processes. In some embodiments, for example, the functional layer 123 may include titanium and titanium silicide. The functional layer 123 can also reduce the resistivity of the first gate protection layer 103 . Therefore, the characteristics of the first gate stack 100 can be improved. As a result, the performance of the semiconductor element 1G can be improved.

Please refer to FIG. 8 , the semiconductor device 1H may have a structure similar to that described in FIG. 1 . Components in FIG. 8 that are the same as or similar to those in FIG. 1 have been labeled with similar component numbers, and repeated descriptions thereof have been omitted.

In the semiconductor device 1H, the interface layer 117 may be disposed on the substrate 301 . The dipole layer 121 may be disposed between the first gate dielectric layer 101 and the interface layer 117 . The functional layer 123 can be disposed between the first gate dielectric layer 101 and the first gate protection layer 103 . The adjustment layer 119 may be disposed between the first work function layer 105 and the first gate protection layer 103 .

It should be understood that the terms "forming", "formed" and "form" may denote and include any creating, building, patterning, planting A method of implanting or depositing an element, a dopant, or a material. Examples of formation methods may include atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusion (diffusing), deposition (depositing), growth (growing), implantation (implantation), photolithography (photolithography), dry etching and wet etching, but not limited thereto.

It should be understood that, in the description of the present disclosure, functions or steps mentioned herein may occur out of the order shown in the accompanying drawings. For example, two graphs displayed in succession can actually may be performed substantially simultaneously, or sometimes in reverse order, depending on the functions or steps involved.

FIG. 9 is a schematic flowchart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. 10 to 23 are schematic cross-sectional views illustrating a process for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure.

Please refer to FIG. 9 and FIG. 10 , in step S11 , a substrate 301 including an array area AA and a peripheral area PA may be provided, and an insulating layer 303 may be formed in the substrate 301 .

Referring to FIG. 10 , the surrounding area PA may surround the array area AA. A series of deposition processes may be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 301 . A lithography process may be performed to define the location of the insulating layer 303 . After the lithography process, an etching process, such as an anisotropic dry etching process, may be performed to form trenches through the pad oxide layer, the pad nitride layer, and the substrate 301 . An isolation material may be deposited into the trenches, and a planarization process, such as chemical mechanical polishing, may then be performed to remove more than the fill material until the base 301 is exposed and the insulating layer 303 is formed. For example, the isolation material can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride or fluorine-doped silicate. The insulating layer 303 can define a first active area 305 and a second active area 307 in the peripheral area PA, and define an array active area 309 in the array area AA.

9 and FIG. 11, in step S13, a word line trench TR1 can be formed in the array region AA, a layer of first isolation material 501 can be conformally formed in the word line trench TR1 and on the substrate 301 superior.

Referring to FIG. 11 , a lithography process may be performed to define the position of the word line trench TR1 at the array area AA. After the lithography process, an etching process, such as an anisotropic dry etching process, may be performed to remove a portion of the substrate 301 and form the word line trench TR1. raise For example, the layer of first isolation material 501 may be conformally formed within the word line trench 501 and on the substrate 301 by chemical vapor deposition, atomic layer deposition, or other applicable deposition processes. For example, the first isolation material 501 may include hafnium oxide, zirconium hafnium oxide, lanthanum hafnium oxide, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium oxide, aluminum oxide, silicon aluminum oxide, titanium oxide, Tantalum pentoxide, lanthanum oxide, lanthanum silicon oxide, strontium titanate, lanthanum aluminate, yttrium oxide, gallium (III) trioxide, gadolinium gallium oxide, lead zirconate titanate (lead zirconium titanate), barium titanate, barium strontium titanate, barium zirconate or mixtures thereof.

Please refer to FIG. 9, FIG. 12 and FIG. 13, in step S15, a layer of protective material 503 may be conformally formed on the layer of first isolation material 501, and the layer of first isolation material 501 is formed on the surrounding area PA, and A layer of first work function material 505 and a layer of second work function material 507 can be conformally formed on the layer of protective material 503 .

Please refer to FIG. 12 , a first mask layer 601 may be formed to cover the array area AA. For example, the first mask layer 601 can be silicon nitride. The protection material 503 can be titanium silicon nitride.

In some embodiments, the fabrication technique of the layer of protective material 503 may include a thermal chemical vapor deposition process. During the thermal chemical vapor deposition process, a titanium-containing gas, a silicon-containing gas, and a nitrogen-containing gas may be introduced into the layer of first isolation material 501 on the peripheral area PA to form a titanium silicon nitride film ( For example, the layer of protective material 503). For example, the titanium-containing gas may be tetraxydimethylaminotitanium (TDMAT) or tetraxydiethylaminotitanium (TDEAT). For example, the silicon-containing gas can be SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiH ₄ or Si2H ₆ . For example, the nitrogen-containing gas may be ammonia or monomethylhydrazine. The flow rate of the titanium-containing gas may be between about 5 standard cubic centimeters per minute (sccm) and about 50 sccm. The flow rate of the silicon-containing gas may be between about 5 seem and about 500 seem. The flow rate of the nitrogen-containing gas may be between about 50 seem and about 500 seem. The process pressure of the thermal chemical vapor deposition process may be between about 0.3 Torr and about 5 Torr. The process temperature may be between about 400°C and about 650°C.

Alternatively, in some embodiments, the fabrication technique of the layer of protective material 503 may include a plasma chemical vapor deposition process. For example, the gases used to generate the plasma can be hydrogen and argon. The frequency of the radio frequency power of the plasma may be 13.56 MHz. The RF power of the plasma may be between about 200W and about 800W. The flow rate of the titanium-containing gas (eg, TiCl ₄ ) may be between about 1 seem and about 10 seem. The flow rate of silicon-containing gas (eg, SiH ₄ ) may be between about 0.1 sccm and about 10 sccm. The flow rate of nitrogen-containing gas (N ₂ ) may be between about 30 sccm and about 500 sccm. The flow rate of hydrogen may be between about 100 to 3000 sccm. The flow rate of argon may be between about 100 to 2000 sccm. The process pressure of the plasma chemical vapor deposition process may be between about 0.5 Torr and about 5 Torr. The process temperature may be between about 350°C and about 450°C.

Alternatively, in some embodiments, a layer of titanium nitride and a layer of silicon nitride can be sequentially formed on the layer of the first isolation material 501 , and the layer of the first isolation material 501 is formed on the peripheral area PA. An annealing process may be performed to convert the layer of titanium nitride and the layer of silicon nitride into a titanium silicon nitride film (eg, the layer of protective material 503 ).

Please refer to FIG. 13 , in some embodiments, the layer of first work function material 505 and the layer of second work function material 507 can be formed separately. In some embodiments, the layer of first work function material 505 and the layer of second work function material 507 may comprise the same material and may be formed at the same time. For example, the first work function material 505 and the second work function material 507 can be aluminum, Silver, titanium, titanium nitride, titanium aluminum, titanium carbide aluminum, titanium nitride aluminum, titanium silicon aluminum, tantalum nitride, tantalum carbide, tantalum silicon nitride , manganese, zirconium or tungsten nitride. For example, the fabrication techniques of the layer of first work function material 505 and the layer of second work function material 507 may include atomic layer deposition, plasma vapor deposition, chemical vapor deposition or other applicable deposition processes.

Please refer to FIG. 9, FIG. 14 and FIG. 15, in step S17, a layer of first barrier material 509 can be conformally formed on the layer of first isolation material 501, on the layer of first work function material 505 and on the layer On the layer of second work function material 507 , and a layer of filling material 511 may be formed on the layer of first barrier material 509 .

Referring to FIG. 14 , the first mask layer 601 can be removed. Next, the layer of first barrier material 509 may be conformally formed on the layer of first work function material 505, on the layer of second work function material 507, and on the layer of first isolation material 501, while the A layer of first isolation material 501 is formed in the array area AA. For example, the fabrication technique of the layer of first barrier material 509 may include chemical vapor deposition, atomic layer deposition, physical vapor deposition or other applicable deposition processes. The first barrier material 509 can be titanium, titanium nitride, tantalum, tantalum nitride or a combination thereof.

Referring to FIG. 15 , the layer of filling material 511 may be formed on the layer of first barrier material 509 . For example, the fabrication technique of the layer filling material 511 may include physical vapor deposition, chemical vapor deposition, sputtering or other applicable deposition processes. For example, the filling material 511 can be tungsten, aluminum, doped polysilicon, silicon germanium, metal, metal alloy, metal silicide, metal nitride or metal carbide. In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed to provide a substantially flat surface for subsequent processing steps.

Please refer to FIG. 9 and FIG. 16 to FIG. 19. In step S19, the layer of first isolation material 501, the layer of protective material 503, the layer of first work function material 505, the layer of second The work function material 507 , the layer of first barrier material 509 and the layer of filling material 511 form a first gate stack 100 and a second gate stack 200 on the surrounding area PA.

Referring to FIG. 16 , a layer of hard mask material 513 may be formed on the layer of filling material 511 . A planarization process, such as chemical mechanical polishing, may be performed to provide a substantially flat surface for subsequent processing steps. A second hard mask layer 603 can be formed on the layer of hard mask material 513 . The second hard mask layer 603 may include patterns of the first gate stack 100 and the second gate stack 200 . It should be understood that the array area AA may be covered by the second hard mask layer 603 .

Referring to FIG. 17, an etching process, such as an anisotropic dry etching process, may be performed to convert the pattern of the first gate stack 100 and the second gate stack 200 to the hard mask layer 515 (also shown as pattern hardened mask layer 515).

Referring to FIG. 18, an etching process can be performed using the patterned hard mask layer 515 as a mask to remove the first isolation material 501, the protection material 503, the first work function material 505, and the second work function material 507. , the first barrier material 509 and some parts of the filling material 511 .

After the etching process, the layer of first isolation material 501 formed on the peripheral area PA can be transformed into the first gate dielectric layer 101 and the second gate dielectric layer 201 . The layer of protection material 503 can be transformed into the first gate protection layer 103 and the second gate protection layer 203 . The layer of first work function material 505 may be converted into the first work function layer 105 . The layer of second work function material 507 may be converted into the second work function layer 205 . The layer of first barrier material 509 formed on the surrounding area PA can be converted into the first gate barrier layer 107 and the second gate barrier layer 207 . The layer filling material 511 formed on the peripheral area PA can be converted into the first gate filling layer 109 and the second gate filling layer 209 .

Please refer to FIG. 18, the first gate dielectric layer 101, the first gate protection layer 103, the first work function layer 105, the first gate barrier layer 107 and the first gate filling layer 109 can be configured as The first gate stack 100 . The second gate dielectric layer 201 , the second gate protection layer 203 , the second work function layer 205 , the second gate barrier layer 207 and the second gate filling layer 209 can be configured into a second gate stack 200 .

Referring to FIG. 19 , an implantation process may be performed to form a plurality of first impurity regions 113 and a plurality of second impurity regions 213 . Dopants for the implantation process may include p-type impurities (dopants) or n-type impurities (dopants). P-type impurities can be added to an intrinsic semiconductor to create multiple valence electron defects. In a silicon-containing substrate, examples of p-type dopants or impurities include, but are not limited to, boron, aluminum, gallium, and indium. N-type impurities can be added to an intrinsic semiconductor to donate free electrons to the intrinsic semiconductor. In a silicon-containing substrate, examples of n-type dopants or impurities include antimony, arsenic, and phosphorus, but are not limited thereto. In some embodiments, the doping concentration of the plurality of first impurity regions 113 and the plurality of second impurity regions 213 may be between about 1E19 atoms/cm ³ and about 1E21 atoms/cm ³ . After the implantation process, the plurality of first impurity regions 113 and the plurality of second impurity regions 213 may have an electrical type, such as n-type or p-type. In some embodiments, the fabrication techniques of the plurality of first impurity regions 113 and the plurality of second impurity regions 213 may include two different implantation processes.

Please refer to FIG. 1 and FIG. 20 to FIG. 23 , in step S21 , a word line structure 400 may be formed in the array area AA.

Referring to FIG. 20 , a third mask layer 605 may be formed to cover the surrounding area PA. A recess process may be performed to remove portions of the first isolation material 501 , the first barrier material 509 and the filling material 511 in the array area AA. After the recess process, the layer of first isolation material 501 may be transformed into the word line isolation layer 401 in the word line trench TR1. The layer of first barrier material 509 can be transformed into the word line barrier layer 403 in the word line trench TR1. The layer fill material 511 may be converted into the wordline conductive layer 405 in the wordline trench TR1.

Referring to FIG. 21, a word line capping layer 407 may be formed to completely fill the word line trench TR1. The word line isolation layer 401 , the word line barrier layer 403 , the word line conductive layer 405 and the word line capping layer 407 are configured together to form a word line structure 400 .

Referring to FIG. 22 , an implantation process may be performed to form a plurality of word line impurity regions 409 . Dopants for the implantation process may include p-type impurities (dopants) or n-type impurities (dopants). In some embodiments, the doping concentration of the plurality of word line impurity regions 409 is between about 1E19 atoms/cm ³ and about 1E21 atoms/cm ³ . After the implantation process, the plurality of word line impurity regions 409 may have an electrical type, such as N type or P type.

Referring to FIG. 23 , the third mask layer 605 can be removed. Next, a layer of spacer material (not shown) may be conformally formed on the substrate 301 to cover the first gate stack 100 and the second gate stack 200 . For example, the interstitial material can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or fluorine-doped silicate. An etching process, such as an anisotropic dry etching process, may be performed to remove a portion of the spacer material and simultaneously form the first gate capping layer 111, the first spacer sublayer 115, the second gate capping layer 211 and the second gap sublayer 215.

An embodiment of the present disclosure provides a semiconductor device, including a substrate; and a first gate stack disposed on the substrate and including: a first gate dielectric layer disposed on the substrate; a first gate stack An electrode protection layer disposed on the first gate dielectric layer includes silicon nitride titanium; a first work function layer disposed on the first gate protection layer; and a first gate filling layer disposed on the on the first work function layer.

Another embodiment of the present disclosure provides a semiconductor device, including a base, including an array area and a surrounding area, the surrounding area surrounds the array area; a word line structure is disposed in the array area; and a first The gate stack is disposed on the surrounding area and includes: a first gate dielectric layer disposed on the surrounding area; a first gate protection layer disposed on the first gate The dielectric layer includes titanium nitride silicon; a first work function layer is arranged on the first gate protection layer; and a first gate filling layer is arranged on the first work function layer.

Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, including an array region and a peripheral region, the peripheral region surrounding the array region; forming a word line trench in the array region; Conformally forming a layer of first isolation material in the word line trench and on the substrate; conformally forming a layer of protective material on the layer of first isolation material formed on the surrounding area; conformally forming a layer of first work function material on the layer of protective material; conformally forming a layer of first barrier material on the layer of first isolation material and on the layer of first work function material; forming a layer of filler material on the layer of first on a barrier material; and patterning the layer of first isolation material, the layer of protection material, the layer of first work function material, the layer of first barrier material and the layer of filling material to form a first gate stack A word line structure is formed on the surrounding area and in the array area; wherein the protection material includes titanium silicon nitride.

Due to the design of the semiconductor device of the present disclosure, the first gate protection layer 103 comprising titanium silicon nitride can have a low resistivity and an excellent barrier property, and is stable under heating conditions. Therefore, the first gate stack 100 including the first gate protection layer 103 including titanium silicon nitride can have excellent characteristics. Therefore, the performance of the semiconductor element 1A can be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that the corresponding method described herein can be used according to this disclosure. The embodiments have the same function or the existing or future development process, machine, manufacture, material composition, means, method, or steps to achieve substantially the same result. Accordingly, such process, machinery, manufacture, material composition, means, method, or steps are included in the patent scope of this application.

1A: Semiconductor components

100: first gate stack

101: The first gate dielectric layer

103: The first gate protection layer

105: The first work function layer

107: The first gate barrier layer

109: The first gate filling layer

111: the first gate cover layer

113: the first impurity region

115: The first gap sublayer

200: second gate stack

201: second gate dielectric layer

203: Second gate protection layer

205: Second work function layer

207: The second gate barrier layer

209: Second gate filling layer

211: second gate cover layer

213: the second impurity region

215: Second gap sublayer

301: Base

303: insulation layer

305: The first active zone

307: The second active area

309: Array active area

400: character line structure

401: word line isolation layer

403: word line barrier layer

405: word line conductive layer

407:Character line cover layer

409: Word line impurity area

AA: array area

PA: Peripheral Area

T1: Thickness

T2: Thickness

Z: Direction

Claims (14)

A semiconductor element, comprising: a substrate including an array area and a surrounding area, the surrounding area surrounding the array area; a word line structure disposed in the array area; and a first gate stack disposed in the array area The peripheral area includes: a first gate dielectric layer disposed on the peripheral area; a first gate protective layer disposed on the first gate dielectric layer and including silicon titanium nitride; a work function layer arranged on the first gate protection layer; a first gate filling layer arranged on the first work function layer; and a first gate barrier layer and a word line barrier layer; wherein the first gate barrier layer is disposed between the first work function layer and the first gate filling layer, wherein the word line structure includes: a word line isolation layer disposed inwardly in the array In the region; a word line conductive layer, disposed on the word line isolation layer; and a word line cover layer, disposed on the word line isolation layer and the word line conductive layer; wherein the character The line barrier layer is disposed between the word line isolation layer and the word line conductive layer; wherein the first gate barrier layer and the word line barrier layer include the same material. The semiconductor device as claimed in claim 1, wherein the word line cover layer includes a lower portion and An upper part, the lower part is arranged between the word line isolation layer and the word line conductive layer, the upper part is arranged on the lower part; wherein the lower part includes an isolation material, the isolation material has a dielectric constant, the dielectric The dielectric constant is about 4.0 or greater; wherein the upper portion includes a low dielectric constant material. The semiconductor device as described in Claim 2, wherein the first work function layer includes a lower work function layer and an upper work function layer, the lower work function layer is disposed on the first gate protection layer, and the upper work function layer It is arranged between the lower work function layer and the first gate barrier layer; wherein the lower work function layer includes aluminum, silver, titanium, titanium nitride, titanium aluminum, aluminum titanium carbide, aluminum titanium nitride, aluminum silicide Titanium, tantalum nitride, tantalum carbide, tantalum silicon nitride, manganese, zirconium or tungsten nitride; wherein the upper work function layer includes titanium nitride, tantalum nitride, tantalum carbide, tungsten nitride or ruthenium. The semiconductor device as claimed in claim 2, wherein the first gate dielectric layer comprises hafnium oxide, hafnium zirconium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, zirconium oxide, aluminum oxide, hafnium oxide Silicon aluminum, titanium oxide, tantalum pentoxide, lanthanum oxide, lanthanum silicon oxide, strontium titanate, lanthanum aluminate, yttrium oxide, lead zirconium titanate, barium titanate , barium strontium titanate, barium zirconate or mixtures thereof. The semiconductor device as claimed in claim 4, further comprising an interfacial layer disposed between the substrate and the first gate dielectric layer; wherein the interfacial layer comprises a chemical oxide of the substrate. The semiconductor device according to claim 2, further comprising an adjustment layer disposed on the first gate between the protective layer and the first work function layer; wherein the adjustment layer includes lanthanide nitride. The semiconductor device as claimed in claim 2, further comprising a dipole layer disposed between the substrate and the first gate dielectric layer; wherein the dipole layer comprises one or more of the following: Lutetium oxide, lutetium silicon oxide, yttrium oxide, yttrium silicon oxide, lanthanum oxide, lanthanum silicon oxide, barium oxide (barium oxide), barium silicon oxide, strontium oxide, strontium silicon oxide, aluminum oxide, aluminum silicon oxide, titanium oxide oxide), titanium silicon oxide, hafnium oxide, hafnium silicon oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide , tantalum silicon oxide, scandium oxide, scandium silicon oxide, magnesium oxide and magnesium silicon oxide. The semiconductor device as claimed in claim 2, further comprising a functional layer disposed between the first gate dielectric layer and the first gate protection layer; wherein the functional layer comprises titanium nitride or tantalum nitride . The semiconductor device as claimed in claim 2, further comprising a first gate capping layer disposed on the first gate filling layer; wherein the first gate capping layer includes silicon oxide, silicon nitride, nitrogen Silicon oxide, silicon oxynitride, or fluorine-doped silicate. The semiconductor device according to claim 2, further comprising a plurality of first impurity regions disposed in the peripheral region and adjacent to the first gate dielectric layer. A method for manufacturing a semiconductor element, comprising: providing a substrate, including an array region and a peripheral region, the peripheral region surrounding the array region; forming a word line trench in the array region; conformally forming a layer of first Isolation material in the word line trench and on the substrate; conformally forming a layer of protective material on the layer of first isolation material formed on the peripheral region; conformally forming a layer of first work function material on the on the layer of protective material; conformally forming a layer of a first barrier material on the layer of first isolation material and on the layer of first work function material; forming a layer of filler material on the layer of first barrier material; and patterning the layer of first isolation material, the layer of protection material, the layer of first work function material, the layer of first barrier material and the layer of filling material to form a first gate stack on the surrounding area and form A word line structure is in the array area; wherein the protection material includes titanium silicon nitride. The method for manufacturing a semiconductor element as claimed in claim 11, wherein forming the layer of protective material includes: introducing a titanium-containing gas, a silicon-containing gas, and a nitrogen-containing gas into the surrounding area on this layer of first isolation material. The method of manufacturing a semiconductor device as claimed in claim 12, wherein a process pressure for forming the layer of protective material is between about 0.3 Torr and about 5 Torr. The method for manufacturing a semiconductor element as claimed in claim 13, wherein a process temperature for forming the layer of protective material is between 400° C. and about 650° C., and the titanium-containing gas includes tetrakis(dimethylamido)titanium (tetraxydimethylaminotitanium, TDMAT) or tetrakis (diethylamido) titanium (tetraxydiethylaminotitanium, TDEAT).

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