TWI817359B - Linear image sensor and image sensing method - Google Patents

Abstract

A linear image sensor and an image sensing method are provided. The linear image sensor includes a main control chip and a plurality of sensing chips. The main control chip is coupled to one end of one chip select trace and one end of one data output enabling trace. The sensor chips includes a plurality of serial peripheral interfaces, a plurality of chip select bar pins, and a plurality of data readout enabling pins. The plurality of chip select bar pins of the serial peripheral interfaces are coupled to another one end of the one chip select trace to receive a chip select bar signal output by the main control chip. The plurality of data readout enabling pins of the plurality of the serial peripheral interfaces are coupled to another one end of the one data output enabling trace to receive an enabling signal output from the main control chip.

Description

Linear image sensor and image sensing method

The present invention relates to a sensing technology, and in particular, to a linear image sensor and an image sensing method.

Multiple sensing chips in a traditional linear image sensor are respectively coupled to the control chip through multiple traces, and the control chip needs to couple to these traces through a large number of pins. The control chip needs to generate multiple control instructions to control these sensing chips respectively. Therefore, traditional linear image sensors have too many internal wirings and occupy a large amount of equipment space. As a result, the size of traditional linear image sensors cannot be reduced, and the control settings are also complicated.

The present invention provides a linear image sensor and an image sensing method, which can effectively reduce the number of wires and the space occupied in the linear image sensor.

The linear image sensor of the present invention includes a main control chip and a plurality of sensing chips. The main control chip is coupled to one end of a chip selection trace and one end of a data output enable trace. The plurality of sensing chips include a plurality of serial peripheral interfaces, a plurality of data output pins and a plurality of data output enable pins. A plurality of chip select pins of a plurality of serial peripheral interfaces are coupled to the other end of a chip select trace to receive a chip select signal output by the main control chip. A plurality of data output enable pins of a plurality of serial peripheral interfaces are coupled to the other end of a data output enable trace to receive an enable signal output by the main control chip. When the chip selection signal and the enable signal are respectively at the first voltage level, the plurality of sensing chips operate in a command receiving mode to receive a plurality of control instructions sequentially and in a time-sharing manner. When the chip selection signal is at the second voltage level and the enable signal is at the first voltage level, the plurality of sensing chips operate in the execution command mode. When the chip selection signal is at the first voltage level and the enable signal is at the second voltage level, the plurality of sensing chips operate in the output data mode to output multiple sensing signals to the main control in sequence and time division. chip, so that the main control chip generates a sensing image based on multiple sensing signals.

The image sensing method of the present invention is suitable for linear image sensors. The main control chip of the linear image sensor is coupled to one end of a chip selection trace and one end of a data output enable trace. The multiple sensing chips of the linear image sensor include multiple serial peripheral interfaces, multiple data output pins, and multiple data output enable pins. A plurality of chip select pins of a plurality of serial peripheral interfaces are coupled to the other end of a chip select trace to receive a chip select signal output by the main control chip. A plurality of data output enable pins of a plurality of serial peripheral interfaces are coupled to the other end of a data output enable trace to receive an enable signal output by the main control chip. The image sensing method includes the following steps: when the chip selection signal and the enable signal are respectively at the first voltage level, multiple sensing chips are operated in a command receiving mode to receive multiple control commands sequentially and in a time-sharing manner; When the chip selection signal is at the second voltage level and the enable signal is at the first voltage level, the plurality of sensing chips are operated in the execution command mode; and when the chip selection signal is at the first voltage level and the When the energy signal is at the second voltage level, the multiple sensing chips are operated in the output data mode to sequentially and time-shared output of multiple sensing signals to the main control chip, so that the main control chip responds to the multiple sensing The signal produces a sensed image.

Based on the above, the linear image sensor and the image sensing method of the present invention can effectively reduce the number of chip selection traces in the linear image sensor, and can efficiently operate multiple sensors in the linear image sensor. Test chip.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

In order to make the content of the present invention easier to understand, the following embodiments are provided as examples according to which the present disclosure can be implemented. In addition, wherever possible, elements/components/steps with the same reference numbers in the drawings and embodiments represent the same or similar parts.

FIG. 1 is a schematic circuit diagram of a linear image sensor according to an embodiment of the present invention. Referring to FIG. 1 , the linear image sensor 100 includes a main control chip 110 and a plurality of sensing chips 120_1 to 120_N, where N is a positive integer. In this embodiment, the main control chip 110 is coupled to one end of a chip select bar (CSB) trace 101 . The sensing chips 120_1~120_N respectively include a serial peripheral interface (Serial Peripheral Interface, SPI) and a plurality of data output pins. A plurality of chip selection pins (CSB pins) of a plurality of serial peripheral interfaces of the sensing chips 120_1~120_N are coupled to the other end of the chip selection trace 101. In this regard, the main control chip 110 may only be coupled to one chip select pin of each of the sensing chips 120_1~120_N through one chip select trace. In this embodiment, the sensing chips 120_1 ~ 120_N can be arranged along one direction to achieve a linear image sensing function. In one embodiment, the number of sensing chips 120_1~120_N may be 17.

In this embodiment, the main control chip 110 is also coupled to one end of a plurality of data transmission lines 102 . The sensing chips 120_1 ~ 120_N also include a plurality of data output pins, and the plurality of data output pins are coupled to the other ends of the plurality of data transmission traces 102 . The number of the plurality of data transmission lines 102 may be, for example, eight. Moreover, the number of data transmission pins of the sensing chips 120_1~120_N is equal to the number of data transmission lines. In this regard, each of the sensing chips 120_1~120_N may include, for example, 8 data transmission pins.

In this embodiment, the main control chip 110 is also coupled to one end of a data output enabling trace 103 . The sensing chips 120_1~120_N also include a plurality of data output enable pins (data output enable pins). A sensing chip has a data output enable pin. The plurality of data output enable pins are coupled to the other end of the one data output enable trace 103 . In this regard, the main control chip 110 is coupled to a data output enable pin of each of the sensing chips 120_1~120_N through a trace.

In this embodiment, the sensing wafers 120_1 ~ 120_N can be exposed at the same time. The sensing chips 120_1 ~ 120_N can be configured to have different chip numbers respectively, and the sensing chips 120_1 ~ 120_N can respectively output sensing signals to the main control chip 110 sequentially and time-sharing according to different chip numbers. Therefore, the linear image sensor 100 of this embodiment can output the respective sensing signals of the sensing chips 120_1~120_N through only one chip selection trace 101, which can effectively reduce the number of traces of the linear image sensor 100. and the volume occupied by its wiring.

In addition, the sensing chips 120_1~120_N may also have other functional pins, but the invention is not limited thereto.

FIG. 2 is a schematic diagram of a sensing chip according to an embodiment of the present invention. Referring to FIG. 2 , each of the sensing chips 120_1 ~ 120_N in the embodiment of FIG. 1 can implement the architecture of the sensing chip 120 shown in FIG. 2 . In this embodiment, the sensing chip 120 includes a chip selection pin 121, a plurality of data transmission pins 122, a data output enable pin 123, one or more chip number pins 124 and a plurality of sensing units. 125_1~125_M, where M is a positive integer. In this embodiment, the chip selection pin 121 of the sensing chip 120 may be coupled to the other end of the chip selection trace 101 as shown in FIG. 1 . The plurality of data transmission pins 122 of the sensing chip 120 may be coupled to the other ends of the plurality of data transmission traces 102 as shown in FIG. 1 . The data output enable pin 123 of the sensing chip 120 can be coupled to the other end of a data output enable trace 103 as shown in FIG. 1 .

In one embodiment, the sensing die 120 may include a plurality of die number pins 124 . The sensing chip 120 can receive different digital signals through a plurality of chip number pins 124 to determine different chip numbers. For example, the sensing chip 120 may have four chip number pins, and may respectively receive digital signals such as having a high voltage level representing the value "1" or having a low voltage level representing the value "0" (eg, The corresponding chip number is determined based on the sequentially arranged value "1011" corresponding to the digital signal received by the four pins). Therefore, the internal control circuit of the sensing chip 120 can output the sensing signals of the sensing units 125_1 to 125_M to the main control chip at a specific time (or a specific time slot) according to a specific chip number.

In another embodiment, the sensing die 120 may include a die number pin. The sensing chip 120 can receive different analog signals through this chip number pin to determine different chip numbers. For example, the sensing die 120 may have a die number pin and may receive an analog signal of a specific voltage. Therefore, the internal control circuit of the sensing chip 120 can determine a specific chip number according to a specific voltage, and output the sensing signals of the sensing units (or sensing pixels) 125_1~125_M at a specific time according to the specific chip number. to the main control chip. In this regard, the sensing chips 120_1~120_N in FIG. 1 can be disposed on the same circuit board (for example, the same printed circuit board (PCB)). Each of the chip number pins of the sensing chips 120_1 ~ 120_N is coupled to the voltage dividing circuit on the circuit board, and respectively receives different voltage dividing signals provided by the voltage dividing circuit. Therefore, the sensing chips 120_1 ~ 120_N can receive analog signals corresponding to different specific voltages (ie, different divided voltage signals) to respectively define different chip numbers.

FIG. 3 is a flow chart of an image sensing method according to an embodiment of the present invention. FIG. 4 is a signal change diagram of the chip selection signal and the enable signal according to an embodiment of the present invention. Referring to FIG. 1 , FIG. 3 and FIG. 4 , the linear image sensor 100 may perform the following steps S310 to S330 . The main control chip 110 can output the chip selection signal CSB to the sensing chips 120_1~120_N through a chip selection trace 101, and can output the enable signal DO_EN to the sensing chips 120_1~120_N through a data output enable trace 103.

In step S310, when the chip selection signal CSB and the enable signal DO_EN are respectively at the first voltage level, the sensing chips 120_1~120_N can automatically operate in the command receiving mode to receive multiple control commands sequentially and in time. As shown in Figure 4, during the period from time t1 to time t2, when the chip selection signal CSB and the enable signal DO_EN are respectively at a low voltage level (for example, the corresponding value is "00"), the sensing chips 120_1~120_N can automatically The ground operation is in the command receiving mode to receive multiple control commands sequentially and in time-sharing. The sensing chips 120_1 ~ 120_N respectively receive multiple control instructions sequentially and in a time-sharing manner from the main control chip 110 (for example, through other pins of the sensing chip or other pins of the SPI interface).

In step S320, when the chip selection signal CSB is at the second voltage level and the enable signal DO_EN is at the first voltage level, the sensing chips 120_1~120_N operate in the execution command mode. In the execution command mode, the sensing chips 120_1 ~ 120_N can perform exposure value adjustment operations, gain (Gain) value adjustment operations, offset value adjustment operations, image sensing operations, enter waiting mode or reset operations, etc., and The present invention is not limited to this. As shown in Figure 4, during the period from time t2 to time t3, when the chip selection signal CSB is at a high voltage level and the enable signal DO_EN is at a low voltage level (for example, the corresponding value is "10"), the main control chip The 110 operable sensing chips 120_1~120_N can respectively perform relevant operations according to the corresponding control instructions received. In addition, in the aforementioned image sensing operation, the sensing chips 120_1 ~ 120_N can be exposed at the same time or in a time-sharing manner, and the present invention is not limited thereto.

In step S330, when the chip selection signal CSB is at the first voltage level and the enable signal DO_EN is at the second voltage level, the sensing chips 120_1~120_N operate in the output data mode to sequentially and time-divided output multiple Sensing signals to the main control chip 110 . The main control chip 110 uses the sensing chips 120_1 to 120_N to sequentially and time-sharing output multiple sensing signals according to the order of respective chip numbers. As shown in Figure 4, during the period from time t3 to time t4, when the chip selection signal CSB is at a low voltage level and the enable signal DO_EN is at a high voltage level (for example, the corresponding value is "01"), the sensing chip 120_1~120_N outputs a plurality of sensing signals sequentially and in a time-divided manner, and transmits them to the main control chip 110 through a plurality of data transmission lines 102, so that the main control chip 110 generates sensing images based on these sensing signals. Therefore, the linear image sensor 100 of this embodiment can output the respective sensing signals of the sensing chips 120_1~120_N through only one chip selection trace 101 and one data output enable trace 103.

It is worth noting that the execution order of the above-mentioned steps S310 to S330 is not limited. Steps S310 to S330 are only used to represent the operating conditions of the sensing chips 120_1 to 120_N. The linear image sensor 100 may decide to perform one of steps S310 to S330 according to current operating requirements. FIG. 3 is only used to show that the sensing chips 120_1 ~ 120_N can perform corresponding modes or operations according to the currently received voltage levels of the chip selection signal CSB and the enable signal DO_EN. In addition, when the chip selection signal CSB and the enable signal DO_EN are respectively at a high voltage level (for example, “11”), the sensing chips 120_1 ~ 120_N are unresponsive, but the invention is not limited thereto.

In summary, the linear image sensor and image sensing method of the present invention can control multiple sensing chips in the linear image sensor through only one chip selection trace and one enable signal trace. , to operate multiple sensing chips in the linear image sensor to transmit multiple sensing signals to the main control chip in a time-shared manner to realize the linear image sensing function. Therefore, the linear image sensor and the image sensing method of the present invention can effectively reduce the number of chip selection traces required in the linear image sensor and the volume occupied by the traces.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100: Linear image sensor 101: Chip selection routing 102: Data transmission wiring 103: Data output enable wiring 110: Main control chip 120, 120_1~120_N: sensing chip 121: Chip selection pin 122: Data transmission pin 123: Data output enable pin 124: Chip number pin 125_1~125_M: Sensing unit CSB: chip select signal DO_EN: enable signal t1, t2, t3, t4: time S310~S330: steps

FIG. 1 is a schematic circuit diagram of a linear image sensor according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a sensing chip according to an embodiment of the present invention. FIG. 3 is a flow chart of an image sensing method according to an embodiment of the present invention. FIG. 4 is a signal timing diagram of signals and enable signals according to an embodiment of the present invention.

100: Linear image sensor

101: Chip selection routing

102: Data transmission wiring

103: Data output enable wiring

110: Main control chip

120_1~120_N: Sensing chip

Claims (16)

A linear image sensor includes: a main control chip, coupled to one end of a single chip selection line and one end of a single data output enable line; and multiple sensing chips, including multiple serial peripheral interfaces, A plurality of data output pins and a plurality of data output enable pins, wherein a plurality of chip selection pins of the serial peripheral interfaces are coupled to the other end of the single chip selection line to receive signals from the main control chip A chip selection signal is output, and the data output enable pins of the serial peripheral interfaces are coupled to the other end of the single data output enable trace to receive an enable signal output by the main control chip , wherein the main control chip only uses the single chip selection line and the single data output enable line to select and enable the sensing chips, wherein when the chip selection signal and the enable When the signals are respectively at a first voltage level, the sensing chips operate in a command receiving mode to receive a plurality of control instructions sequentially and in time division, wherein when the chip selection signal is at a second voltage level, and When the enable signal is the first voltage level, the sensing chips operate in an execution command mode, where the chip selection signal is the first voltage level, and the enable signal is the second voltage level. When bit, the sensing chips operate in a data output mode to sequentially and time-sharing output multiple sensing signals to the main control chip, so that the main control chip generates a sensing image based on the sensing signals. . The linear image sensor of claim 1, wherein the main control chip is also coupled to one end of a plurality of data transmission lines, the sensing chips also include a plurality of data transmission pins, and the data transmission connections The pins are coupled to the other ends of the data transmission traces. The linear image sensor of claim 2, wherein the number of the data transmission pins of the sensing chips is equal to the number of the data transmission lines. The linear image sensor of claim 1, wherein the first voltage level is a low voltage level, and the second voltage level is a high voltage level. The linear image sensor of claim 1, wherein the sensing chips are respectively configured to have different chip numbers, and the sensing chips are sequentially and time-shared according to the different chip numbers. Output the sensing signals to the main control chip. The linear image sensor as described in claim 5, wherein the sensing chips further include a plurality of chip numbering pins, and the sensing chips respectively receive different digital signals through the chip numbering pins, To determine the different chip numbers. The linear image sensor of claim 5, wherein the sensing chips each further include a chip number pin, and the sensing chips receive different analog signals through the chip number pin. , to determine the different wafer numbers. The linear image sensor of claim 7, wherein the sensing chips are arranged on the same circuit board, and the chip number pin of each of the sensing chips is coupled to a voltage divider on the circuit board. circuit, and respectively receive different divided voltage signals provided by the voltage dividing circuit. An image sensing method suitable for a linear image sensor. The main control chip of the linear image sensor is coupled to one end of a single chip selection trace and one end of a single data output enable trace. The linear image sensor The plurality of sensing chips of the sensor include a plurality of serial peripheral interfaces, a plurality of data output pins and a plurality of data output enable pins. The plurality of chip selection pins of the serial peripheral interfaces are coupled to the single The other end of a chip select trace is used to receive a chip select signal output by the main control chip, and the data output enable pins of the serial peripheral interfaces are coupled to the single data output enable trace The other end is to receive an enable signal output by the main control chip, wherein the image sensing method includes: when the chip selection signal and the enable signal are respectively at a first voltage level, through these sensors The test chip operates in a command receiving mode to receive multiple control commands sequentially and in time-divided manner; when the chip selection signal is a second voltage level and the enable signal is a first voltage level, by The sensing chips operate in an execution command mode; and when the chip selection signal is the first voltage level and the enable signal is the second voltage level, the sensing chips operate in an execution command mode. The output data mode is to output multiple sensing signals to the main control chip sequentially and in a time-sharing manner, so that the main control chip The chip generates a sensing image based on the sensing signals, wherein the main control chip only uses the single chip selection trace and the single data output enable trace to select and enable the sensing chips. operate. The image sensing method as described in claim 9, wherein the main control chip is also coupled to one end of a plurality of data transmission lines, the sensing chips also include a plurality of data transmission pins, and the data transmission pins Couple the other ends of the data transmission traces. The image sensing method of claim 10, wherein the number of the data transmission pins of the sensing chips is equal to the number of the data transmission lines. The image sensing method of claim 9, wherein the first voltage level is a low voltage level, and the second voltage level is a high voltage level. The image sensing method as described in claim 9, wherein the sensing chips are respectively configured to have different chip numbers, and the sensing chips output sequentially and time-sharing according to the different chip numbers. These sensing signals are sent to the main control chip. The image sensing method as described in claim 13, wherein the sensing chips further include a plurality of chip numbering pins, and the sensing chips respectively receive different digital signals through the chip numbering pins, so as to Determine the different wafer numbers. The image sensing method as described in claim 13, wherein the sensing chips each further include a chip number pin, and the sensing chips respectively The chip number pin receives different analog signals to determine different chip numbers. The image sensing method as described in claim 15, wherein the sensing chips are arranged on the same circuit board, and the chip number pin of each of the sensing chips is coupled to a piezoelectric divider on the circuit board. circuit, and respectively receive different divided voltage signals provided by the voltage dividing circuit.

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