TWI816415B - Verification method,system and computer readable storage medium for pin naming - Google Patents

Abstract

The application provides a verification method, system and computer-readable storage medium for pin naming. The verification method of pin naming includes: storing the information of several parts; Run the circuit to be verified and generate part pin report; Compare the part pin report with the information of several parts stored to confirm whether the part pin name in the circuit to be verified is correct; When the comparison shows that the part pin report is different from the information of several parts stored, confirm that the part pin name in the circuit to be verified is incorrect; When the comparison shows that the part pin report is the same as the stored information of several parts, it is confirmed that the part pin names in the circuit to be verified are correct, thus improving the efficiency and accuracy of verification pin names.

Description

Verification method, system and computer-readable storage medium for pin naming

This application relates to the field of circuit design technology, and in particular to a pin naming verification method, system and computer-readable storage medium.

Usually, when naming chip pins in circuit design, pins that perform low-level actions are usually named with "N" as the suffix, while pins that perform high-level actions usually do not add "N" as the suffix. Named after the suffix code. During the circuit development stage, naming errors are prone to occur, which in turn leads to the need to modify the circuit. This requires manual inspection and confirmation to avoid errors as much as possible. However, manual detection is less efficient and omissions or misjudgments are inevitable. Therefore, a method is needed that can accurately and quickly verify whether the chip pin naming in the designed circuit is correct.

In view of this, it is necessary for this application to propose a pin naming verification method, system and computer-readable storage medium to solve the above problems.

This application proposes a verification method for pin naming. The method includes: storing information on multiple parts; running the circuit to be verified and generating a part pin report; and comparing the part pin report with the stored information on multiple parts to confirm the circuit to be verified. Whether the part pin naming in the circuit is correct; when the part pin report is compared with the stored information of multiple parts, it is confirmed that the part pin naming in the circuit to be verified is incorrect; when the part pin report is compared with the stored information If the information of multiple parts is the same, it is confirmed that the pin names of the parts in the circuit to be verified are correct.

Further, the method also includes, before running the circuit to be verified, detecting the components in the circuit to be verified, and confirming whether there are components in the circuit to be verified. The information is not preset and stored; when it is confirmed that there are components in the circuit to be verified, When the information has not been preset and stored, the information of the unpreset and stored parts will be preset and stored according to the parts list; when it is confirmed that all the parts in the circuit to be verified have been stored, the circuit to be verified will be run.

Further, the method further includes that the part pin report includes the pin of the part and the name of the pin; when the pin of the part is named with a preset letter as the suffix, the signal transmitted by the pin is the first signal; when the part When the pin is not named with the default letter as the suffix, the signal transmitted by the pin is the second signal.

Furthermore, the method also includes confirming whether the pin naming is correct based on the logic output mode of the part and the signal of the pin; when the signal transmitted by the input pin of the part is the same as the signal transmitted by the output pin signal, then the part The logic output mode is to perform same-direction logic output; when the signal transmitted by the input pin of the component is different from the signal transmitted by the output pin, the logic output mode of the component is to perform reverse logic output.

Further, the method also includes: when the logic output mode of the stored part is the same as the logic output mode of the part in the circuit to be verified, then the pin naming of the part in the circuit to be verified is correct; when the logic output mode of the stored part is the same as the logic output mode of the part to be verified. When the logic output modes of the components in the verification circuit are different, the pin names of the components in the circuit to be verified are incorrect.

Further, the method further includes: when it is determined that the component pins in the circuit to be verified are incorrectly named, issuing a prompt to indicate that the circuit to be verified needs to be modified.

This application also proposes a pin naming verification system. The pin naming verification system is used to implement the pin naming verification method. The pin naming verification system includes: a storage module. The storage module is used to preset and store complex numbers. Part information; the first run module, which is used to run the circuit to be verified and generate a part pin report; the inspection module, which is used to convert the part pins generated in the first run module The report is compared with the information of multiple parts stored in the storage module.

Furthermore, the pin naming verification system also includes a second running module; the second running module is used to generate a parts list, and the parts list includes information on various parts.

Further, when the storage module lacks component information in the circuit to be verified, the storage module obtains the missing component information from the second running module and presets and stores it.

This application also proposes a computer-readable storage medium on which at least one computer instruction is stored. The computer instruction is loaded by the processor and executes the pin naming verification method.

The pin naming verification method proposed in this application presets and stores the part information in the storage module, and combines the operation of the first operation module and the second operation module, and then through the detection module The group determines whether the pin naming of the part matches the default. That is, the circuit to be verified is run according to the program of the first running module to generate a part pin report, and then the detection module determines whether the pins of the part are named correctly by comparing the part pin report with the preset part specifications. At the same time, the parts list generated by the program running in the second running module is used to supplement the parts information required for verification. This improves the efficiency and accuracy of verifying pin naming.

1: Verification system

10:Storage module

20: First running module

30: Second running module

40:Detection module

50:Memory

60: Processor

S1: first part

A:The first pin

B: Second pin

S2: Second part

C: The third pin

D:Fourth pin

S101~S107: Steps

Figure 1 is a flow chart of the pin naming verification method according to the embodiment of the present application; Figure 2 is the architecture diagram of the pin naming verification system according to the embodiment of the present application; Figure 3 is the structural schematic diagram of the verification system according to the embodiment of the present application; Figure 4 is a schematic structural diagram of the first component of the embodiment of the present application; FIG. 5 is a schematic structural diagram of the second component of the embodiment of the present application.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application. Not all examples. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the description of the present application are only for describing specific embodiments and are not intended to limit the present application.

The terms "first" and "second" in the description of this application and the above-mentioned drawings are used to distinguish different objects, rather than describing a specific sequence. Furthermore, the term "include" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules that are not listed, or may optionally This also includes other steps or modules that are inherent to such processes, methods, products or devices.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following embodiments and features in the embodiments may be combined with each other without conflict.

This application proposes a verification method for pin naming. This method generates a part pin report by running the circuit to be verified according to the program of the basic design toolkit (Allegro PCB Designer). The content of the part pin report includes the location of the part, Pins and pin naming. Compare the part pin report with the preset part specifications to verify whether the part pins are correctly named. This method also uses the parts list generated by running the OrCAD program to supplement the part information required for verification.

Usually, when the pin of a part is named with "N" as the suffix, the signal of this pin is a low-level bit signal. When the pin of the part is not named with "N" as the suffix, the signal of this pin is a high-level bit signal.

When the input and output signals of the part are all low-level bit signals or high-level bit signals, the logic output mode of the part is to perform same-direction logic output. When the input and output signals of the part are different, for example, the output signal is a low-level bit and the output signal is a high-level bit, the logic output mode of the part is to perform reverse logic output. Then, based on the logic output mode of the part and the signals of the pins, you can determine whether the pins are named correctly.

Please refer to Figure 1, which is a flow chart of a pin naming verification method according to an embodiment of the present application. Methods include:

S101: Preset the information of multiple parts and store it.

In some embodiments, the preset component information may be the electrical specifications of the component, including the input pins and corresponding output pins of the component, and the logic output form of the component (for example, same-direction logic output, reverse logic output ).

S102: Confirm whether the information of all components in the circuit to be verified is preset and stored.

When it is confirmed that the information of a part in the circuit to be verified has not been preset and stored, the information of the part is preset and stored according to the parts list, and then S103 is executed.

When it is confirmed that the parts in the circuit to be verified have been stored, S104 is executed.

S103: Obtain the information of the parts in the circuit to be verified from the parts list, preset and store it, and then execute S104.

S104: Run the circuit to be verified and generate a part pin report, then execute S105.

In some embodiments, after the circuit to be verified is run through the program, a part pin report is generated. The content of the part pin report includes the material number, location, pins, and pin naming of the parts in the circuit to be verified.

S105: Compare the part pin report with the stored part information to confirm whether the part pin naming in the circuit to be verified is correct.

When the part pin report is different from the stored part information, it is confirmed that the part pin name in the circuit to be verified is incorrect, and then S106 is executed.

When the part pin report is the same as the stored part information, it is confirmed that the part pins in the circuit to be verified are correctly named, and then S107 is executed.

S106: Issue a prompt to indicate that the circuit needs to be modified.

S107: Verification completed.

Please refer to Figure 2, which is an architecture diagram of the pin naming verification system 1 according to the embodiment of the present application. Verification system 1 is used to perform the verification method of pin naming. The verification system 1 includes a storage module 10 , a first operation module 20 , a second operation module 30 and a detection module 40 .

The storage module 10 is used to preset and store information on a plurality of parts, and the stored part information can be used as a standard for verification.

The first running module 20 can be a basic design toolkit. The basic design toolkit includes a program for running the circuit to be verified. By running the circuit to be verified and generating a component pin report, that is, the information of the components in the circuit to be verified.

The second running module 30 can be OrCAD, and OrCAD can generate a parts list, and the parts list includes information on various parts. In some embodiments, when the storage module 10 lacks component information in the circuit to be verified, the component information can be obtained from the second operating module 30 and preset and stored.

The detection module 40 includes a preset program for comparing the component pin report generated in the first running module 20 with the component information stored in the storage module 10, and then detecting the component pins in the circuit to be verified. Is the naming correct?

Please refer to Figure 3, which is a schematic structural diagram of the verification system 1 according to the embodiment of the present application. In one embodiment, the verification system 1 includes a memory 50 and at least one processor 60 . Those skilled in the art should understand that the structure of the verification system 1 shown in Figure 3 does not constitute a limitation of the embodiment of the present application. The verification system 1 may also include more or less other hardware or software than shown in the figure. Or different component arrangements.

In some embodiments, the verification system 1 includes a terminal that can automatically perform numerical calculations and/or information processing according to preset or stored instructions. Its hardware includes but is not limited to microprocessors, special integrated circuits, Programmable gate arrays, digital processors and embedded devices, etc. In some embodiments, the memory 50 is used to store program codes and various data. The memory 50 may include read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable memory. In addition to programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), one-time programmable read-only memory (OTPROM), electronically erasable programmable read-only memory (EEPROM), read-only disc (Compact Disc Read-Only Memory, CD-ROM) or other optical disc memory, magnetic disk memory, tape memory, or any other computer-readable medium that can be used to carry or store data.

In some embodiments, the at least one processor 60 may include an integrated circuit, for example, may include a single packaged integrated circuit, or may include multiple integrated circuits packaged with the same function or different functions, including a microprocessor, Combinations of digital word processing chips, graphics processors and various control chips, etc. At least one processor 60 is the control core (Control Unit) of the verification system 1, by running or executing programs or modules stored in the memory 50, and calling data stored in the memory 50, to Execute various functions and process data of the verification system 1, such as the operation of the first operation module 20.

The above-mentioned integrated units implemented in the form of software function modules can be stored in a computer-readable storage medium. The above-mentioned software function module is stored in a storage medium and includes a plurality of instructions to cause a computer device (such as a personal computer, terminal, or network device, etc.) or processor to execute the methods described in various embodiments of this application. part.

Program codes are stored in the memory 50 , and the at least one processor 60 can call the program codes stored in the memory 50 to perform related functions. In one embodiment of the present application, the memory 50 stores a plurality of instructions, and the plurality of instructions are executed by the at least one processor 60 to implement the pin naming verification method. Specifically, for the specific implementation method of the above instructions by the at least one processor 60, reference can be made to the description of the relevant steps in the corresponding embodiment in Figure 1, which will not be described again here.

Please refer to FIG. 4 , which is a schematic structural diagram of the first component S1 according to the embodiment of the present application. This embodiment uses the first component S1 as an example to introduce the operation of the pin naming verification method.

In this embodiment, the first part S1 can be a Dual N-MOS part, and the material number is DMN601DWK-7. The logic output mode of the first part S1 preset and stored in the storage module 10 is reverse logic output. .

In this embodiment, the first component S1 includes a first pin A and a second pin B. The first pin A is an input port, and the second pin B is an output port corresponding to the first pin A. The name of the first pin A is CPLD_CPU_RST. If the name does not include the suffix "N", the signal of the first pin A is a high-level bit signal. The second pin B is named CPU1_RST_N, and the name contains the suffix "N", then the signal of the second pin B is a low-level bit signal. It can be concluded that the logic output mode of the first component S1 is reverse logic output.

Furthermore, the operation result of the first part S1 is consistent with the information of the part stored in the storage module 10. Through the verification method of pin naming, it can be obtained that the first pin A and the first pin A of the first part S1 are The second pin B is named correctly.

Please refer to FIG. 5 , which is a schematic structural diagram of the second component S2 according to the embodiment of the present application. This embodiment uses the second part S2 as an example to introduce the operation of the pin naming verification method.

In this embodiment, the second part S2 can be a GTL transceiver part, and the material number is GTL2014PW. The logic output mode of the second part S2 preset and stored in the storage module 10 is a same-direction logic output.

In this embodiment, the second component S2 includes a third pin C and a fourth pin D. The third pin C is an input port, and the fourth pin D is an output port corresponding to the third pin C. The name of the third pin C is CPLD_CPU_PROCHOT. If the name does not include the suffix "N", the signal of the third pin C is a high-level bit signal. The fourth pin D is named LVC1_PROCHOT_R_N, and the name contains the suffix "N", so the signal of the fourth pin D is a low-level bit signal. It can be concluded that the logic output mode of the second part S2 is reverse logic output.

Furthermore, the operation result of the second part S2 is inconsistent with the information of the part stored in the storage module 10. By verifying the pin naming verification method, it can be concluded that the third pin C and the third pin C in the second part S2 are The four-pin D is named correctly.

The program code and data used in the pin naming verification method proposed above can be stored in a computer-readable storage medium. Based on this understanding, the present application can implement all or part of the processes in the above embodiment methods by instructing relevant hardware through computer programs. The computer program described above can be stored in a computer-readable storage medium, and when executed by a processor, the computer program can implement the steps of each of the above method embodiments. Wherein, the computer program includes computer program code, and the computer program code can be in the form of original program code, object code form, executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording media, USB flash drive, mobile hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read -Only Memory), random access memory (RAM, Random Access Memory).

The pin naming verification method proposed in this application presets and stores the part information in the storage module 10, and combines the operation of the first operation module 20 and the second operation module 30, and then borrows The detection module 40 determines whether the pin naming of the component matches the preset. That is, the circuit to be verified is run according to the program of the first running module 20 to generate a part pin report, and then the detection module 40 determines whether the pins of the part are named by comparing the part pin report with the preset part specifications. correct. At the same time, the parts list generated by running the program of the second running module 30 is used to supplement the parts information required for verification. This improves the efficiency and accuracy of verifying pin naming.

Persons of ordinary skill in the art should realize that the above embodiments are only used to illustrate the present application and are not used to limit the present application. The above embodiments should only be modified within the scope of the essential spirit of the present application. Appropriate changes and variations should fall within the scope of protection claimed in this application.

S101~S107: Steps

Claims (9)

A pin naming verification method, the improvement of which is that the method includes: storing information of a plurality of parts; running the circuit to be verified, and generating a part pin report; comparing the part pin report with the stored information of the plurality of parts Information to confirm whether the component pin naming in the circuit to be verified is correct; when the comparison shows that the component pin report is different from the stored information of the multiple components, confirm the component pin naming in the circuit to be verified Incorrect; when the comparison shows that the part pin report is the same as the stored information of the plurality of parts, it is confirmed that the part pins in the circuit to be verified are named correctly; and based on the logic output method of the part, confirm Whether the pin naming is correct; when the logic output mode of the stored component is the same as the logic output mode of the component in the circuit to be verified, then the pin naming of the component in the circuit to be verified is correct; when the stored location When the logic output mode of the component is different from the logic output mode of the component in the circuit to be verified, the pin naming of the component in the circuit to be verified is incorrect. The pin naming verification method as described in claim 1, wherein the method further includes, before running the circuit to be verified, detecting the components in the circuit to be verified, and confirming whether there are any components in the circuit to be verified. The information of the parts has not been preset and stored; when it is confirmed that the information of the parts in the circuit to be verified has not been preset and stored, the information of the parts that have not been preset and stored will be preset and stored according to the parts list. Store; when it is confirmed that the parts in the circuit to be verified have been stored, run the circuit to be verified. The method for verifying pin naming as described in claim 1, wherein the method further includes: the part pin report includes the pin of the part and the naming of the pin; when the pin of the part is predetermined When the letter is the suffix, the signal transmitted by the pin is the first signal; when the pin of the part is not named with the preset letter as the suffix, the signal transmitted by the pin is the second signal. signal. The method for verifying pin naming as described in claim 1, wherein the step of confirming whether the pin naming is correct according to the logic output mode of the component includes: when the signal transmitted by the input pin of the component is connected to the output pin. When the signals transmitted by the pin signals are the same, the logic output mode of the part is to perform logic output in the same direction; when the signals transmitted by the input pins of the parts are different from the signals transmitted by the output pins, the logic output mode of the parts is The output mode is reverse logic output. The pin naming verification method as described in request item 1, wherein the method further includes: when it is determined that the component pin naming in the circuit to be verified is incorrect, issuing a prompt to remind the circuit to be verified that the circuit to be verified needs to be Revise. A pin naming verification system, the improvement of which is that the pin naming verification system is used to implement the pin naming verification method as described in any one of claims 1 to 5; the pin naming verification The system includes: a storage module used to preset and store information on a plurality of parts; a first running module used to run the circuit to be verified and generate a part pin report; An inspection module, the inspection module is used to compare the part pin report generated in the first running module with the information of the plurality of parts stored in the storage module. The pin naming verification system according to claim 6, wherein the pin naming verification system further includes a second running module; the second running module is used to generate a parts list, and the parts list includes Information on various parts. The pin naming verification system as described in claim 7, wherein when the storage module lacks component information in the circuit to be verified, the storage module obtains it from the second running module Information about missing parts is preset and stored. A computer-readable storage medium on which at least one computer instruction is stored. The improvement is that the computer instruction is loaded by a processor and executes the pin naming verification method described in any one of claims 1 to 5.

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