TWI815531B - Pip structure and manufacturing methods of high voltage device and capacitor device having pip structure - Google Patents

Pip structure and manufacturing methods of high voltage device and capacitor device having pip structure Download PDF

Info

Publication number
TWI815531B
TWI815531B TW111124579A TW111124579A TWI815531B TW I815531 B TWI815531 B TW I815531B TW 111124579 A TW111124579 A TW 111124579A TW 111124579 A TW111124579 A TW 111124579A TW I815531 B TWI815531 B TW I815531B
Authority
TW
Taiwan
Prior art keywords
region
polycrystalline silicon
insulating
polysilicon
layer
Prior art date
Application number
TW111124579A
Other languages
Chinese (zh)
Other versions
TW202332057A (en
Inventor
蔡晉欽
永中 胡
Original Assignee
立錡科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 立錡科技股份有限公司 filed Critical 立錡科技股份有限公司
Priority to US17/933,126 priority Critical patent/US20230238242A1/en
Publication of TW202332057A publication Critical patent/TW202332057A/en
Application granted granted Critical
Publication of TWI815531B publication Critical patent/TWI815531B/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A poly silicon-insulator-poly silicon (PIP) structure includes: a first poly silicon region formed on a substrate; a first insulation region formed outside a first side of the first poly silicon region and adjoined to the first poly silicon region in a horizontal direction; and a second poly silicon region formed outside a third side of the first insulation region, such that the first poly silicon region, the first insulation region and the second poly silicon region are adjoined in sequence in the horizontal direction; wherein the second poly silicon region is formed outside the third side of the first insulation region by a first self-aligned process step; wherein the first insulation region is formed outside the first side of the first poly silicon region by a second self-aligned process step.

Description

PIP結構及具有PIP結構之高壓元件與電容元件之製造方法PIP structure and manufacturing method of high-voltage components and capacitive components having PIP structure

本發明有關於一種PIP結構及具有PIP結構之高壓元件與電容元件之製造方法，特別是指一種能夠縮短閘極與分離閘極間的距離之PIP結構及具有PIP結構之高壓元件與電容元件之製造方法。The present invention relates to a PIP structure and a method of manufacturing a high-voltage element and a capacitive element having a PIP structure. In particular, it relates to a PIP structure that can shorten the distance between a gate and a separate gate, and a high-voltage element and a capacitive element having a PIP structure. Manufacturing method.

請參考圖1，其係顯示一習知之高壓元件的剖視示意圖。如圖1所示，傳統之高壓元件10若未來想要進行微縮，會被閘極G1與分離閘極G2間的間隔層116、自對準氧化層108及降低表面電場(RESURF)氧化層104之厚度所限制。再者，分離閘極G2會因為閘極G1與分離閘極G2間之間隔層116、自對準氧化層108及降低表面電場(RESURF, reduced surface field)氧化層104的堆疊而位移或變形，換言之，由於降低表面電場(RESURF)氧化層104之厚度較厚，閘極G1及分離閘極G2間的距離被拉長之狀況明顯，若分離閘極G2太過靠近閘極G1，而擠壓到降低表面電場(RESURF)氧化層104，則會容易造成分離閘極G2傾斜，而使製程控制不易。Please refer to Figure 1, which shows a schematic cross-sectional view of a conventional high-voltage component. As shown in FIG. 1 , if the traditional high-voltage device 10 wants to be miniaturized in the future, it will be separated by a spacer layer 116 between the gate G1 and the separation gate G2 , a self-aligned oxide layer 108 and a reduced surface electric field (RESURF) oxide layer 104 limited by its thickness. Furthermore, the separation gate G2 will be displaced or deformed due to the stacking of the spacer layer 116 between the gate G1 and the separation gate G2, the self-aligned oxide layer 108 and the RESURF (reduced surface field) oxide layer 104. In other words, due to the thick thickness of the RESURF oxide layer 104, the distance between the gate G1 and the separation gate G2 is obviously stretched. If the separation gate G2 is too close to the gate G1, it will be squeezed. If the surface electric field (RESURF) oxide layer 104 is reduced, it will easily cause the separation gate G2 to tilt, making process control difficult.

有鑑於此，本發明提出一種嶄新的PIP結構及具有PIP結構之高壓元件與電容元件之製造方法。In view of this, the present invention proposes a brand-new PIP structure and a manufacturing method of high-voltage components and capacitive components having a PIP structure.

於一觀點中，本發明提供了一種多晶矽-絕緣物-多晶矽(poly silicon-insulator-poly silicon, PIP)結構，包括：一第一多晶矽區，形成於一基板上；一第一絕緣區，形成於該第一多晶矽區之一第一側外，而與該第一多晶矽區在一橫向上鄰接；以及一第二多晶矽區，形成於該第一絕緣區之一第三側外，而使得該第一多晶矽區、該第一絕緣區與該第二多晶矽區於該橫向上依次鄰接；其中該第二多晶矽區以一第一自對準製程步驟而形成於該第一絕緣區之該第三側外；其中該第一絕緣區以一第二自對準製程步驟而形成於該第一多晶矽區之該第一側外。In one aspect, the present invention provides a polysilicon-insulator-polysilicon (PIP) structure, including: a first polysilicon region formed on a substrate; a first insulating region , formed outside a first side of the first polycrystalline silicon region and adjacent to the first polycrystalline silicon region in a lateral direction; and a second polycrystalline silicon region formed on one of the first insulating regions outside the third side, so that the first polycrystalline silicon region, the first insulation region and the second polycrystalline silicon region are sequentially adjacent in the lateral direction; wherein the second polycrystalline silicon region is aligned with a first The first insulating region is formed outside the first side of the first polysilicon region by a second self-aligned process step.

於一實施例中，該PIP結構應用於一高壓元件，其中該高壓元件除了該多晶矽-絕緣區-多晶矽結構外，更包括：一源極，形成於該第一多晶矽區之一第二側外下方該基板中，其中該第一側與該第二側為該第一多晶矽區之相對的兩側；以及一汲極，形成於該第二多晶矽區之一第四側外下方該基板中，其中該第四側為該第二多晶矽區之相對鄰接該第一絕緣區之該第三側的另一側；其中該第一多晶矽區用以形成該高壓元件之一閘極，而控制該高壓元件的導通與不導通操作；其中該第二多晶矽區用以形成該高壓元件之一分離閘極，用以於該高壓元件操作時，調整一漂移區之電場。In one embodiment, the PIP structure is applied to a high-voltage device, wherein the high-voltage device, in addition to the polycrystalline silicon-insulating region-polycrystalline silicon structure, further includes: a source electrode formed in the first polycrystalline silicon region and the second polycrystalline silicon region. In the substrate below the side, the first side and the second side are opposite sides of the first polycrystalline silicon region; and a drain is formed on a fourth side of the second polycrystalline silicon region. In the substrate below, the fourth side is the other side of the second polycrystalline silicon region opposite to the third side adjacent to the first insulating region; wherein the first polycrystalline silicon region is used to form the high voltage A gate of the component is used to control conduction and non-conduction operations of the high-voltage component; wherein the second polysilicon region is used to form a separate gate of the high-voltage component to adjust a drift when the high-voltage component is operating. area’s electric field.

於一實施例中，該PIP結構應用於一電容元件，其中該第一多晶矽區用以形成該電容元件之一第一電極，且該第一絕緣區用以形成該電容元件之一介電層，且該第二多晶矽區用以形成該電容元件之一第二電極。In one embodiment, the PIP structure is applied to a capacitive element, wherein the first polysilicon region is used to form a first electrode of the capacitive element, and the first insulating region is used to form a dielectric of the capacitive element. electrical layer, and the second polycrystalline silicon region is used to form a second electrode of the capacitor element.

於一實施例中，該電容元件更包括：一第二絕緣區，形成於該第一多晶矽區之一第二側外，而與該第一多晶矽區在該橫向上鄰接；以及一第三多晶矽區，形成於該第二絕緣區之一第五側外，而使得該第一多晶矽區、該第二絕緣區與該第三多晶矽區於該橫向上之反向上依次鄰接；其中該第三多晶矽區以該第一自對準製程步驟而形成於該第二絕緣區之該第五側外；其中該第二絕緣區以該第二自對準製程步驟而形成於該第一多晶矽區之該第二側外。In one embodiment, the capacitive element further includes: a second insulating region formed outside a second side of the first polycrystalline silicon region and adjacent to the first polycrystalline silicon region in the lateral direction; and A third polycrystalline silicon region is formed outside a fifth side of the second insulation region, so that the first polycrystalline silicon region, the second insulation region and the third polycrystalline silicon region are in the lateral direction. adjacent in reverse order; wherein the third polysilicon region is formed outside the fifth side of the second insulating region using the first self-aligned process step; wherein the second insulating region is formed using the second self-aligned process step The process steps are formed outside the second side of the first polycrystalline silicon region.

於一實施例中，該閘極之一閘極氧化層之厚度介於80Å與130Å之間。In one embodiment, a gate oxide layer of the gate has a thickness between 80Å and 130Å.

於一實施例中，該高壓元件更包括：一矽化金屬區，形成於該第二多晶矽區之該第四側外，用以作為該第二多晶矽區之電性接點；以及一第三絕緣區，以一第三自我對準製程步驟形成於該第二多晶矽區之外；其中該第三絕緣區用以定義該高壓元件之一汲極延伸區，該汲極延伸區於該橫向上之長度介於200Å與300Å之間。In one embodiment, the high-voltage component further includes: a siliconized metal region formed outside the fourth side of the second polycrystalline silicon region for serving as an electrical contact of the second polycrystalline silicon region; and A third insulating region is formed outside the second polysilicon region in a third self-aligned process step; wherein the third insulating region is used to define a drain extension region of the high-voltage device, and the drain extension region The length of the region in this transverse direction is between 200Å and 300Å.

於另一觀點中，本發明係提供一種具有PIP結構之高壓元件之製造方法，包括：形成一第一多晶矽層於一基板上；形成一犧牲層於該第一多晶矽層上；形成一高度決定層於該犧牲層上；以一第一微影(lithography)製程步驟蝕刻該第一多晶矽層、該犧牲層與該高度決定層，而形成一第一堆疊區，其中該第一堆疊區包括一第一多晶矽區、一犧牲區與一高度決定區；形成一第一絕緣層包覆於該第一堆疊區之外側；形成一第二多晶矽層包覆於該第一絕緣層之外側；以一第一自對準製程步驟形成一第二多晶矽區於該第一絕緣層之外側；以一第二自對準製程步驟形成一第一絕緣區於該第一多晶矽區之一第一側外；以及移除該高度決定區而形成一PIP結構；以一第二微影製程步驟蝕刻該PIP結構之該犧牲區與該第一多晶矽區，而形成一雙閘極結構；形成一源極於該第一多晶矽區之一第二側外下方該基板中，其中該第一側與該第二側為該第一多晶矽區之相對的兩側；以及形成一汲極於該第二多晶矽區之一第四側外下方該基板中，其中該第四側為該第二多晶矽區之相對鄰接該第一絕緣區之一第三側的另一側；其中該第一多晶矽區用以形成該高壓元件之一閘極，而控制該高壓元件的導通與不導通操作；其中該第二多晶矽區用以形成該高壓元件之一分離閘極，用以於該高壓元件操作時，調整一漂移區之電場；其中該雙閘極結構之該第一多晶矽區、該第一絕緣區與該第二多晶矽區於一橫向上依次鄰接。In another aspect, the present invention provides a method for manufacturing a high-voltage component with a PIP structure, including: forming a first polycrystalline silicon layer on a substrate; forming a sacrificial layer on the first polycrystalline silicon layer; Forming a height-determining layer on the sacrificial layer; etching the first polysilicon layer, the sacrificial layer and the height-determining layer with a first lithography process step to form a first stacking region, wherein the The first stacking area includes a first polycrystalline silicon area, a sacrificial area and a height determining area; a first insulating layer is formed to cover the outside of the first stacking area; a second polycrystalline silicon layer is formed to cover the outside of the first stacking area. outside the first insulating layer; using a first self-aligned process step to form a second polysilicon region outside the first insulating layer; using a second self-aligned process step to form a first insulating region outside a first side of the first polycrystalline silicon region; and removing the height-determining region to form a PIP structure; etching the sacrificial region and the first polycrystalline silicon of the PIP structure with a second lithography process step region to form a dual gate structure; forming a source in the substrate outside and below a second side of the first polysilicon region, wherein the first side and the second side are the first polysilicon on opposite sides of the region; and forming a drain in the substrate below a fourth side of the second polycrystalline silicon region, wherein the fourth side is opposite to the second polycrystalline silicon region and adjacent to the first The other side of the third side of the insulating region; wherein the first polysilicon region is used to form a gate of the high-voltage component and control the conduction and non-conduction operations of the high-voltage component; wherein the second polysilicon The region is used to form a separate gate of the high-voltage component, and is used to adjust the electric field of a drift region when the high-voltage component is operated; wherein the first polysilicon region, the first insulating region of the double gate structure and The second polycrystalline silicon regions are successively adjacent in a lateral direction.

於一實施例中，該第二多晶矽區之高度為該第一多晶矽區之高度的1.5倍到2倍。In one embodiment, the height of the second polycrystalline silicon region is 1.5 times to 2 times the height of the first polycrystalline silicon region.

於一實施例中，該具有PIP結構之高壓元件之製造方法更包括：形成一矽化金屬區於該第二多晶矽區之該第四側外，用以作為該第二多晶矽區之電性接點；以及以一第三自我對準製程步驟形成一第三絕緣區於該第二多晶矽區之外；其中該第三絕緣區用以定義該高壓元件之一汲極延伸區，該汲極延伸區於該橫向上之長度介於200Å與300Å之間。In one embodiment, the manufacturing method of the high-voltage component with the PIP structure further includes: forming a siliconized metal region outside the fourth side of the second polycrystalline silicon region to serve as the second polycrystalline silicon region. electrical contacts; and a third self-aligned process step is used to form a third insulating region outside the second polysilicon region; wherein the third insulating region is used to define a drain extension region of the high-voltage component , the length of the drain extension in the lateral direction is between 200Å and 300Å.

於一實施例中，該分離閘極電連接於該閘極或一接地電位。In one embodiment, the split gate is electrically connected to the gate or a ground potential.

於又一觀點中，本發明係提供一種具有PIP結構之電容元件之製造方法，包括：形成一第一多晶矽層於一基板上；形成一犧牲層於該第一多晶矽層上；形成一高度決定層於該犧牲層上；以一第一微影(lithography)製程步驟蝕刻該第一多晶矽層、該犧牲層與該高度決定層，而形成一第一堆疊區，其中該第一堆疊區包括一第一多晶矽區、一犧牲區與一高度決定區；形成一第一絕緣層包覆於該第一堆疊區之外側；形成一第二多晶矽層包覆於該第一絕緣層之外側；以一第一自對準製程步驟形成一第二多晶矽區於該第一絕緣層之外側；以一第二自對準製程步驟形成一第一絕緣區於該第一多晶矽區之一第一側外；以及移除該高度決定區而形成一PIP結構；其中該第一多晶矽區用以形成該電容元件之一第一電極，且該第一絕緣區用以形成該電容元件之一介電層，且該第二多晶矽區用以形成該電容元件之一第二電極。In another aspect, the present invention provides a method for manufacturing a capacitor element with a PIP structure, which includes: forming a first polycrystalline silicon layer on a substrate; forming a sacrificial layer on the first polycrystalline silicon layer; Forming a height-determining layer on the sacrificial layer; etching the first polysilicon layer, the sacrificial layer and the height-determining layer with a first lithography process step to form a first stacking region, wherein the The first stacking area includes a first polycrystalline silicon area, a sacrificial area and a height determining area; a first insulating layer is formed to cover the outside of the first stacking area; a second polycrystalline silicon layer is formed to cover the outside of the first stacking area. outside the first insulating layer; using a first self-aligned process step to form a second polysilicon region outside the first insulating layer; using a second self-aligned process step to form a first insulating region outside a first side of the first polycrystalline silicon region; and removing the height-determining region to form a PIP structure; wherein the first polycrystalline silicon region is used to form a first electrode of the capacitor element, and the third An insulating region is used to form a dielectric layer of the capacitive element, and the second polysilicon region is used to form a second electrode of the capacitive element.

於一實施例中，該具有PIP結構之電容元件之製造方法更包括：形成一第二絕緣區於該第一多晶矽區之一第二側外，而與該第一多晶矽區在該橫向上鄰接；以及形成一第三多晶矽區於該第二絕緣區之一第五側外，而使得該第一多晶矽區、該第二絕緣區與該第三多晶矽區於該橫向上之反向上依次鄰接；其中該第三多晶矽區以該第一自對準製程步驟而形成於該第二絕緣區之該第五側外；其中該第二絕緣區以該第二自對準製程步驟而形成於該第一多晶矽區之該第二側外。In one embodiment, the manufacturing method of the capacitor element with the PIP structure further includes: forming a second insulating region outside a second side of the first polycrystalline silicon region and in contact with the first polycrystalline silicon region. the lateral adjoining; and forming a third polycrystalline silicon region outside a fifth side of the second insulation region, such that the first polycrystalline silicon region, the second insulation region and the third polycrystalline silicon region adjacent in the opposite direction in the lateral direction; wherein the third polysilicon region is formed outside the fifth side of the second insulating region by the first self-aligned process step; wherein the second insulating region is formed by the first self-aligned process step; A second self-aligned process step is formed outside the second side of the first polysilicon region.

於一實施例中，該第二電極之高度為該第一電極之高度的1.5倍到2倍。In one embodiment, the height of the second electrode is 1.5 times to 2 times the height of the first electrode.

於一實施例中，該第一絕緣區由一高溫氧化(high temperature oxidation，HTO)製程步驟或一快速熱氧化(rapid thermal oxidation, RTO)製程步驟所形成。In one embodiment, the first insulating region is formed by a high temperature oxidation (HTO) process step or a rapid thermal oxidation (RTO) process step.

於一實施例中，形成該第一絕緣層使用之材質包括四乙氧基矽烷(TEOS, tetraethoxysilane)。In one embodiment, the material used to form the first insulating layer includes tetraethoxysilane (TEOS).

於一實施例中，該第一絕緣區於該橫向上之厚度為400Å與900Å之間。In one embodiment, the thickness of the first insulating region in the lateral direction is between 400Å and 900Å.

本發明之優點係為本發明藉由PIP結構形成高壓元件及電容元件，可達到使分離閘極不會因為絕緣區、間隔層的層層堆疊而導致變形或位移，且使閘極與分離閘極間的距離僅與第一絕緣區之橫向厚度相關。The advantage of the present invention is that the high-voltage components and capacitive components are formed through a PIP structure, so that the separation gate will not be deformed or displaced due to the layer-by-layer stacking of insulating areas and spacers, and the gate and separation gate The distance between the poles is only related to the lateral thickness of the first insulating region.

底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。It will be easier to understand the purpose, technical content, characteristics and achieved effects of the present invention through detailed description of specific embodiments below.

有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之較佳實施例的詳細說明中，將可清楚的呈現。本發明中的圖式均屬示意，主要意在表示製程步驟以及各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the drawings. The drawings in the present invention are schematic and are mainly intended to represent the process steps and the sequential relationship between each layer. The shape, thickness and width are not drawn to scale.

請參考圖2，其根據本發明之一實施例顯示具有PIP結構之高壓元件的剖視示意圖。如圖2所示，本發明之具有PIP(多晶矽-絕緣物-多晶矽, poly silicon-insulator-poly silicon)結構之高壓元件20包括第一多晶矽區202、第一絕緣區203、第二多晶矽區204、矽化金屬區207、第三絕緣區208、源極218及汲極219。第一多晶矽區202形成於基板201上。基板201例如但不限於為一P型或N型的半導體基板。形成基板201的方式，為本領域中具有通常知識者所熟知，在此不予贅述。第一絕緣區203形成於第一多晶矽區202之第一側209外，而與第一多晶矽區202在橫向上鄰接。第二多晶矽區204形成於第一絕緣區203之第三側211外，而使得第一多晶矽區202、第一絕緣區203與第二多晶矽區204於橫向上依次鄰接。Please refer to FIG. 2 , which shows a schematic cross-sectional view of a high-voltage component with a PIP structure according to an embodiment of the present invention. As shown in Figure 2, the high-voltage device 20 with a PIP (poly silicon-insulator-poly silicon) structure of the present invention includes a first polysilicon region 202, a first insulation region 203, a second polysilicon region Crystalline silicon region 204, siliconized metal region 207, third insulating region 208, source electrode 218 and drain electrode 219. The first polysilicon region 202 is formed on the substrate 201 . The substrate 201 is, for example, but not limited to, a P-type or N-type semiconductor substrate. The method of forming the substrate 201 is well known to those with ordinary knowledge in the art and will not be described in detail here. The first insulation region 203 is formed outside the first side 209 of the first polycrystalline silicon region 202 and is laterally adjacent to the first polycrystalline silicon region 202 . The second polycrystalline silicon region 204 is formed outside the third side 211 of the first insulation region 203, so that the first polycrystalline silicon region 202, the first insulation region 203 and the second polycrystalline silicon region 204 are laterally adjacent in sequence.

於一實施例中，第二多晶矽區204以第一自對準製程步驟而形成於第一絕緣區203之第三側211外。於一實施例中，第一絕緣區203以第二自對準製程步驟而形成於第一多晶矽區202之第一側209外。矽化金屬區207形成於第二多晶矽區204之第四側212外，用以作為第二多晶矽區204之電性接點。第三絕緣區208以第三自我對準製程步驟形成於第二多晶矽區204之外。第三絕緣區208用以定義高壓元件20之汲極延伸區。於一實施例中，汲極延伸區於橫向上之長度介於200Å與300Å之間。源極218形成於第一多晶矽區202之第二側210外下方基板201中。第一側209與第二側210為第一多晶矽區202之相對的兩側。汲極219形成於第二多晶矽區204之第四側212外下方基板201中。第四側212為第二多晶矽區204之相對鄰接第一絕緣區203之第三側211的另一側。第一多晶矽區202用以形成高壓元件20之閘極，而控制高壓元件20的導通與不導通操作，而第二多晶矽區204用以形成高壓元件20之分離閘極，用以於高壓元件20操作時調整漂移區之電場。間隔層216分別形成並連接於第一絕緣區203之第六側221、第二多晶矽區204之第四側212及第一多晶矽區202之第二側210外。In one embodiment, the second polysilicon region 204 is formed outside the third side 211 of the first insulating region 203 using a first self-aligned process step. In one embodiment, the first insulation region 203 is formed outside the first side 209 of the first polysilicon region 202 using a second self-aligned process step. The siliconized metal region 207 is formed outside the fourth side 212 of the second polycrystalline silicon region 204 to serve as an electrical contact of the second polycrystalline silicon region 204 . A third insulating region 208 is formed outside the second polysilicon region 204 in a third self-aligned process step. The third insulating region 208 is used to define the drain extension region of the high voltage component 20 . In one embodiment, the length of the drain extension in the lateral direction is between 200Å and 300Å. The source 218 is formed in the lower substrate 201 outside the second side 210 of the first polysilicon region 202 . The first side 209 and the second side 210 are opposite sides of the first polysilicon region 202 . The drain electrode 219 is formed in the lower substrate 201 outside the fourth side 212 of the second polysilicon region 204 . The fourth side 212 is the other side of the second polysilicon region 204 adjacent to the third side 211 of the first insulation region 203 . The first polysilicon region 202 is used to form the gate of the high-voltage device 20 to control the conduction and non-conduction operations of the high-voltage device 20 , while the second polysilicon region 204 is used to form the separation gate of the high-voltage device 20 to control the conduction and non-conduction of the high-voltage device 20 . The electric field in the drift region is adjusted when the high-voltage component 20 is operated. The spacer layers 216 are respectively formed and connected outside the sixth side 221 of the first insulation region 203, the fourth side 212 of the second polycrystalline silicon region 204, and the second side 210 of the first polycrystalline silicon region 202.

於一實施例中，第二多晶矽區204之高度為第一多晶矽區202之高度的1.5倍到2倍。於一實施例中，第一絕緣區203由高溫氧化(high temperature oxidation，HTO)製程步驟或快速熱氧化(rapid thermal oxidation, RTO)製程步驟所形成。於一實施例中，形成第一絕緣區203使用之材質包括四乙氧基矽烷(TEOS, tetraethoxysilane)。於一實施例中，第一絕緣區203於橫向上之厚度例如為400Å與900Å之間。於一實施例中，閘極之閘極氧化層(例如第一多晶矽區202正下方的第一絕緣區203)之厚度介於80Å與130Å之間。分離閘極(例如第二多晶矽區204)電連接於閘極(例如第一多晶矽區202)或接地電位。In one embodiment, the height of the second polycrystalline silicon region 204 is 1.5 times to 2 times the height of the first polycrystalline silicon region 202 . In one embodiment, the first insulation region 203 is formed by a high temperature oxidation (HTO) process step or a rapid thermal oxidation (RTO) process step. In one embodiment, the material used to form the first insulating region 203 includes tetraethoxysilane (TEOS). In one embodiment, the thickness of the first insulating region 203 in the lateral direction is, for example, between 400Å and 900Å. In one embodiment, the thickness of the gate oxide layer of the gate (eg, the first insulating region 203 directly below the first polysilicon region 202 ) is between 80 Å and 130 Å. The split gate (eg, second polysilicon region 204) is electrically connected to the gate (eg, first polysilicon region 202) or ground potential.

圖3係根據本發明之另一實施例顯示具有PIP結構之電容元件的剖視示意圖。如圖3所示，本發明之具有PIP(多晶矽-絕緣物-多晶矽, poly silicon-insulator-poly silicon)結構之電容元件30包括第一多晶矽區302、第一絕緣區303、第二多晶矽區304、第二絕緣區305、第三多晶矽區306及矽化金屬區307。第一多晶矽區302形成於基板301上。第一絕緣區303形成於第一多晶矽區302之第一側309外，而與第一多晶矽區302在橫向上鄰接。第二多晶矽區304形成於第一絕緣區303之第三側311外，而使得第一多晶矽區302、第一絕緣區303與第二多晶矽區304於橫向上依次鄰接。於一實施例中，第二多晶矽區304以第一自對準製程步驟而形成於第一絕緣區303之第三側311外。於一實施例中，第一絕緣區303以第二自對準製程步驟而形成於第一多晶矽區302之第一側309外。FIG. 3 is a schematic cross-sectional view showing a capacitive element with a PIP structure according to another embodiment of the present invention. As shown in Figure 3, the capacitive element 30 with a PIP (poly silicon-insulator-poly silicon) structure of the present invention includes a first polysilicon region 302, a first insulating region 303, a second polysilicon region Crystalline silicon region 304, second insulation region 305, third polycrystalline silicon region 306 and siliconized metal region 307. The first polysilicon region 302 is formed on the substrate 301 . The first insulation region 303 is formed outside the first side 309 of the first polycrystalline silicon region 302 and is laterally adjacent to the first polycrystalline silicon region 302 . The second polycrystalline silicon region 304 is formed outside the third side 311 of the first insulation region 303, so that the first polycrystalline silicon region 302, the first insulation region 303 and the second polycrystalline silicon region 304 are laterally adjacent in sequence. In one embodiment, the second polysilicon region 304 is formed outside the third side 311 of the first insulating region 303 using a first self-aligned process step. In one embodiment, the first insulation region 303 is formed outside the first side 309 of the first polysilicon region 302 using a second self-aligned process step.

第一多晶矽區302用以形成電容元件30之第一電極，且第一絕緣區303用以形成電容元件30之介電層，且第二多晶矽區304用以形成電容元件30之第二電極。第二絕緣區305形成於第一多晶矽區302之第二側310外，而與第一多晶矽區302在橫向上鄰接。第三多晶矽區306形成於第二絕緣區305之第五側313外，而使得第一多晶矽區302、第二絕緣區305與第三多晶矽區306於橫向上之反向上依次鄰接。於一實施例中，第三多晶矽區306以第一自對準製程步驟而形成於第二絕緣區305之第五側313外。於一實施例中，第二絕緣區305以第二自對準製程步驟而形成於第一多晶矽區302之第二側310外。The first polycrystalline silicon region 302 is used to form the first electrode of the capacitor element 30 , the first insulation region 303 is used to form the dielectric layer of the capacitor element 30 , and the second polycrystalline silicon region 304 is used to form the capacitor element 30 . Second electrode. The second insulation region 305 is formed outside the second side 310 of the first polycrystalline silicon region 302 and is laterally adjacent to the first polycrystalline silicon region 302 . The third polycrystalline silicon region 306 is formed outside the fifth side 313 of the second insulation region 305, so that the first polycrystalline silicon region 302, the second insulation region 305 and the third polycrystalline silicon region 306 are on opposite sides in the lateral direction. adjacent in sequence. In one embodiment, the third polysilicon region 306 is formed outside the fifth side 313 of the second insulation region 305 using a first self-aligned process step. In one embodiment, the second insulating region 305 is formed outside the second side 310 of the first polysilicon region 302 using a second self-aligned process step.

矽化金屬區307分別形成於第二多晶矽區304之第四側312外及第三多晶矽區306之第八側323外，分別用以作為第二多晶矽區304及第三多晶矽區306之電性接點。間隔層316分別形成於第一絕緣區303之第六側321、第二多晶矽區304之第四側312、第二絕緣區305之第七側322及第三多晶矽區306之第八側323上。於一較佳實施例中，電容元件30係形成於一絕緣層上，絕緣層例如但不限於淺溝槽隔絕(shallow trench isolation, STI)結構317。於一實施例中，第二多晶矽區304及第三多晶矽區306之高度為第一多晶矽區302之高度的1.5倍到2倍。於一實施例中，第一絕緣區303及第二絕緣區305由高溫氧化(high temperature oxidation，HTO)製程步驟或快速熱氧化(rapid thermal oxidation, RTO)製程步驟所形成。於一實施例中，形成第一絕緣區303及第二絕緣區305使用之材質包括四乙氧基矽烷(TEOS, tetraethoxysilane)。The siliconized metal regions 307 are respectively formed outside the fourth side 312 of the second polycrystalline silicon region 304 and outside the eighth side 323 of the third polycrystalline silicon region 306 to serve as the second polycrystalline silicon region 304 and the third polycrystalline silicon region 306 respectively. The electrical contacts of the crystalline silicon area 306. The spacer layers 316 are respectively formed on the sixth side 321 of the first insulating region 303, the fourth side 312 of the second polysilicon region 304, the seventh side 322 of the second insulating region 305, and the third side of the third polysilicon region 306. Eight sides 323 on. In a preferred embodiment, the capacitor element 30 is formed on an insulating layer, such as but not limited to a shallow trench isolation (STI) structure 317 . In one embodiment, the heights of the second polycrystalline silicon region 304 and the third polycrystalline silicon region 306 are 1.5 times to 2 times the height of the first polycrystalline silicon region 302 . In one embodiment, the first insulation region 303 and the second insulation region 305 are formed by a high temperature oxidation (HTO) process step or a rapid thermal oxidation (RTO) process step. In one embodiment, the material used to form the first insulation region 303 and the second insulation region 305 includes tetraethoxysilane (TEOS).

於一實施例中，第一絕緣區303及第二絕緣區305於橫向上之厚度例如為400Å與900Å之間。於一實施例中，電容元件30可從第一多晶矽區302之中間切開而形成兩個電容，此兩個電容可加以並聯成一個電容。於一實施例中，當上述兩個電容並聯時，第二多晶矽區304之矽化金屬區307可與第三多晶矽區306之矽化金屬區307電連接，且被切開成兩部分的第一多晶矽區302可彼此電連接。In one embodiment, the thickness of the first insulating region 303 and the second insulating region 305 in the lateral direction is, for example, between 400Å and 900Å. In one embodiment, the capacitor element 30 can be cut from the middle of the first polysilicon region 302 to form two capacitors, and the two capacitors can be connected in parallel to form one capacitor. In one embodiment, when the above two capacitors are connected in parallel, the silicide metal region 307 of the second polysilicon region 304 can be electrically connected to the silicide metal region 307 of the third polysilicon region 306 and be cut into two parts. The first polysilicon regions 302 may be electrically connected to each other.

圖4A~4N係根據本發明之實施例顯示具有PIP結構之高壓元件及電容元件之製造方法的剖視示意圖。如圖4A所示，首先，形成一絕緣層例如但不限於淺溝槽隔絕(shallow trench isolation, STI)結構417於基板401上。接著，如圖4B所示，例如但不限於以沉積製程步驟形成第一多晶矽層402’於基板401上。之後，如圖4B所示，例如但不限於以沉積製程步驟形成犧牲層414’於第一多晶矽層402’上。接續，如圖4B所示，例如但不限於以沉積製程步驟形成高度決定層415’於犧牲層414’上。4A to 4N are schematic cross-sectional views showing a method of manufacturing a high-voltage component and a capacitive component with a PIP structure according to an embodiment of the present invention. As shown in FIG. 4A , first, an insulating layer such as but not limited to a shallow trench isolation (STI) structure 417 is formed on the substrate 401 . Next, as shown in FIG. 4B, a first polysilicon layer 402' is formed on the substrate 401 by, for example but not limited to, deposition process steps. Thereafter, as shown in FIG. 4B, a sacrificial layer 414' is formed on the first polycrystalline silicon layer 402', for example but not limited to a deposition process step. Next, as shown in FIG. 4B , a height-determining layer 415' is formed on the sacrificial layer 414' by, for example but not limited to, a deposition process step.

之後，如圖4C及4D所示，利用遮罩420以第一微影(lithography)製程步驟蝕刻第一多晶矽層402’、犧牲層414’與高度決定層415’，而形成第一堆疊區，其中第一堆疊區包括第一多晶矽區402、犧牲區414與高度決定區415。接著，如圖4E所示，例如但不限於以沉積製程步驟形成第一絕緣層403’包覆於第一堆疊區之外側。接續，如圖4E所示，例如但不限於以沉積製程步驟形成第二多晶矽層404’包覆於第一絕緣層403’之外側。之後，如圖4F、4G及4H所示，以第一自對準製程步驟形成第二多晶矽區404於第一絕緣層403’之外側(即第三側411)，且形成第三多晶矽區406於第一絕緣層403’之第五側413外，而使得第一多晶矽區402、第二絕緣區405與第三多晶矽區406於橫向上之反向上依次鄰接。Thereafter, as shown in FIGS. 4C and 4D , the first polycrystalline silicon layer 402 ′, the sacrificial layer 414 ′ and the height determining layer 415 ′ are etched using the mask 420 in a first lithography process step to form a first stack. area, wherein the first stacking area includes a first polysilicon area 402, a sacrificial area 414 and a height determining area 415. Next, as shown in FIG. 4E, a first insulating layer 403' is formed to cover the outside of the first stacking region, for example but not limited to, using a deposition process step. Next, as shown in FIG. 4E, a second polycrystalline silicon layer 404' is formed to cover the outside of the first insulating layer 403', for example but not limited to a deposition process step. 4F, 4G and 4H, a first self-aligned process step is used to form a second polysilicon region 404 outside the first insulating layer 403' (ie, the third side 411), and a third polysilicon region 404 is formed. The crystalline silicon region 406 is outside the fifth side 413 of the first insulation layer 403', so that the first polycrystalline silicon region 402, the second insulation region 405 and the third polycrystalline silicon region 406 are sequentially adjacent in opposite directions in the lateral direction.

接續，如圖4H所示，以第二自對準製程步驟形成第一絕緣區403於第一多晶矽區402之第一側409外，且形成第二絕緣區405於第一多晶矽區402之第二側410外，而使第二絕緣區405與第一多晶矽區402在橫向上鄰接。接著，如圖4I所示，例如以濕式蝕刻製程步驟移除高度決定區415而形成PIP結構。之後，如圖4J所示，利用遮罩(未圖示)以第二微影製程步驟蝕刻高壓元件20之PIP結構之犧牲區414與第一多晶矽區402，而形成雙閘極結構。接著，如圖4K所示，分別形成間隔層416於第一絕緣區403之第六側421、第二多晶矽區404之第四側412、第一多晶矽區402之第二側410、第二絕緣區405之第七側422及第三多晶矽區406之第八側423上。Continuing, as shown in FIG. 4H , a second self-aligned process step is used to form a first insulation region 403 outside the first side 409 of the first polycrystalline silicon region 402, and a second insulation region 405 is formed outside the first polycrystalline silicon region. Outside the second side 410 of the region 402, the second insulating region 405 is laterally adjacent to the first polysilicon region 402. Next, as shown in FIG. 4I , the height determining region 415 is removed by, for example, a wet etching process step to form a PIP structure. Then, as shown in FIG. 4J , a mask (not shown) is used to etch the sacrificial region 414 and the first polysilicon region 402 of the PIP structure of the high-voltage device 20 in a second lithography process step to form a double gate structure. Next, as shown in FIG. 4K , spacer layers 416 are formed on the sixth side 421 of the first insulating region 403 , the fourth side 412 of the second polycrystalline silicon region 404 , and the second side 410 of the first polycrystalline silicon region 402 . , on the seventh side 422 of the second insulation region 405 and the eighth side 423 of the third polysilicon region 406 .

接續，如圖4L所示，形成源極418於第一多晶矽區402之第二側410外下方基板401中，其中第一側409與第二側410為第一多晶矽區402之相對的兩側。如圖4L所示，形成汲極419於第二多晶矽區404之第四側412外下方基板401中，其中第四側412為第二多晶矽區404之相對鄰接第一絕緣區403之第三側411的另一側。形成源極418與汲極419之步驟，例如但不限於利用由微影製程步驟形成光阻層為遮罩，視高壓元件20為N型元件或P型元件，將N型或P型雜質透過離子植入製程步驟，以加速離子的形式，分別摻雜至基板401中，以形成源極418與汲極419。第一多晶矽區402用以形成高壓元件20之閘極，而控制高壓元件20的導通與不導通操作，而第二多晶矽區404用以形成高壓元件20之分離閘極，用以於高壓元件20操作時，調整漂移區之電場。雙閘極結構之第一多晶矽區402、第一絕緣區403與第二多晶矽區404於橫向上依次鄰接。Continuing, as shown in FIG. 4L , the source electrode 418 is formed in the lower substrate 401 outside the second side 410 of the first polycrystalline silicon region 402 , wherein the first side 409 and the second side 410 are between the first polycrystalline silicon region 402 Opposite sides. As shown in FIG. 4L , the drain electrode 419 is formed in the lower substrate 401 outside the fourth side 412 of the second polysilicon region 404 , where the fourth side 412 is the first insulating region 403 opposite to the second polysilicon region 404 . The other side of the third side 411. The steps of forming the source electrode 418 and the drain electrode 419 include, but are not limited to, using a photoresist layer formed by a photolithography process as a mask. The high-voltage component 20 is regarded as an N-type component or a P-type component, and N-type or P-type impurities are allowed to pass through. In the ion implantation process step, accelerated ions are doped into the substrate 401 respectively to form the source electrode 418 and the drain electrode 419. The first polysilicon region 402 is used to form the gate of the high-voltage device 20 to control the conduction and non-conduction operations of the high-voltage device 20 , while the second polysilicon region 404 is used to form the separation gate of the high-voltage device 20 to control the conduction and non-conduction of the high-voltage device 20 . When the high-voltage component 20 is operating, the electric field in the drift region is adjusted. The first polycrystalline silicon region 402, the first insulation region 403 and the second polycrystalline silicon region 404 of the double gate structure are adjacent in sequence in the lateral direction.

於一實施例中，第二多晶矽區404及/或第三多晶矽區406之高度為第一多晶矽區402之高度的1.5倍到2倍。於一實施例中，第一絕緣層403’由高溫氧化(high temperature oxidation，HTO)製程步驟或快速熱氧化(rapid thermal oxidation, RTO)製程步驟所形成。於一實施例中，形成第一絕緣層403’使用之材質包括四乙氧基矽烷(TEOS, tetraethoxysilane)。於一實施例中，第一絕緣區403及/或第二絕緣區405於橫向上之厚度為400Å與900Å之間。In one embodiment, the height of the second polycrystalline silicon region 404 and/or the third polycrystalline silicon region 406 is 1.5 times to 2 times the height of the first polycrystalline silicon region 402 . In one embodiment, the first insulating layer 403' is formed by a high temperature oxidation (HTO) process step or a rapid thermal oxidation (RTO) process step. In one embodiment, the material used to form the first insulating layer 403' includes tetraethoxysilane (TEOS). In one embodiment, the thickness of the first insulating region 403 and/or the second insulating region 405 in the lateral direction is between 400Å and 900Å.

接著，如圖4M所示，以第三自我對準製程步驟形成第三絕緣區408於第二多晶矽區404之外。第三絕緣區408用以定義高壓元件20之汲極延伸區。於一實施例中，汲極延伸區於橫向上之長度介於200Å與300Å之間。之後，如圖4N所示，分別形成矽化金屬區407於第二多晶矽區404之第四側412外及第三多晶矽區406之第八側423外，用以分別作為第二多晶矽區404及第三多晶矽區406之電性接點。高壓元件20之分離閘極(例如第二多晶矽區404)電連接於閘極(例如第一多晶矽區402)或接地電位。如圖4N所示，第一多晶矽區402用以形成電容元件30之第一電極，且第一絕緣區403用以形成電容元件30之介電層，且第二多晶矽區404用以形成電容元件30之第二電極。Next, as shown in FIG. 4M , a third self-aligned process step is used to form a third insulation region 408 outside the second polysilicon region 404 . The third insulating region 408 is used to define the drain extension region of the high voltage component 20 . In one embodiment, the length of the drain extension in the lateral direction is between 200Å and 300Å. Afterwards, as shown in FIG. 4N , siliconized metal regions 407 are formed outside the fourth side 412 of the second polycrystalline silicon region 404 and outside the eighth side 423 of the third polycrystalline silicon region 406 to serve as second polycrystalline silicon regions. The electrical contacts of the crystalline silicon region 404 and the third polycrystalline silicon region 406. The separate gate of the high-voltage device 20 (eg, the second polysilicon region 404) is electrically connected to the gate (eg, the first polysilicon region 402) or ground potential. As shown in FIG. 4N, the first polycrystalline silicon region 402 is used to form the first electrode of the capacitor element 30, the first insulating region 403 is used to form the dielectric layer of the capacitor element 30, and the second polycrystalline silicon region 404 is used to form the first electrode of the capacitor element 30. To form the second electrode of the capacitive element 30 .

如上所述，本發明藉由PIP結構形成高壓元件及電容元件，可達到使分離閘極不會因為絕緣區、間隔層的層層堆疊而導致變形或位移，且使閘極與分離閘極間的距離僅與第一絕緣區之橫向厚度相關。As mentioned above, the present invention uses a PIP structure to form high-voltage components and capacitive components, so that the separation gate will not be deformed or displaced due to the layer-by-layer stacking of insulation regions and spacers, and the gap between the gate and the separation gate will be reduced. The distance is only related to the lateral thickness of the first insulating region.

以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，在不影響元件主要的特性下，可加入其他製程步驟或結構，如輕摻雜汲極區等；又如，微影技術並不限於光罩技術，亦可包含電子束微影技術。凡此種種，皆可根據本發明的教示類推而得。此外，所說明之各個實施例，並不限於單獨應用，亦可以組合應用，例如但不限於將兩實施例併用。因此，本發明的範圍應涵蓋上述及其他所有等效變化。此外，本發明的任一實施型態不必須達成所有的目的或優點，因此，請求專利範圍任一項也不應以此為限。The present invention has been described above with reference to the preferred embodiments. However, the above description is only to make it easy for those familiar with the art to understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Various equivalent changes may be devised by those skilled in the art within the same spirit of the present invention. For example, without affecting the main characteristics of the device, other process steps or structures can be added, such as lightly doped drain regions; for another example, lithography technology is not limited to photomask technology, but can also include electron beam lithography technology. All these can be derived by analogy based on the teachings of the present invention. In addition, each of the described embodiments is not limited to being used alone, but can also be used in combination, such as but not limited to using two embodiments together. Accordingly, the scope of the present invention is intended to cover the above and all other equivalent changes. In addition, any implementation form of the present invention may not necessarily achieve all the objectives or advantages, and therefore, the scope of the claimed patent should not be limited by this.

10, 20: 高壓元件 101, 201, 301, 401: 基板 104: 降低表面電場氧化層 108: 自對準氧化層 116, 216, 316, 416: 間隔層 202, 302, 402: 第一多晶矽區 203, 303, 403: 第一絕緣區 204, 304, 404: 第二多晶矽區 207, 307, 407: 矽化金屬區 208, 408: 第三絕緣區 209, 309, 409: 第一側 210, 310, 410: 第二側 211, 311, 411: 第三側 212, 312, 412: 第四側 218, 418: 源極 219, 419: 汲極 221, 321, 421: 第六側 30: 電容元件 305, 405: 第二絕緣區 306, 406: 第三多晶矽區 313, 413: 第五側 317, 417: 淺溝槽隔絕結構 322, 422: 第七側 323, 423: 第八側 402’: 第一多晶矽層 403’: 第一絕緣層 404’ 第二多晶矽層 414: 犧牲區 414’: 犧牲層 415: 高度決定區 415’: 高度決定層 420: 遮罩 G1: 閘極 G2: 分離閘極 10, 20: High voltage components 101, 201, 301, 401: Substrate 104: Reduce surface electric field oxide layer 108: Self-aligned oxide layer 116, 216, 316, 416: Spacer layer 202, 302, 402: First polysilicon area 203, 303, 403: First insulation zone 204, 304, 404: Second polysilicon area 207, 307, 407: Siliconized metal area 208, 408: Third insulation zone 209, 309, 409: first side 210, 310, 410: Second side 211, 311, 411: Third side 212, 312, 412: Fourth side 218, 418: Source 219, 419: Drainage 221, 321, 421: Sixth side 30: Capacitive element 305, 405: Second insulation zone 306, 406: The third polysilicon area 313, 413: Fifth side 317, 417: Shallow trench isolation structure 322, 422: Seventh side 323, 423: Eighth side 402’: First polysilicon layer 403’: First insulation layer 404’ Second polycrystalline silicon layer 414: Sacrifice Zone 414’: Sacrificial layer 415: Height Determination Zone 415’: height determining layer 420: Mask G1: Gate G2: Split gate

圖1係顯示一習知之高壓元件的剖視示意圖。Figure 1 is a schematic cross-sectional view of a conventional high-voltage component.

圖2係根據本發明之一實施例顯示具有PIP結構之高壓元件的剖視示意圖。FIG. 2 is a schematic cross-sectional view showing a high-voltage component with a PIP structure according to an embodiment of the present invention.

圖3係根據本發明之另一實施例顯示具有PIP結構之電容元件的剖視示意圖。FIG. 3 is a schematic cross-sectional view showing a capacitive element with a PIP structure according to another embodiment of the present invention.

圖4A~4N係根據本發明之實施例顯示具有PIP結構之高壓元件及電容元件之製造方法的剖視示意圖。4A to 4N are schematic cross-sectional views showing a method of manufacturing a high-voltage component and a capacitive component with a PIP structure according to an embodiment of the present invention.

20: 高壓元件 201: 基板 202: 第一多晶矽區 203: 第一絕緣區 204: 第二多晶矽區 207: 矽化金屬區 208: 第三絕緣區 209: 第一側 210: 第二側 211: 第三側 212: 第四側 216: 間隔層 218: 源極 219: 汲極 221: 第六側 20: High voltage components 201: Substrate 202: First polysilicon area 203: First insulation zone 204: Second polysilicon area 207: Siliconized metal area 208: Third insulation zone 209: First side 210: Second side 211: Third side 212: Fourth side 216: Spacer layer 218: Source 219: Jiji 221: Sixth Side

Claims (25)

一種多晶矽-絕緣物-多晶矽(poly silicon-insulator-poly silicon, PIP)結構，包含： 一第一多晶矽區，形成於一基板上； 一第一絕緣區，形成於該第一多晶矽區之一第一側外，而與該第一多晶矽區在一橫向上鄰接；以及 一第二多晶矽區，形成於該第一絕緣區之一第三側外，而使得該第一多晶矽區、該第一絕緣區與該第二多晶矽區於該橫向上依次鄰接； 其中該第二多晶矽區以一第一自對準製程步驟而形成於該第一絕緣區之該第三側外； 其中該第一絕緣區以一第二自對準製程步驟而形成於該第一多晶矽區之該第一側外。 A polysilicon-insulator-polysilicon (PIP) structure, including: a first polycrystalline silicon region formed on a substrate; a first insulating region formed outside a first side of the first polycrystalline silicon region and adjacent to the first polycrystalline silicon region in a lateral direction; and A second polycrystalline silicon region is formed outside a third side of the first insulation region, so that the first polycrystalline silicon region, the first insulation region and the second polycrystalline silicon region are sequentially located in the lateral direction adjacency; wherein the second polysilicon region is formed outside the third side of the first insulating region using a first self-aligned process step; The first insulating region is formed outside the first side of the first polysilicon region using a second self-aligned process step. 如請求項1所述之多晶矽-絕緣區-多晶矽結構，應用於一高壓元件，其中該高壓元件除了該多晶矽-絕緣區-多晶矽結構外，更包含： 一源極，形成於該第一多晶矽區之一第二側外下方該基板中，其中該第一側與該第二側為該第一多晶矽區之相對的兩側；以及 一汲極，形成於該第二多晶矽區之一第四側外下方該基板中，其中該第四側為該第二多晶矽區之相對鄰接該第一絕緣區之該第三側的另一側； 其中該第一多晶矽區用以形成該高壓元件之一閘極，而控制該高壓元件的導通與不導通操作； 其中該第二多晶矽區用以形成該高壓元件之一分離閘極，用以於該高壓元件操作時，調整一漂移區之電場。 The polycrystalline silicon-insulating region-polycrystalline silicon structure described in claim 1 is applied to a high-voltage component, wherein in addition to the polycrystalline silicon-insulating region-polycrystalline silicon structure, the high-voltage component further includes: a source formed in the substrate below a second side of the first polycrystalline silicon region, wherein the first side and the second side are opposite sides of the first polycrystalline silicon region; and A drain is formed in the substrate below a fourth side of the second polycrystalline silicon region, wherein the fourth side is opposite to the third side of the second polycrystalline silicon region adjacent to the first insulating region. the other side; The first polysilicon region is used to form a gate of the high-voltage component and control the conduction and non-conduction operations of the high-voltage component; The second polycrystalline silicon region is used to form a separation gate of the high-voltage element, and is used to adjust the electric field of a drift region when the high-voltage element is operated. 如請求項1所述之多晶矽-絕緣區-多晶矽結構，應用於一電容元件，其中該第一多晶矽區用以形成該電容元件之一第一電極，且該第一絕緣區用以形成該電容元件之一介電層，且該第二多晶矽區用以形成該電容元件之一第二電極。The polycrystalline silicon-insulating region-polycrystalline silicon structure as described in claim 1 is applied to a capacitive element, wherein the first polycrystalline silicon region is used to form a first electrode of the capacitive element, and the first insulating region is used to form A dielectric layer of the capacitor element, and the second polysilicon region is used to form a second electrode of the capacitor element. 如請求項3所述之多晶矽-絕緣區-多晶矽結構，其中該電容元件更包括： 一第二絕緣區，形成於該第一多晶矽區之一第二側外，而與該第一多晶矽區在該橫向上鄰接；以及 一第三多晶矽區，形成於該第二絕緣區之一第五側外，而使得該第一多晶矽區、該第二絕緣區與該第三多晶矽區於該橫向上之反向上依次鄰接； 其中該第三多晶矽區以該第一自對準製程步驟而形成於該第二絕緣區之該第五側外； 其中該第二絕緣區以該第二自對準製程步驟而形成於該第一多晶矽區之該第二側外。 The polycrystalline silicon-insulating region-polycrystalline silicon structure as described in claim 3, wherein the capacitor element further includes: a second insulating region formed outside a second side of the first polysilicon region and adjacent to the first polysilicon region in the lateral direction; and A third polycrystalline silicon region is formed outside a fifth side of the second insulation region, so that the first polycrystalline silicon region, the second insulation region and the third polycrystalline silicon region are in the lateral direction. Adjacent in sequence in reverse direction; wherein the third polysilicon region is formed outside the fifth side of the second insulating region using the first self-aligned process step; The second insulating region is formed outside the second side of the first polysilicon region using the second self-aligned process step. 如請求項1所述之多晶矽-絕緣區-多晶矽結構，其中該第二多晶矽區之高度為該第一多晶矽區之高度的1.5倍到2倍。The polycrystalline silicon-insulating region-polycrystalline silicon structure as claimed in claim 1, wherein the height of the second polycrystalline silicon region is 1.5 to 2 times the height of the first polycrystalline silicon region. 如請求項1所述之多晶矽-絕緣區-多晶矽結構，其中該第一絕緣區由一高溫氧化(high temperature oxidation，HTO)製程步驟或一快速熱氧化(rapid thermal oxidation, RTO)製程步驟所形成。The polysilicon-insulating region-polysilicon structure as claimed in claim 1, wherein the first insulating region is formed by a high temperature oxidation (HTO) process step or a rapid thermal oxidation (RTO) process step. . 如請求項1所述之多晶矽-絕緣區-多晶矽結構，其中形成該第一絕緣區使用之材質包括四乙氧基矽烷(TEOS, tetraethoxysilane)。The polycrystalline silicon-insulating region-polycrystalline silicon structure as claimed in claim 1, wherein the material used to form the first insulating region includes tetraethoxysilane (TEOS). 如請求項1所述之多晶矽-絕緣區-多晶矽結構，其中該第一絕緣區於該橫向上之厚度為400Å與900Å之間。The polycrystalline silicon-insulating region-polycrystalline silicon structure as described in claim 1, wherein the thickness of the first insulating region in the lateral direction is between 400Å and 900Å. 如請求項2所述之多晶矽-絕緣區-多晶矽結構，其中該閘極之一閘極氧化層之厚度介於80Å與130Å之間。The polycrystalline silicon-insulating region-polycrystalline silicon structure as described in claim 2, wherein the thickness of a gate oxide layer of the gate is between 80Å and 130Å. 如請求項2所述之多晶矽-絕緣區-多晶矽結構，其中該高壓元件更包括： 一矽化金屬區，形成於該第二多晶矽區之該第四側外，用以作為該第二多晶矽區之電性接點；以及 一第三絕緣區，以一第三自我對準製程步驟形成於該第二多晶矽區之外； 其中該第三絕緣區用以定義該高壓元件之一汲極延伸區，該汲極延伸區於該橫向上之長度介於200Å與300Å之間。 The polycrystalline silicon-insulating region-polycrystalline silicon structure as described in claim 2, wherein the high-voltage component further includes: A siliconized metal region is formed outside the fourth side of the second polycrystalline silicon region to serve as an electrical contact of the second polycrystalline silicon region; and a third insulating region formed outside the second polysilicon region using a third self-aligned process step; The third insulating region is used to define a drain extension region of the high-voltage component, and the length of the drain extension region in the lateral direction is between 200Å and 300Å. 如請求項2所述之多晶矽-絕緣區-多晶矽結構，其中該分離閘極電連接於該閘極或一接地電位。The polysilicon-insulating region-polysilicon structure of claim 2, wherein the separation gate is electrically connected to the gate or a ground potential. 如請求項3所述之多晶矽-絕緣區-多晶矽結構，其中該第二電極之高度為該第一電極之高度的1.5倍到2倍。The polycrystalline silicon-insulating region-polycrystalline silicon structure as described in claim 3, wherein the height of the second electrode is 1.5 times to 2 times the height of the first electrode. 一種具有PIP結構之高壓元件之製造方法，包含： 形成一第一多晶矽層於一基板上； 形成一犧牲層於該第一多晶矽層上； 形成一高度決定層於該犧牲層上； 以一第一微影(lithography)製程步驟蝕刻該第一多晶矽層、該犧牲層與該高度決定層，而形成一第一堆疊區，其中該第一堆疊區包括一第一多晶矽區、一犧牲區與一高度決定區； 形成一第一絕緣層包覆於該第一堆疊區之外側； 形成一第二多晶矽層包覆於該第一絕緣層之外側； 以一第一自對準製程步驟形成一第二多晶矽區於該第一絕緣層之外側； 以一第二自對準製程步驟形成一第一絕緣區於該第一多晶矽區之一第一側外； 移除該高度決定區而形成一PIP結構； 以一第二微影製程步驟蝕刻該PIP結構之該犧牲區與該第一多晶矽區，而形成一雙閘極結構； 形成一源極於該第一多晶矽區之一第二側外下方該基板中，其中該第一側與該第二側為該第一多晶矽區之相對的兩側；以及 形成一汲極於該第二多晶矽區之一第四側外下方該基板中，其中該第四側為該第二多晶矽區之相對鄰接該第一絕緣區之一第三側的另一側； 其中該第一多晶矽區用以形成該高壓元件之一閘極，而控制該高壓元件的導通與不導通操作； 其中該第二多晶矽區用以形成該高壓元件之一分離閘極，用以於該高壓元件操作時，調整一漂移區之電場； 其中該雙閘極結構之該第一多晶矽區、該第一絕緣區與該第二多晶矽區於一橫向上依次鄰接。 A method of manufacturing a high-voltage component with a PIP structure, including: forming a first polysilicon layer on a substrate; forming a sacrificial layer on the first polycrystalline silicon layer; forming a height-determining layer on the sacrificial layer; Etching the first polycrystalline silicon layer, the sacrificial layer and the height determining layer in a first lithography process step to form a first stacking region, wherein the first stacking region includes a first polycrystalline silicon zone, a sacrifice zone and a height determination zone; Form a first insulating layer to cover the outside of the first stacking area; Form a second polysilicon layer to cover the outside of the first insulating layer; Using a first self-aligned process step to form a second polysilicon region outside the first insulating layer; Using a second self-aligned process step to form a first insulating region outside a first side of the first polysilicon region; Remove the height-determining area to form a PIP structure; Etching the sacrificial region and the first polysilicon region of the PIP structure with a second lithography process step to form a dual gate structure; Forming a source in the substrate below a second side of the first polycrystalline silicon region, wherein the first side and the second side are opposite sides of the first polycrystalline silicon region; and A drain is formed in the substrate below a fourth side of the second polycrystalline silicon region, wherein the fourth side is a third side of the second polycrystalline silicon region adjacent to the first insulating region. other side; The first polysilicon region is used to form a gate of the high-voltage component and control the conduction and non-conduction operations of the high-voltage component; The second polycrystalline silicon region is used to form a separation gate of the high-voltage component, and is used to adjust the electric field of a drift region when the high-voltage component is operated; The first polycrystalline silicon region, the first insulation region and the second polycrystalline silicon region of the double gate structure are adjacent in sequence in a lateral direction. 如請求項13所述之具有PIP結構之高壓元件之製造方法，其中該第二多晶矽區之高度為該第一多晶矽區之高度的1.5倍到2倍。As claimed in claim 13, the method for manufacturing a high-voltage component with a PIP structure, wherein the height of the second polycrystalline silicon region is 1.5 to 2 times the height of the first polycrystalline silicon region. 如請求項13所述之具有PIP結構之高壓元件之製造方法，其中該第一絕緣層由一高溫氧化(high temperature oxidation，HTO)製程步驟或一快速熱氧化(rapid thermal oxidation, RTO)製程步驟所形成。The manufacturing method of a high-voltage component with a PIP structure as claimed in claim 13, wherein the first insulating layer is formed by a high temperature oxidation (HTO) process step or a rapid thermal oxidation (RTO) process step. formed. 如請求項13所述之具有PIP結構之高壓元件之製造方法，其中形成該第一絕緣層使用之材質包括四乙氧基矽烷(TEOS, tetraethoxysilane)。The method of manufacturing a high-voltage component with a PIP structure as described in claim 13, wherein the material used to form the first insulating layer includes tetraethoxysilane (TEOS). 如請求項13所述之具有PIP結構之高壓元件之製造方法，其中該第一絕緣區於該橫向上之厚度為400Å與900Å之間。As claimed in claim 13, the method for manufacturing a high-voltage component with a PIP structure, wherein the thickness of the first insulating region in the lateral direction is between 400Å and 900Å. 如請求項13所述之具有PIP結構之高壓元件之製造方法，更包含： 形成一矽化金屬區於該第二多晶矽區之該第四側外，用以作為該第二多晶矽區之電性接點；以及 以一第三自我對準製程步驟形成一第三絕緣區於該第二多晶矽區之外； 其中該第三絕緣區用以定義該高壓元件之一汲極延伸區，該汲極延伸區於該橫向上之長度介於200Å與300Å之間。 The manufacturing method of a high-voltage component with a PIP structure as described in claim 13 further includes: Forming a siliconized metal region outside the fourth side of the second polycrystalline silicon region to serve as an electrical contact of the second polycrystalline silicon region; and using a third self-aligned process step to form a third insulating region outside the second polysilicon region; The third insulating region is used to define a drain extension region of the high-voltage component, and the length of the drain extension region in the lateral direction is between 200Å and 300Å. 如請求項13所述之具有PIP結構之高壓元件之製造方法，其中該分離閘極電連接於該閘極或一接地電位。The manufacturing method of a high-voltage component with a PIP structure as claimed in claim 13, wherein the separation gate is electrically connected to the gate or a ground potential. 一種具有PIP結構之電容元件之製造方法，包含： 形成一第一多晶矽層於一基板上； 形成一犧牲層於該第一多晶矽層上； 形成一高度決定層於該犧牲層上； 以一第一微影(lithography)製程步驟蝕刻該第一多晶矽層、該犧牲層與該高度決定層，而形成一第一堆疊區，其中該第一堆疊區包括一第一多晶矽區、一犧牲區與一高度決定區； 形成一第一絕緣層包覆於該第一堆疊區之外側； 形成一第二多晶矽層包覆於該第一絕緣層之外側； 以一第一自對準製程步驟形成一第二多晶矽區於該第一絕緣層之外側； 以一第二自對準製程步驟形成一第一絕緣區於該第一多晶矽區之一第一側外；以及 移除該高度決定區而形成一PIP結構； 其中該第一多晶矽區用以形成該電容元件之一第一電極，且該第一絕緣區用以形成該電容元件之一介電層，且該第二多晶矽區用以形成該電容元件之一第二電極。 A method of manufacturing a capacitive element with a PIP structure, including: forming a first polysilicon layer on a substrate; forming a sacrificial layer on the first polycrystalline silicon layer; forming a height-determining layer on the sacrificial layer; Etching the first polycrystalline silicon layer, the sacrificial layer and the height determining layer in a first lithography process step to form a first stacking region, wherein the first stacking region includes a first polycrystalline silicon zone, a sacrifice zone and a height determination zone; Form a first insulating layer to cover the outside of the first stacking area; Form a second polysilicon layer to cover the outside of the first insulating layer; Using a first self-aligned process step to form a second polysilicon region outside the first insulating layer; Using a second self-aligned process step to form a first insulating region outside a first side of the first polysilicon region; and Remove the height-determining area to form a PIP structure; The first polycrystalline silicon region is used to form a first electrode of the capacitor element, the first insulating region is used to form a dielectric layer of the capacitor element, and the second polycrystalline silicon region is used to form the One of the second electrodes of the capacitive element. 如請求項20所述之電容元件之製造方法，更包含： 形成一第二絕緣區於該第一多晶矽區之一第二側外，而與該第一多晶矽區在該橫向上鄰接；以及 形成一第三多晶矽區於該第二絕緣區之一第五側外，而使得該第一多晶矽區、該第二絕緣區與該第三多晶矽區於該橫向上之反向上依次鄰接； 其中該第三多晶矽區以該第一自對準製程步驟而形成於該第二絕緣區之該第五側外； 其中該第二絕緣區以該第二自對準製程步驟而形成於該第一多晶矽區之該第二側外。 The manufacturing method of the capacitive element as described in claim 20 further includes: forming a second insulating region outside a second side of the first polysilicon region and adjacent to the first polysilicon region in the lateral direction; and A third polycrystalline silicon region is formed outside a fifth side of the second insulation region, so that the first polycrystalline silicon region, the second insulation region and the third polycrystalline silicon region are opposite to each other in the lateral direction. Adjacent in order upward; wherein the third polysilicon region is formed outside the fifth side of the second insulating region using the first self-aligned process step; The second insulating region is formed outside the second side of the first polysilicon region using the second self-aligned process step. 如請求項20所述之電容元件之製造方法，其中該第二電極之高度為該第一電極之高度的1.5倍到2倍。The method of manufacturing a capacitive element as claimed in claim 20, wherein the height of the second electrode is 1.5 to 2 times the height of the first electrode. 如請求項20所述之電容元件之製造方法，其中該第一絕緣區由一高溫氧化(high temperature oxidation，HTO)製程步驟或一快速熱氧化(rapid thermal oxidation, RTO)製程步驟所形成。The method of manufacturing a capacitor element according to claim 20, wherein the first insulating region is formed by a high temperature oxidation (HTO) process step or a rapid thermal oxidation (RTO) process step. 如請求項20所述之電容元件之製造方法，其中形成該第一絕緣層使用之材質包括四乙氧基矽烷(TEOS, tetraethoxysilane)。The method of manufacturing a capacitor element according to claim 20, wherein the material used to form the first insulating layer includes tetraethoxysilane (TEOS). 如請求項20所述之電容元件之製造方法，其中該第一絕緣區於該橫向上之厚度為400Å與900Å之間。The manufacturing method of a capacitor element as claimed in claim 20, wherein the thickness of the first insulating region in the lateral direction is between 400Å and 900Å.
TW111124579A 2022-01-25 2022-06-30 Pip structure and manufacturing methods of high voltage device and capacitor device having pip structure TWI815531B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/933,126 US20230238242A1 (en) 2022-01-25 2022-09-19 Pip structure and manufacturing methods of high voltage device and capacitor device having pip structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202263302911P 2022-01-25 2022-01-25
US63/302911 2022-01-25

Publications (2)

Publication Number Publication Date
TW202332057A TW202332057A (en) 2023-08-01
TWI815531B true TWI815531B (en) 2023-09-11

Family

ID=87451179

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111124579A TWI815531B (en) 2022-01-25 2022-06-30 Pip structure and manufacturing methods of high voltage device and capacitor device having pip structure

Country Status (2)

Country Link
CN (1) CN116544218A (en)
TW (1) TWI815531B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210126089A1 (en) * 2019-10-25 2021-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Selective polysilicon growth for deep trench polysilicon isolation structure

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210126089A1 (en) * 2019-10-25 2021-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Selective polysilicon growth for deep trench polysilicon isolation structure

Also Published As

Publication number Publication date
TW202332057A (en) 2023-08-01
CN116544218A (en) 2023-08-04

Similar Documents

Publication Publication Date Title
US7923777B2 (en) Power semiconductor device and method for manufacturing the same
TWI656642B (en) Lateral double-diffused metal oxide semiconductor device and method of manufacturing same
CN109801965B (en) Transistor with double-layer spacer and forming method thereof
KR19980018751A (en) SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
TWI644441B (en) High voltage device and manufacturing method thereof
TW201519446A (en) Lateral double diffused metal oxide semiconductor device and manufacturing method thereof
TWI770452B (en) High voltage device and manufacturing method thereof
JP5183959B2 (en) Method for manufacturing MOSFET type semiconductor device
TWI815531B (en) Pip structure and manufacturing methods of high voltage device and capacitor device having pip structure
JP6103453B2 (en) Semiconductor device and manufacturing method thereof
TW202228212A (en) High voltage device, high voltage control device and manufacturing methods thereof
TWI704606B (en) Trench power semiconductor device and manufacturing method thereof
TW202310025A (en) Power device and manufacturing method thereof
US8049274B2 (en) Semiconductor integrated circuit and method of manufacturing the same
TWI844035B (en) Manufacturing method of integrated structure of semiconductor devices having split gate
US20230238242A1 (en) Pip structure and manufacturing methods of high voltage device and capacitor device having pip structure
TWI821940B (en) Integration manufacturing method of high voltage device and low voltage device
TWI841913B (en) High voltage device and manufacturing method thereof
TWI736300B (en) Radio frequency integrated circuit and method of fabricating the same
TW202324746A (en) Nmos half-bridge power device and manufacturing method thereof
TWI811036B (en) Integrated structure of semiconductor devices having shared contact plug and manufacturing method thereof
TWI668802B (en) Metal oxide semiconductor (mos) device and manufacturing method thereof
TW202324612A (en) High voltage cmos device and manufacturing method thereof
US7482228B1 (en) Method of forming a MOS transistor with a litho-less gate
JP2003008018A (en) Semiconductor device and its manufacturing method