TWI814346B - Pixel array substrate and manufacturing method therof - Google Patents

Abstract

A pixel array substrate includes a base, pixel structures, a first insulating layer, a second insulating layer, a common electrode layer and a third insulating layer. The pixel structures are disposed on the base. Each of the pixel structures includes an active element, a pixel electrode electrically connected to the active element, and a color filter pattern overlapping the pixel electrode. The first insulating layer is disposed on active elements of the pixel structures. Color filter patterns of the pixel structures are disposed on the first insulating layer. The second insulating layer is disposed on the color filter patterns. The common electrode layer is disposed on the second insulating layer. The third insulating layer is disposed on the common electrode layer and covers an inner sidewall of the common electrode layer, an inner sidewall of the second insulating layer and an inner sidewall of the color filter pattern. Moreover, a manufacturing method of the pixel array substrate is also provided.

Description

Pixel array substrate and manufacturing method thereof

The invention relates to a pixel array substrate and a manufacturing method thereof.

Generally speaking, a display device includes a pixel array substrate, an opposite substrate relative to the pixel array substrate, and a display medium (eg, liquid crystal) sandwiched between the pixel array substrate and the opposite substrate. In some models, color filter patterns are integrated into the pixel array substrate. The pixel array substrate integrated with the color filter pattern includes the color filter pattern, a first insulating layer located under the color filter pattern, a second insulating layer located on the color filter pattern, and a common insulating layer disposed on the second insulating layer. The electrode layer and the third insulating layer provided on the common electrode layer, wherein the first insulating layer, the color filter pattern, the second insulating layer and the third insulating layer are respectively an inorganic layer, an organic layer, an inorganic layer and an organic layer. The first insulating layer, the color filter pattern, the second insulating layer and the third insulating layer form a structure in which organic/inorganic layers are alternately stacked.

After the display device has passed the oven test, the structure in which organic/inorganic layers are alternately stacked will easily cause cracks at the interface of the organic/inorganic layers, causing problems such as cell gap variation and light leakage of the display device. .

The invention provides a pixel array substrate with good characteristics.

The present invention provides another pixel array substrate with good characteristics.

A pixel array substrate according to an embodiment of the present invention includes a substrate, a plurality of pixel structures, a first insulating layer, a second insulating layer, a common electrode layer and a third insulating layer. The base has an active area and a peripheral area outside the active area. Multiple pixel structures are disposed in the active area of the substrate. Each pixel structure includes an active element, a pixel electrode electrically connected to the active element, and a color filter pattern overlapping the pixel electrode, and the color filter pattern has a top surface facing away from the substrate, a bottom surface facing the substrate, and a connection on the inner wall between the top and bottom surfaces. The first insulating layer is disposed on the plurality of active elements of the plurality of pixel structures, wherein the plurality of color filter patterns of the plurality of pixel structures are disposed on the first insulating layer. The second insulating layer is disposed on the plurality of color filter patterns, wherein the inner wall of the second insulating layer is disposed on the top surface of the color filter patterns of the pixel structure. The common electrode layer is disposed on the second insulating layer, and the inner wall of the common electrode layer is disposed on the top surface of the color filter pattern of the pixel structure. The third insulating layer is disposed on the common electrode layer and covers the inner sidewall of the common electrode layer, the inner sidewall of the second insulating layer and the inner sidewall of the color filter pattern, wherein multiple pixel electrodes of the multiple pixel structures are disposed on on the third insulating layer.

A method for manufacturing a pixel array substrate according to an embodiment of the present invention includes the following steps: providing a substrate, wherein the substrate has an active region; forming a plurality of active elements on the active region of the substrate; forming a first insulating material layer to cover the plurality of active Component; forming a plurality of color filter patterns on the first insulating material layer, wherein each color filter pattern has an opening that overlaps the active component, and each color filter pattern has a top surface facing away from the substrate and a bottom surface facing the substrate and an inner wall connected between the top surface and the bottom surface, and the inner wall defines an opening; forming a second insulating material layer on a plurality of color filter patterns; forming a common electrode layer on the second insulating material layer; using the common electrode layer Patterning the second insulating material layer for masking to form a second insulating layer, and patterning the first insulating material layer to form a first insulating layer, wherein the second insulating layer has a top of a color filter pattern disposed on the pixel structure on the inner sidewall of the surface; forming a third insulating layer on the common electrode layer to cover the inner sidewall of the common electrode layer, the second insulating layer and the inner sidewall of the color filter pattern; and forming a plurality of Pixel electrodes, wherein a plurality of pixel electrodes are electrically connected to the active element respectively.

In an embodiment of the present invention, the above-mentioned third insulating layer directly covers the inner side wall of the common electrode layer, the inner side wall of the second insulating layer and the inner side wall of the color filter pattern.

In an embodiment of the present invention, the inner wall of the common electrode layer and the inner wall of the second insulating layer are substantially aligned.

In an embodiment of the present invention, in the top view of the above-mentioned pixel array substrate, the common electrode layer and the second insulating layer substantially overlap.

In an embodiment of the present invention, the above-mentioned pixel array substrate further includes a common electrode line disposed on the peripheral area of the substrate. The plurality of pixel structures includes a corner pixel structure, which is arranged at the corner of the active area. The common electrode layer includes a main part and a first extension part. The main part of the common electrode layer overlaps the pixel electrode of the corner pixel structure. The first extension part of the common electrode layer is disposed in the peripheral area and is electrically connected to the common electrode line. The color filter pattern of the corner pixel structure includes a main part and a first extension part. The main part of the color filter pattern of the corner pixel structure overlaps the pixel electrode of the corner pixel structure, and the color filter pattern of the corner pixel structure The first extending portion of the pattern partially overlaps the first extending portion of the common electrode layer. The second insulating layer has a first extension portion that overlaps the first extension portion of the common electrode layer. The outer side walls of the first extension portion of the second insulating layer and the outer side walls of the first extension portion of the common electrode layer are disposed on the top surface of the first extension portion of the color filter pattern of the corner pixel structure. The third insulating layer covers the outer side wall of the first extension portion of the second insulating layer, the outer side wall of the first extension portion of the common electrode layer, and the outer side wall of the first extension portion of the color filter pattern of the corner pixel structure, wherein the corners The outer side wall of the first extended portion of the color filter pattern of the pixel structure is connected between the top surface and the bottom surface of the color filter pattern and is located on the peripheral area.

In an embodiment of the present invention, the above-mentioned third insulating layer directly covers the outer side wall of the first extension part of the common electrode layer, the outer side wall of the first extension part of the second insulating layer and the color filter of the corner pixel structure. The outer side wall of the first extension of the light pattern.

In an embodiment of the present invention, the outer side wall of the first extension portion of the common electrode layer is substantially flush with the outer side wall of the first extension portion of the second insulating layer.

In an embodiment of the present invention, in the top view of the above-mentioned pixel array substrate, the first extending portion of the common electrode layer substantially overlaps with the first extending portion of the second insulating layer.

In an embodiment of the present invention, the widths of the first extending portion of the common electrode layer and the first extending portion of the second insulating layer in the extending direction of the common electrode line are substantially equal.

In an embodiment of the present invention, the above-mentioned common electrode layer further includes a second extension portion, which is disposed in the peripheral area and extends outside the color filter pattern of the corner pixel structure; the second insulating layer further includes a second extension portion, The second extended portion of the common electrode layer is stacked with the second extended portion of the second insulating layer. And there is a height difference between it and part of the first insulating layer provided in the peripheral area.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numbers are used in the drawings and descriptions to refer to the same or similar parts.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element, or Intermediate elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein, "connected" may refer to a physical and/or electrical connection. Furthermore, "electrical connection" or "coupling" may mean the presence of other components between two components.

As used herein, "about," "approximately," or "substantially" includes the stated value and the average within an acceptable range of deviations from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the A specific amount of error associated with a measurement (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5%. Furthermore, the terms "about", "approximately" or "substantially" used herein may be used to select a more acceptable deviation range or standard deviation based on optical properties, etching properties or other properties, and one standard deviation may not apply to all properties. .

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed to have meanings consistent with their meanings in the context of the relevant technology and the present invention, and are not to be construed as idealistic or excessive Formal meaning, unless expressly defined as such herein.

1A to 1C are schematic cross-sectional views of a method for manufacturing a pixel array substrate according to an embodiment of the present invention.

Please refer to FIG. 1A. First, a substrate 110 is provided, wherein the substrate 110 has an active region 110a. For example, in this embodiment, the material of the substrate 110 may be glass. However, the present invention is not limited thereto. According to other embodiments, the material of the substrate 110 may also be quartz, organic polymer, or opaque/reflective material (such as wafer, ceramic, etc.), or other applicable materials. Material.

Next, the active element T is formed on the active region 110a of the substrate 110. For example, in this embodiment, the first metal layer 120, the gate insulating layer 130, the semiconductor layer 140 and the second metal layer 150 can be formed sequentially. The active element T includes a thin film transistor, and the first metal layer 120 can include The gate electrode 121 and the semiconductor layer 140 of the thin film transistor may include the semiconductor pattern 141 of the thin film transistor. The gate insulating layer 130 is at least disposed between the gate electrode 121 and the semiconductor pattern 141. The second metal layer 150 may include the source of the thin film transistor. The source electrode 151 and the drain electrode 152 are respectively electrically connected to two different areas of the semiconductor pattern 141, but the invention is not limited thereto.

Next, a first insulating material layer 160' is formed to cover the active element T. Next, a color filter pattern 170 is formed on the first insulating material layer 160'. The color filter pattern 170 has an opening 170a overlapping the active element T. The color filter pattern 170 has a top surface 170s1 facing away from the substrate 110, a bottom surface 170s2 facing the substrate 110, and an inner wall 170s3 connected between the top surface 170s1 and the bottom surface 170s2, and the inner wall 170s3 defines the opening 170a of the color filter pattern 170. .

Next, a second insulating material layer 180' is formed on the color filter pattern 170. The second insulating material layer 180' covers the top surface 170s1 of the color filter pattern 170, the inner side wall 170s3 of the color filter pattern 170, and the portion of the first insulating material layer 160' that overlaps the opening 170a of the color filter pattern 170.

Next, a common electrode layer 190 is formed on the second insulating material layer 180'. The common electrode layer 190 is disposed on the top surface 170s1 of the color filter pattern 170 and has an opening 190a. The opening 190a of the common electrode layer 190 overlaps the opening 170a of the color filter pattern 170. In this embodiment, the common electrode layer 190 is formed on the first transparent conductive layer, for example. The material of the first transparent conductive layer may include metal oxide, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, Al-zinc oxide, indium-germanium-zinc oxide, other suitable oxides, or a stacked layer of at least two of the above, but the invention is not limited thereto.

Referring to FIGS. 1A and 1B , then, the second insulating material layer 180 ′ is patterned using the common electrode layer 190 as a mask to form the second insulating layer 180 , and the first insulating material layer 160 ′ is patterned to form the first insulating layer. Layer 160. The second insulating layer 180 has an inner wall 180s3 disposed on the top surface 170s1 of the color filter pattern 170.

Specifically, in this embodiment, the first insulating layer 160 and the second insulating layer 180 are patterned simultaneously in the same etching process, in which the second insulating layer 180 uses the common electrode layer 190 as a hard mask. is patterned, therefore, the second insulating layer 180 will have an opening 180a that substantially coincides with the opening 190a of the common electrode layer 190, and the inner sidewall 190s3 of the common electrode layer 190 defines the opening 190a of the common electrode layer 190. The inner wall 180s3 of the layer 180 defines the opening 180a of the second insulating layer 180, and the inner wall 190s3 of the common electrode layer 190 is substantially flush with the inner wall 180s3 of the second insulating layer 180; on the other hand, the first insulating layer 160 is The color filter pattern 170 is patterned with the color filter pattern 170 as a hard mask. Therefore, the first insulating layer 160 will have an opening 160a that substantially coincides with the opening 170a of the color filter pattern 170. The inner side wall 160s3 of the first insulating layer 160 The opening 160a of the first insulating layer 160 is defined, the inner sidewall 170s3 of the color filter pattern 170 defines the opening 170a of the color filter pattern 170, and the inner sidewall 160s3 of the first insulating layer 160 and the inner sidewall 170s3 of the color filter pattern 170 are substantially Cut all the way up. The opening 160a of the first insulating layer 160, the opening 170a of the color filter pattern 170, the opening 180a of the second insulating layer 180 and the opening 190a of the common electrode layer 190 expose the drain 152 of the active element T.

Please refer to FIG. 1C . Next, a third insulating layer 200 is formed on the common electrode layer 190 to cover the common electrode layer 190 , the inner sidewall 180s3 of the second insulating layer 180 and the inner sidewall 170s3 of the color filter pattern 170 . The third insulating layer 200 has an opening 200a exposing the drain electrode 152 of the active element T.

Please refer to FIG. 1C. Next, a pixel electrode 211 is formed on the third insulating layer 200, where the pixel electrode 211 is electrically connected to the active element T. Specifically, in this embodiment, the pixel electrode 211 is filled in the opening 200a of the third insulating layer 200 and is electrically connected to the drain electrode 152 of the active element T. At this point, the pixel array substrate 100 of this embodiment is completed. In this embodiment, the pixel electrode 211 is formed on the second transparent conductive layer 210, for example. The material of the second transparent conductive layer 210 may include metal oxide, such as indium tin oxide, indium zinc oxide, aluminum tin oxide. oxide, aluminum zinc oxide, indium germanium zinc oxide, other suitable oxides, or a stacked layer of at least two of the above, but the invention is not limited thereto.

FIG. 2 is a schematic top view of a pixel array substrate according to an embodiment of the present invention. FIG. 2 schematically depicts the gate line GL, the transfer line gl and the substrate 110, while omitting other components of the pixel array substrate 100.

FIG. 3 is a partially enlarged schematic diagram of a pixel array substrate according to an embodiment of the present invention. FIG. 3 corresponds to part R1 of the pixel array substrate 100 in FIG. 1 . The local R1 system is located in the active region 110a. Figure 1C corresponds to the section line I-I' of Figure 3 . Figure 3 omits the color filter pattern 170 of Figure 1C.

Referring to FIG. 1C , FIG. 2 and FIG. 3 , the pixel array substrate 100 includes a base 110 . The substrate 110 has an active area 110a and a peripheral area 110b outside the active area 110a. The pixel array substrate 100 also includes a plurality of pixel structures PX, which are disposed in the active area 110a of the substrate 110. Each pixel structure PX includes an active element T, a pixel electrode 211 electrically connected to the active element T, and a color filter pattern 170 overlapping the pixel electrode 211 . The color filter pattern 170 has a top surface 170s1 facing away from the substrate 110, a bottom surface 170s2 facing the substrate 110, and an inner wall 170s3 connected between the top surface 170s1 and the bottom surface 170s2.

In this embodiment, the pixel array substrate 100 further includes a plurality of data lines DL arranged in the first direction x, where each data line DL is electrically connected to the source 151 of a corresponding active element T. In this embodiment, the pixel array substrate 100 further includes a plurality of gate lines GL arranged in the second direction y, where each gate line GL is electrically connected to the gate 121 of a corresponding active element T. In this embodiment, the pixel array substrate 100 further includes a plurality of transfer lines gl arranged in the first direction x and interspersed in the active area 110a, wherein each transfer line gl is associated with a corresponding gate line GL electrical connection.

Referring to FIG. 1C and FIG. 3 , the pixel array substrate 100 further includes a first insulating layer 160 disposed on the active element T of the pixel structure PX. The color filter pattern 170 of the pixel structure PX is disposed on the first insulating layer 160 . The pixel array substrate 100 further includes a second insulating layer 180 disposed on the color filter pattern 170, wherein the inner sidewall 180s3 of the second insulating layer 180 is disposed on the top surface 170s1 of the color filter pattern 170 of the pixel structure PX.

The pixel array substrate 100 further includes a common electrode layer 190 disposed on the second insulating layer 180, wherein the inner sidewall 190s3 of the common electrode layer 190 is disposed on the top surface 170s1 of the color filter pattern 170 of the pixel structure PX. The pixel array substrate 100 further includes a third insulating layer 200 disposed on the common electrode layer 190 . The pixel electrode 211 of the pixel structure PX is disposed on the third insulating layer 200.

It is worth noting that the third insulating layer 200 covers the inner sidewall 190s3 of the common electrode layer 190 disposed on the top surface 170s1, the inner sidewall 180s3 of the second insulating layer 180 disposed on the top surface 170s1, and the color filter pattern 170. Medial wall 170s3. That is to say, the second insulating layer 180 does not cover the entire color filter pattern 170 , and the inner sidewall 170s3 of the color filter pattern 170 that is not covered by the second insulating layer 180 is covered by the third insulating layer 200 .

Please refer to FIG. 1C . In this embodiment, the material of the first insulating layer 160 is an inorganic material, the material of the color filter pattern 170 is an organic material, the material of the second insulating layer 180 is an inorganic material, and the third insulating layer 200 The materials are organic materials. The first insulating layer 160, the color filter pattern 170, the second insulating layer 180 and the third insulating layer 200 form an inorganic/organic/inorganic/organic stack structure. Since the inner side wall 170s3 of the organic color filter pattern 170 is not covered by the inorganic second insulating layer 180 but is covered by the organic third insulating layer 200, the pixel array substrate 100 is less likely to suffer from internal stress. And/or the color filter pattern 170 contains cracks caused by gas exhaust.

Please refer to FIG. 1C and FIG. 3 . In this embodiment, the third insulating layer 200 directly covers the inner sidewall 190s3 of the common electrode layer 190 , the inner sidewall 180s3 of the second insulating layer 180 and the inner sidewall 170s3 of the color filter pattern 170 . That is to say, the third insulating layer 200 is in contact with the inner sidewall 190s3 of the common electrode layer 190, the inner sidewall 180s3 of the second insulating layer 180, and the inner sidewall 170s3 of the color filter pattern 170.

In this embodiment, since the second insulating layer 180 is patterned using the common electrode layer 190 as a hard mask, the inner sidewall 190s3 of the common electrode layer 190 will be substantially in contact with the inner sidewall 180s3 of the second insulating layer 180. Cut all the way up. In a top view of the pixel array substrate 100, the common electrode layer 190 and the second insulating layer 180 substantially overlap.

FIG. 4 is a partially enlarged schematic diagram of a pixel array substrate according to an embodiment of the present invention. FIG. 4 corresponds to part R2 of the pixel array substrate 100 of FIG. 1 .

FIG. 5 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the present invention. Figure 5 corresponds to the section line II-II' of Figure 4.

FIG. 6 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the present invention. Figure 6 corresponds to the section line III-III' of Figure 4.

FIG. 7 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the present invention. Figure 7 corresponds to the section line IV-IV' of Figure 4 .

FIG. 4 omits the color filter pattern 170 of FIG. 5 , FIG. 6 and FIG. 7 .

Please refer to FIG. 4. In this embodiment, the pixel array substrate 100 further includes a common electrode line CL disposed on the peripheral area 110b. The common electrode line CL extends in the first direction x. The extending direction of the common electrode line CL is the first direction x. Please refer to FIG. 1C and FIG. 4 . For example, in this embodiment, the common electrode line CL and the gate line GL and/or the gate 121 of the active element T are formed on the same first metal layer 120 . However, the present invention does not This is the limit.

Referring to FIG. 2 and FIG. 4 , the plurality of pixel structures PX of the pixel array substrate 100 includes a corner pixel structure PXc, which is disposed at the corner of the active area 110 a. Please refer to Figures 4, 5, 6 and 7. In this embodiment, the common electrode layer 190 includes a main part 191 and a first extension part 192. The main part 191 of the common electrode layer 190 and the corner pixel structure PXc The pixel electrodes 211 overlap, and the first extending portion 192 of the common electrode layer 190 is disposed in the peripheral area 110b and is electrically connected to the common electrode line CL.

Please refer to FIG. 4. Specifically, in this embodiment, the first extending portion 192 of the common electrode layer 190 extends upward from the active area 110a toward the common electrode line CL. The pixel array substrate 100 further includes a connection pattern 212. In the top view of the pixel array substrate 100, the connection pattern 212 overlaps the first extending portion 192 of the common electrode layer 190 and the common electrode line CL and is disposed between the first extending portion 192 of the common electrode layer 190 and the common electrode line CL. The first extending portion 192 of the common electrode layer 190 is electrically connected to the common electrode line CL through the connection pattern 212 . For example, in this embodiment, the connection pattern 212 and the pixel electrode 211 belong to the second transparent conductive layer 210, but the invention is not limited thereto.

Please refer to Figures 4, 5, 6 and 7. In this embodiment, the color filter pattern 170 of the corner pixel structure PXc includes a main part 171 and a first extension part 172. The color filter pattern 170 of the corner pixel structure PXc The main part 171 of the light pattern 170 overlaps the pixel electrode 211 of the corner pixel structure PXc, and the first extension part 172 of the color filter pattern 170 of the corner pixel structure PXc partially overlaps the first extension of the common electrode layer 190 Department 192. The second insulation layer 180 has a main portion 181 and a first extension portion 182 . The main portion 181 of the second insulating layer 180 overlaps the main portion 191 of the common electrode layer 190 . The first extending portion 182 of the second insulating layer 180 overlaps the first extending portion 192 of the common electrode layer 190 . The main portion 181 of the second insulating layer 180 substantially overlaps the main portion 191 of the common electrode layer 190 . The first extending portion 182 of the second insulating layer 180 substantially overlaps the first extending portion 192 of the common electrode layer 190 .

4, 5 and 6, the outer side wall 180s4 of the first extension portion 182 of the second insulating layer 180 and the outer side wall 190s4 of the first extension portion 192 of the common electrode layer 190 are disposed on the color of the corner pixel structure PXc. On the top surface 170s1 of the first extending portion 172 of the filter pattern 170. The third insulating layer 200 covers the outer sidewall 180s4 of the first extending portion 182 of the second insulating layer 180, the outer sidewall 190s4 of the first extending portion 192 of the common electrode layer 190, and the third insulating layer of the color filter pattern 170 of the corner pixel structure PXc. The outer side wall 170s4 of an extension portion 172, wherein the outer side wall 170s4 of the first extension portion 172 of the color filter pattern 170 of the corner pixel structure PXc is connected between the top surface 170s1 and the bottom surface 170s2 of the color filter pattern 170 and is located at the periphery Area 110b.

In this embodiment, the third insulating layer 200 directly covers the outer sidewall 180s4 of the first extension portion 182 of the second insulating layer 180, the outer sidewall 190s4 of the first extension portion 192 of the common electrode layer 190, and the corner pixel structure PXc The outer side wall 170s4 of the first extending portion 172 of the color filter pattern 170.

Please refer to FIG. 4 and FIG. 6 . In this embodiment, the outer side wall 190s4 of the first extension portion 192 of the common electrode layer 190 is substantially flush with the outer side wall 180s4 of the first extension portion 182 of the second insulation layer 180 . In this embodiment, the widths W182 and W192 of the first extending portion 192 of the common electrode layer 190 and the first extending portion 182 of the second insulating layer 182 in the extending direction of the common electrode line CL (ie, the first direction x) Substantially equal. Please refer to FIG. 4 . In this embodiment, in the top view of the pixel array substrate 100 , the first extending portion 192 of the common electrode layer 190 and the first extending portion 182 of the second insulating layer 180 substantially overlap.

Please refer to FIG. 4 and FIG. 7 . In this embodiment, the common electrode layer 190 further includes a second extension part 193 , which is provided in the peripheral area 110 b and extends outside the color filter pattern 170 of the corner pixel structure PXc. The second insulating layer 180 further includes a second extension portion 183 disposed in the peripheral area 110b, extending outside the color filter pattern 170 of the corner pixel structure PXc, and overlapping the second extension portion 193 of the common electrode layer 190. The second extending portion 193 of the common electrode layer 190 substantially overlaps the second extending portion 183 of the second insulating layer 180 . The second extended portion 193 of the common electrode layer 190 is stacked with the second extended portion 183 of the second insulating layer 180 and has a height difference ΔH with the portion of the first insulating layer 160 disposed in the peripheral region 110b.

100: Pixel array substrate 110: Base 110a: Active area 110b: Surrounding area 120: First metal layer 121: Gate 130: Gate insulation layer 140: Semiconductor layer 141:Semiconductor pattern 150: Second metal layer 151:Source 152:Jiji 160: First insulation layer 160’: first insulating material layer 160a, 170a, 180a, 190a, 200a: opening 160s3, 170s3, 180s3, 190s3: inner wall 170: Color filter pattern 170s1:Top surface 170s2: Bottom 170s4, 180s4, 190s4: outer wall 180: Second insulation layer 180’: Second layer of insulating material 171, 181, 191: Main Department 172, 182, 192: First extension 183, 193: Second extension 190: Common electrode layer 200:Third insulation layer 210: Second transparent conductive layer 211: Pixel electrode 212:Connection pattern CL: Common electrode line DL: data line GL: gate line gl: adapter cable PX: pixel structure PXc: corner pixel structure R1, R2: local T: active component W182, W192: Width x: first direction y: second direction І-І’, II-II’, III-III’, IV-IV’: section line ΔH: height difference

1A to 1C are schematic cross-sectional views of a method for manufacturing a pixel array substrate according to an embodiment of the present invention. FIG. 2 is a schematic top view of a pixel array substrate according to an embodiment of the present invention. FIG. 3 is a partially enlarged schematic diagram of a pixel array substrate according to an embodiment of the present invention. FIG. 4 is a partially enlarged schematic diagram of a pixel array substrate according to an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the present invention. FIG. 7 is a schematic cross-sectional view of a pixel array substrate according to an embodiment of the present invention.

100: Pixel array substrate

110: Base

110a: Active area

120: First metal layer

121: Gate

130: Gate insulation layer

140: Semiconductor layer

141:Semiconductor pattern

150: Second metal layer

151:Source

152:Jiji

160: First insulation layer

160a, 170a, 180a, 190a, 200a: opening

160s3, 170s3, 180s3, 190s3: inner wall

170: Color filter pattern

170s1:Top surface

170s2: Bottom

180: Second insulation layer

190: Common electrode layer

200:Third insulation layer

210: Second transparent conductive layer

211: Pixel electrode

PX: pixel structure

T: active component

I-I’: section line

Claims (11)

A pixel array substrate includes: a substrate having an active area and a peripheral area outside the active area; a plurality of pixel structures disposed in the active area of the substrate, wherein each pixel structure includes an active element, A pixel electrode electrically connected to the active element and a color filter pattern overlapping the pixel electrode. The color filter pattern has a top surface facing away from the substrate, a bottom surface facing the substrate and connected to An inner wall between the top surface and the bottom surface, and the material of the color filter pattern is an organic material; a first insulating layer is provided on a plurality of active components of the pixel structures, wherein the pixels A plurality of color filter patterns of the structure are disposed on the first insulating layer; a second insulating layer is disposed on the color filter patterns, wherein an inner wall of the second insulating layer is disposed on a pixel structure On the top surface of the color filter pattern; a common electrode layer is disposed on the second insulating layer, wherein an inner wall of the common electrode layer is disposed on the top surface of the color filter pattern of the pixel structure on; and a third insulating layer disposed on the common electrode layer and covering the inner wall of the common electrode layer, the inner wall of the second insulating layer and the inner wall of the color filter pattern, wherein the A plurality of pixel electrodes of some pixel structures are disposed on the third insulating layer, and the material of the third insulating layer is an organic material. The pixel array substrate of claim 1, wherein the third insulating layer directly covers the inner sidewall of the common electrode layer, the inner sidewall of the second insulating layer and the inner sidewall of the color filter pattern. The pixel array substrate of claim 1, wherein the inner wall of the common electrode layer is substantially flush with the inner wall of the second insulating layer. The pixel array substrate of claim 1, wherein in a top view of the pixel array substrate, the common electrode layer and the second insulating layer substantially overlap. The pixel array substrate as claimed in claim 1, further comprising: a common electrode line disposed on the peripheral area of the substrate; wherein the pixel structures include a corner pixel structure disposed on the active area A corner; the common electrode layer includes a main part and a first extension part, the main part of the common electrode layer overlaps the pixel electrode of the corner pixel structure, and the first extension part of the common electrode layer is provided in the peripheral area and electrically connected to the common electrode line; the color filter pattern of the corner pixel structure includes a main part and a first extension part, and the main part of the color filter pattern of the corner pixel structure partially overlaps the pixel electrode of the corner pixel structure, and the first extending portion of the color filter pattern of the corner pixel structure partially overlaps the first extending portion of the common electrode layer; the second The insulating layer has a first extension portion that overlaps the first extension portion of the common electrode layer; An outer side wall of the first extension portion of the second insulating layer and an outer side wall of the first extension portion of the common electrode layer are disposed on the first extension portion of the color filter pattern of the corner pixel structure. On the top surface; the third insulating layer covers the outer side wall of the first extension part of the second insulating layer, the outer side wall of the first extension part of the common electrode layer and the color of the corner pixel structure An outer side wall of the first extension portion of the color filter pattern, wherein the outer side wall of the first extension portion of the color filter pattern of the corner pixel structure is connected to the top surface and the bottom surface of the color filter pattern between and on the surrounding area. The pixel array substrate of claim 5, wherein the third insulating layer directly covers the outer side wall of the first extending portion of the common electrode layer and the outer side of the first extending portion of the second insulating layer. wall and the outer side wall of the first extension portion of the color filter pattern of the corner pixel structure. The pixel array substrate of claim 5, wherein the outer side wall of the first extension portion of the common electrode layer is substantially flush with the outer side wall of the first extension portion of the second insulating layer. The pixel array substrate of claim 5, wherein in a top view of the pixel array substrate, the first extending portion of the common electrode layer substantially overlaps the first extending portion of the second insulating layer. The pixel array substrate of claim 5, wherein the widths of the first extending portion of the common electrode layer and the first extending portion of the second insulating layer in an extending direction of the common electrode line are substantially equal. . The pixel array substrate of claim 5, wherein the common electrode layer further includes a second extension portion disposed in the peripheral area and extending outside the color filter pattern of the corner pixel structure; the second insulation The layer further includes a second extension portion disposed in the peripheral area, extending outside the color filter pattern of the corner pixel structure, and overlapping the second extension portion of the common electrode layer; the second extension portion of the common electrode layer The second extending portion is stacked with the second extending portion of the second insulating layer and has a height difference with the portion of the first insulating layer disposed in the peripheral region. A method of manufacturing a pixel array substrate, including: providing a substrate, wherein the substrate has an active area; forming a plurality of active elements on an active area of the substrate; forming a first insulating material layer to cover the active areas Component; forming a plurality of color filter patterns on the first insulating material layer, wherein the material of the color filter patterns is an organic material, each color filter pattern has an opening overlapping one of the active components, each The color filter pattern has a top surface facing away from the base, a bottom surface facing the base, and an inner wall connected between the top surface and the bottom surface, and the inner wall defines the opening; in the color filters forming a second insulating material layer on the light pattern; forming a common electrode layer on the second insulating material layer; patterning the second insulating material layer using the common electrode layer as a mask to form a second insulating layer, and Patterning the first insulating material layer to form a first insulating layer, wherein the second insulating layer has an inner wall disposed on the top surface of the color filter pattern of a pixel structure; A third insulating layer is formed on the common electrode layer to cover the common electrode layer, the inner sidewall of the second insulating layer and the inner sidewall of the color filter pattern, wherein the material of the third insulating layer is organic material; and forming a plurality of pixel electrodes on the third insulating layer, wherein the pixel electrodes are electrically connected to the active element respectively.