TWI813273B - Resistive memory device and forming method thereof - Google Patents

Abstract

A resistive memory device includes a plurality of word lines, a plurality of first memory cells, a plurality of second memory cells, a plurality of bit lines, a plurality of source lines, and a driver. The first memory cells and the second memory cells are coupled to the word lines, the bit lines, and the source lines. The driver is configured to provide a forming voltage to the first memory cells and the second memory cells through the bit lines and the source lines in a forming process. A first connection length along the bit lines and the source lines between the first memory cells and the driver is longer than a second connection length along the bit lines and the source lines between the second memory cells and the driver, and the forming process is performed to the first memory cells before the forming process is performed to the second memory cells. During the forming process, a first value of the forming voltage provided to the first memory cells is less than a second value of the forming voltage provided to the second memory cells.

Description

Resistive memory device and method of forming the same

The embodiments described in this disclosure relate to memory technology, and particularly to a resistive memory device and a forming method thereof that can improve forming time and uniformity.

With the development of technology, various memories have been developed. Variable resistive memory is a non-volatile memory and has the advantages of large storage capacity and fast access speed. The variable resistive memory needs to execute a forming process in advance to initialize it. After being programmed, the variable resistive memory can operate between a set state and a reset state to store corresponding values (eg, logic values 1 and 0).

Some embodiments of the present disclosure relate to a resistive memory device. The resistive memory device includes a plurality of digital element lines, a plurality of first memory cells, a plurality of second memory cells, a plurality of bit lines, a plurality of source lines and a driver. The first memory cells are coupled to the word lines. The second memory cells are coupled to the word lines. The bit lines are coupled to the first memories unit and the second memory units. The source lines are coupled to the first memory cells and the second memory cells. The driver is used to provide a forming voltage to the first memory cells and the second memory cells through the bit lines and the source lines in a forming process. The formation program is executed on the first memory units and the second memory units. A first connection distance between the first memory cells and the driver along the bit lines and the source lines is longer than a first connection distance between the second memory cells and the driver along the bit lines and the A second connection distance of the source line, and the first memory cells are formed earlier than the second memory cells. In the forming process, a first value of the forming voltage provided to the first memory cells is less than a second value of the forming voltage provided to the second memory cells.

Some embodiments of the present disclosure relate to a method of forming a resistive memory device. The method of forming a resistive memory device includes: setting a forming voltage, and providing the forming voltage to a plurality of first memory cells in the resistive memory device and a plurality of second memory cells in the resistive memory device, wherein the first A first connection distance between the memory unit and a driver along the bit lines and the source lines is longer than a first connection distance between the second memory cells and the driver along the bit lines and the source lines. the second connection distance; performing a forming process on the first memory cells according to the forming voltage; and after the forming process is performed on the first memory cells, performing a forming process on the second memory cells according to the forming voltage. A first value of the formation voltage provided to the first memory cells is less than a second value of the formation voltage provided to the second memory cells.

In summary, in the present disclosure, the formation time and formation uniformity of resistive memory devices can be improved.

100: Resistive memory device

302,304:Electrode

306:Insulation layer

308: Low resistance conductive path

310: High resistance conductive path

400: Formation method

MC, MC0, MC1: memory unit

BL0-BL63: bit lines

WL0-WL2047: character line

SL0-SL63: source line

WDVH-WDVL: driver

YMUX0-YMUX43,YMUXR0-YMUXR43: multiplexer

XDE: decoder

READ0-READ43: read circuit

BUF: page buffer

VH_F: bit line voltage

VL_F: source line voltage

Icmp: limit current

A1,A2,A3,A4: area

M: transistor

R: Resistive memory

S402, S404, S406, S408, S410, S412, S414, S416, S418, S420, S422: Operation

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying drawings are described as follows: Figure 1 is a resistive memory device according to some embodiments of the present disclosure. Figure 2 is a schematic diagram of a memory unit according to some embodiments of the present disclosure; Figure 3 is a schematic diagram of the operation of a resistive memory according to some embodiments of the present disclosure; Figure 4 is a flow chart of a forming method according to some embodiments of the present disclosure; and Figure 5 is a flow chart of a bit line voltage value, a source line voltage value in different areas according to some embodiments of the present disclosure, and Limit current value.

The term "coupling" used in this article may also refer to "electrical coupling", and the term "connection" may also refer to "electrical connection". "Coupling" and "connection" can also refer to the cooperation or interaction of two or more components with each other.

Refer to Figure 1. FIG. 1 is a schematic diagram of a resistive memory device 100 according to some embodiments of the present disclosure.

Taking the example in Figure 1 as an example, the resistive memory device 100 includes a plurality of memory cells MC, a plurality of bit lines BL0-BL63, a plurality of bit lines WL0-WL2047, a plurality of source lines SL0-SL63, and a plurality of drivers WDVH-WDVL. , complex multiplexers YMUX0-YMUX43, decoder XDE, complex multiplexers YMUXR0-YMUXR43, complex read circuits READ0-READ43 and page buffer BUF. Drivers WDVH-WDVL can be implemented using Application Specific Integrated Circuits (ASICs), which include multiplexers, voltage sources, current sources or other electronic components (such as transistors, resistors, capacitors, amplifiers, etc.) .

The memory unit MC is configured in an array type. The bit lines BL0-BL63, the word lines WL0-WL2047 and the source lines SL0-SL63 are coupled to the memory cell MC. One of the drivers WDVH and one of the drivers WDVL are respectively coupled to one of the multiplexers YMUX0-YMUX43. For example, the drivers WDVH and WDVL in Figure 1 are coupled to the multiplexer YMUX0, and the multiplexer YMUX0 is coupled to the bit lines BL0-BL63 and the source lines SL0-SL63. The driver WDVH and the driver WDVL are used to provide a forming voltage in a forming process of the memory cell MC. Specifically, the forming voltage includes bit line voltage VH_F and source line voltage VL_F. For example, the driver WDVH is used to receive the bit line voltage VH_F and provide the bit line voltage VH_F to the memory cell MC through the multiplexer YMUX0 and the bit lines BL0-BL63. The driver WDVL is used to receive the source line voltage VL_F and pass the source line voltage VL_F through the multiplexer YMUX0 and the source Polar lines SL0-SL63 are provided to memory cells MC. The driver WDVL is further used to receive the limiting current Icmp and provide the limiting current Icmp to the memory unit MC through the multiplexer YMUX0. In other words, the multiplexer YMUX0 can connect the driver WDVH and the driver WDVL to a specified memory cell MC according to a specified address to provide the bit line voltage VH_F, the source line voltage VL_F and the limiting current Icmp to the The designated memory unit MC. Since other multiplexers have similar structures and similar operations, other multiplexers are omitted in Figure 1 and the description. Decoder XDE is coupled to word lines WL0-WL2047. Multiplexers YMUXR0-YMUXR43 are coupled to bit lines BL0-BL63. The read circuits READ0-READ43 are respectively coupled to the multiplexers YMUXR0-YMUXR43, and the read circuits READ0-READ43 are coupled to the page buffer BUF.

Taking the example in Figure 1 as an example, based on the connection distance between the memory cell MC and the driver WDVH (WDVL) along the bit lines and the source lines, the memory cell MC can be divided into four areas A1- A4. The memory cell MC located in area A1 is connected to the word lines between word line WL2047 and word line WL1535, and the memory cell MC located in area A2 is connected to the word lines between word line WL1535 and word line WL1023. Of these word lines, the memory cell MC located in area A3 is connected to the word lines between word line WL1023 and word line WL511, and the memory cell MC located in area A4 is connected to word lines WL511 and WL511. The word lines between word lines WL0.

Accordingly, the connection distance between the memory cell MC and the driver WDVH (WDVL) in the area A1 is longer than the connection distance between the memory cell MC and the driver WDVH (WDVL) in the area A2. The connection distance between the memory cell MC and the driver WDVH (WDVL) in the area A2 is longer than the connection distance between the memory cell MC and the driver WDVH (WDVL) in the area A3. The connection distance between the memory cell MC and the driver WDVH (WDVL) in the area A3 is longer than the connection distance between the memory cell MC and the driver WDVH (WDVL) in the area A4. In other words, the memory cell MC in area A1 is located at the farthest end of the bit lines/source lines from the driver WDVH (WDVL), and the memory cell MC in area A4 is located at the farthest end of the bit lines/source lines. The line is closest to the driver WDVH (WDVL), so the memory cell MC in area A1 will experience the largest voltage drop along the bit lines/source lines.

The number of the regions (for example, 4) in Figure 1 is only used as an example, but the present disclosure is not limited thereto. Various suitable region numbers are within the scope of this disclosure.

Refer to Figure 2. Figure 2 is a schematic diagram of a memory cell MC according to some embodiments of the present disclosure.

Taking the example in Figure 2 as an example, the memory cell MC includes a resistive memory R and a transistor M. The resistive memory R is, for example, a variable resistive memory (resistive random-access memory, ReRAM). The first end of the resistive memory R is coupled to the bit line BL0, and the resistive memory The second terminal of the body R is coupled to the first terminal of the transistor M. The second terminal of the transistor M is coupled to the source line SL0, and the control terminal of the transistor M is coupled to the word line WL0.

Refer to Figure 3. FIG. 3 is a schematic diagram of the operation of the resistive memory R in FIG. 2 according to some embodiments of the present disclosure.

Taking the example of Figure 3 as an example, the resistive memory R includes electrodes 302, electrodes 304 and an insulating layer 306. Insulating layer 306 is located between electrode 302 and electrode 304 .

When the resistive memory R is manufactured, the resistive memory R is in its original state. Appropriate voltages need to be applied to the electrodes 302 and 304 to perform a forming process on the resistive memory R so that the resistive memory R can be written or read. After the formation process, the low-resistance conductive path 308 is formed and the resistive memory R is in a set state (low-resistance state). By applying a reset voltage between electrode 302 and electrode 304, a high-resistance conductive path 310 is formed and the resistive memory R is in a reset state (high-resistance state). By applying a set voltage between electrode 302 and electrode 304, the low resistance conductive path 308 is formed again and the resistive memory R is in the set state (low resistance state) again. The set state (low resistance state) and the reset state (high resistance state) can be used to store logic values 1 and 0 respectively.

In the present disclosure, the formation sequence (ie, the sequence of the above-mentioned formation procedures) is from a position farther from the drivers WDVH-WDVL to a position closer to the drivers WDVH-WDVL. For example, the formation order is the memory unit MC in the area A1, the memory unit MC in the area A2, the memory unit MC in the area A3, and the memory unit MC in the area A4. Change In other words, the memory unit MC in area A1 is executed to form a program earlier than the memory unit MC in area A2, the memory unit MC in area A2 is executed to form a program earlier than the memory unit MC in area A3, and in area A3 The memory unit MC is executed earlier than the memory unit MC in area A4 to form the program.

Details about the formation process will be described in the following paragraphs with Figure 4.

Refer to Figure 4. FIG. 4 is a flowchart of a forming method 400 according to some embodiments of the present disclosure. In some embodiments, the formation method 400 is applied to the resistive memory device 100 in FIG. 1 . Taking the example of FIG. 4 as an example, the forming method 400 includes operations S402, S404, S406, S408, S410, S412, S414, S416, S418, and S420.

In operation S402, the bit line voltage VH_F, the source line voltage VL_F and the limiting current Icmp have preset values, and the values of the bit line voltage VH_F, the source line voltage VL_F and the limiting current Icmp are determined according to the area. A1-A4 settings. The limiting current Icmp is used to limit the resistance value of the memory cell MC to a resistance value range, so that the memory cell MC can change between the set state and the reset state. In addition, the retry value RETRY is set to the initial value (for example: 0).

Refer to Figure 5. FIG. 5 illustrates the values of the bit line voltage VH_F, the source line voltage VL_F and the limiting current Icmp for the memory cells MC in different areas A1 - A4 according to some embodiments of the present disclosure.

Taking the example of Figure 5 as an example, the first value of the bit line voltage VH_F provided to the memory cell MC in area A1 (for example: 3 volts plus 0 volts) is less than the bit line voltage VH_F provided to the memory cell MC in area A2. second value (for example: 3 volts plus 0.1 volts). The second value of the bit line voltage VH_F provided to the memory cell MC in area A2 (for example: 3 volts plus 0.1 volts) is less than the third value of the bit line voltage VH_F provided to the memory cell MC in area A3 (for example: 3 volts plus 0.2 volts). The third value of the bit line voltage VH_F provided to the memory cell MC in area A3 (for example: 3 volts plus 0.2 volts) is equal to the fourth value of the bit line voltage VH_F provided to the memory cell MC in area A4 (for example: 3 volts plus 0.2 volts). In some other embodiments, the third value (for example: 3 volts plus 0.2 volts) of the bit line voltage VH_F provided to the memory cell MC in the area A3 is less than the bit line voltage VH_F provided to the memory cell MC in the area A4 Fourth value. Accordingly, the first value (for example: 3 volts plus 0 volts) of the bit line voltage VH_F provided to the memory cell MC in the area A1 is the minimum.

In addition, the first value of the source line voltage VL_F provided to the memory cell MC in the area A1 (for example: 2.5 volts plus 0 volts) is less than the second value of the source line voltage VL_F provided to the memory cell MC in the area A2 (for example: 2.5 volts plus 0.1 volts). The second value of the source line voltage VL_F provided to the memory cell MC in area A2 (for example: 2.5 volts plus 0.1 volts) is less than the third value of the source line voltage VL_F provided to the memory cell MC in area A3 (for example: 2.5 volts plus 0.1 volts). 0.2 volts). The third value of the source line voltage VL_F provided to the memory cell MC in area A3 (for example: 2.5 volts plus 0.2 volts) is equal to the source line voltage provided to the memory cell MC in area A4. Press the fourth value of VL_F (for example: 2.5 volts plus 0.2 volts). In some other embodiments, the third value of the source line voltage VL_F provided to the memory cell MC in area A3 (for example: 2.5 volts plus 0.2 volts) is less than the source line voltage VL_F provided to the memory cell MC in area A4. Fourth value. Accordingly, the first value (for example: 2.5 volts plus 0 volts) of the source line voltage VL_F provided to the memory cell MC in the area A1 is the minimum.

Furthermore, the first value of the limiting current Icmp provided to the memory cell MC in the area A1 (for example: 125 microamps plus 0 microamps) is smaller than the second value of the limiting current Icmp provided to the memory cell MC in the area A2 (for example: 125 microamps plus 25 microamps). The second value of the limiting current Icmp provided to the memory cell MC in area A2 (for example: 125 microamps plus 25 microamps) is less than the third value of the limiting current Icmp provided to the memory cell MC in area A3 (for example: 125 microamps) plus 50 microamps). The third value of the limiting current Icmp provided to the memory cell MC in area A3 (for example: 125 microamps plus 50 microamps) is less than the fourth value of the limiting current Icmp provided to the memory cell MC in area A4 (for example: 125 microamps) plus 75 microamps). Accordingly, the first value of the limiting current Icmp (for example: 125 microamps plus 0 microamps) provided to the memory cell MC in the area A1 is minimum.

In operation S404, a first forming step is performed. Specifically, when the decoder XDE provides a gate voltage (for example: 2.5 volts) to a corresponding word line (ie, to the control end of the target transistor M in the target memory cell MC), the driver WDVH provides the bit line voltage VH_F to a target memory cell MC corresponding to a target address. As mentioned before, the order of formation is from the position farther away from the drivers WDVH-WDVL to the position closer. therefore, The target memory unit MC may be, for example, the memory unit MC0 in the area A1, and the target address may be, for example, the address of the memory unit MC0. Decoder XDE provides gate voltage (for example: 2.5 volts) to word line WL2047. In addition, since the target address belongs to the area A1, the driver WDVH provides the bit line voltage VH_F with the first value (for example: 3 volts plus 0 volts) to the bit line BL0, so the resistive memory R in the target memory cell MC0 One end receives the bit line voltage VH_F having a first value. Additionally, driver WDVL provides 0 volts to source line SL0, so the second terminal of resistive memory R in target memory cell MC0 receives 0 volts. In this way, a high-resistance pulse (HR pulse) forming process is executed on the target memory cell MC0.

In operation S406, a second forming step is performed. Specifically, when the decoder XDE provides a gate voltage (for example: 3 volts) to the corresponding word line (ie, to the control end of the target transistor M in the target memory cell MC), the driver WDVL provides the source line voltage VL_F to the source lines and limiting current Icmp to the target memory cell MC corresponding to at least one target address. As mentioned above, the target memory unit MC is, for example, the memory unit MC0. Accordingly, the decoder XDE provides the gate voltage (for example: 3 volts) to the word line WL2047. In addition, since the target address belongs to area A1, the driver WDVH provides 0 volts to the target bit line, and the driver WDVL provides the source line voltage VL_F with a first value (eg, 2.5 volts plus 0 volts) and a source line voltage VL_F with a first value (eg, 2.5 volts plus 0 volts). : 125 microamps plus 0 microamps) limit current Icmp to the target memory cell MC0. Accordingly, the first terminal of the resistive memory R in the target memory cell MC receives 0 volts, and the second terminal of the transistor M Source line voltage VL_F is received having a first value (eg: 2.5 volts plus 0 volts). In this way, a low-resistance pulse (LR pulse) forming process is executed on the target memory cell MC0.

In operation S408, the verification program is executed on the target memory cell MC corresponding to the target address, and the retry value RETRY is increased by 1. For example, the decoder XDE can provide a gate voltage (for example: 1.2 volts) to the target memory cell MC0 through the word line WL2047, and the driver WDVH can provide a read voltage (for example: 0.5 volts) to the target memory cell through the bit line BL0 MC0, and the driver WDVL provides 0V to the target memory cell MC0 through the source line SL0. Then, the read circuit READ0 can receive the read current Icell from the target memory cell MC0 through the multiplexer YMUXR0.

In operation S410, it is determined whether the read current Icell is greater than the threshold current Ith. As described in operation S408, the read circuit READ0 may receive the read current Icell from the target memory cell MC. When the read current Icell is greater than the threshold current Ith (that is, the determination result of operation S410 is "Yes"), it means that the formation process executed on the target memory cell MC is successful and operation S412 is entered. When the read current Icell is equal to or less than the threshold current Ith (ie, the determination result of operation S410 is "No"), it means that the formation process executed in the target memory cell MC fails and operation S416 is entered.

In operation S412, it is determined whether the target address is the final address. When the target address is the final address (that is, the determination result of operation S412 is "yes"), the forming method 400 ends. When the target address is not the final address (that is, the determination result of operation S412 is "No"), operation S414 is entered.

In operation S414, the target address is changed and the retry value RETRY is reset to an initial value (for example: 0). For example, the target address is changed to the new target address of the next memory cell (for example, memory cell MC1 in Figure 1) and the retry value RETRY is reset to 0. Then, operations S404, S406 and S408 are performed again. Specifically, the decoder XDE provides the aforementioned gate voltage to the word line corresponding to the new target address, and provides the bit line voltage VH_F with the corresponding value and the source with the corresponding value based on the area to which the new target address belongs. The pole line voltage VL_F and the limiting current Icmp with corresponding values are sent to the next memory cell MC corresponding to the new target address. When the new target address still belongs to the area A1, the driver WDVH provides the bit line voltage VH_F with the first value (for example: 3 volts plus 0 volts) to the target memory cell MC, and the driver WDVL provides the bit line voltage VH_F with the first value (for example: 2.5 volts plus 0 volts) source line voltage VL_F and a limiting current Icmp having a first value (for example: 125 microamps plus 0 microamps) to the target memory cell MC. When the new target address belongs to the area A2, the driver WDVH provides the bit line voltage VH_F with the second value (for example: 3 volts plus 0.1 volts) to the target memory cell MC, and the driver WDVL provides the bit line voltage VH_F with the second value (for example: 2.5 volts plus 0.1 volt) source line voltage VL_F and a limit current Icmp having a second value (for example: 125 microamps plus 25 microamps) to the target memory cell MC. When the new target address belongs to area A3, the driver WDVH provides the bit line voltage VH_F with the third value (for example: 3 volts plus 0.2 volts) to the target memory cell MC, and the driver WDVL provides the bit line voltage VH_F with the third value (for example: 2.5 volts plus 0.2 volts) source line voltage VL_F and a limit with a third value (for example: 125 microamps plus 50 microamps) Control the current Icmp to the target memory cell MC. When the new target address belongs to area A4, the driver WDVH provides the bit line voltage VH_F with the fourth value (for example: 3 volts plus 0.2 volts) to the target memory cell MC, and the driver WDVL provides the bit line voltage VH_F with the fourth value (for example: 2.5 volts plus 0.2 volts) source line voltage VL_F and a limiting current Icmp having a fourth value (for example: 125 microamps plus 75 microamps) to the target memory cell MC.

In operation S416, it is determined whether the retry value RETRY is equal to the maximum retry value Rth (for example: 3). If the current retry value RETRY is less than the maximum retry value Rth (that is, the judgment result of operation S416 is "No"), operations S404, S406 and S408 are entered again. In other words, the bit line voltage VH_F with the original value, the source line voltage VL_F with the original value and the limiting current Icmp with the original value will be provided to the original target memory cell MC again. When the retry value RETRY is equal to the maximum retry value Rth (that is, the determination result of operation S416 is "yes"), operation S418 is entered.

In operation S418, it is determined whether the current value of the bit line voltage VH_F is equal to the maximum bit line voltage value VHmax (for example: 3.2 volts). If the current value of the bit line voltage VH_F is less than the maximum bit line voltage value VHmax (that is, the determination result of operation S418 is "No"), operation S420 is entered. When the current value of the bit line voltage VH_F is equal to the maximum bit line voltage value VHmax (that is, the determination result of operation S418 is "yes"), operation S422 is entered.

In operation S420, when the current value of the bit line voltage VH_F is less than the maximum bit line voltage value VHmax, the value of the bit line voltage VH_F is increased and the retry value RETRY is reset to an initial value (eg, 0). Then, enter Operation S404 is entered and the bit line voltage VH_F with the increased value is provided to the original target memory cell MC.

In operation S422, when the current value of the bit line voltage VH_F is equal to the maximum bit line voltage value VHmax, the target address is set to a failed address. In some embodiments, the invalid address is recorded in the page buffer BUF or a register (not shown).

For example, assume that the target memory cell is the memory cell MC0 in area A1, the maximum retry value Rth is 3, and the maximum bit line voltage value VHmax is 3.2 volts. In this example, operation S404 is performed three times based on the bit line voltage VH_F having 3 volts. Since it is determined in operation S418 that the bit line voltage VH_F with 3 volts is not equal to the maximum bit line voltage value VHmax (for example: 3.2 volts), in operation S420 the bit line voltage VH_F will be increased by an incremental voltage. (For example: the bit line voltage VH_F will be increased by 0.1 volts from 3 volts to 3.1 volts). Next, operation S404 is performed three times based on the bit line voltage VH_F having 3.1 volts. Since it is determined in operation S418 that the bit line voltage VH_F with 3.1 volts is not equal to the maximum bit line voltage value VHmax (for example: 3.2 volts), the bit line voltage VH_F will be increased by an incremental voltage (for example: the bit line voltage VH_F will be increased by 0.1 volts from 3.1 volts to 3.2 volts). Next, operation S404 is performed three times based on the bit line voltage having 3.2 volts. In operation S418, it is determined that the bit line voltage VH_F having 3.2 volts is equal to the maximum bit line voltage value VHmax (for example: 3.2 volts). Then, the self-retry procedure exits and the target memory unit MC0 is recorded as an invalid address in operation S422.

After the target address is set as the invalid address, operation S412 is entered to determine whether the target address is a final address. When the target address is the final address (that is, the determination of operation S412 is "Yes"), the forming method 400 will end.

In the above embodiment, the target address is a single address. In some other embodiments, the target address includes a plurality of word line addresses, and the word line addresses belong to one word line. In other words, in these other embodiments, operations S404, S406 and S408 are performed on the word line addresses belonging to one word line, and the new target address in operation S414 belongs to an adjacent word line. Yuan line.

In some related technologies, the forming process is performed from a location closer to the driver to a location farther away from the driver, and the forming voltage gradually increases due to the voltage drop and leakage current flowing through the closer location. In addition, the difference between the source line voltage values or the difference between the limit current values will be larger due to leakage current flowing through closer locations. This method will result in poor formation time and formation uniformity.

Compared with the aforementioned related technologies, in this disclosure, the memory cell MC is divided into areas A1-A4, and the formation order is area A1, area A2, area A3 and area A4 (from the area far away from the driver WDVH-WDVL). position to a position closer to the driver WDVH-WDVL) to avoid leakage current flowing through a closer position. In addition, according to the position of the memory cell MC, the bit line voltage VH_F with appropriate values (the source line voltage VL_F with appropriate values and the limiting current Icmp) can be provided to the memory cell MC. Accordingly, the formation time and formation uniformity will be better.

In some embodiments, a processing circuit (not shown) or a control circuit (not shown) is used to perform some operations in the forming method (for example: part of operation S402, part of operation S408, operation S410, Operation S412, a part of operation S412, operation S414, operation S416, operation S418, operation S420, and operation S422). The processing circuit or control circuit may include a comparator to compare the currents and the voltages. In addition, the processing circuit or the control circuit further includes a reader to access the computer program stored in the non-transitory computer-readable memory medium. The processing circuit or control circuit can then set or reset the retry value RETRY, set the invalid address, and change the address based on the computer program.

In summary, in the present disclosure, the formation time and formation uniformity of resistive memory devices can be improved.

Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Anyone with ordinary knowledge in the art can make various modifications and modifications without departing from the spirit and scope of the present disclosure. Therefore, this disclosure The scope of protection shall be subject to the scope of the patent application attached.

100: Resistive memory device

MC, MC0, MC1: memory unit

BL0-BL63: bit lines

WL0-WL2047: character line

SL0-SL63: source line

WDVH-WDVL: driver

YMUX0-YMUX43,YMUXR0-YMUXR43: multiplexer

XDE: decoder

READ0-READ43: read circuit

BUF: page buffer

VH_F: bit line voltage

VL_F: source line voltage

Icmp: limit current

A1,A2,A3,A4: area

Claims (14)

A resistive memory device includes: a plurality of character lines; a plurality of first memory cells coupled to the character lines; a plurality of second memory cells coupled to the character lines; a plurality of bit lines coupled to the character lines. a plurality of first memory cells and a plurality of second memory cells; a plurality of source lines coupling the first memory cells and the second memory cells; and a driver for passing the bit cells in a forming process lines and the source lines provide a forming voltage to the first memory cells and the second memory cells, wherein the forming process is executed on the first memory cells and the second memory cells, wherein the A first connection distance between a memory cell and the driver along the bit lines and the source lines is longer than a first connection distance between the second memory cells and the driver along the bit lines and the source lines. a second connection distance of the pole lines, and the first memory cells are executed earlier than the second memory cells, wherein in the formation process, the formation voltage provided to the first memory cells A first value is less than a second value of the formation voltage provided to the second memory cells, wherein the formation voltage includes a cell line voltage and a source line voltage, and the driver includes: a first driver , used to provide the bit line voltage to the bits line; and a second driver for providing the source line voltage to the source lines, wherein in the forming process, a first value of the bit line voltage provided to the first memory cells is less than A second value of the bit line voltage provided to the second memory cells, and a first value of the source line voltage provided to the first memory cells is less than a first value provided to the second memory cells. a second value of the source line voltage. The resistive memory device of claim 1, further comprising a plurality of third memory cells coupled to the word lines, wherein the second connection distance along the bit lines and the source lines longer than a third connection distance between the third memory cells and the driver along the bit lines and the source lines, and the second memory cells are executed earlier than the third memory cells The forming process, wherein in the forming process, the second value of the forming voltage provided to the second memory cells is less than a third value of the forming voltage provided to the third memory cells. The resistive memory device of claim 2, wherein in the forming process, the second value of the bit line voltage provided to the second memory cells is smaller than the second value of the bit line voltage provided to the third memory cells. A third value of the bit line voltage, and the second value of the source line voltage provided to the second memory cells is less than the source line voltage provided to the third memory cells. A third value of pressure. The resistive memory device of claim 2, further comprising: a multiplexer coupled to the second driver, the first memory cells and the second memory cells, wherein the second driver is further used to A limiting current is provided to the multiplexer, wherein in the forming process, a first value of the limiting current provided to the first memory cells is less than a first value of the limiting current provided to the second memory cells. binary value. The resistive memory device of claim 4, wherein in the forming process, the second value of the limiting current provided to the second memory cells is less than the limiting current provided to the third memory cells. a third value. A method of forming a resistive memory device, including: setting a forming voltage, the forming voltage being provided to a plurality of first memory cells in the resistive memory device and a plurality of second memory cells in the resistive memory device, wherein a first connection distance between the first memory cells and a driver along the plurality of bit lines and the plurality of source lines is longer than that between the second memory cells and the driver along the plurality of bit lines and the plurality of source lines. a second connection distance of the source lines; performing a formation process on the first memory cells according to the formation voltage; and after the first memory cells are executed with the formation process, the formation process is executed with respect to the second memory cells according to the formation voltage, wherein a first value of the formation voltage provided to the first memory cells is less than A second value of the forming voltage is provided to the second memory cells, wherein the forming voltage includes a bit line voltage and a source line voltage, and the driver includes a first driver and a second driver, wherein The forming method further includes: providing the bit line voltage to the bit lines through the first driver; and providing the source line voltage to the source lines through the second driver, wherein providing A first value of the bit line voltage of the first memory cell is less than a second value of the bit line voltage provided to the second memory cells, and the source line provided to the first memory cells A first value of the voltage is less than a second value of the source line voltage provided to the second memory cells. The forming method of claim 6, further comprising: setting a limiting current, the limiting current being provided from the second driver to the first memory cells and the second memory cells; and by the second driver The limiting current is provided to a multiplexer coupled to the second driver, wherein a first limit current is provided to the first memory cells. The value is less than a second value of the limiting current provided to the second memory cells. The forming method of claim 7, further comprising: performing a verification process on the first memory units using a target memory unit among the second memory units, wherein the target memory unit corresponds to at least one target address. ; and increase a retry value from an initial value. The forming method of claim 8 further includes: determining whether a read current from the target memory cell is greater than a threshold current; when the read current is greater than the threshold current, determining whether the at least one target address is a final address; and when the at least one target address is the final address, the forming method ends. The formation method described in claim 9 further includes: when the read current is equal to or less than the threshold current, determining whether the retry value is equal to a maximum retry value; when the retry value is less than the maximum retry value when the bit line voltage is provided to the target memory cell; and when the retry value is equal to the maximum retry value, it is determined whether a value of the bit line voltage is equal to a maximum bit line voltage value. The forming method of claim 10 further includes: when the value of the bit line voltage is equal to the maximum bit line voltage value, setting the at least one target address as a failure address; setting the failure address After the address is reached, it is determined whether the at least one target address is the final address; and when the at least one target address is the final address, the forming method ends. The forming method as described in claim 11, further comprising: when the value of the bit line voltage is less than the maximum bit line voltage value, increasing the value of the bit line voltage and setting the retry value to 0 ; and provide the increased bit line voltage to the target memory cell. The forming method of claim 11 further includes: when the at least one target address is not the final address, changing the at least one target address; and resetting the retry value to the initial value. The forming method of claim 8, wherein the at least one target address includes a complex element line address.

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