TWI717269B - Memory unit operation method - Google Patents

Memory unit operation method Download PDF

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TWI717269B
TWI717269B TW109113475A TW109113475A TWI717269B TW I717269 B TWI717269 B TW I717269B TW 109113475 A TW109113475 A TW 109113475A TW 109113475 A TW109113475 A TW 109113475A TW I717269 B TWI717269 B TW I717269B
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data writing
switching element
voltage
resistance element
memory cell
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TW109113475A
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TW202141488A (en
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陳亮瑜
曾柏皓
李明修
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旺宏電子股份有限公司
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Abstract

The present disclosure relates to a memory unit operation method. During a writing period, a first switching element in a memory unit is turned on to receive a first data writing voltage through a matching line electrically coupled to the memory unit, so that a first resistance element electrically coupled to the first switching element in series has a first impedance value corresponding to the first data writing voltage. During the writing period, a second switching element in the memory unit is turned off, so that a second resistance element electrically coupled to the second switching element in series remains disconnected from the matching line, and have a second impedance value. The second impedance value is greater than the first impedance value.

Description

記憶單元操作方法Memory unit operation method

本揭示內容關於一種記憶單元操作方法,特別是能在記憶單元內設定不同阻抗值,以儲存不同邏輯訊號之技術。The present disclosure relates to a method for operating a memory cell, particularly a technology capable of setting different impedance values in the memory cell to store different logic signals.

隨著電腦速度越來越快,對於記憶體的速度以及穩定性的要求越來越高。近年來,對於非揮發性記憶體的設計的相關討論越來越多。非揮發性記憶體有多種實施類型,例如包含相變化記憶體、電阻式記憶體、磁阻式記憶體等等。然而,目前上述的記憶體可能會因為一些製程(例如為回焊製程等)的操作溫度過高,而造成記憶體內部的資料發生錯誤。As computers get faster and faster, the requirements for memory speed and stability are getting higher and higher. In recent years, there have been more and more discussions on the design of non-volatile memory. There are many types of non-volatile memory, including phase change memory, resistive memory, magnetoresistive memory, and so on. However, the above-mentioned memory may cause errors in the internal data of the memory due to the high operating temperature of some processes (for example, reflow process, etc.).

本揭示內容係關於一種記憶單元操作方法,包含下列步驟:在資料寫入期間,導通記憶單元之第一開關元件,以從與記憶單元電性連接之匹配線接收第一資料寫入電壓,使得與第一開關元件串聯連接之第一電阻元件具有對應於第一資料寫入電壓之第一阻抗值。在資料寫入期間,關斷記憶單元之第二開關元件,使得與第二開關元件串聯連接之第二電阻元件與匹配線之間保持斷路並具有第二阻抗值。第二阻抗值大於第一阻抗值。The present disclosure relates to a method for operating a memory cell, which includes the following steps: during a data writing period, a first switching element of the memory cell is turned on to receive a first data writing voltage from a match line electrically connected to the memory cell, so that The first resistance element connected in series with the first switching element has a first impedance value corresponding to the first data writing voltage. During the data writing period, the second switching element of the memory cell is turned off, so that the second resistance element connected in series with the second switching element and the matching line remain open and have a second impedance value. The second impedance value is greater than the first impedance value.

本揭示內容還關於一種記憶單元操作方法,包含下列步驟:在資料寫入期間,透過匹配線對記憶單元中之第一電阻元件施加第一資料寫入電壓,使第一電阻元件具有對應於第一資料寫入電壓之第一阻抗值。其中匹配線係電性連接於第一電阻元件。在資料寫入期間,維持記憶單元之第二電阻元件與匹配線間之斷路,使第二電阻元件在無電流通過的情況下具有第二阻抗值。匹配線係電性連接於第二電阻元件。第二阻抗值大於該第一阻抗值。The present disclosure also relates to a method for operating a memory cell, including the following steps: during a data writing period, applying a first data writing voltage to a first resistance element in the memory cell through a matching line, so that the first resistance element has a A first impedance value of the data writing voltage. The matching line is electrically connected to the first resistance element. During the data writing period, the disconnection between the second resistance element of the memory cell and the matching line is maintained, so that the second resistance element has a second impedance value when no current flows. The matching line is electrically connected to the second resistance element. The second impedance value is greater than the first impedance value.

據此,由於第二阻抗值遠大於第一阻抗值,故當後續執行資料搜索時,匹配搜索結果的記憶單元將能維持高阻抗,以維持匹配線上的電壓。此外,不匹配搜索結果的記憶單元則具有低電壓,使匹配線上的電壓產生明顯的變化,以提昇搜索精確性。Accordingly, since the second impedance value is much greater than the first impedance value, when the data search is subsequently performed, the memory cell matching the search result will be able to maintain a high impedance to maintain the voltage on the matching line. In addition, the memory cell that does not match the search result has a low voltage, which causes the voltage on the matching line to change significantly to improve the search accuracy.

以下將以圖式揭露本發明之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。Hereinafter, multiple embodiments of the present invention will be disclosed in the form of drawings. For clear description, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventionally used structures and elements will be shown in a simple schematic manner in the drawings.

於本文中,當一元件被稱為「連接」或「耦接」時,可指「電性連接」或「電性耦接」。「連接」或「耦接」亦可用以表示二或多個元件間相互搭配操作或互動。此外,雖然本文中使用「第一」、「第二」、…等用語描述不同元件,該用語僅是用以區別以相同技術用語描述的元件或操作。除非上下文清楚指明,否則該用語並非特別指稱或暗示次序或順位,亦非用以限定本發明。In this text, when a component is referred to as “connected” or “coupled”, it can be referred to as “electrically connected” or “electrically coupled”. "Connected" or "coupled" can also be used to mean that two or more components cooperate or interact with each other. In addition, although terms such as “first”, “second”, etc. are used herein to describe different elements, the terms are only used to distinguish elements or operations described in the same technical terms. Unless clearly indicated by the context, the terms do not specifically refer to or imply order or sequence, nor are they used to limit the present invention.

本揭示內容係關於一種記憶單元的操作方法。第1A係根據本揭示內容之部份實施例的記憶單元100(memory cell)的示意圖。如第1A圖所示,記憶單元100用以電性連接於匹配線ML及搜索線SL1、SL2,其中搜索線SL1、SL2的邏輯準位為互為相反(即,當搜索線SL1具有致能電壓的準位時,搜索線SL2具有禁能電壓的準位)。The present disclosure relates to an operating method of a memory unit. 1A is a schematic diagram of a memory cell 100 (memory cell) according to some embodiments of the present disclosure. As shown in FIG. 1A, the memory cell 100 is used to electrically connect to the match line ML and the search lines SL1 and SL2. The logic levels of the search lines SL1 and SL2 are opposite to each other (that is, when the search line SL1 has an enable When the voltage is at the level, the search line SL2 has the disable voltage level).

第1B係根據本揭示內容之部份實施例的記憶體裝置200的示意圖。如第1B圖所示,記憶體裝置200包含多個如第1A圖所示的記憶單元100,且多條匹配線ML及搜索線SL1、SL2連接於相應的記憶單元100。在部份實施例中,上述多個記憶單元100係以陣列形式設置於記憶體裝置200中,以儲存各種不同的資料(如:路由表)。1B is a schematic diagram of the memory device 200 according to some embodiments of the present disclosure. As shown in FIG. 1B, the memory device 200 includes a plurality of memory cells 100 as shown in FIG. 1A, and a plurality of match lines ML and search lines SL1 and SL2 are connected to the corresponding memory cells 100. In some embodiments, the above-mentioned plurality of memory cells 100 are arranged in the memory device 200 in an array form to store various data (such as routing tables).

在一實施例中,當記憶體裝置200執行資料寫入(write)之動作時(以下簡稱「資料寫入期間」),匹配線ML用以被充電至特定的寫入電壓,以調整記憶單元100內的阻抗特性。不同的阻抗特性將對應於不同的邏輯訊號。在一實施例中,當記憶體裝置200執行資料搜索(search)之動作時(以下簡稱「資料搜索期間」),搜索線SL1、SL2提供對應的禁能或致能電壓至記憶單元100,以控制記憶單元100內不同路徑的導通或關斷。據此,根據匹配線ML上的電壓變化,記憶體裝置200即可判斷記憶單元100內儲存之邏輯訊號是否與搜索指令中欲搜索的資訊(以下簡稱「搜索目標」)相符。In one embodiment, when the memory device 200 performs a data write operation (hereinafter referred to as "data writing period"), the match line ML is used to be charged to a specific write voltage to adjust the memory cell Impedance characteristics within 100. Different impedance characteristics will correspond to different logic signals. In one embodiment, when the memory device 200 performs a data search operation (hereinafter referred to as "data search period"), the search lines SL1 and SL2 provide corresponding disable or enable voltages to the memory cell 100 to Control the on or off of different paths in the memory unit 100. Accordingly, according to the voltage change on the match line ML, the memory device 200 can determine whether the logic signal stored in the memory cell 100 matches the information to be searched in the search command (hereinafter referred to as "search target").

第2A圖係根據本揭示內容之部份實施例的記憶單元100之等效電路示意圖。在一實施例中,記憶單元100為三態內容可定址記憶體(Ternary Content Addressable Memory,TCAM),可運用於網路路由器中,但本揭示內容並不以此為限。由於本領域人士能理解三態內容可定址記憶體及記憶體裝置的結構及原理,故在此不另贅述。FIG. 2A is a schematic diagram of an equivalent circuit of the memory cell 100 according to some embodiments of the present disclosure. In an embodiment, the memory unit 100 is a Ternary Content Addressable Memory (Ternary Content Addressable Memory, TCAM), which can be used in a network router, but the present disclosure is not limited to this. Since those skilled in the art can understand the structure and principle of tri-state content addressable memory and memory devices, it will not be described here.

如第2A圖所示,記憶單元100包含第一電路110及第二電路120。第一電路110及第二電路120係電性連接於匹配線ML與字元線BL之間。在一實施例中,字元線BL係連接於參考電位(如:接地電壓)。第一電路110包含第一開關元件T1及第一電阻元件R1。第二電路120包含第二開關元件T2及第二電阻元件R2。匹配線ML分別電性連接於第一電阻元件R1之一端及第二電阻元件R2之一端。第一開關元件T1與第一電阻元件R1相串聯,第二開關元件T2與第二電阻元件R2相串聯。第一電路110與第二電路120則相並聯。As shown in FIG. 2A, the memory unit 100 includes a first circuit 110 and a second circuit 120. The first circuit 110 and the second circuit 120 are electrically connected between the match line ML and the word line BL. In one embodiment, the word line BL is connected to a reference potential (eg, ground voltage). The first circuit 110 includes a first switching element T1 and a first resistance element R1. The second circuit 120 includes a second switching element T2 and a second resistance element R2. The matching line ML is electrically connected to one end of the first resistance element R1 and one end of the second resistance element R2, respectively. The first switching element T1 is connected in series with the first resistance element R1, and the second switching element T2 is connected in series with the second resistance element R2. The first circuit 110 and the second circuit 120 are connected in parallel.

第2B圖係根據本揭示內容之部份實施例的開關元件之半導體結構的示意圖。在一實施例中,第2B圖所示之半導體結構可用以實現第2A圖所示之第一開關元件T1及/或第二開關元件T2,但本案不以此為限。如第2B圖所示,開關元件之半導體結構包含閘極Tg、汲極Td及源極Ts。當閘極Tg接收到致能電壓時,將能於汲極Td及源極Ts間形成導通路徑,根據汲極Td及源極Ts間的電壓差形成不同大小的導通電流。FIG. 2B is a schematic diagram of the semiconductor structure of the switching element according to some embodiments of the present disclosure. In one embodiment, the semiconductor structure shown in FIG. 2B can be used to realize the first switching element T1 and/or the second switching element T2 shown in FIG. 2A, but this case is not limited to this. As shown in FIG. 2B, the semiconductor structure of the switching element includes a gate Tg, a drain Td, and a source Ts. When the gate Tg receives the enabling voltage, a conduction path can be formed between the drain Td and the source Ts, and conduction currents of different magnitudes are formed according to the voltage difference between the drain Td and the source Ts.

在不同實施例中,第2A圖所示之第一電阻元件R1亦可形成於第一開關元件T1中。舉例而言,第一電阻元件R1可由第一開關元件T1中具有特定阻抗值的半導體結構來實現(詳細結構將於後續段落中說明)。意即,第一電阻元件R1及第一開關元件T1可整合於同一個電晶體結構中。為便於說明,在第2A圖中將兩個元件分別繪示,第一開關元件T1視為理想開關元件、第一電阻元件R1則為第一電路110中的阻抗部份,且第一電阻元件R1的阻抗值將會根據第一電路110(或第一開關元件T1)的跨壓而改變。In different embodiments, the first resistance element R1 shown in FIG. 2A can also be formed in the first switching element T1. For example, the first resistance element R1 can be realized by a semiconductor structure having a specific impedance value in the first switching element T1 (the detailed structure will be described in subsequent paragraphs). That is, the first resistance element R1 and the first switching element T1 can be integrated in the same transistor structure. For ease of description, in Figure 2A, the two elements are shown separately, the first switching element T1 is regarded as an ideal switching element, the first resistance element R1 is the impedance part of the first circuit 110, and the first resistance element The impedance value of R1 will change according to the voltage across the first circuit 110 (or the first switching element T1).

相應於上述實施例,在不同實施例中,第2A圖所示之第二電阻元件R2亦可形成於第二開關元件T2中,且第二電阻元件R2的阻抗值會根據第二電路120(或第二開關元件T2)的跨壓而改變。Corresponding to the above embodiment, in different embodiments, the second resistance element R2 shown in Figure 2A can also be formed in the second switching element T2, and the impedance value of the second resistance element R2 will be based on the second circuit 120 ( Or the cross voltage of the second switching element T2) changes.

操作上,在資料寫入期間,匹配線ML被充電至第一資料寫入電壓,且第一電路110導通,使得第一電阻元件R1具有對應於第一資料寫入電壓的第一阻抗值。換言之,第一電阻元件R1的阻抗值會根據導通第一電路110的第一資料寫入電壓進行改變,由初始阻抗值改變為第一阻抗值。在部份實施例中,第一資料寫入電壓為相對低電壓。在一些實施例中,第一資料寫入電壓為1~4伏特,但本揭示內容並不以此為限,第一資料寫入電壓的數值可依據實際製作記憶體的材料、製程或其他參數而調整。In operation, during the data writing period, the match line ML is charged to the first data writing voltage, and the first circuit 110 is turned on, so that the first resistance element R1 has a first resistance value corresponding to the first data writing voltage. In other words, the impedance value of the first resistance element R1 is changed according to the first data writing voltage that turns on the first circuit 110, from the initial impedance value to the first impedance value. In some embodiments, the first data writing voltage is a relatively low voltage. In some embodiments, the first data writing voltage is 1 to 4 volts, but the present disclosure is not limited to this. The value of the first data writing voltage can be based on the material, manufacturing process or other parameters of the actual memory. And adjust.

在一些實施例中,當匹配線ML充電至第一資料寫入電壓時,第一開關元件T1被導通、第二開關元件T2被關斷,使得第一電路110上響應於導通之第一開關元件T1及第一寫入電壓而形成第一電流。In some embodiments, when the match line ML is charged to the first data writing voltage, the first switching element T1 is turned on and the second switching element T2 is turned off, so that the first switch on the first circuit 110 responds to the conduction The element T1 and the first write voltage form a first current.

同時,在資料寫入期間及匹配線ML具有第一資料寫入電壓時,第二電阻元件R2與匹配線ML間係維持斷路狀態,使第二電路120不會因為第一資料寫入電壓而產生電流。此時,第二電阻元件R2在無電流流過的情況下具有第二阻抗值,且第二阻抗值將遠大於第一阻抗值。在部份實施例中,第二開關元件T2於資料寫入期間始終保持關斷,確保第二電路120上不會產生電流,且第二開關元件T2從未被電流貫穿。At the same time, during the data writing period and when the matching line ML has the first data writing voltage, the second resistance element R2 and the matching line ML maintain an open state, so that the second circuit 120 will not be affected by the first data writing voltage. Generate current. At this time, the second resistance element R2 has a second resistance value when no current flows, and the second resistance value will be much larger than the first resistance value. In some embodiments, the second switching element T2 is always turned off during the data writing period to ensure that no current is generated on the second circuit 120 and the second switching element T2 is never penetrated by current.

為便於說明,在此將第一電阻元件R1/第二電阻元件R2(或第一電路110/第二電路120)對應於第一資料寫入電壓而形成的第一阻抗值稱為「低阻抗狀態(Low Resistance State)」,且將第二阻抗值則稱為「初始阻抗狀態」。如前述實施例所述,當第一電路110為低阻抗狀態、第二電路為初始阻抗狀態時,可用以紀錄邏輯訊號「0」。相對地,若第一電路110為初始阻抗狀態、第二電路為低阻抗狀態時,可用以紀錄邏輯訊號「1」。若第一電路110、第二電路120皆為初始阻抗狀態,則對應於邏輯訊號「X(don’t care)」,代表搜索時可忽略。For ease of description, the first resistance value formed by the first resistance element R1/second resistance element R2 (or the first circuit 110/second circuit 120) corresponding to the first data writing voltage is referred to herein as "low impedance State (Low Resistance State)” and the second impedance value is called the “initial impedance state”. As described in the foregoing embodiment, when the first circuit 110 is in the low impedance state and the second circuit is in the initial impedance state, the logic signal "0" can be recorded. In contrast, if the first circuit 110 is in the initial impedance state and the second circuit is in the low impedance state, the logic signal "1" can be recorded. If both the first circuit 110 and the second circuit 120 are in the initial impedance state, it corresponds to the logic signal "X (don't care)", which means that it can be ignored during search.

在記憶體裝置200進行資料搜索的動作時(以下簡稱「資料搜索期間」),搜索線SL1、SL2係根據搜索指令被控制於致能準位或禁能準位,以控制第一開關元件T1及第二開關元件T2的導通及關斷。透過判斷匹配線ML上的電壓變化,記憶體裝置200即可確認記憶單元100中儲存的邏輯訊號是否為搜索目標。在一實施例中,若記憶單元100中儲存的邏輯訊號確實為搜索目標,則第一電路110及第二電路120中的其中之一會因為搜索線(SL1或SL2)的禁能而保持斷路,第一電路110及第二電路120中的其中之另一個則會具有「初始阻抗狀態」的高阻抗特性,使得匹配線ML上幾乎無電壓變化。本揭示內容利用第二電阻元件R2(或第二開關元件T2中的半導體結構,將於後續段落詳述)未曾被電流貫穿時,第二電阻元件R2具有的高阻抗特性,確保匹配線ML於搜索到正確目標時,不會產生漏電壓,避免記憶體裝置200不必要的耗電。When the memory device 200 performs a data search operation (hereinafter referred to as "data search period"), the search lines SL1 and SL2 are controlled at the enable or disable level according to the search command to control the first switching element T1 And the second switching element T2 is turned on and off. By determining the voltage change on the match line ML, the memory device 200 can confirm whether the logic signal stored in the memory cell 100 is the search target. In one embodiment, if the logic signal stored in the memory cell 100 is indeed the search target, one of the first circuit 110 and the second circuit 120 will remain open due to the disablement of the search line (SL1 or SL2) , The other of the first circuit 110 and the second circuit 120 will have a high impedance characteristic of the "initial impedance state", so that there is almost no voltage change on the matching line ML. The present disclosure utilizes the high impedance characteristic of the second resistance element R2 (or the semiconductor structure in the second switch element T2, which will be described in detail in subsequent paragraphs) when the second resistance element R2 has not been penetrated by current to ensure that the matching line ML is at When the correct target is searched, no leakage voltage is generated, and unnecessary power consumption of the memory device 200 is avoided.

另一方面,由於「第一阻抗值(低阻抗狀態)」及「第二阻抗值(初始阻抗狀態)」間具有足夠大的阻抗差異,因此,在資料搜索期間,匹配搜索目標的記憶單元100及不匹配搜索目標的記憶單元100之間,將會因為阻抗的明顯不同,使得匹配線ML上的電壓變化有極為明顯的差異,藉此能提昇記憶體裝置200於進行資料搜索時的精確性。On the other hand, since there is a sufficiently large impedance difference between the "first impedance value (low impedance state)" and the "second impedance value (initial impedance state)", during the data search period, the memory cell 100 of the search target is matched. And the memory cell 100 that does not match the search target will have a very significant difference in the voltage change on the matching line ML due to the obvious difference in impedance, thereby improving the accuracy of the memory device 200 during data search .

在此說明記憶單元100之「資料寫入程序」如後。第3圖為資料寫入程序的步驟流程圖。下述為方便清楚說明第3圖起見,係以第2A圖所示實施例搭配第3圖進行說明,然而第3圖所示實施例的應用不以第2A圖的實施例為限。The "data writing procedure" of the memory unit 100 is described here as follows. Figure 3 is a flow chart of the steps of the data writing procedure. For the convenience and clarity of the description of FIG. 3, the following description uses the embodiment shown in FIG. 2A in conjunction with FIG. 3. However, the application of the embodiment shown in FIG. 3 is not limited to the embodiment in FIG. 2A.

在步驟S301,記憶體裝置200中的處理器(圖中未示)判斷寫入指令中欲寫入之邏輯訊號的準位為「1」、「0」或者是「X(don’t care)」。在記憶體裝置200中的處理器判斷需寫入的邏輯訊號為「0」時,執行步驟S302,處理器將匹配線ML充電至第一資料寫入電壓。在步驟S303中,導通第一開關元件T1,使第一電阻元件R1具有對應於第一資料寫入電壓之第一阻抗值,且在第一電路110上形成「低阻抗狀態」。In step S301, the processor (not shown in the figure) in the memory device 200 determines whether the level of the logic signal to be written in the write command is "1", "0" or "X (don't care)" ". When the processor in the memory device 200 determines that the logic signal to be written is "0", step S302 is executed, and the processor charges the match line ML to the first data write voltage. In step S303, the first switching element T1 is turned on, so that the first resistance element R1 has a first impedance value corresponding to the first data writing voltage, and a "low impedance state" is formed on the first circuit 110.

在步驟S304中,在資料寫入期間,維持關斷第二開關元件T2,使第二電阻元件R2與匹配線ML間保持斷路。此時第二電路120或第二電阻元件R2上未曾有電流產生。此外,由於第二電阻元件R2未曾被電流所貫穿而具有第二阻抗值,因此能使第二電路120形成「初始阻抗狀態」。In step S304, during the data writing period, the second switching element T2 is kept turned off, so that the second resistance element R2 and the match line ML are kept open. At this time, no current is generated on the second circuit 120 or the second resistance element R2. In addition, since the second resistance element R2 has not been penetrated by current and has the second impedance value, the second circuit 120 can be formed into an "initial impedance state".

在記憶體裝置200中的處理器判斷需寫入的邏輯訊號為「1」時,執行步驟S305。處理器將匹配線ML充電至第一資料寫入電壓。在步驟S306中,導通第二開關元件T2,使第二電阻元件R2具有對應於第一資料寫入電壓之第一阻抗值,且在第二電路120上形成「低阻抗狀態」。When the processor in the memory device 200 determines that the logic signal to be written is "1", step S305 is executed. The processor charges the match line ML to the first data writing voltage. In step S306, the second switching element T2 is turned on, so that the second resistance element R2 has a first impedance value corresponding to the first data writing voltage, and a "low impedance state" is formed on the second circuit 120.

在步驟S307中,在資料寫入期間,維持關斷第一開關元件T1,使第一電阻元件R1與匹配線ML間保持斷路。此時第一電阻元件R1因為未曾被電流流經而具有第二阻抗值,且使第一電路110形成「初始阻抗狀態」。In step S307, during the data writing period, the first switching element T1 is kept turned off, so that the first resistance element R1 and the match line ML are kept open. At this time, the first resistance element R1 has the second impedance value because no current flows through it, and the first circuit 110 is formed into an "initial impedance state".

在判斷需寫入的邏輯訊號為「X」時,執行步驟S308,在資料寫入期間,維持關斷第一開關元件T1,使第一電阻元件R1與匹配線ML間保持斷路。此時第一電阻元件R1因為未曾被電流流經而具有第二阻抗值,且在第一電路110上形成「初始阻抗狀態」。When it is judged that the logic signal to be written is "X", step S308 is executed. During the data writing period, the first switching element T1 is kept off, so that the first resistance element R1 and the matching line ML are kept open. At this time, the first resistance element R1 has a second impedance value because no current flows through it, and an "initial impedance state" is formed on the first circuit 110.

同樣地,在步驟S309中,關斷第二開關元件T2,使第二電阻元件R2與匹配線ML間保持斷路。此時第二電阻元件R2因為未曾被電流流經而具有第二阻抗值,且在第二電路120上形成「初始阻抗狀態」。Similarly, in step S309, the second switching element T2 is turned off, so that the second resistance element R2 and the matching line ML are kept open. At this time, the second resistance element R2 has a second impedance value because no current flows through it, and an "initial impedance state" is formed on the second circuit 120.

在一實施例中,記憶單元100係利用其未曾被導通時具備高阻抗之「初始阻抗狀態」的特性,作為記憶邏輯訊號的特性。因此,記憶單元100應用於「一次性寫入」的記憶體時,可具有更佳的儲存效果。In one embodiment, the memory cell 100 uses the "initial impedance state" characteristic of high impedance when it is not turned on as the characteristic of the memory logic signal. Therefore, when the memory unit 100 is applied to a "write-once" memory, it can have a better storage effect.

請參閱第4圖,第4圖係對應於第一電路110/第二電路120的半導體結構的特性圖。其中,第4圖的橫軸為阻抗值、縱軸為出現對應之阻抗值的機率(在本實施例中,縱軸數值係經過多次測試後統計出的數量累積百分比)。根據不同的阻抗特性,開關元件具有「低阻抗狀態LRS」、「高阻抗狀態HRS」及「初始阻抗狀態ORS」。「低阻抗狀態LRS」為開關元件響應於第一資料寫入電壓而導通時,對應之電阻元件具有的第一阻抗值(如:10 3~10 5歐姆)。「高阻抗狀態HRS」為開關元件響應於第二資料寫入電壓而導通時,對應之電阻元件具有的第三阻抗值(如:10 5~10 8歐姆),其中第二資料寫入電壓相對於第一資料寫入電壓為高電壓。在部份實施例中,第二資料寫入電壓為-1~-2伏特,但本揭示內容並不以此為限,第二資料寫入電壓的數值的數值可依據實際製作記憶體的材料、製程或其他參數而調整。「初始阻抗狀態ORS」則為開關元件未曾被導通時,對應之電阻元件所呈現出的第二阻抗值(如:10 9~10 10歐姆)。根據製程的差異,第一阻抗值、第二阻抗值及第三阻抗值將不會是一個固定值,而是一個阻抗範圍。如第4圖所示,「高阻抗狀態HRS」對應之第三阻抗值係介於「低阻抗狀態LRS」對應之第一阻抗值及「初始阻抗狀態ORS」對應的第二阻抗值之間。「初始阻抗狀態ORS」具有最高的阻抗特性。 Please refer to FIG. 4, which is a characteristic diagram of the semiconductor structure corresponding to the first circuit 110/the second circuit 120. Among them, the horizontal axis of Figure 4 is the impedance value, and the vertical axis is the probability of the corresponding impedance value (in this embodiment, the vertical axis value is the cumulative percentage of the number after multiple tests). According to different impedance characteristics, the switching element has "low impedance state LRS", "high impedance state HRS" and "initial impedance state ORS". The “low impedance state LRS” refers to the first impedance value (for example, 10 3 -10 5 ohms) of the corresponding resistance element when the switching element is turned on in response to the first data writing voltage. "High-impedance state HRS" refers to the third impedance value (such as 10 5 ~10 8 ohms) of the corresponding resistance element when the switching element is turned on in response to the second data writing voltage, where the second data writing voltage is relatively The first data writing voltage is a high voltage. In some embodiments, the second data writing voltage is -1 to -2 volts, but the present disclosure is not limited to this. The value of the second data writing voltage can be based on the material used to actually make the memory , Manufacturing process or other parameters. The "initial impedance state ORS" is the second impedance value (such as 10 9 ~10 10 ohms) exhibited by the corresponding resistance element when the switching element has not been turned on. According to the difference of the manufacturing process, the first impedance value, the second impedance value and the third impedance value will not be a fixed value, but an impedance range. As shown in Figure 4, the third impedance value corresponding to the "high impedance state HRS" is between the first impedance value corresponding to the "low impedance state LRS" and the second impedance value corresponding to the "initial impedance state ORS". The "initial impedance state ORS" has the highest impedance characteristics.

如第4圖所示之特性圖,曲線L1為開關元件響應於第一資料寫入電壓而第一次導通時,對應之電阻元件的阻抗特性。曲線H1為開關元件響應於第一資料寫入電壓導通後,再響應於第二資料寫入電壓而第二次導通時,對應之電阻元件的阻抗特性。由第4圖可知,當匹配線ML上的電壓被控制於第一資料寫入電壓、第二資料寫入電壓間切換,使記憶單元100中的電路反覆地處於「高阻抗狀態HRS」及「初始阻抗狀態ORS」時,阻抗特性也會隨之改變。曲線Ln為開關元件響應於第一資料寫入電壓而第N次導通時,對應之電阻元件呈現出的阻抗特性。As shown in the characteristic diagram in Fig. 4, the curve L1 is the impedance characteristic of the corresponding resistance element when the switching element is turned on for the first time in response to the first data writing voltage. The curve H1 is the impedance characteristic of the corresponding resistance element when the switch element is turned on in response to the first data writing voltage and then turned on for the second time in response to the second data writing voltage. It can be seen from Figure 4 that when the voltage on the match line ML is controlled to switch between the first data writing voltage and the second data writing voltage, the circuit in the memory cell 100 is repeatedly in the "high impedance state HRS" and " In the initial impedance state ORS", the impedance characteristics will also change accordingly. The curve Ln is the impedance characteristic of the corresponding resistance element when the switch element is turned on for the Nth time in response to the first data writing voltage.

承上,如第4圖所示,曲線Hn為開關元件響應於第二資料寫入電壓而第N次導通時,對應之電阻元件呈現出的阻抗特性。經過多次的切換,曲線會逐漸朝阻抗更低的方向變化。在一實施例中,若第一開關元件T1需被控制於「低阻抗狀態」,則第一開關元件T1透過匹配線ML反覆接收第一資料寫入電壓及第二資料寫入電壓,直到第一開關元件T1接收第一資料寫入電壓時,第一電阻元件R1之阻抗值等於或低於阻抗門檻值(如:10 4歐姆)。換言之,第一電路110將被反覆控制於「高阻抗狀態HRS」及「低阻抗狀態LRS」間,具體方法為:在資料寫入期間,在第一開關元件T1響應於第一資料寫入電壓導通時,匹配線ML上之電壓被調整為第二資料寫入電壓,使第一開關元件T1接收第二資料寫入電壓。接著,匹配線ML上之電壓再次被調整回第一資料寫入電壓,使第一開關元件T1再次接收第一資料寫入電壓。依據前述步驟反覆執行N次。在一實施例中,N為大於8之正整數。意即,匹配線ML切換第一資料寫入電壓及第二資料寫入電壓的次數大於8次。第4圖所示之曲線Ln為開關元件被第10次響應於第一資料寫入電壓時,對應之電阻元件呈現的特性曲線。 In addition, as shown in Figure 4, the curve Hn is the impedance characteristic of the corresponding resistance element when the switching element is turned on for the Nth time in response to the second data writing voltage. After many times of switching, the curve will gradually change towards a lower impedance. In one embodiment, if the first switching element T1 needs to be controlled in the "low impedance state", the first switching element T1 repeatedly receives the first data writing voltage and the second data writing voltage through the match line ML until the first a first data switching element T1 receives the write voltage, the resistance value of the first resistor element R1 is equal to or lower than the threshold impedance (eg: 104 ohms). In other words, the first circuit 110 will be repeatedly controlled between the "high impedance state HRS" and the "low impedance state LRS". The specific method is: during the data writing period, the first switching element T1 responds to the first data writing voltage When turned on, the voltage on the match line ML is adjusted to the second data writing voltage, so that the first switching element T1 receives the second data writing voltage. Then, the voltage on the match line ML is adjusted back to the first data writing voltage again, so that the first switching element T1 receives the first data writing voltage again. Perform N times repeatedly according to the foregoing steps. In one embodiment, N is a positive integer greater than 8. That is, the number of times that the match line ML switches the first data writing voltage and the second data writing voltage is greater than 8 times. The curve Ln shown in FIG. 4 is the characteristic curve of the corresponding resistance element when the switching element is responsive to the first data writing voltage for the tenth time.

請參閱第5圖,第5圖為記憶單元100中第一電路110及/或第二電路120的開關元件的另一實施例的半導體結構示意圖。在一實施例中,前述開關元件包含閘極Tg、汲極Td及源極Ts。其中,閘極Ts還包含浮動閘極Tf,浮動閘極Tf係位於兩層絕緣層Ti之間。汲極Td及源極Ts上則設有金屬層Tm。此外,如前所述,在半導體結構中可同時形成有電阻元件。如第5圖所示,汲極Td上設有介電層Te。介電層Te具有特定阻抗值,可作為前述實施例中之第一電阻元件R1及/或第二電阻元件R2,或作為前述實施例中第一電阻元件R1及/或第二電阻元件R2之至少一部份的半導體結構。舉例來說,在第一電路110/第二電路120被施加第一資料寫入電壓或第二資料寫入電壓時,介電層Te將會被貫穿,而形成低阻抗狀態LRS。Please refer to FIG. 5, which is a schematic diagram of a semiconductor structure of another embodiment of the switching element of the first circuit 110 and/or the second circuit 120 in the memory cell 100. In an embodiment, the aforementioned switching element includes a gate Tg, a drain Td, and a source Ts. Among them, the gate Ts also includes a floating gate Tf, which is located between the two insulating layers Ti. The drain electrode Td and the source electrode Ts are provided with a metal layer Tm. In addition, as described above, the resistance element may be simultaneously formed in the semiconductor structure. As shown in FIG. 5, a dielectric layer Te is provided on the drain electrode Td. The dielectric layer Te has a specific resistance value and can be used as the first resistance element R1 and/or the second resistance element R2 in the foregoing embodiment, or as the first resistance element R1 and/or the second resistance element R2 in the foregoing embodiment At least part of the semiconductor structure. For example, when the first data writing voltage or the second data writing voltage is applied to the first circuit 110/the second circuit 120, the dielectric layer Te will be penetrated to form a low impedance state LRS.

在此進一步舉例說明記憶單元100之「資料搜索程序」如後。如前述步驟,記憶單元100係根據下列特性紀錄邏輯訊號: 儲存之邏輯訊號 第一電路 第二電路 0 LRS ORS 1 ORS LRS X ORS ORS Here, the "data search procedure" of the memory unit 100 is further illustrated as follows. As in the foregoing steps, the memory unit 100 records logical signals according to the following characteristics: Stored logic signal First circuit Second circuit 0 LRS ORS 1 ORS LRS X ORS ORS

在一實施例中,根據搜索目標的不同,搜索線SL1、SL2將根據下列表格調整致能電壓或禁能電壓,以導通或關斷對應之開關元件: 搜索目標 SL1 SL2 0 禁能 致能 1 致能 禁能 In one embodiment, according to the different search targets, the search lines SL1 and SL2 will adjust the enable voltage or disable voltage according to the following table to turn on or turn off the corresponding switching element: Search target SL1 SL2 0 Disable Enable 1 Enable Disable

如上述兩個表格所示,當資料搜索期間,在記憶體裝置200判斷搜索指令中之搜索目標為「0」的情形下,搜索線SL1將關斷第一開關元件T1、搜索線SL2則導通第二開關元件T2。若記憶單元100內儲存的邏輯訊號與搜索目標匹配(即,「0」),則第一電路110、第二電路120分別為低阻抗狀態LRS及初始阻抗狀態ORS。此時,雖然第二開關元件T2被導通,但由於第二電路120處於初始阻抗狀態ORS,具有極高電阻,因此匹配線ML上並不會產生明顯的電壓變化,而能使記憶體裝置200精確地搜索出儲存有搜索目標的記憶單元100。此外,由於在資料搜索期間,匹配線ML上的電壓值小於資料寫入期間充電的電壓(即,第一資料寫入電壓或第二資料寫入電壓),因此第二開關元件T2(如:第5圖中之介電層Te)不會因為被電流貫穿而破壞最初的阻抗特性,使得第二開關元件T2能維持在初始阻抗狀態ORS。As shown in the above two tables, during data search, when the memory device 200 determines that the search target in the search command is "0", the search line SL1 will turn off the first switching element T1 and the search line SL2 will turn on The second switching element T2. If the logic signal stored in the memory unit 100 matches the search target (ie, "0"), the first circuit 110 and the second circuit 120 are in the low impedance state LRS and the initial impedance state ORS, respectively. At this time, although the second switching element T2 is turned on, because the second circuit 120 is in the initial impedance state ORS and has a very high resistance, there is no significant voltage change on the matching line ML, which enables the memory device 200 The memory unit 100 storing the search target is accurately searched out. In addition, since during the data search period, the voltage value on the match line ML is less than the voltage charged during the data writing period (ie, the first data writing voltage or the second data writing voltage), the second switching element T2 (such as: The dielectric layer Te in Figure 5 will not destroy the initial impedance characteristics due to current penetration, so that the second switching element T2 can maintain the initial impedance state ORS.

另一方面,若搜索指令之搜索目標為「0」,但記憶單元100內儲存的邏輯訊號與搜索目標並不匹配(即,「1」),此時,第二開關元件T2同樣會被導通,但第二電路120處於低阻抗狀態LRS,具有低電阻。因此,匹配線ML會產生明顯的電壓變化,使得記憶體單元200能輕易地分辨出「不匹配」之搜索結果。On the other hand, if the search target of the search command is "0", but the logic signal stored in the memory unit 100 does not match the search target (ie, "1"), at this time, the second switching element T2 will also be turned on , But the second circuit 120 is in the low impedance state LRS and has low resistance. Therefore, the matching line ML will produce a significant voltage change, so that the memory cell 200 can easily distinguish the search result of "not matching".

請參閱第6圖,第6圖為本揭示內容之部份實施例中記憶單元的應用示意圖。記憶體裝置200包含多個記憶單元100,該些記憶單元100可組成多個記憶資料庫TCAM1~TCAM8。在一實施例中,記憶資料庫TCAM1~TCAM8用以儲存對應於神經網路的資料庫,分別儲存不同類型的資料。由於記憶單元100係作為資料庫,因此只須執行一次資料寫入程序。Please refer to FIG. 6, which is a schematic diagram of the application of the memory unit in some embodiments of the disclosure. The memory device 200 includes a plurality of memory cells 100, and the memory cells 100 can form a plurality of memory data banks TCAM1 to TCAM8. In one embodiment, the memory database TCAM1 to TCAM8 are used to store the database corresponding to the neural network, respectively storing different types of data. Since the memory unit 100 is used as a database, the data writing process only needs to be executed once.

舉例而言,當神經網路600接收到待比對的分析資料(如:一張動物的影像)時,分析資料將經過神經網路600的多層神經分析單元CV1~CV4,逐一判斷分析資料內的特徵向量,最後經過連接層Ly(connected layer)產生分析後的一組邏輯特徵向量LSH(binary vector)。邏輯特徵向量LSH可作為輸入至記憶體裝置200中的搜索指令,以在多種類別的記憶資料庫TCAM1~TCAM8(如:陸地動物、水生動物等不同資料庫)中搜索出對應的結果(如:兔子的影像)。由於本領域人士能理解神經網路的運作及分析原理,故在此不另贅述。For example, when the neural network 600 receives the analysis data to be compared (such as an image of an animal), the analysis data will pass through the multi-layer neural analysis units CV1 to CV4 of the neural network 600, and determine the analysis data one by one. Finally, through the connected layer Ly (connected layer), a set of logical feature vectors LSH (binary vector) is generated after analysis. The logical feature vector LSH can be used as a search command input to the memory device 200 to search for corresponding results in various types of memory databases TCAM1 to TCAM8 (such as terrestrial animals, aquatic animals, etc.). Images of rabbits). Since those in the field can understand the operation and analysis principles of neural networks, I will not repeat them here.

前述各實施例中的各項元件、方法步驟或技術特徵,係可相互結合,而不以本揭示內容中的文字描述順序或圖式呈現順序為限。The various elements, method steps, or technical features in the foregoing embodiments can be combined with each other, and are not limited to the order of description or presentation of figures in the present disclosure.

雖然本揭示內容已以實施方式揭露如上,然其並非用以限定本揭示內容,任何熟習此技藝者,在不脫離本揭示內容之精神和範圍內,當可作各種更動與潤飾,因此本揭示內容之保護範圍當視後附之申請專利範圍所界定者為準。Although the content of this disclosure has been disclosed in the above manner, it is not intended to limit the content of this disclosure. Anyone who is familiar with this technique can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection of the content shall be subject to the scope of the attached patent application.

100:記憶單元 110:第一電路 120:第二電路 200:記憶體裝置 600:神經網路 T1:第一開關元件 T2:第二開關元件 R1:第一電阻元件 R2:第二電阻元件 S301-S309:步驟 ML:匹配線 SL1:搜索線 BL:字元線 Ts:源極 Td:汲極 Tg:閘極 Tb:基極 Tf:浮動閘極 Ti:絕緣層 Te:介電層 Tm:金屬層 L1:曲線 Ln:曲線 H1:曲線 Hn:曲線 LRS:低阻抗狀態 HRS:高阻抗狀態 ORS:初始阻抗狀態 TCAM1-TCAM8:記憶資料庫 CV1-CV4:神經分析單元 Ly:連接層 LSH:邏輯特徵向量100: memory unit 110: The first circuit 120: second circuit 200: Memory device 600: Neural Network T1: the first switching element T2: second switching element R1: the first resistance element R2: second resistance element S301-S309: steps ML: match line SL1: search line BL: character line Ts: source Td: drain Tg: gate Tb: base Tf: floating gate Ti: insulating layer Te: Dielectric layer Tm: Metal layer L1: Curve Ln: Curve H1: Curve Hn: Curve LRS: low impedance state HRS: high impedance state ORS: initial impedance state TCAM1-TCAM8: Memory database CV1-CV4: Neural Analysis Unit Ly: connection layer LSH: Logical feature vector

第1A圖為根據本揭示內容之部份實施例之記憶單元的示意圖。 第1B圖為根據本揭示內容之部份實施例之記憶體裝置的示意圖。 第2A圖為根據本揭示內容之部份實施例之記憶單元的等效電路圖。 第2B圖為根據本揭示內容之部份實施例之開關元件的半導體結構示意圖。 第3圖為根據本揭示內容之部份實施例之記憶單元操作方法的步驟流程圖。 第4圖為根據本揭示內容之部份實施例之記憶單元之阻抗特性圖。 第5圖為根據本揭示內容之部份實施例之第一電路/第二電路的半導體結構示意圖。 第6圖為根據本揭示內容之部份實施例之記憶單元的應用示意圖。 FIG. 1A is a schematic diagram of a memory cell according to some embodiments of the present disclosure. FIG. 1B is a schematic diagram of a memory device according to some embodiments of the present disclosure. FIG. 2A is an equivalent circuit diagram of a memory cell according to some embodiments of the present disclosure. FIG. 2B is a schematic diagram of the semiconductor structure of the switching element according to some embodiments of the present disclosure. FIG. 3 is a flow chart of the steps of the memory unit operation method according to some embodiments of the present disclosure. FIG. 4 is an impedance characteristic diagram of a memory cell according to some embodiments of the present disclosure. FIG. 5 is a schematic diagram of the semiconductor structure of the first circuit/second circuit according to some embodiments of the present disclosure. FIG. 6 is a schematic diagram of the application of the memory unit according to some embodiments of the present disclosure.

國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic deposit information (please note in the order of deposit institution, date and number) no Foreign hosting information (please note in the order of hosting country, institution, date and number) no

S301-S309:步驟 S301-S309: steps

Claims (10)

一種記憶單元操作方法,包含: 在一資料寫入期間,導通一記憶單元之一第一開關元件,以從與該記憶單元電性連接之一匹配線接收一第一資料寫入電壓,使得與該第一開關元件串聯連接之一第一電阻元件具有對應於該第一資料寫入電壓之一第一阻抗值;以及 在該資料寫入期間,關斷該記憶單元之一第二開關元件,使得與該第二開關元件串聯連接之一第二電阻元件與該匹配線之間保持斷路並具有一第二阻抗值,其中該第二阻抗值大於該第一阻抗值。 A method for operating a memory cell includes: during a data writing period, turning on a first switching element of a memory cell to receive a first data writing voltage from a matching line electrically connected to the memory cell, so that A first resistance element of the first switch element connected in series has a first impedance value corresponding to the first data writing voltage; and During the data writing period, a second switching element of the memory cell is turned off, so that a second resistance element connected in series with the second switching element remains open and has a second impedance value between the matching line and the matching line. The second impedance value is greater than the first impedance value. 如請求項1所述之記憶單元操作方法,還包含: 在該第二開關元件未曾被電流貫穿的情況下,進入一資料搜索期間; 在該資料搜索期間,根據一搜索指令控制該第一開關元件及該第二開關元件的導通及關斷;以及 判斷該匹配線上的電壓變化。 The operating method of the memory unit according to claim 1, further comprising: entering a data search period when the second switch element has not been penetrated by current; During the data search, controlling the on and off of the first switching element and the second switching element according to a search command; and Determine the voltage change on the matching line. 如請求項1所述之記憶單元操作方法,還包含: 在該資料寫入期間,在該第一開關元件導通的情況下,該第一開關元件從該匹配線接收一第二資料寫入電壓;以及 在該資料寫入期間,該第一開關元件從該匹配線再次接收該第一資料寫入電壓。 The operating method of the memory unit as described in claim 1, further comprising: During the data writing period, when the first switching element is turned on, the first switching element receives a second data writing voltage from the match line; and During the data writing period, the first switch element receives the first data writing voltage from the match line again. 如請求項3所述之記憶單元操作方法,其中該第一開關元件透過該匹配線反覆接收該第一資料寫入電壓及該第二資料寫入電壓,直到該第一開關元件接收該第一資料寫入電壓時,該第一電阻元件之阻抗值等於或低於一阻抗門檻值。The memory cell operation method of claim 3, wherein the first switching element repeatedly receives the first data writing voltage and the second data writing voltage through the match line until the first switching element receives the first When the data is written into the voltage, the impedance of the first resistance element is equal to or lower than an impedance threshold. 如請求項4所述之記憶單元操作方法,其中在該資料寫入期間,該匹配線上切換該第一資料寫入電壓及該第二資料寫入電壓的次數大於8次。The memory cell operation method according to claim 4, wherein during the data writing period, the number of switching the first data writing voltage and the second data writing voltage on the match line is greater than 8 times. 一種記憶單元操作方法,包含: 在一資料寫入期間,透過一匹配線對一記憶單元中之一第一電阻元件施加一第一資料寫入電壓,使該第一電阻元件具有對應於該第一資料寫入電壓之一第一阻抗值,其中該匹配線係電性連接於該第一電阻元件;以及 在該資料寫入期間,維持該記憶單元之一第二電阻元件與該匹配線間之斷路,使該第二電阻元件在無電流通過的情況下具有一第二阻抗值,其中該匹配線係電性連接於該第二電阻元件,該第二阻抗值大於該第一阻抗值。 An operating method of a memory cell includes: during a data writing period, applying a first data writing voltage to a first resistance element in a memory cell through a match line, so that the first resistance element has a value corresponding to the first resistance element A first impedance value of a data writing voltage, wherein the matching line is electrically connected to the first resistance element; and During the data writing period, the open circuit between the second resistance element of the memory cell and the matching line is maintained, so that the second resistance element has a second impedance value under the condition that no current flows, wherein the matching line is Electrically connected to the second resistance element, the second impedance value is greater than the first impedance value. 如請求項6所述之記憶單元操作方法,還包含: 導通該記憶單元中與該第一電阻元件相串聯之一第一開關元件;以及 關斷該記憶單元中與該第二電阻元件相串聯之一第二開關元件。 The operating method of the memory unit as described in claim 6, further comprising: Turn on a first switching element in the memory cell connected in series with the first resistance element; and Turning off a second switch element in the memory cell connected in series with the second resistance element. 如請求項7所述之記憶單元操作方法,還包含: 在該第二開關元件未曾被電流貫穿的情況下,進入一資料搜索期間; 在該資料搜索期間,根據一搜索指令控制該第一開關元件及該第二開關元件的導通及關斷;以及 判斷該匹配線上的電壓變化。 The operating method of the memory unit as described in claim 7, further comprising: When the second switching element has not been penetrated by current, enter a data search period; During the data search, controlling the on and off of the first switching element and the second switching element according to a search command; and Determine the voltage change on the matching line. 如請求項7所述之記憶單元操作方法,還包含: 在該資料寫入期間,在該第一開關元件導通的情況下,該第一開關元件從該匹配線接收一第二資料寫入電壓;以及 在該資料寫入期間,該第一開關元件從該匹配線再次接收該第一資料寫入電壓。 The operating method of the memory unit as described in claim 7, further comprising: During the data writing period, when the first switching element is turned on, the first switching element receives a second data writing voltage from the match line; and During the data writing period, the first switch element receives the first data writing voltage from the match line again. 如請求項9所述之記憶單元操作方法,其中該第一開關元件透過該匹配線反覆接收該第一資料寫入電壓及該第二資料寫入電壓,直到該第一開關元件接收該第一資料寫入電壓時,該第一電阻元件之阻抗值等於或低於一阻抗門檻值。The memory cell operating method according to claim 9, wherein the first switching element repeatedly receives the first data writing voltage and the second data writing voltage through the match line until the first switching element receives the first When the data is written into the voltage, the impedance of the first resistance element is equal to or lower than an impedance threshold.
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