TW202141488A - Memory unit operation method - Google Patents

Abstract

The present disclosure relates to a memory unit operation method. During a writing period, a first switching element in a memory unit is turned on to receive a first data writing voltage through a matching line electrically coupled to the memory unit, so that a first resistance element electrically coupled to the first switching element in series has a first impedance value corresponding to the first data writing voltage. During the writing period, a second switching element in the memory unit is turned off, so that a second resistance element electrically coupled to the second switching element in series remains disconnected from the matching line, and have a second impedance value. The second impedance value is greater than the first impedance value.

Description

Memory unit operation method

The present disclosure relates to a method for operating a memory cell, particularly a technology capable of setting different impedance values in the memory cell to store different logic signals.

As computers get faster and faster, the requirements for memory speed and stability are getting higher and higher. In recent years, there have been more and more discussions on the design of non-volatile memory. There are many types of non-volatile memory, including phase change memory, resistive memory, magnetoresistive memory, and so on. However, the above-mentioned memory may be caused by excessively high operating temperatures in some processes (such as reflow processes, etc.), which may cause errors in data in the memory.

The present disclosure relates to a method for operating a memory cell, which includes the following steps: during a data writing period, a first switching element of the memory cell is turned on to receive a first data writing voltage from a match line electrically connected to the memory cell, so that The first resistance element connected in series with the first switching element has a first impedance value corresponding to the first data writing voltage. During the data writing period, the second switching element of the memory cell is turned off, so that the second resistance element connected in series with the second switching element and the matching line remain open and have a second impedance value. The second impedance value is greater than the first impedance value.

The present disclosure also relates to a method for operating a memory cell, which includes the following steps: during a data writing period, applying a first data writing voltage to a first resistance element in the memory cell through a matching line, so that the first resistance element has a first resistance element corresponding to the first resistance element A first impedance value of the data writing voltage. The matching line is electrically connected to the first resistance element. During the data writing period, the open circuit between the second resistance element of the memory cell and the matching line is maintained, so that the second resistance element has a second impedance value when no current flows. The matching line is electrically connected to the second resistance element. The second impedance value is greater than the first impedance value.

Accordingly, since the second impedance value is much larger than the first impedance value, when the data search is subsequently performed, the memory cell matching the search result will be able to maintain a high impedance to maintain the voltage on the matching line. In addition, the memory cell that does not match the search result has a low voltage, which causes a significant change in the voltage on the matching line to improve the search accuracy.

Hereinafter, a plurality of embodiments of the present invention will be disclosed in drawings. For clear description, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are unnecessary. In addition, in order to simplify the drawings, some conventionally used structures and elements are shown in the drawings in a simple and schematic manner.

In this text, when an element is referred to as “connected” or “coupled”, it can be referred to as “electrically connected” or “electrically coupled”. "Connected" or "coupled" can also be used to mean that two or more components cooperate or interact with each other. In addition, although terms such as “first”, “second”, etc. are used herein to describe different elements, the terms are only used to distinguish elements or operations described in the same technical terms. Unless the context clearly indicates, the terms do not specifically refer to or imply order or sequence, nor are they used to limit the present invention.

The present disclosure relates to an operating method of a memory unit. 1A is a schematic diagram of a memory cell 100 (memory cell) according to some embodiments of the present disclosure. As shown in FIG. 1A, the memory cell 100 is used to electrically connect to the match line ML and the search lines SL1 and SL2. The logic levels of the search lines SL1 and SL2 are opposite to each other (that is, when the search line SL1 has an enable When the voltage is at the level, the search line SL2 has the level of the disable voltage).

1B is a schematic diagram of the memory device 200 according to some embodiments of the present disclosure. As shown in FIG. 1B, the memory device 200 includes a plurality of memory cells 100 as shown in FIG. 1A, and a plurality of match lines ML and search lines SL1 and SL2 are connected to the corresponding memory cells 100. In some embodiments, the above-mentioned multiple memory cells 100 are arranged in the memory device 200 in an array form to store various data (such as routing tables).

In one embodiment, when the memory device 200 performs a data write operation (hereinafter referred to as "data write period"), the match line ML is used to be charged to a specific write voltage to adjust the memory cell Impedance characteristics within 100. Different impedance characteristics will correspond to different logic signals. In one embodiment, when the memory device 200 performs a data search (hereinafter referred to as "data search period"), the search lines SL1 and SL2 provide corresponding disable or enable voltages to the memory cell 100 to Control the on or off of different paths in the memory unit 100. Accordingly, according to the voltage change on the match line ML, the memory device 200 can determine whether the logic signal stored in the memory cell 100 matches the information to be searched in the search command (hereinafter referred to as the “search target”).

FIG. 2A is a schematic diagram of an equivalent circuit of the memory cell 100 according to some embodiments of the present disclosure. In an embodiment, the memory unit 100 is a Ternary Content Addressable Memory (Ternary Content Addressable Memory, TCAM), which can be used in a network router, but the present disclosure is not limited to this. Since those skilled in the art can understand the structure and principle of tri-state content addressable memory and memory device, it will not be described in detail here.

As shown in FIG. 2A, the memory unit 100 includes a first circuit 110 and a second circuit 120. The first circuit 110 and the second circuit 120 are electrically connected between the match line ML and the word line BL. In one embodiment, the word line BL is connected to a reference potential (eg, ground voltage). The first circuit 110 includes a first switching element T1 and a first resistance element R1. The second circuit 120 includes a second switching element T2 and a second resistance element R2. The matching line ML is electrically connected to one end of the first resistance element R1 and one end of the second resistance element R2, respectively. The first switching element T1 is connected in series with the first resistance element R1, and the second switching element T2 is connected in series with the second resistance element R2. The first circuit 110 and the second circuit 120 are connected in parallel.

FIG. 2B is a schematic diagram of the semiconductor structure of the switching element according to some embodiments of the present disclosure. In one embodiment, the semiconductor structure shown in FIG. 2B can be used to realize the first switching element T1 and/or the second switching element T2 shown in FIG. 2A, but the present case is not limited to this. As shown in FIG. 2B, the semiconductor structure of the switching element includes a gate Tg, a drain Td, and a source Ts. When the gate Tg receives the enabling voltage, a conduction path can be formed between the drain Td and the source Ts, and conduction currents of different magnitudes are formed according to the voltage difference between the drain Td and the source Ts.

In different embodiments, the first resistance element R1 shown in FIG. 2A can also be formed in the first switching element T1. For example, the first resistance element R1 can be realized by a semiconductor structure with a specific impedance value in the first switching element T1 (the detailed structure will be described in subsequent paragraphs). That is, the first resistance element R1 and the first switching element T1 can be integrated in the same transistor structure. For ease of description, in Figure 2A, the two elements are shown separately. The first switching element T1 is regarded as an ideal switching element, the first resistive element R1 is the impedance part of the first circuit 110, and the first resistive element The impedance value of R1 will change according to the voltage across the first circuit 110 (or the first switching element T1).

Corresponding to the above embodiment, in different embodiments, the second resistance element R2 shown in Figure 2A can also be formed in the second switching element T2, and the impedance value of the second resistance element R2 will be based on the second circuit 120 ( Or the cross voltage of the second switching element T2) changes.

In operation, during the data writing period, the match line ML is charged to the first data writing voltage, and the first circuit 110 is turned on, so that the first resistance element R1 has a first resistance value corresponding to the first data writing voltage. In other words, the impedance value of the first resistance element R1 is changed according to the first data write voltage that turns on the first circuit 110, from the initial impedance value to the first impedance value. In some embodiments, the first data writing voltage is a relatively low voltage. In some embodiments, the first data writing voltage is 1 to 4 volts, but the present disclosure is not limited to this. The value of the first data writing voltage may be based on the material, manufacturing process, or other parameters of the actual memory. And adjust.

In some embodiments, when the match line ML is charged to the first data writing voltage, the first switching element T1 is turned on and the second switching element T2 is turned off, so that the first switch on the first circuit 110 responds to the conduction The element T1 and the first write voltage form a first current.

At the same time, during the data writing period and when the matching line ML has the first data writing voltage, the second resistance element R2 and the matching line ML maintain an open state, so that the second circuit 120 will not be affected by the first data writing voltage. Generate current. At this time, the second resistance element R2 has a second resistance value when no current flows, and the second resistance value will be much larger than the first resistance value. In some embodiments, the second switching element T2 is always turned off during the data writing period to ensure that no current is generated on the second circuit 120 and the second switching element T2 is never penetrated by current.

For ease of description, the first resistance value formed by the first resistance element R1/second resistance element R2 (or the first circuit 110/the second circuit 120) corresponding to the first data writing voltage is referred to herein as "low impedance". State (Low Resistance State)”, and the second impedance value is called the “initial impedance state”. As described in the foregoing embodiment, when the first circuit 110 is in the low impedance state and the second circuit is in the initial impedance state, the logic signal "0" can be recorded. In contrast, if the first circuit 110 is in the initial impedance state and the second circuit is in the low impedance state, the logic signal "1" can be recorded. If both the first circuit 110 and the second circuit 120 are in the initial impedance state, it corresponds to the logic signal "X (don't care)", which means that it can be ignored during search.

When the memory device 200 performs a data search operation (hereinafter referred to as "data search period"), the search lines SL1 and SL2 are controlled at the enable level or the disable level according to the search command to control the first switching element T1 And the second switching element T2 is turned on and off. By judging the voltage change on the matching line ML, the memory device 200 can confirm whether the logic signal stored in the memory cell 100 is the search target. In one embodiment, if the logic signal stored in the memory cell 100 is indeed the search target, one of the first circuit 110 and the second circuit 120 will remain open due to the disablement of the search line (SL1 or SL2) , The other of the first circuit 110 and the second circuit 120 will have a high impedance characteristic of the "initial impedance state", so that there is almost no voltage change on the matching line ML. The present disclosure utilizes the high impedance characteristic of the second resistance element R2 (or the semiconductor structure in the second switching element T2, which will be described in detail in subsequent paragraphs) when the second resistance element R2 has not been penetrated by current to ensure that the matching line ML is at When the correct target is searched, no leakage voltage is generated, and unnecessary power consumption of the memory device 200 is avoided.

On the other hand, since there is a sufficiently large impedance difference between the "first impedance value (low impedance state)" and the "second impedance value (initial impedance state)", during the data search period, the memory cell 100 of the search target is matched. Between the memory cell 100 that does not match the search target, there will be a very significant difference in the voltage change on the matching line ML due to the obvious difference in impedance, thereby improving the accuracy of the memory device 200 during data search. .

The "data writing procedure" of the memory unit 100 is described here as follows. Figure 3 is a flow chart of the steps of the data writing procedure. For the convenience and clarity of the description of FIG. 3 below, the embodiment shown in FIG. 2A is used in conjunction with FIG. 3 for description. However, the application of the embodiment shown in FIG. 3 is not limited to the embodiment shown in FIG. 2A.

In step S301, the processor (not shown in the figure) in the memory device 200 determines whether the level of the logic signal to be written in the write command is "1", "0" or "X (don't care)" ". When the processor in the memory device 200 determines that the logic signal to be written is "0", step S302 is executed, and the processor charges the match line ML to the first data write voltage. In step S303, the first switching element T1 is turned on, so that the first resistance element R1 has a first impedance value corresponding to the first data writing voltage, and a "low impedance state" is formed on the first circuit 110.

In step S304, during the data writing period, the second switching element T2 is kept turned off, so that the second resistance element R2 and the match line ML are kept disconnected. At this time, no current is generated on the second circuit 120 or the second resistance element R2. In addition, since the second resistance element R2 has not been penetrated by the current and has the second impedance value, the second circuit 120 can be formed into an "initial impedance state".

When the processor in the memory device 200 determines that the logic signal to be written is "1", step S305 is executed. The processor charges the match line ML to the first data writing voltage. In step S306, the second switching element T2 is turned on, so that the second resistance element R2 has a first impedance value corresponding to the first data writing voltage, and a "low impedance state" is formed on the second circuit 120.

In step S307, during the data writing period, the first switching element T1 is kept turned off, so that the first resistance element R1 and the match line ML are kept disconnected. At this time, the first resistance element R1 has a second impedance value because no current flows through it, and the first circuit 110 is formed into an "initial impedance state".

When it is determined that the logic signal to be written is "X", step S308 is executed. During the data writing period, the first switching element T1 is kept off, so that the first resistance element R1 and the matching line ML are kept open. At this time, the first resistance element R1 has a second impedance value because no current flows through it, and an "initial impedance state" is formed on the first circuit 110.

Similarly, in step S309, the second switching element T2 is turned off, so that the second resistance element R2 and the matching line ML are kept open. At this time, the second resistance element R2 has a second impedance value because no current flows through it, and an "initial impedance state" is formed on the second circuit 120.

In one embodiment, the memory cell 100 uses the "initial impedance state" characteristic of having a high impedance when it is not turned on as the characteristic of the memory logic signal. Therefore, when the memory unit 100 is applied to a "write-once" memory, it can have a better storage effect.

Please refer to FIG. 4, which is a characteristic diagram of the semiconductor structure corresponding to the first circuit 110/the second circuit 120. Among them, the horizontal axis of Figure 4 is the impedance value, and the vertical axis is the probability of the corresponding impedance value (in this embodiment, the vertical axis value is the cumulative percentage of the number calculated after multiple tests). According to different impedance characteristics, the switching element has "low impedance state LRS", "high impedance state HRS" and "initial impedance state ORS". The “low impedance state LRS” refers to the first impedance value (for example, 10 ³ -10 ⁵ ohms) of the corresponding resistance element when the switching element is turned on in response to the first data writing voltage. ^{"High-impedance state HRS" refers to the third impedance value (such as 10 5} ～10 ⁸ ohms) of the corresponding resistance element when the switching element is turned on in response to the second data writing voltage, where the second data writing voltage is relatively The voltage for writing the first data is a high voltage. In some embodiments, the second data writing voltage is -1 to -2 volts, but the present disclosure is not limited to this. The value of the second data writing voltage can be based on the material used to actually make the memory , Manufacturing process or other parameters. The "initial impedance state ORS" is the second impedance value (such as 10 ⁹ ～10 ¹⁰ ohms) exhibited by the corresponding resistance element when the switching element has not been turned on. According to the difference in the manufacturing process, the first impedance value, the second impedance value, and the third impedance value will not be a fixed value, but an impedance range. As shown in Figure 4, the third impedance value corresponding to the "high impedance state HRS" is between the first impedance value corresponding to the "low impedance state LRS" and the second impedance value corresponding to the "initial impedance state ORS". The "initial impedance state ORS" has the highest impedance characteristics.

As shown in the characteristic diagram in Fig. 4, the curve L1 is the impedance characteristic of the corresponding resistive element when the switching element is turned on for the first time in response to the first data writing voltage. The curve H1 is the impedance characteristic of the corresponding resistance element when the switch element is turned on in response to the first data writing voltage and then is turned on for the second time in response to the second data writing voltage. It can be seen from Figure 4 that when the voltage on the match line ML is controlled to switch between the first data writing voltage and the second data writing voltage, the circuit in the memory cell 100 is repeatedly in the "high impedance state HRS" and " In the initial impedance state ORS", the impedance characteristics will also change accordingly. The curve Ln is the impedance characteristic of the corresponding resistance element when the switch element is turned on for the Nth time in response to the first data writing voltage.

In addition, as shown in FIG. 4, the curve Hn is the impedance characteristic of the corresponding resistance element when the switch element is turned on for the Nth time in response to the second data writing voltage. After many times of switching, the curve will gradually change in the direction of lower impedance. In one embodiment, if the first switching element T1 needs to be controlled in the "low impedance state", the first switching element T1 repeatedly receives the first data writing voltage and the second data writing voltage through the match line ML, until the first a first data switching element T1 receives the write voltage, the resistance value of the first resistor element R1 is equal to or lower than the threshold impedance (eg: ¹⁰⁴ ohms). In other words, the first circuit 110 will be repeatedly controlled between the "high impedance state HRS" and the "low impedance state LRS". The specific method is: during the data writing period, the first switching element T1 responds to the first data writing voltage When turned on, the voltage on the match line ML is adjusted to the second data writing voltage, so that the first switching element T1 receives the second data writing voltage. Then, the voltage on the match line ML is adjusted back to the first data writing voltage again, so that the first switching element T1 receives the first data writing voltage again. Perform N times repeatedly according to the foregoing steps. In one embodiment, N is a positive integer greater than 8. That is, the number of times that the match line ML switches the first data writing voltage and the second data writing voltage is greater than 8 times. The curve Ln shown in FIG. 4 is the characteristic curve of the corresponding resistance element when the switching element is responsive to the first data writing voltage for the tenth time.

Please refer to FIG. 5. FIG. 5 is a schematic diagram of a semiconductor structure of another embodiment of the switching element of the first circuit 110 and/or the second circuit 120 in the memory cell 100. In an embodiment, the aforementioned switching element includes a gate Tg, a drain Td, and a source Ts. Among them, the gate Ts also includes a floating gate Tf, and the floating gate Tf is located between the two insulating layers Ti. The drain electrode Td and the source electrode Ts are provided with a metal layer Tm. In addition, as mentioned above, resistance elements may be formed in the semiconductor structure at the same time. As shown in Figure 5, a dielectric layer Te is provided on the drain electrode Td. The dielectric layer Te has a specific resistance value, and can be used as the first resistance element R1 and/or the second resistance element R2 in the foregoing embodiment, or as the first resistance element R1 and/or the second resistance element R2 in the foregoing embodiment At least part of the semiconductor structure. For example, when the first data writing voltage or the second data writing voltage is applied to the first circuit 110/the second circuit 120, the dielectric layer Te will be penetrated to form a low impedance state LRS.

Here, the "data search procedure" of the memory unit 100 is further illustrated as follows. As in the foregoing steps, the memory unit 100 records logical signals according to the following characteristics: Stored logic signal First circuit Second circuit 0 LRS ORS 1 ORS LRS X ORS ORS

In one embodiment, according to different search targets, the search lines SL1 and SL2 will adjust the enable voltage or disable voltage according to the following table to turn on or turn off the corresponding switching element: Search target SL1 SL2 0 Disable Enable 1 Enable Disable

As shown in the above two tables, during data search, when the memory device 200 determines that the search target in the search command is "0", the search line SL1 will turn off the first switching element T1 and the search line SL2 will turn on The second switching element T2. If the logic signal stored in the memory unit 100 matches the search target (ie, "0"), the first circuit 110 and the second circuit 120 are in the low impedance state LRS and the initial impedance state ORS, respectively. At this time, although the second switching element T2 is turned on, since the second circuit 120 is in the initial impedance state ORS and has a very high resistance, there is no significant voltage change on the matching line ML, which enables the memory device 200 The memory unit 100 storing the search target is accurately searched out. In addition, since the voltage value on the match line ML during the data search period is less than the voltage charged during the data writing period (ie, the first data writing voltage or the second data writing voltage), the second switching element T2 (such as: The dielectric layer Te in Figure 5 will not destroy the initial impedance characteristics due to current penetration, so that the second switching element T2 can maintain the initial impedance state ORS.

On the other hand, if the search target of the search command is "0", but the logic signal stored in the memory unit 100 does not match the search target (ie, "1"), at this time, the second switching element T2 will also be turned on , But the second circuit 120 is in a low impedance state LRS and has a low resistance. Therefore, the matching line ML will produce a significant voltage change, so that the memory cell 200 can easily distinguish the search result of "not matching".

Please refer to FIG. 6, which is a schematic diagram of the application of the memory unit in some embodiments of the disclosure. The memory device 200 includes a plurality of memory cells 100, and the memory cells 100 can form a plurality of memory data banks TCAM1 to TCAM8. In one embodiment, the memory database TCAM1 to TCAM8 are used to store the database corresponding to the neural network, respectively storing different types of data. Since the memory unit 100 is used as a database, the data writing process only needs to be executed once.

For example, when the neural network 600 receives the analysis data to be compared (such as an image of an animal), the analysis data will pass through the multi-layer neural analysis units CV1 to CV4 of the neural network 600, and judge the analysis data one by one. The feature vector of, and finally through the connected layer Ly (connected layer) to generate a set of logical feature vector LSH (binary vector) after analysis. The logical feature vector LSH can be used as a search command input to the memory device 200 to search for corresponding results (such as: Images of rabbits). Since those in the field can understand the operation and analysis principles of neural networks, I will not repeat them here.

The various elements, method steps, or technical features in the foregoing embodiments can be combined with each other, and are not limited to the order of description or presentation of figures in the present disclosure.

Although the content of this disclosure has been disclosed in the above manner, it is not intended to limit the content of this disclosure. Anyone who is familiar with this technique can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection of the content shall be subject to the scope of the attached patent application.

100: memory unit 110: The first circuit 120: second circuit 200: Memory device 600: Neural Network T1: The first switching element T2: second switching element R1: the first resistance element R2: second resistance element S301-S309: steps ML: match line SL1: search line BL: character line Ts: source Td: drain Tg: gate Tb: base Tf: floating gate Ti: insulating layer Te: Dielectric layer Tm: Metal layer L1: Curve Ln: Curve H1: Curve Hn: Curve LRS: Low impedance state HRS: High impedance state ORS: initial impedance state TCAM1-TCAM8: Memory database CV1-CV4: Neural Analysis Unit Ly: connection layer LSH: Logical feature vector

FIG. 1A is a schematic diagram of a memory cell according to some embodiments of the present disclosure. FIG. 1B is a schematic diagram of a memory device according to some embodiments of the present disclosure. FIG. 2A is an equivalent circuit diagram of a memory cell according to some embodiments of the present disclosure. FIG. 2B is a schematic diagram of the semiconductor structure of the switching element according to some embodiments of the present disclosure. FIG. 3 is a flow chart of the steps of the memory unit operation method according to some embodiments of the present disclosure. FIG. 4 is an impedance characteristic diagram of a memory cell according to some embodiments of the present disclosure. FIG. 5 is a schematic diagram of the semiconductor structure of the first circuit/second circuit according to some embodiments of the present disclosure. FIG. 6 is a schematic diagram of the application of the memory unit according to some embodiments of the present disclosure.

Domestic deposit information (please note in the order of deposit institution, date and number) none Foreign hosting information (please note in the order of hosting country, institution, date, and number) none

S301-S309: steps

Claims (10)

An operating method of a memory cell includes: during a data writing period, turning on a first switching element of a memory cell to receive a first data writing voltage from a matching line electrically connected to the memory cell, so that the A first resistance element of the first switch element connected in series has a first impedance value corresponding to the first data writing voltage; and During the data writing period, a second switching element of the memory cell is turned off, so that a second resistance element connected in series with the second switching element remains open and has a second impedance value between the matching line and the matching line. The second impedance value is greater than the first impedance value. The operating method of the memory unit according to claim 1, further comprising: entering a data search period when the second switch element has not been penetrated by current; During the data search, controlling the on and off of the first switching element and the second switching element according to a search command; and Determine the voltage change on the matching line. The operating method of the memory unit as described in claim 1, further comprising: During the data writing period, when the first switching element is turned on, the first switching element receives a second data writing voltage from the match line; and During the data writing period, the first switch element receives the first data writing voltage from the match line again. The memory cell operation method of claim 3, wherein the first switching element repeatedly receives the first data writing voltage and the second data writing voltage through the match line until the first switching element receives the first When the data is written into the voltage, the impedance value of the first resistance element is equal to or lower than an impedance threshold value. The memory cell operation method according to claim 4, wherein during the data writing period, the number of times of switching the first data writing voltage and the second data writing voltage on the match line is greater than 8 times. A method for operating a memory cell includes: during a data writing period, applying a first data writing voltage to a first resistance element in a memory cell through a match line, so that the first resistance element has a value corresponding to the first resistance element A first impedance value of a data write voltage, wherein the matching line is electrically connected to the first resistance element; and During the data writing period, the open circuit between the second resistance element of the memory cell and the matching line is maintained, so that the second resistance element has a second impedance value under the condition that no current flows, wherein the matching line is It is electrically connected to the second resistance element, and the second impedance value is greater than the first impedance value. The operating method of the memory unit as described in claim 6, further comprising: Turn on a first switching element in the memory cell connected in series with the first resistance element; and Turning off a second switching element in the memory cell connected in series with the second resistance element. The operating method of the memory unit as described in claim 7, further comprising: When the second switch element has not been penetrated by current, enter a data search period; During the data search, controlling the on and off of the first switching element and the second switching element according to a search command; and Determine the voltage change on the matching line. The operating method of the memory unit as described in claim 7, further comprising: During the data writing period, when the first switching element is turned on, the first switching element receives a second data writing voltage from the match line; and During the data writing period, the first switch element receives the first data writing voltage from the match line again. The memory cell operation method according to claim 9, wherein the first switching element repeatedly receives the first data writing voltage and the second data writing voltage through the match line until the first switching element receives the first When the data is written into the voltage, the impedance value of the first resistance element is equal to or lower than an impedance threshold value.

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