TWI812189B - Power supply and electronic system - Google Patents

Abstract

A power supply and an electronic system are provided. The power supply includes a driver, a transducer and a controller. The driver provides a switching signal in response to an activating signal. When an electronic device is at a standby state, the controller provides the activating signal with a first frequency, based on a low-device voltage provided by the electronic device and a sensing voltage associated with an output power. When the electronic device is at a power-on state, the controller provides the activating signal with a second frequency, based on a high-device voltage provided by the electronic device and the sensing voltage. Then, the controller makes the activating signal be discharged, so as that the output power is provided to the electronic device.

Description

Power supplies and electronic systems

The present invention relates to a power supply and an electronic system, and in particular to a power supply and an electronic system with low standby loss.

Current power supplies can be embedded in electronic devices (eg, computers). The embedded power supply starts or stops providing power to the electronic device based on a startup signal generated by the electronic device. However, the electronic device still needs to output a high-voltage startup signal to the power supply during standby to drive the power supply to perform corresponding operations, so that the electronic device still generates energy loss during standby.

Embodiments of the present invention provide a power supply and an electronic system, which can reduce the power consumption of an electronic device in a standby state.

The power supply according to the embodiment of the present invention includes a driver, a converter and a controller. The driver provides the first switching signal in response to the enable signal at a low voltage level. The converter is coupled to the driver. The converter generates output power. The controller is coupled to the electronic device and the driver. When the electronic device is in a standby state, the electronic device provides a low device voltage. When the electronic device is powered on, the electronic device provides a high device voltage. When the electronic device is in the standby state, the controller provides the activation signal with the first frequency based on the low device voltage and the sensing voltage associated with the output power supply. When the electronic device enters the power-on state from the standby state, the controller provides the startup signal with the second frequency based on the high device voltage and the sensing voltage. Subsequently, the controller discharges the startup signal to a low voltage level, causing the converter to respond to the first switching signal to provide output power to the electronic device.

An embodiment of the present invention further provides an electronic system. Electronic systems include electronic devices and power supplies. When the electronic device is in a standby state, the electronic device provides a low device voltage. When the electronic device is powered on, the electronic device provides a high device voltage. The power supply supplies power to the electronic device. Power supplies include drivers, converters and controllers. The driver provides the first switching signal in response to the enable signal at a low voltage level. The converter is coupled to the driver. The converter generates output power. The controller is coupled to the electronic device and the driver. The controller provides the activation signal with a first frequency based on a low device voltage from the electronic device and a sensed voltage associated with the output power supply. The controller provides the activation signal with the second frequency based on the high device voltage of the electronic device and the sensing voltage. Subsequently, the controller discharges the startup signal to a low voltage level, causing the converter to respond to the first switching signal to provide output power to the electronic device.

Based on the above, the power supply and the electronic system according to the embodiments of the present invention can provide non-constant voltage signals with corresponding frequencies when the electronic device is in different states, so that the power supply and the electronic system can reduce the average energy loss.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Some embodiments of the present invention will be described in detail with reference to the accompanying drawings. The component symbols cited in the following description will be regarded as the same or similar components when the same component symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementations of the present invention. Rather, these embodiments are only examples within the scope of the patent application of the invention.

Please refer to FIG. 1 , which is a block diagram of an electronic system according to an embodiment of the present invention. In this embodiment, the electronic system 100 includes an electronic device DT and a power supply PS. The electronic device DT supplies power to the electronic device DT based on the input power supply VIN. The electronic device DT provides the low device voltage VF_L to the power supply PS when it is in a standby state (eg, a shutdown state or a hibernation state). When the electronic device DT is in a powered-on state, it provides the high device voltage VF_H to the power supply PS. That is, the electronic device DT can provide the device voltage VF_L or VF_H to indicate the current state (standby state or power-on state) of the electronic device DT. The low device voltage VF_L and the high device voltage VF_H have different voltage levels. The electronic device DT can be a mobile phone, a tablet computer, a notebook computer, a desktop computer, etc. In this embodiment, the power supply PS can be embedded in the electronic device DT.

In this embodiment, the power supply PS includes a driver 110, a converter 120 and a controller 130. The driver 110 responds to the enable signal PS_ON at a low voltage level to provide the switching signal GD. The converter 120 is coupled to the driver 110 . Converter 120 generates output power VO. The controller 130 is coupled to the electronic device DT and the driver 110 .

In this embodiment, when the electronic device DT is in the standby state, the controller 130 provides the startup signal PS_ON with the first frequency based on the low device voltage VF_L and the sensing voltage VOR associated with the output power VO. Therefore, the driver 110 does not provide the switching signal GD. The converter 120 does not provide the output power VO to the electronic device DT.

In this embodiment, when the electronic device DT enters the power-on state from the standby state, the controller 130 provides the start-up signal PS_ON with the second frequency based on the high device voltage VF_H and the sensing voltage VOR. Subsequently, the controller 130 discharges the start signal PS_ON to a low voltage level, so that the output power VO is provided to the electronic device DT. Furthermore, the driver 110 responds to the low voltage level of the enable signal PS_ON to provide the switching signal GD. The converter 120 responds to the switching signal GD to provide the output power VO to the electronic device DT.

In this embodiment, the first frequency is different from the second frequency. The first frequency is greater than the second frequency. In some embodiments, the first frequency is substantially equal to the second frequency.

It should be noted that the activation signal PS_ON is generated by the controller 130 and not from the electronic device DT. That is to say, the electronic device DT of this embodiment does not provide the high voltage level startup signal PS_ON when it is in standby or shut down. Therefore, the power consumption of the electronic device DT during standby or shutdown can be further reduced.

It is worth mentioning here that when the electronic device DT is in different states, the activation signal PS_ON is a non-constant voltage signal with a first frequency or a second frequency for the power supply PS to perform corresponding operations. The average voltage value of the start signal PS_ON can be reduced. In this way, when the electronic device DT is in the standby state, the power consumption of the power supply PS can be reduced.

Please refer to FIGS. 1 and 2 . FIG. 2 is a schematic diagram of the operation of the power supply PS when the electronic device DT enters the power-on state from the standby state according to the embodiment of FIG. 1 of the present invention. In FIG. 2 , the horizontal axis represents the operating time of the power supply PS, and the vertical axis represents the voltage value.

Before time point t1_1, the electronic device DT is in a standby state. At this time, the start signal PS_ON has the first frequency. The start signal PS_ON is a pulse signal with voltage value VA and voltage value VB. In this embodiment, voltage value VA is greater than voltage value VB, and both voltage values VA and VB are greater than zero. At this time, the output power VO received by the power input terminal of the electronic device DT has a zero voltage value.

At time point t1_1, the electronic device DT enters the pre-power-on state from the standby state. At this time, the start signal PS_ON switches from the first frequency to the second frequency.

During the period from time point t1_1 to time point t3_1, the electronic device DT is in a pre-power-on state. During this period, the start signal PS_ON has the second frequency. At time point t2_1, that is, after the electronic device DT is in the pre-power-on state for a period of time, the startup signal PS_ON is discharged and the voltage value of the startup signal PS_ON begins to decrease. After time point t2_1, the voltage value of the output power supply VO begins to rise.

It should be noted that before time point t2_1, the voltage level of the start signal PS_ON is pulled up to be greater than or equal to the voltage value VB. Therefore, before the time point t2_1, the driver 110 will not misoperate in providing the switching signal GD.

In this embodiment, when the electronic device DT is in the pre-power-on state, the waveform of the startup signal PS_ON is gradually pulled down to a zero voltage value. At this time, the power input end of the electronic device DT begins to receive the output power VO having the voltage value VOUT.

After time point t3_1, the electronic device DT has been completely powered on and is in a powered-on state. During this period, the voltage value of the start signal PS_ON is zero. The voltage value of the output power supply VO is maintained at the voltage value VOUT.

Please refer to FIG. 1 and FIG. 3. FIG. 3 is a schematic diagram of the operation of the power supply PS when the electronic device DT enters the standby state from the power-on state according to the embodiment of FIG. 1 of the present invention. In this embodiment, when the electronic device DT enters the standby state from the power-on state, the controller 130 provides the start-up signal PS_ON with the second frequency based on the low device voltage VF_L and the sensing voltage VOR. Subsequently, the controller 130 provides the activation signal PS_ON with the first frequency based on the low device voltage VF_L and the sensing voltage VOR, and the controller 130 stops providing the output power VO to the electronic device DT. In FIG. 3 , the horizontal axis represents the operating time of the power supply PS, and the vertical axis represents the voltage value.

At time point t1_2, the electronic device DT enters the pre-standby state from the power-on state. At this time, the start signal PS_ON has a second frequency (for example, twice the frequency). The voltage level of the start signal PS_ON starts to rise from the zero voltage value.

During the period from time point t1_2 to time point t3_2, the electronic device DT is in a pre-standby state. During this period, the frequency of the start signal PS_ON is maintained at the second frequency. First, during the period from time point t1_2 to time point t2_2, the waveform of the start signal PS_ON gradually rises from the zero voltage value. Then, at time point t2_2, that is, after the electronic device DT has been in the pre-standby state for a period of time, the waveform of the start signal PS_ON is maintained between the voltage values VA and VB. At this time, the power input terminal of the electronic device DT cannot receive the output power VO. Therefore, the voltage value VOUT of the output power supply VO will gradually decrease to the zero voltage value.

At time point t3_2, that is, after a period of time after the voltage value of the output power supply VO is equal to the zero voltage value, the electronic device DT enters the pre-standby state from the pre-standby state. At this time, the start signal PS_ON switches from the second frequency to the first frequency. After time point t3_2, the electronic device DT has been completely shut down and is in a standby state.

In some embodiments, during the period from time point t1_2 to time point t3_2, the frequency of the activation signal PS_ON is the first frequency.

The length of each period from time point t1_1 to time point t3_1, the length of each period from time point t1_2 to time point t3_2, and the configuration of the duty cycle of the start signal PS_ON in each period in the embodiments of FIG. 2 and FIG. 3 are only examples.

It is worth mentioning here that when the electronic device DT enters different states, the activation signal PS_ON can switch to different frequencies (ie, switching between the first frequency and the second frequency), so that the power supply PS decreases Electromagnetic Interference (EMI) phenomenon.

Please refer to FIG. 4 , which is a circuit diagram of an electronic system according to another embodiment of the present invention. In this embodiment, the electronic system 400 includes an electronic device DT and a power supply PS. The power supply PS includes a driver 410, a converter 420, and a controller 430.

In this embodiment, the driver 410 receives the activation signal PS_ON generated by the controller 430 . The driver 410 outputs the switching signals GD1 to GD3 to the converter 420 and the controller 430 to control the converter 420 and the controller 430 to perform corresponding operations.

In this embodiment, the converter 420 includes a rectifier 421, a transformer 422, a magnetizing inductor LM, a power switch Q1, an output diode DO, and an output capacitor CO. Rectifier 421 rectifies input power VIN to generate rectified power VR. In this embodiment, the rectifier 211 is a full-bridge rectifier. The configuration of the rectifier 421 in this embodiment is only an example. Any rectifier circuit capable of rectifying alternating current is within the scope of the present invention.

In this embodiment, the first terminal of the magnetizing inductor LM receives the rectified power supply VR. The second terminal of the magnetizing inductor LM is coupled to the first terminal of the power switch Q1. The second terminal of the power switch Q1 is coupled to the ground terminal GND1. The control terminal of the power switch Q1 is coupled to the driver 410 . The power switch Q1 is controlled by the driver 410 and performs switching operations according to the switching signal GD1 from the driver 410 . In this embodiment, the switching signals GD1 and GD2 may be the same signal.

In this embodiment, the primary side winding NP of the transformer 422 is coupled in parallel to the magnetizing inductor LM. The transformer 422 performs a transforming operation on the rectified power supply VR to generate the output power supply VO. The configuration of the transformer 422 in this embodiment is only an example. Any transformer circuit capable of transforming a power supply is within the scope of the present invention.

In this embodiment, the anode of the output diode DO is coupled to the first end of the secondary side winding NS of the transformer 422 . The cathode of the output diode DO is coupled to the first terminal of the output capacitor CO. The first terminal of the output capacitor CO serves as the output terminal of the converter 420 . The second terminal of the output capacitor CO is coupled to the second terminal of the secondary winding NS and the ground terminal GND2.

In this embodiment, the converter 420 is a flyback power converter with synchronous rectification function. However, the present invention is not limited to this. In some embodiments, the converter 420 may be implemented as a flyback power converter without synchronous rectification function. Based on different requirements, in some embodiments, the converter 420 may be implemented by at least one of a boost converter with improved power factor and an LLC resonant converter.

In this embodiment, the controller 430 provides the control signal CS_1 with the first frequency and the control signal CS_2 with the second frequency according to the switching signal GD2 from the driver 410 . The controller 430 includes a start signal generating unit 431, a selection circuit 432 and a discharge circuit 433. The start signal generating unit 431 is coupled to the selection circuit 432, the discharge circuit 433 and the driver 410. The selection circuit 432 is coupled to the electronic device DT and the driver 410 .

In this embodiment, the selection circuit 432 selects the control signal CS_1 with the first frequency according to the low device voltage VF_L. The selection circuit 432 provides the control signal CS_1 to the startup signal generating unit 431, so that the startup signal generating unit 431 provides the startup signal PS_ON with the first frequency to the discharging circuit 433 and the driver 410. On the other hand, the selection circuit 432 selects the control signal CS_2 with the second frequency according to the high device voltage VF_H. The selection circuit 432 provides the control signal CS_2 to the startup signal generating unit 431, so that the startup signal generating unit 431 provides the startup signal PS_ON with the second frequency to the discharging circuit 433 and the driver 410.

In this embodiment, the discharge circuit 433 is controlled by the selection circuit 432 to discharge the start signal PS_ON. Furthermore, when the high device voltage VF_H is provided, the selection circuit 432 controls the discharge circuit 433 to discharge the enable signal PS_ON.

In this embodiment, the controller 430 further includes signal generators 434~435. The signal generator 434 is coupled to the driver 410 and the selection circuit 432 . The signal generator 434 is controlled by the driver 410 and provides the control signal CS_1 according to the switching signal GD2 from the driver 410 . On the other hand, the signal generator 435 is coupled to the driver 410 and the selection circuit 432 . The signal generator 435 is controlled by the driver 410 and provides the control signal CS_2 according to the switching signal GD2 from the driver 410.

In this embodiment, the signal generator 434 includes a frequency multiplier circuit FTC and a voltage level shifter LS_1. The frequency multiplier circuit FTC is coupled to the voltage level shifter LS_1. The frequency multiplier circuit FTC changes the frequency of the switching signal GD2. For example, the switching signal GD2 has a second frequency. The frequency multiplier circuit FTC increases the second frequency of the switching signal GD2 to the first frequency to generate the switching signal GD2' with the first frequency. The voltage level shifter LS_1 raises the voltage level of the switching signal GD2' to generate the control signal CS_1.

In this embodiment, the frequency multiplier circuit FTC includes a fast Fourier Transform (FFT) unit FTC_1 and an inverse Fast Fourier Transform (IFFT) unit FTC_2. The FFT unit FTC_1 and the IFFT unit FTC_2 are coupled in series between the driver 410 and the voltage level shifter LS_1. Specifically, the FFT unit FTC_1 converts the switching signal GD2 from a voltage signal in the time domain into a voltage signal in the frequency domain. The frequency multiplier circuit FTC obtains the frequency of the switching signal GD2 (ie, the second frequency) based on the switching signal GD2 converted into the frequency domain. The frequency multiplier circuit FTC increases the frequency of the switching signal GD2 in the frequency domain (ie, the first frequency). In this embodiment, the first frequency may be twice the second frequency (the invention is not limited thereto). Then, the IFFT unit FTC_2 converts the switching signal GD2 from the frequency domain voltage signal into the time domain voltage signal to generate the switching signal GD2'.

In this embodiment, the signal generator 435 includes a voltage level shifter LS_2. The voltage level shifter LS_2 raises the voltage level of the switching signal GD2 to generate the control signal CS_2.

It should be noted that the voltage level shifters LS_1 and LS_2 can raise the voltage level of the switching signal GD2 so that the voltage level of the output signal (ie, the control signal CS_1 and CS_2) is different from the zero voltage value. In this way, the lowest voltage level of the startup signal PS_ON generated according to the control signals CS_1 and CS_2 is not a zero voltage value, so that the power supply PS can avoid malfunction when operating according to the startup signal PS_ON. In this embodiment, the voltage difference raised by the voltage level shifters LS_1 and LS_2 may be equal to the voltage value VB shown in the embodiments of FIGS. 2 and 3 .

In this embodiment, the selection circuit 432 includes voltage dividing resistors RO1 to RO2, a comparator CMP, switches Q2 to Q3, and a buffer BF. The first terminal of the voltage dividing resistor RO1 is coupled to the output terminal of the converter 420 . The second terminal of the voltage dividing resistor RO1 is coupled to the first terminal of the voltage dividing resistor RO2 and the non-inverting input terminal of the comparator CMP. The second terminal of the voltage dividing resistor RO2 is coupled to the ground terminal GND2. In this embodiment, the voltage dividing resistors RO1 and RO2 form a voltage dividing circuit. The voltage dividing circuit divides the output voltage of the output power supply VO to generate the sensing voltage VOR. That is, the sensing voltage VOR is directly related to the output power supply VO.

In this embodiment, the non-inverting input terminal of the comparator CMP receives the sensing voltage VOR. The inverting input terminal of the comparator CMP is coupled to the electronic device DT. The inverting input terminal of the comparator CMP receives one of the low device voltage VF_L and the high device voltage VF_H. The comparator CMP may provide the first signal V1 with a low voltage level (eg, logic low voltage) based on the comparison result of the low device voltage VF_L and the sensing voltage VOR. The comparator CMP may provide the first signal V1 with a high voltage level (eg, logic high voltage) based on the comparison result of the high device voltage VF_H and the sensing voltage VOR.

In this embodiment, the first terminal of the switch Q2 is coupled to the signal generator 434 . The first terminal of the switch Q2 receives the control signal CS_1 with the first frequency. The second terminal of the switch Q2 is coupled to the activation signal generating unit 431 . The control terminal of switch Q2 is coupled to the output terminal of comparator CMP. The switch Q2 is controlled by the comparator CMP, and performs switching operations according to the first signal V1 from the comparator CMP.

In this embodiment, the buffer BF is coupled to the output terminal of the comparator CMP. The buffer BF provides a second signal V2 with a low voltage level (eg, a logic low voltage) based on the first signal V1 with a high voltage level (eg, a logic high voltage), and provides a second signal V2 with a low voltage level based on the first signal V1 with a low voltage level. A signal V1 provides a second signal V2 with a high voltage level. The buffer BF inverts the voltage level of the first signal V1 so that the first signal V1 and the second signal V2 are inverted.

The buffer BF of this embodiment can be implemented by a comparator. The non-inverting input terminal of the buffer BF receives the reference voltage VREF. The inverting input terminal of the buffer BF is coupled to the output terminal of the comparator CMP.

In this embodiment, the first terminal of the switch Q3 is coupled to the signal generator 435 . The first terminal of the switch Q3 receives the control signal CS_2 with the second frequency. The second terminal of the switch Q3 is coupled to the activation signal generating unit 431 . The control terminal of the switch Q3 is coupled to the output terminal of the buffer BF. The switch Q3 is controlled by the buffer BF, and performs a switching operation according to the second signal V2 from the buffer BF.

In this embodiment, when the electronic device DT is in the standby state, the inverting input terminal of the comparator CMP receives the low device voltage VF_L. The first signal V1 output by the comparator CMP has a logic high voltage. Therefore switch Q2 is turned on. Since the first signal V1 is an inverse signal of the second signal V2, the second signal V2 has a logic low voltage. Therefore switch Q3 is opened. At this time, the activation signal generating unit 431 receives the control signal CS_1 with the first frequency to provide the activation signal PS_ON with the first frequency.

In this embodiment, when the electronic device DT enters the power-on state from the standby state, the inverting input terminal of the comparator CMP receives the high device voltage VF_H. Therefore, the first signal V1 output by the comparator CMP has a logic low voltage. The second signal V2 output by the buffer BF has a logic high voltage. Therefore, switch Q2 is turned off. Switch Q3 is turned on. At this time, the activation signal generating unit 431 receives the control signal CS_2 with the second frequency to provide the activation signal PS_ON with the second frequency. In addition, the discharging circuit 433 starts discharging the activation signal PS_ON with the second frequency based on a delay of a preset time length.

It should be noted that due to the signal processing delay of the comparator CMP and the buffer BF, the response speed of the comparator CMP and the buffer BF is slower than the response speed of the switches Q2 and Q3. Therefore, when the electronic device DT enters the standby state from the power-on state, the comparator CMP has not yet switched the first signal V1 to a logic high voltage, and the buffer BF has not yet switched the second signal V2 to a logic low voltage, so the startup signal PS_ON is still Has a second frequency. In this way, when the electronic device DT is in the pre-standby state, the activation signal PS_ON will be temporarily maintained at the second frequency, as shown in the embodiment of FIG. 3 . Subsequently, the start signal PS_ON is switched to the first frequency. In an ideal situation, when the electronic device DT enters the standby state from the power-on state, the activation signal PS_ON will have the first frequency.

In addition, when the electronic device DT enters the standby state from the power-on state, the discharge circuit 433 stops discharging the start signal PS_ON. Therefore, the voltage level of the enable signal PS_ON is gradually pulled up. In some embodiments, the discharge circuit 433 stops discharging the enable signal PS_ON in response to the low device voltage VF_L.

In this embodiment, the converter 420 further includes a blocking switch Q5. The first terminal of the blocking switch Q5 is coupled to the first terminal of the voltage dividing resistor RO1 and the output terminal of the converter 420 . The second terminal of the blocking switch Q5 is coupled to the electronic device DT. The control terminal of the blocking switch Q5 is coupled to the driver 410 . The blocking switch Q5 is controlled by the driver 410 and performs switching operations according to the switching signal GD3 from the driver 410 .

In this embodiment, the switch signal GD3 is generated by the driver 410 according to the enable signal PS_ON. Specifically, when the enable signal PS_ON has a low voltage level (eg, zero voltage value), the switching signal GD3 has a logic high level to turn on the blocking switch Q5. When the enable signal PS_ON has a high voltage level, the switching signal GD3 has a logic low level to turn off the blocking switch Q5. That is, the switching signal GD3 can determine whether to turn on the blocking switch Q5 to provide the output power VO to the electronic device DT.

In this embodiment, the switch signal GD3 is determined based on the enable signal PS_ON. The start signal PS_ON is determined based on the device voltage VF_L/VF_H provided by the electronic device DT.

In this embodiment, the discharge circuit 433 includes a timer TMR, a discharge switch Q4 and a delay circuit DLC. The first terminal of the timer TMR is coupled to the output terminal of the buffer BF. The second terminal of the timer TMR is coupled to the control terminal of the discharge switch Q4. The timer TMR starts timing in response to the second signal V2 having a high voltage level (eg, logic high voltage). When the time length of the second signal V2 at the high voltage level reaches the preset time length, the timer TMR provides the discharge control signal DCS.

In this embodiment, the first terminal of the discharge switch Q4 is coupled to the output terminal of the startup signal generating unit 431 . The second terminal of the discharge switch Q4 is coupled to the delay circuit DLC. The discharge switch Q4 is controlled by the timer TMR and performs switching operations based on the discharge control signal DCS.

In this embodiment, the delay circuit DLC is coupled between the second terminal of the discharge switch Q4 and the ground terminal GND2. The delay circuit DLC provides the discharge delay time. The discharge switch Q4 is turned on in response to the discharge control signal DCS, so that the voltage value of the start signal PS_ON is pulled down to a zero voltage value based on the discharge delay time.

In some embodiments, timer TMR also responds to low device voltage VF_L to turn off power switch Q4.

It should be noted that since the discharge switch Q4 is turned on after the discharge delay time, when the electronic device DT enters the on state from the off state, the start signal PS_ON is slowly discharged to a zero voltage value, as shown in the embodiment of Figure 2 Show.

In this embodiment, the delay circuit DLC includes a delay resistor RX and a delay capacitor CX. The delay resistor RX and the delay capacitor CX are coupled in series between the second terminal of the discharge switch Q4 and the ground terminal GND2. In this embodiment, the discharge delay time is directly related to the product of the resistance value of the delay resistor RX and the capacitance value of the delay capacitor CX.

In this embodiment, the discharge circuit 433 also includes a unidirectional diode D1. The anode of the one-way diode D1 is coupled to the output end of the startup signal generating unit 431 . The cathode of the unidirectional diode D1 is coupled to the first terminal of the discharge switch Q4. The one-way diode D1 is turned on in response to the start signal PS_ON to provide the start signal PS_ON to the discharge switch Q4.

In summary, the power supply and the electronic system including the power supply according to the embodiments of the present invention can provide a start signal of a non-constant voltage signal when the electronic device is in different states, so that the electronic device and the power supply can reduce the average energy. loss. In some embodiments, when the electronic device transitions to different states, the activation signal can be gradually switched to different frequencies so that the power supply can reduce electromagnetic interference. In addition, when the electronic device is in a standby state, the waveform of the startup signal can be boosted to prevent the power supply from malfunctioning.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100, 400: Electronic systems 110, 410: drive 120, 420: Converter 130, 430: Controller 421: Rectifier 422:Transformer 431: Start signal generation unit 432: Select circuit 433: Discharge circuit 434, 435: Signal generator BF: buffer CMP: Comparator CO: output capacitor CS_1, CS_2: control signal CX: delay capacitor D1: One-way diode DCS: discharge control signal DLC: delay circuit DO: output diode DT: electronic device FTC: frequency multiplier circuit FTC_1: Fast Fourier Transform Unit FTC_2: Inverse Fast Fourier Transform Unit GD, GD1, GD2, GD2’, GD3: switching signal GND1, GND2: ground terminal LM: Magnetizing inductor LS_1, LS_2: voltage level shifter NP: primary side winding NS: secondary side winding PS: power supply PS_ON: start signal Q1, Q2, Q3, Q4, Q5: switch RO1, RO2: RX: delay resistor t1_1, t2_1, t3_1, t1_2, t2_2, t3_2: time points TMR: timer V1, V2: signal VA, VB, VOUT: voltage value VF_L: low device voltage VF_H: high device voltage VIN: input power VO: output power VOR: sensing voltage VR: rectified power supply VREF: reference voltage

FIG. 1 is a block diagram of an electronic system according to an embodiment of the invention. FIG. 2 is a schematic diagram of the operation of the power supply when the electronic device enters the power-on state from the standby state according to the embodiment of FIG. 1 of the present invention. FIG. 3 is a schematic diagram of the operation of the power supply when the electronic device enters the standby state from the power-on state according to the embodiment of FIG. 1 of the present invention. FIG. 4 is a circuit diagram of an electronic system according to another embodiment of the present invention.

100:Electronic systems

110:drive

120:Converter

130:Controller

DT: electronic device

GD: switch signal

PS: power supply

PS_ON: start signal

VIN: input power

VO: output power

VOR: sensing voltage

Claims (10)

A power supply for supplying power to an electronic device, wherein the electronic device provides a low device voltage when it is in a standby state, and provides a high device voltage when it is in a power-on state, wherein the power supply includes: a driver , configured to provide a first switching signal in response to an enable signal at a low voltage level; a converter coupled to the driver, configured to generate an output power supply; and a controller coupled to the The electronic device and the driver are configured to: when the electronic device is in the standby state, provide the startup signal with a first frequency based on the low device voltage and a sensing voltage associated with the output power supply, and when When the electronic device enters the power-on state from the standby state, the start-up signal with a second frequency is provided based on the high device voltage and the sensing voltage, and then the start-up signal is discharged to a low voltage level, so that the start-up signal is discharged to a low voltage level. The converter responds to the first switching signal to provide the output power to the electronic device, wherein the first frequency is greater than the second frequency. The power supply of claim 1, wherein when the electronic device enters the standby state from the power-on state, the controller provides the startup signal with the second frequency based on the low device voltage and the sensing voltage. , and then provide the start signal with the first frequency, and stop providing the output power to the electronic device. The power supply of claim 1, wherein: the controller provides a control signal with the first frequency and the control signal with the second frequency based on a second switch signal from the driver, and The controller includes: a startup signal generating unit; a selection circuit coupled to the electronic device and the startup signal generating unit, configured to: select the control signal having the first frequency according to the low device voltage, and The control signal with the first frequency is provided to the startup signal generation unit, so that the startup signal generation unit provides the startup signal with the first frequency, and selects the startup signal with the second frequency according to the high device voltage. control signal, and provide the control signal with the second frequency to the startup signal generation unit, so that the startup signal generation unit provides the startup signal with the second frequency; and a discharge circuit coupled to the selection circuit , discharge the start signal. The power supply of claim 3, wherein the controller further includes: a first signal generator coupled to the driver and configured to provide the control with the first frequency according to the second switch signal. signal; and A second signal generator is coupled to the driver and configured to provide the control signal with the second frequency according to the second switch signal. The power supply of claim 4, wherein: the second switching signal has the second frequency, and the first signal generator includes: a frequency doubling circuit configured to convert the third frequency of the second switching signal two frequencies are raised to the first frequency; and a first voltage level shifter, coupled to the frequency multiplier circuit, is configured to boost the voltage level of the control signal having the first frequency. The power supply of claim 5, wherein the second signal generator includes: a second voltage level shifter configured to boost the voltage level of the control signal having the second frequency. The power supply of claim 3, wherein the selection circuit includes: a voltage dividing circuit configured to divide an output voltage of the output power supply to generate the sensing voltage; a comparator, the comparing The non-inverting input terminal of the comparator is coupled to the voltage divider circuit to receive the sensing voltage, and the inverting input terminal of the comparator is coupled to the electronic device and is configured to operate based on the low device voltage and the sensing voltage. The comparison result is used to provide a first signal with a low voltage level, and the first signal with a high voltage level is provided based on the comparison result of the high device voltage and the sensing voltage; A first switch, the first end of the first switch receives the control signal with the first frequency, the second end of the first switch is coupled to the startup signal generating unit, and the control end of the first switch is coupled to at the output of the comparator; a buffer coupled to the output of the comparator configured to provide a second signal with a low voltage level based on the first signal with a high voltage level, and providing the second signal with a high voltage level based on the first signal with a low voltage level; and a second switch, a first end of the second switch receiving the control signal with the second frequency, the The second terminal of the second switch is coupled to the startup signal generating unit, and the control terminal of the second switch is coupled to the output terminal of the buffer. The power supply of claim 7, wherein: when the inverting input terminal of the comparator receives the low device voltage, the first switch is turned on, the second switch is turned off, and when the comparator When the inverting input terminal receives the high device voltage, the first switch is turned off and the second switch is turned on. The power supply of claim 7, wherein the discharge circuit includes: a timer configured to start timing in response to the second signal having a high voltage level, and when the second signal is at the high voltage level When the time length of the bit reaches a preset time length, a discharge control signal is provided; a discharge switch, the first end of the discharge switch is coupled to the output end of the startup signal generating unit, and the control end of the discharge switch is coupled to the timer; and A delay circuit coupled between the second terminal of the discharge switch and a ground terminal, configured to provide a discharge delay time, wherein the discharge switch is turned on in response to the discharge control signal, such that the voltage of the activation signal The value is pulled down to a zero voltage value based on this discharge delay time. An electronic system, including: an electronic device configured to provide a low device voltage when the electronic device is in a standby state, and to provide a high device voltage when the electronic device is in a power-on state; and a power supply, Used to power the electronic device, including: a driver configured to respond to a startup signal at a low voltage level to provide a first switching signal; a converter coupled to the driver configured to generate a an output power supply; and a controller coupled to the electronic device and the driver, configured to provide a voltage with a first frequency based on the low device voltage from the electronic device and a sensing voltage associated with the output power supply. The startup signal is provided, and the startup signal with a second frequency is provided based on the high device voltage of the electronic device and the sensing voltage, and then the startup signal is discharged to a low voltage level to cause the converter to react The output power is provided to the electronic device based on the first switching signal, wherein the first frequency is greater than the second frequency.

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