TW202135453A - Partial zero voltage switching (zvs) for flyback power converter and method therefor - Google Patents

Abstract

A controller is for use in a power converter having a flyback transformer having a primary winding switched by a primary side transistor and a secondary winding switched by a secondary side transistor. The controller includes a line voltage detection circuit that activates a high line detect signal in response to detecting that an input line voltage is greater than a first threshold, a discontinuous conduction mode detection circuit activates a discontinuous conduction mode signal in response to detecting that the controller is operating in discontinuous conduction mode, and a switching controller coupled to the line voltage detection circuit and to the discontinuous conduction mode detection circuit that controls the primary side transistor and the secondary side transistor using partial zero voltage switching in response to an activation of the high line detect signal and the discontinuous conduction mode signal, and without using partial zero voltage switching otherwise.

Description

Partial zero voltage switching (ZVS) and its method for flyback power converter

The present disclosure generally relates to power converters, and more specifically, to power converters using flyback transformers.

The switching mode power supply can be used to generate a direct current (DC) voltage from an alternating current (AC) voltage by switching the current through an energy storage element, such as a transformer. The duty cycle of the switching is controlled to adjust the output voltage to a desired level. Switching mode power supplies are generally more efficient at heavier loads and less efficient at lighter loads. Two popular types of isolated switching mode power supplies are forward mode converters and flyback mode converters.

Flyback converters are commonly used in AC voltage to DC voltage applications. Flyback converters are based on flyback transformers that alternately build flux in the magnetic core and transfer energy to the output. When the current is switched through the primary winding, the primary current on the transformer increases, storing energy in the transformer. When the switch is turned off, the primary current in the transformer drops, and the secondary current flows based on the energy stored in the magnetizing inductance (labeled "Lm"). When the secondary current flows, the primary voltage of the transformer is determined by the reflected output voltage. Even when the synchronous rectifier (SR) transistor is not conducting, the secondary current can still flow through the internal diode at the SR transistor. The controller changes the turn-on and turn-off time of the primary switch connected in series with the primary winding to adjust the output voltage to a desired level.

The flyback converter can be configured to use a topology known as active clamp flyback (ACF) to switch additional reactive elements in parallel with the primary winding. The ACF converter can reduce the electrical stress on the components and improve the efficiency by achieving zero volt switching (ZVS) close to one-time switching to produce a clean drain waveform without any ringing. It also allows a soft increase in the secondary current. However, although the ACF converter has high efficiency at medium and heavy loads, its efficiency at lighter loads is reduced due to the continuous conduction loss from the magnetizing current that continues to circulate on the primary side of the transformer due to additional reactance elements . In addition, ACF converters are generally not used with other technologies that improve efficiency under light loads, such as cycle skipping and frequency foldback.

For example, battery-powered consumer electronic devices continue to become smaller and more powerful, but this trend requires higher power, faster, and smaller AC/DC chargers. For example, the Universal Serial Bus (USB) Power Delivery (PD) standard has begun to become more and more popular among smart device and laptop computer manufacturers. The USB PD standard allows higher power levels (up to 100 watts (W)) and adaptive output voltages to realize next-generation battery-powered electronic devices. However, existing power supply designs (such as ACF converters) cannot meet these new higher power transmission demands while maintaining high efficiency and low cost.

FIG. 1 shows a partial block diagram and partial schematic form of a flyback power converter 100 using partial zero voltage switching (ZVS) according to an embodiment of the present invention. The flyback power converter 100 generally includes an input section 110, a transformer 120, a primary switching circuit 130, an output circuit 140, a controller 150, a driving network 160, a voltage sensing and supply circuit 170, a secondary circuit 180, And resistor 190.

The input section 110 includes a fuse 111, a common mode choke 112, a diode bridge rectifier 113, a capacitor 114, an inductor 115, a capacitor 116, and a resistor 117. The input section 110 receives an alternating current (AC) input voltage (labeled as “AC IN”) on its first terminal and second terminal, and the first terminal and the second terminal can be connected to an AC main power supply, for example. The fuse 111 has a first terminal connected to the first terminal of the input section 110 and a second terminal. The common mode choke coil 112 has a first terminal connected to the second terminal of the fuse 111, a second terminal, a third terminal connected to the second terminal of the input section 110, and a fourth terminal. The diode bridge 113 has a first input terminal connected to the second terminal of the common mode choke coil 112, a second input terminal connected to the fourth terminal of the common mode choke coil 112, a first output terminal, and The second output terminal that is grounded at a time. The capacitor 115 has a first terminal connected to the first output terminal of the diode bridge rectifier 113 and a second terminal connected to the primary ground. The inductor 115 has a first terminal connected to the second terminal of the common mode choke coil 112 and a second terminal. The capacitor 116 has a first terminal connected to the second terminal of the inductor 115 and a second terminal connected to the primary ground. The resistor 117 has a first terminal connected to the second terminal of the inductor 115 and a second terminal.

The transformer 120 has a magnetic core 121, a primary winding 122, a secondary winding 123, and an auxiliary winding 124. The primary winding 122 has a first end connected to the second terminal of the inductor 115 and a second end, and has a number of N _P turns. The secondary winding 123 has a first end and a second end, and has a number of N _S turns. The auxiliary winding 124 has first and second ends and having a number of turns N _A. "

The primary switching circuit 130 includes a transistor 131, a resistor 132, a diode 133, a capacitor 134, and a resistor 135. The transistor 131 is a high-power N-channel metal-oxide-semiconductor (MOS) transistor, which has a drain, a gate, and a source connected to the second end of the primary winding 122. The resistor 132 has a first terminal connected to the source of the transistor 131 and a second terminal connected to the primary ground. The diode 133 has an anode connected to the second end of the primary winding 122 and a cathode. The capacitor 134 has a first terminal connected to the second terminal of the inductor 115 and a second terminal connected to the anode of the diode 133. The resistor 135 has a first terminal connected to the second terminal of the inductor 115 and a second terminal connected to the anode of the diode 133.

The output circuit 140 includes an output capacitor 141, a transistor 142, a bus capacitor 143, a resistor 144, a transistor 145, resistors 146 and 147, and a gate driver chip 148. The output capacitor 142 has a first terminal connected to the first terminal of the secondary winding 123 and a second terminal connected to the secondary ground. The transistor 142 is an N-channel MOS transistor, which has a drain connected to the first end of the secondary winding 123, a gate, and a source connected to the first output terminal of the flyback power converter 100. The bus capacitor 143 has a first terminal connected to the source of the transistor 142 and connected to the first output terminal of the flyback power converter 100, and a first terminal connected to the second output terminal of the flyback power converter 100 Two ends. The resistor 144 is a current sensing resistor, which has a first terminal connected to the second terminal of the bus capacitor 143 and connected to the second output terminal of the flyback power converter 100, and a first terminal connected to the secondary ground Two terminals. The transistor 145 is an N-channel MOS transistor, which has a drain connected to the second end of the secondary winding 123, a gate, and a source connected to the secondary ground. The resistor 146 has a first terminal connected to the gate of the transistor 145, and a second terminal, and has an associated resistance _{labeled "R G ".} The resistor 147 has a first terminal connected to the gate of the transistor 142. The gate driver chip 148 has serial data and address terminals (labeled "SDA"), a serial clock terminal (labeled "SCL"), and a gate drive output terminal connected to the second terminal of the resistor 147 .

The controller 150 is an integrated primary and secondary flyback controller, which includes a primary controller 151, a secondary controller 152, and an isolator 153. The primary controller 151 has a set of terminals including: a high voltage terminal (labeled "HV") connected to the second terminal of the resistor 117; a primary voltage terminal (labeled "VDDP") connected to The first end of the auxiliary winding of the transformer 120; the voltage sensing terminal (labeled "VS"), the primary current sensing (labeled "CSP"), which is connected to the first terminal of the resistor 132; a primary grounding terminal (Labeled as "GNDP"), which is connected to the primary ground; and a multi-function terminal (labeled as "SD/IMOD"), which is connected to the first terminal of the resistor 190.

The secondary controller 152 has a set of terminals, the set of terminals includes: a drain terminal (labeled "DRAIN"), which is connected to the second end of the secondary winding 123 of the transformer 120 and connected to the drain of the transistor 145; The input voltage terminal (labeled "VIN"), which is connected to the first end of the secondary winding 123 of the transformer 120; the secondary gate drive terminal (labeled "GATES"), which is connected to the second terminal of the resistor 146 ; Power supply voltage terminal (labeled "VDDS"); serial data and feedback terminals (labeled "SDA/FB"); serial clock and serial data signals (labeled "SCL/SD"); 2. The secondary ground terminal (labeled "GNDS"); and the secondary current sensing terminal (labeled "CSS"), which is connected to the first terminal of the resistor 144.

The isolator 153 provides a physical and electrical isolation gap between the primary controller 151 and the secondary controller 152. In order for the secondary controller 152 to transmit the switching phase information to the primary controller 151, the isolator 153 has one or more capacitors through which electrical signals can be transmitted while maintaining galvanic isolation. As shown in FIG. 1, the isolator 153 has a first capacitor for transferring signals from the secondary controller 152 to the primary controller 151, and a second capacitor for transferring signals from the primary controller 151 to the secondary controller 152. Two capacitors. In an exemplary embodiment, the primary controller 151 and the secondary controller 152 are implemented on separate semiconductor chips, which are combined into a multi-chip module in a single integrated circuit package.

The driving network 160 includes resistors 161 and 162 and a diode 163. The resistor 161 has a first terminal and a second terminal connected to the gate of the transistor 131. The resistor 162 has a first terminal connected to the first terminal of the resistor 161 and a second terminal. The diode 163 has a cathode connected to the second terminal of the resistor 162 and an anode connected to the gate of the transistor 131.

The voltage sensing and supply circuit 170 includes a diode 171, a capacitor 172, and resistors 173 and 174. The diode 171 has an anode connected to the first end of the auxiliary winding 124 and a cathode. The capacitor 172 has a first terminal connected to the cathode of the diode 171 and a second terminal connected to the primary ground. The resistor 173 has a first terminal connected to the first end of the auxiliary winding 124 and a second terminal. The resistor 174 has a first terminal connected to the second terminal of the resistor 173 and a second terminal connected to the primary ground.

The secondary circuit 180 includes a capacitor 181 and resistors 182 and 183. The capacitor 181 has a first terminal connected to the VDDS terminal of the controller 150 and a second terminal connected to the secondary ground. The resistor 182 has a first terminal connected to the VDDS terminal of the controller 150 and a second terminal connected to the SDA/FB terminal of the controller 150. The resistor 183 has a first terminal connected to the VDDS terminal of the controller 150 and a second terminal connected to the SCL/SD terminal of the controller 150.

The resistor 190 has a first terminal connected to the SD/IMOD terminal of the controller 150 and a second terminal connected to the primary ground. In the illustrated embodiment, the resistor 190 is a negative temperature coefficient (NTC) resistor, and the flyback power converter 100 uses the resistor for the thermal shutdown function.

In operation, the flyback power converter 100 converts the smoothed input voltage derived from the AC power source into a DC voltage. The input section 110 receives, rectifies, and filters AC IN signals. The common mode choke 112 filters the AC IN signal to remove high frequency noise. The diode bridge rectifier 113 converts the AC IN sine wave into a full-wave rectified sine wave. The capacitors 114 and 116 and the inductor 115 together form a pi filter for smoothing the ripples in the full-wave rectified sine wave, and present a smooth low ripple voltage at the first end of the primary winding 122 .

Based on the turns ratio of the transformer 120 N _S / N _P of the primary winding 122 of the voltage converter to the voltage on the secondary winding 123, wherein the number of turns on the secondary winding N _S lines 123, and N _P based on the primary winding 122 The number of turns. Similarly, the transformer 120 based on the turns ratio N _A / N _P of the primary winding voltage 122 into a voltage on the auxiliary winding 124, where N _A based on the number of turns of the auxiliary winding 124.

The flyback power converter 100 uses a transistor 131 connected to the second end of the primary winding 122 to switch the smoothed rectified voltage at the first end of the primary winding 122. The primary controller 151 switches the transistor 131 through a network including resistors 161 and 162 and a diode 163 by providing a driving signal GATEP. The resistor 132 senses the primary side current and provides a current sensing signal to the CSP terminal of the primary controller 151. Then, the primary controller 151 uses the isolator 153 to provide information about the primary current to the secondary controller 152 as part of the constant current, constant voltage ("CC/CV") control loop. The primary controller 151 receives on the HV pin the initial power from the input line, through the resistor 117, and from the auxiliary winding 124 through the voltage sensing and supply circuit 170 after the transformer 120 starts to switch. The voltage sensing and supply circuit 170 also provides an indication of the line voltage on the VS terminal.

On the secondary side, the gate driver chip 148 enables and disables the output voltage by turning on or off the transistor 142. The gate driver chip 148 uses pins SDA (serial data and address) and SCL (serial clock) and uses a 2-wire serial link to communicate with the secondary controller 152. The secondary controller 152 derives operating power from the VIN pin, and charges the capacitor 181 through the VDDS pin to smooth the internal power supply voltage. The secondary controller 152 uses the DRAIN input to sense the voltage at the drain of the transistor 145, and this voltage provides polarity information used in the primary-side and secondary-side switching decisions. The secondary controller 152 also uses the CSS input to sense the secondary current, and uses the GATES pin to control the conductivity state of the transistor 145.

The flyback power converter 100 uses a technique called partial zero voltage switching (ZVS). As used herein, "partial zero voltage switching" and "partial ZVS (partial ZVS)" mean that the controller only achieves ZVS for a part of its operating range. As will be described more fully below, when the line voltage is relatively high, when the output voltage is relatively high, and when the flyback power converter 100 is operating in a discontinuous conduction mode (DCM), the flyback The power converter 100 performs ZVS. If none of these three conditions are met, it will operate without the use of ZVS. In other embodiments, different partial ZVS control schemes, such as high line and DCM, or high output voltage and DCM, can also be used.

When in the ZVS mode, the flyback power converter 100 activates the transistor 145 for the second time to control the ZVS instant. After turning off the transistor 145, the secondary controller 152 detects the valley value of the drain voltage of the primary transistor, and then based on the CV/CS control loop, restarts the secondary transistor for a predetermined amount of time, so that the primary transistor A negative current is generated in the magnetizing inductance on the winding. Then, this additional current is sufficient to _{completely discharge the output capacitor C OSS of the} transistor 131, ensuring that more energy stored in the reactance element is recycled and leading to a higher converter efficiency.

C _OSS is the output capacitance of the transistor, and in the flyback power converter 100 is equal to the drain-to-source capacitance (Cds) and the gate-to-drain capacitance (Cgd) plus the difference between the primary winding 122 of the transformer 120 The sum of stray capacitance. Transistor 131 is a high-power MOS transistor, and has a large C _OSS that stores energy during switching. As will be explained more fully below, the controller 150 considers the C _OSS and selectively activates the secondary transistor 145 for the second time to achieve better switching efficiency during the ZVS operation, so as to more completely switch the transistor The C _{OSS of} 131 discharges and thus achieves true ZVS.

The controller 150 includes both a primary side controller and a secondary side controller integrated in a single integrated circuit package, wherein the primary controller and the secondary controller communicate with an isolator. Using a single IC to control the two FETs (where the CC/CV loop is implemented on the secondary side) can be used to implement part of the ZVS technology. The secondary controller 152 uses the isolator 153 to communicate the switching moment to the primary side.

FIG. 2 illustrates a timing diagram 200 showing part of the ZVS technology used in the flyback power converter 100 of FIG. 1. In the timing chart 200, the horizontal axis represents time in microseconds (µs), and the vertical axis represents the amplitude of various signals in volts. The timing diagram 200 shows the waveforms of the seven signals of interest, including: the primary gate waveform 210, which is labeled "Pri_Gate"; the secondary gate waveform 220, which is labeled "SR_Gate"; and the primary drain waveform 230, It is marked as "Pri_Drain"; the secondary drain waveform 240 is marked as "SR_Drain"; the valley detection waveform 250 is marked as "SR_NVW"; the constant current and constant voltage regulation loop trigger waveform 260 is marked as "CC/CV_Pulse"; and a trigger waveform 230 of a regulation loop, which is marked as "Pri_Pulse_OUT". The time sequence diagram 200 also shows five attention time points, which are labeled "t ₁ ", "t ₂ ", "t ₃ ", "t ₄ ", and "t ₅ ".

The sequence starts with the activation of the Pri_Gate signal. The transistor 131 is turned on and current flows through the primary winding 122, causing the transformer 120 to build flux in its core. The Pri_Drain signal drops to about zero volts, which corresponds to the voltage of the primary ground signal. At this time, the SR_Drain signal rises to a level corresponding to the line voltage, that is, the voltage at the first end of the primary winding 122. The three other control signals SR_NVW, CC/CV_Pulse and Pri_Pulse_OUT shown in Figure 2 are all inactive.

At time t ₁ , once the controller 151 disables the Pri_Gate signal, the transistor 131 becomes non-conducting. After the transient spike around time t ₁ , the Pri_Drain signal stabilizes at a value corresponding to the rectified line voltage. After a short delay of t _1, the second controller 152 by the sensed voltage drops below a secondary SR_Drain ground to detect the off transistor 131. In response to detecting the polarity reversal by the internal diode, the secondary controller 152 activates the SR_Gate signal to turn on the transistor 145 (synchronous rectifier transistor) and transfer the energy from the magnetic core of the transformer to the load. When the secondary controller 152 detects that the secondary side current has been discharged to zero, it keeps the SR_Gate signal active until time t ₂ .

At t ₂ , the secondary controller 152 deactivates the SR_Gate signal. Subsequently, due to the magnetizing inductance (labeled "Lm") of the transformer 120 connected in parallel with the output capacitor C _{OSS, the voltage on the Pri_Drain signal begins to resonate.} The capacitor 134 and the resistor 135 operate as a snubber circuit. When the transistor 131 is turned off, the leakage inductance generates a voltage spike when combined with the drain-to-source capacitance of the transistor 131. When the voltage spike is greater than the sum of the line voltage, the turns ratio N multiplied by the output voltage (labeled as "VOUT"), and the voltage across the capacitor 134, then the diode 133 is turned on, and the voltage spike is limited by the cross capacitor 134 voltage. The SR_Drain signal resonates with the opposite polarity. During this time, the secondary controller 152 compares the SR_Drain signal with a relatively low threshold voltage, and activates the SR_NVW signal when the SR_Drain signal is lower than the low threshold voltage to sense resonance.

At time t ₃ , the secondary controller 152 starts CC/CV_Pulse according to its constant current/constant voltage control loop. If the SR_Drain signal is also in the valley as indicated by the SR_NVW signal, the secondary controller 152 activates the SR_Gate signal for the second time and keeps the signal active for a time between time t ₃ and t ₄ ( Marked as "T _ZVS "). _{The setting of T ZVS} to an appropriate value will be further explained below. T _ZVS can be, for example, 1 microsecond (1 µs).

The second activation of the SR_Gate signal induces a negative current in the magnetizing inductance Lm, and then the _{transistor 145 is deactivated again between times t 4} and t ₅ for an amount of time (labeled as T _DELAY ). This negative current Discharge C _OSS. After time t ₄ , the voltage on Pri_Drain starts to resonate downward, and the voltage on SR_Drain starts to resonate upward. Once the voltage of Pri_Drain reaches the minimum value (ie, the valley value), then the secondary controller 152 transmits a signal to the primary controller 151 to activate the transistor 131 (which occurs at t ₅ ), and another cycle starts.

In order to achieve a precise ZVS instant, T _ZVS can be adjusted to establish sufficient negative current in the magnetizing inductance Lm to discharge _{the C OSS of the transistor 131 before the next switching cycle.} T _ZVS can be set as follows. First, whether the C _OSS discharged to zero the desired negative current I _PN. Then, based on I _PN , the amount of time required to activate the transistor 145 for the second time is determined.

=

[1] 展開方程式[1] 並且代入用於磁化電感L_m 中之能量及C_OSS 中之能量的公式得出：

=

[2] 求解I_PN 得出：

[3] 但是：

[4] 將方程式[3] ]代入方程式[4] 的左側，得出：

[5] 因此：

[6] T_ZVS 可諸如依設計來預設、藉由在測量C_OSS 之後的最終測試期間程式化熔絲來設定，或以其他方式程式化或設定以匹配特定系統參數。T_ZVS 之值影響可用的切換頻率。隨著V_IN 及C_OSS 增加，T_ZVS 亦增加，但導致切換週期增加，且因此導致切換頻率降低。In order to _{fully discharge C OSS} , the energy of the magnetizing inductance must be equal to the energy stored in _{C OSS:}

=

[1] Expand the equation [1] and substitute the formula for the energy in the magnetizing inductance L _m and the energy in C _{OSS to get:}

=

[2] Solving I _PN gives:

[3] But:

[4] Substituting equation [3] ] into the left side of equation [4], we get:

[5] Therefore:

[6] T _ZVS can be preset by design, set by programming fuses during the final test after the C _{OSS is} measured, or programmed or set in other ways to match specific system parameters. The value of T _ZVS affects the available switching frequency. As V _IN and C _OSS increase, T _ZVS also increases, but this results in an increase in the switching period and therefore a reduction in the switching frequency.

FIG. 3 shows a timing diagram 300 that can be used to understand the operation of the flyback power converter 100 of FIG. 1. In action block 310, the secondary controller 152 detects the line input voltage. In action block 320, the secondary controller 152 detects the output voltage. In the action block 330, the secondary controller 152 detects the operation mode. For example, during a period of heavy load requiring high power output, the secondary controller 152 controls the primary controller 151 to operate the transistor 131 at a fast enough rate that the transformer 120 will not completely discharge the magnetizing inductance before the start of another switching cycle. . This mode is known as continuous conduction mode (CCM). On the other hand, during periods of light load (where it is important to provide high efficiency while delivering lower total power), the secondary controller 152 controls the primary controller 151 to operate the transistor 131 before the start of another switching cycle Discharge the magnetizing inductance completely. This mode is known as discontinuous conduction mode (DCM). In decision block 340, the secondary controller 152 determines whether the input voltage is greater than the first threshold (labeled "TH ₁ "), the output voltage is greater than the second threshold (labeled "TH ₂ "), and whether the converter Operating in DCM. If yes, the process proceeds to action block 350, where the secondary controller 152 operates in the ZVS mode. If not, the flow continues to action block 360, where the secondary controller 152 continues to operate without using zero voltage switching.

FIG. 4 shows in partial block diagram and partial schematic form the line voltage detection circuit 400 used in the secondary controller 152 of FIG. 1 to determine whether the line voltage exceeds the first threshold. The line voltage detection circuit 400 generally includes a drain voltage detection circuit 410, an output voltage detection circuit 420, a threshold voltage generation circuit 430, a comparator 440, and an output latch 450.

The drain voltage detection circuit 410 includes a current amplifier 411, resistors 412 and 413, and a diode 414. The current amplifier 411 has a first input connected to the DRAIN terminal of the secondary controller 152, a second input terminal, a first output terminal labeled "BIAS", and a second output terminal. The resistor 412 has a first terminal connected to the second input terminal of the current amplifier 411 and a second terminal connected to the secondary ground. The resistor 413 has a first terminal connected to the second output terminal of the current amplifier 411, and a second terminal connected to the secondary ground. The diode 414 has an anode connected to the second output terminal of the current amplifier 411 and a cathode connected to the first output terminal of the current amplifier 411.

The output voltage detection circuit 420 includes a current amplifier 421, a resistor 422, and a diode 423. The current amplifier 421 has a first input connected to the VOUT terminal of the secondary controller 152, a second input terminal, a first output terminal connected to the second output terminal of the current amplifier 411, and a second output connected to the secondary ground Terminal. The resistor 422 has a first terminal connected to the second input terminal of the current amplifier 421 and a second terminal connected to the secondary ground. The diode 423 has an anode connected to the secondary ground and a cathode connected to the first output terminal of the current amplifier 421.

The threshold voltage generating circuit 430 includes a voltage source 431, a current amplifier 432, resistors 433 and 434, a diode 435, a switch 436, and a resistor 437. The voltage source 431 provides a voltage measured relative to the secondary ground voltage (labeled "VTrim"). In the example shown in Figure 4, VTrim is equal to 590 millivolts. The current amplifier 432 has a first input terminal (for receiving VTrim) connected to the voltage source 431, a second input terminal, a first output terminal connected to the BIAS terminal, and a second output terminal. The resistor 433 has a first terminal connected to the second input terminal of the current amplifier 432, and a second terminal connected to the secondary ground. The resistor 434 has a first terminal connected to the second output terminal of the current amplifier 432 and a second terminal connected to the secondary ground. The diode 435 has an anode connected to the second output terminal of the current amplifier 432 and a cathode connected to the first output terminal of the current amplifier 432. The switch 436 has a first terminal connected to the second output terminal of the current amplifier 432, a second terminal, and a control terminal for receiving a signal labeled "HI_LINE". The resistor 437 has a first terminal connected to the second terminal of the switch 436, and a second terminal connected to the secondary ground.

The comparator 440 has a positive input terminal connected to the second current output terminal of the current amplifier 411, a negative input connected to the output of the threshold voltage generating circuit 430, and a true output terminal.

The output latch 450 is a time-controlled D-type latch, which has a D input connected to the real output terminal of the comparator 440, a clock input for receiving the signal labeled "TURN_ON ALLOW", and a receiving flag It is the reset input of the "Pulse_out" signal, the complementary setting input for receiving the Pulse_out signal, and the real output of the control input connected to the switch 436 (used to provide the HI_LINE signal).

In operation, the secondary controller 152 of FIG. 1 uses the line voltage detection circuit 400 to determine whether the line voltage is high, as determined by whether it exceeds the first threshold. It relies on the nature of the flyback voltage converter, that is, during the forward phase, the voltage on the drain of the synchronous rectifier transistor is proportional to the primary voltage. Therefore, all control can advantageously occur on the secondary side, and the secondary controller 152 can provide appropriate switching information to the primary controller 151.

=

[7] 其中

係一次對二次匝數比。若

且

，則：

[8] 且：

[9] 當

時偵測到HI_LINE狀況，因此其係在以下情況時開始偵測：

=

[10] 如果

，則：

[11] Specifically, the drain voltage detection circuit 410 uses the voltage of the DRAIN signal to establish the current passing through the input side of the current amplifier 411, the magnitude of which is equal to the voltage of the DRAIN signal divided by the resistance of the resistor 412. According to a current gain "K1", the current amplifier 411 conducts a current through its output side. Therefore, at the first terminal of the resistor 413, the output voltage of the drain voltage detection circuit 410 is expressed as:

=

[7] where

It is the ratio of primary to secondary turns. like

and

,but:

[8] And:

[9] When

HI_LINE is detected at time, so it starts to detect when:

=

[10] If

,but:

[11]

It should be noted that V _Trim can be adjusted in various ways, such as using internal trim options or by using external integrated circuit terminals. If external terminals are used, external impedance can be used to adjust V _Trim .

FIG. 5 shows in partial block diagram and partial schematic form the output voltage detection circuit 500 used in the secondary controller 152 of FIG. 1 to determine whether the output voltage exceeds the second threshold. The output voltage detection circuit 500 generally includes a voltage divider 510, a high output voltage detection circuit 520, a low output voltage detection circuit 530, a latch 540, and an OR gate 550.

The voltage divider 510 includes resistors 511 and 512. The resistor 511 has a first terminal for receiving VOUT and a second terminal. The resistor 512 has a first terminal connected to the second terminal of the resistor 511 and a second terminal connected to the secondary ground.

The high output voltage detection circuit 520 includes resistors 521 and 522 and a comparator 523. The resistor 521 has a first terminal and a second terminal for receiving a signal labeled "BIAS". The resistor 522 has a first terminal connected to the second terminal of the resistor 521 and a second terminal connected to the secondary ground. The comparator 523 has a positive input terminal connected to the output terminal of the voltage divider 510, a negative input connected to the second terminal of the resistor 521, and a real output terminal.

The low output voltage detection circuit 530 includes resistors 531 and 532, and a comparator 533. The resistor 531 has a first terminal and a second terminal for receiving the BIAS signal. The resistor 532 has a first terminal connected to the second terminal of the resistor 531 and a second terminal connected to the secondary ground. The comparator 533 has a positive input terminal connected to the second terminal of the resistor 531, a negative input terminal connected to the second terminal of the voltage divider 510, and a real output terminal.

The latch 540 is an SR latch, which has a setting input (labeled "S") connected to the real output of the comparator 523, and a reset input (labeled "R" connected to the real output of the comparator 533) ), and the real output (marked as "Q").

The OR gate 550 has a first input for receiving a signal labeled "EXT_CTL", a second input connected to the Q output of the latch 540, and an output for providing a HI_LINE signal.

In operation, the output voltage detection circuit 500 determines whether the output voltage VOUT is relatively high (ie, higher than the threshold). The voltage divider 510 initially scales VOUT to a lower voltage, which is more suitable for evaluating CMOS logic circuits. The output voltage detection circuit 520 determines whether the scaled voltage is higher than the high threshold, and if so, the latch 540 is set. Similarly, the low output voltage detection circuit 530 determines whether the scaled voltage is less than the low threshold (where the low threshold is lower than the high threshold), and if so, resets the latch 540. Therefore, the combination of the high-output voltage detection circuit 520, the low-output voltage detection circuit 530, and the latch 540 creates a hysteresis in the high-voltage detection operation to ensure that, for example, a switching transient in the load causes a voltage on VOUT. Stability in the presence of noise and interference. The output voltage detection circuit 500 includes an OR gate 550 so that the HI_VOUT condition can be disabled by external control. Specifically, regardless of the level of VOUT, if EXT_CTL is high, HI_VOUT is high, so the level of VOUT does not determine whether the flyback power converter 100 is operating in the ZVS mode.

Entering the ZVS mode based on HI_VOUT helps to avoid extending the operation switching frequency of the controller 150 when in the ZVS mode. Specifically, since T _ZVS fixed, low VOUT, the establishment of the negative magnetizing current is not large enough to discharge C _OSS to an acceptable voltage level. Therefore, when VOUT is relatively low, ZVS is disabled. In a specific example, when VOUT> 5 volts, HI_VOUT can be detected.

6 is a timing diagram 600 describing the operation of the DCM detection circuit (not shown) used by the controller 150 of FIG. 1 to detect whether it is operating in the DCM mode. In the timing diagram 600, the horizontal axis represents time in microseconds (µs), and the vertical axis represents the amplitude of various signals in volts. The timing diagram 600 shows the waveforms of the four signals of interest, including the Pri_Gate waveform 610, the first SR_Gate waveform 620, the second SR_Gate waveform 630, and the control pulse signal (labeled "Pulse_IN").

As shown in Figure 6, shortly after the end of the SR_Gate_B pulse of the previous cycle, the first Pri_Gate pulse occurs. Soon after the end of the first Pri_Gate pulse, the controller 150 provides the main SR_Gate pulse. The controller 150 activates the Pulse_IN signal (corresponding to the CC/CV_Pulse signal in FIG. 2) to start another switching cycle. When operating in continuous conduction mode (CCM) (for example, in a medium or heavy load), the controller 150 activates the Pulse_IN signal before the end of the SR_Gate pulse plus the hysteresis period after the SR_Gate pulse becomes inactive. Figure 6 shows this operation in the dashed box labeled "CCM Operation Area", where the positions of two possible pulses will cause the flyback converter 100 to operate in the CCM mode. When operating in DCM (for example, at light load), the controller 150 activates the Pulse_IN signal after the end of the SR_Gate pulse plus the hysteresis period. Figure 6 shows this operation in the dashed box labeled "DCM Operation Area", where possible pulse positions indicate the operation in DCM mode.

The controller 150 implements the DCM detection circuit as a CMOS logic circuit, which detects the Pulse_IN signal before or after the deactivation of the SR_Gate pulse plus the hysteresis period. If the Pulse_IN signal occurs in the DCM operating area and other conditions of the ZVS are met, the controller 150 activates the transistor 145 for the second time, which is illustrated by the activation of the SR_Gate_B signal in FIG. 6.

FIG. 7 shows a part of the ZVS decision circuit 700 in the form of a block diagram according to an embodiment of the present invention. Part of the ZVS decision circuit 700 includes a line voltage detection circuit 710, an output voltage detection circuit 720, a DCM detection circuit 730, and a gate 740. The line voltage detection circuit 710 has an output for providing the HI_LINE signal, and can be implemented by the line voltage detection circuit 400 of FIG. 4 or any other suitable circuit that detects whether the line voltage is higher than the first threshold. The output voltage detection circuit 720 has an output for providing the HI_VOUT signal, and can be implemented by the voltage detection circuit 720 of FIG. 5 or any other suitable circuit that detects whether the output voltage is higher than the second threshold. The DCM detection circuit has an output for providing a signal labeled "DCM MODE", and can be implemented by any suitable circuit that detects whether the flyback power converter 100 is operating in the DCM mode, such as the implementation shown in FIG. 6 The detection circuit. The gate 740 has a first terminal connected to the output of the line voltage detection circuit 710, a second input connected to the output of the output voltage detection circuit 720, a third output connected to the output of the DCM detection circuit 730, and To provide the output of the control signal (marked as "ZVS_EN"). ZVS_EN is used as an indication for the controller 150 to turn on the transistor 145 for the second time, so as to establish the required negative current in Lm before the secondary controller 152 sends the signal to the primary controller 151 to turn on the transistor 131. In response to the activation of the ZVS_EN signal, the controller 150 executes the ZVS valley switching as shown above in relation to FIG. 2. +

Therefore, a flyback power converter using part of the ZVS technology has been described, as well as a controller and various circuits used in the controller to implement the technology. This technique is known as partial ZVS because it only operates in ZVS based on operating conditions. The operating conditions for implementing the ZVS technology include operating in DCM, operating at high line voltage, and operating at high output voltage. When using this ZVS technology, the synchronous rectifier transistor is activated as a typical case until the drain voltage decays to zero volts, but then activated a second time to form a negative current through the magnetizing inductance, which can be used to _{The output capacitor (C OSS} ) of the switching transistor on the primary side is completely discharged.

Part of the disclosed ZVS technology is advantageously implemented with the control of the secondary side of the transformer. For example, when the switching transistor on the primary side of the transformer is turned on, the voltage on the drain of the synchronous rectifier transistor can be used to detect the line voltage, because the magnitude of the drain voltage is reflected in the first end of the primary winding The line voltage at the location. In addition, the output voltage can be easily and directly detected by the secondary controller. In some embodiments, the primary controller and the secondary controller may be implemented using separate semiconductor chips, which are combined in a multi-chip module using a single integrated circuit package. In this case, an isolator can be used to maintain galvanic isolation between the primary circuit and the secondary circuit, but allows the communication of switching signals between them.

Using some of the disclosed ZVS technology, it is believed that the controller 150 can meet the high power density, high switching frequency, high efficiency, and electromagnetic compatibility (EMC) standards required by the emerging USB power delivery (PD) standard. At the same time maintain the low cost of applications such as AC/DC chargers.

The topics disclosed above are regarded as explanatory and non-limiting, and the scope of the attached patent application intends to cover all such modifications, enhancements, and other embodiments that fall within the true scope of the patent application. For example, some ZVS technologies determine whether the converter is operating in DCM, whether the line (input) voltage is higher than the first threshold, and whether the output voltage is higher than the second threshold. If it is, it operates in ZVS mode. In other embodiments, if the converter is operating in the DCM mode and the line voltage is higher than the first threshold, it enters the ZVS mode regardless of whether the output voltage is higher than the second threshold. In still other embodiments, if the converter operates in the DCM mode and the output voltage is higher than the second threshold, it enters the ZVS mode, regardless of whether the pipeline voltage is higher than the first threshold. In the illustrated embodiment, a specific circuit is described to use signals available to the secondary controller to determine whether these conditions are met, but in other embodiments, other circuits that perform the same function may be used.

×

其中V_Trim 係修整電壓，V_Line 係高線電壓臨限，n 係返馳式變壓器的匝數比，R₅ 係與輸入電流源串聯的電阻器，且R₆ 係與輸出電流源串聯的電阻器。In one form, a controller for use in a power converter is provided. The power converter has a flyback transformer with a primary winding switched by a primary transistor and a secondary winding. A secondary winding switched by a secondary side transistor. According to one aspect, the controller sets the trim voltage used in the line voltage detection circuit according to the following formula: V _Trim =

X

V _Trim is the trim voltage, V _Line is the high line voltage threshold, n is the turns ratio of the flyback transformer, R ₅ is the resistor in series with the input current source, and R ₆ is the resistor in series with the output current source Device.

According to another aspect, the controller further includes an output voltage detection circuit for activating a high output voltage detection signal in response to detecting that an output voltage across the secondary winding is greater than a second threshold . In this case, the output voltage detection circuit may include: a resistor ladder having an input for receiving the output voltage, and a signal for providing a scaled output voltage as a predetermined fraction of the output voltage An output; a high output voltage signal detection circuit for activating a high output voltage signal in response to the scaled output voltage signal being greater than a third threshold; a low output voltage signal detection circuit for responding Starting a low output voltage signal when the scaled output voltage signal is less than a fourth threshold, where the fourth threshold is lower than the third threshold; and a latch having a device for receiving the high output voltage A setting input of the signal, a reset input for receiving the low output voltage signal, and an output for providing the high output voltage detection signal.

×

其中V_Trim 係修整電壓，V_Line 係高線電壓臨限，n 係返馳式變壓器的匝數比，R₅ 係與輸入電流源串聯的電阻器，且R₆ 係與輸出電流源串聯的電阻器。In another form, a power converter includes: a flyback transformer having a primary winding and a secondary winding; a primary side transistor coupled in series with the primary winding; and a secondary side A transistor, which is coupled in series with the secondary winding, and a controller, which includes a line voltage detection circuit, a discontinuous conduction mode detection circuit, and a switching controller. According to one aspect, the controller may include: a drain voltage detection circuit for providing a drain voltage sensing signal proportional to a voltage of a drain of the secondary side transistor system; An output voltage detection circuit for providing an output voltage sensing signal proportional to an output voltage of the power converter; and a comparator for comparing the drain voltage sensing signal with the output voltage A difference between sensing signals and a second threshold is detected, wherein the line voltage detection circuit provides the high line detection signal in response to the comparator detecting that the difference is greater than the second threshold. In this case, the line voltage detection circuit may further include a threshold voltage generating circuit having an input for receiving a trim voltage and an input for thresholding the flyback transformer based on a high line voltage The turns ratio provides an output of the second threshold. In addition, if it is, the controller can set the trim voltage according to the following formula: V _Trim =

X

V _Trim is the trim voltage, V _Line is the high line voltage threshold, n is the turns ratio of the flyback transformer, R ₅ is the resistor in series with the input current source, and R ₆ is the resistor in series with the output current source Device.

According to another aspect, the discontinuous conduction mode detection circuit detects that the controller is operating in the discontinuous conduction mode in response to detecting that the following two do not overlap: the controller responds to a control loop and A trigger pulse used to activate a primary gate drive signal to the primary side transistor; and after one of the previous primary side gate drive signals is disabled, to a secondary gate of the secondary side transistor One of the drive signals is activated first.

According to yet another aspect, the controller further includes an output voltage detection circuit for activating a high output voltage detection in response to detecting that an output voltage across the secondary winding is greater than a second threshold Signal. In this case, the output voltage detection circuit may include: a resistor ladder having an input for receiving the output voltage, and a signal for providing a scaled output voltage as a predetermined fraction of the output voltage An output; a high output voltage signal detection circuit for activating a high output voltage signal in response to the scaled output voltage signal being greater than a third threshold; a low output voltage signal detection circuit for responding Starting a low output voltage signal when the scaled output voltage signal is less than a fourth threshold, where the fourth threshold is lower than the third threshold; and a latch having a device for receiving the high output voltage A setting input of the signal, a reset input for receiving the low output voltage signal, and an output for providing the high output voltage detection signal.

According to yet another aspect, the controller is formed in a single integrated circuit package and has a primary controller and a secondary controller, wherein the secondary controller and the primary controller are galvanically isolated and communicatively coupled Connect to the primary controller.

In yet another form, a method for selectively operating a power converter in a partial zero-voltage switching mode is provided. The power converter has a flyback transformer. A primary winding switched by a secondary side transistor and a secondary winding switched by a secondary side transistor. The method includes: detecting an input line voltage; detecting an output voltage; detecting an operation mode of a control loop of the power converter; responding to detecting that the input line voltage is greater than a first threshold, detecting When the output voltage is greater than a second threshold, and it is detected that the operation mode is a discontinuous conduction mode, the control loop is operated in the partial zero voltage switching mode; and in response to the detection of the input line voltage At least one of less than the first threshold, detecting that the output voltage is less than the second threshold, and detecting that the operation mode is the discontinuous conduction mode, so that the control loop is operated at the partial zero voltage In another mode other than the switching mode.

According to one aspect, the method further includes setting the predetermined time based on an output capacitance of the primary side transistor and a desired output voltage.

According to another aspect, the method further includes setting the predetermined time further based on a magnetizing inductance and a turns ratio of the flyback transformer.

Therefore, to the greatest extent permitted by law, the scope of the present invention is determined by the broadest permissible interpretation of the scope of the following patent applications and their equivalent interpretations, and should not be limited by the above-mentioned embodiments.

100: Flyback power converter/converter 110: input section 111: Fuse 112: common mode choke 113: Diode bridge rectifier/diode bridge 114: Capacitor 115: inductor/capacitor 116: capacitor 117: Resistor 120: Transformer 121: magnetic core 122: primary winding 123: Secondary winding 124: auxiliary winding 130: One switching circuit 131: Transistor 132: Resistor 133: Diode 134: Capacitor 135: Resistor 140: output circuit 141: output capacitor 142: Transistor/Output Capacitor 143: Bus capacitor 144: Resistor 145: Transistor 146: Resistor 147: Resistor 148: Gate driver chip 150: Controller 151: one controller 152: Secondary Controller 153: Isolator 160: drive network 161: Resistor 162: Resistor 163: Diode 170: Voltage sensing and supply circuit 171: Diode 172: Capacitor 173: Resistor 174: Resistor 180: Secondary circuit 181: Capacitor 182: Resistor 183: Resistor 190: resistor 200: Timing diagram 210: Primary gate waveform 220: Secondary gate waveform 230: One-time drain waveform/one-time adjustment loop trigger waveform 240: Secondary drain waveform 250: Bottom detection waveform 260: constant current, constant voltage regulation loop trigger waveform 300: Timing diagram 310: Action Cube 320: Action Block 330: Action Block 340: Decision Cube 350: Action Block 360: Action Cube 400: Line voltage detection circuit 410: Drain voltage detection circuit 411: current amplifier 412: Resistor 413: resistor 414: Diode 420: Output voltage detection circuit 421: current amplifier 422: Resistor 423: Diode 430: threshold voltage generating circuit 431: Voltage Source 432: Current Amplifier 433: Resistor 434: Resistor 435: Diode 436: switch 437: Resistor 440: Comparator 450: output latch 500: Output voltage detection circuit 510: Voltage divider 511: Resistor 512: resistor 520: High output voltage detection circuit 521: Resistor 522: Resistor 523: Comparator 530: Low output voltage detection circuit 531: resistor 532: resistor 533: Comparator 540: Latch 550: or gate 600: Timing diagram 610: Pri_Gate waveform 620: The first SR_Gate waveform 630: Second SR_Gate waveform 700: Part of the ZVS decision circuit 710: Line voltage detection circuit 720: Output voltage detection circuit/voltage detection circuit 730: DCM detection circuit 740: and gate AC IN: alternating current (AC) input voltage BIAS: the first output terminal CC/CV_Pulse: constant current, constant voltage regulation loop trigger waveform/control signal CSP: Primary current sensing terminal CSS: Secondary current sensing terminal D: input DCM_MODE: signal DRAIN: terminal EXT_CTL: signal GATEP: drive signal GATES: Secondary gate drive terminal GNDP: Primary ground terminal GNDS: secondary ground terminal HI_LINE: signal HI_VOUT: signal HV: High voltage terminal Pri_Drain: Drain waveform/signal once Pri_Gate: Primary gate waveform/signal Pri_Pulse_OUT: Trigger waveform/control signal of a regulation loop Pulse_IN: control pulse signal Pulse_OUT: signal Q: Real output R: Reset input S: Setting input SCL: Serial clock terminal SCL/SD: Serial clock and serial data signal SD/IMOD: Multi-function terminal/terminal SDA: Serial data and address terminal SDA/FB: Serial data and feedback terminal/terminal SR_Drain: secondary drain waveform/signal/voltage SR_Gate: secondary gate waveform/signal/pulse SR_Gate_B: Pulse SR_NVW: Valley detection waveform/control signal TDELAY: amount of time TH1: first threshold TH2: second threshold TZVS: time t1: focus on time t2: focus on time t3: focus on time t4: focus on time t5: focus on time TDelay: amount of time TURN_ON ALLOW: signal VDDP: Primary voltage terminal VDDS: Power supply voltage terminal/terminal VIN: Input voltage terminal/pin VOUT: Output voltage/terminal VS: Voltage sensing terminal/terminal VTrim: Voltage ZVS_EN: Control signal

Those with ordinary knowledge in the technical field can better understand the present disclosure by referring to the accompanying drawings, and many features and advantages of the present disclosure become obvious. In the accompanying drawings: [Figure 1] According to an embodiment of the present invention, a partial block diagram and a partial schematic form of a flyback power converter using partial zero voltage switching (ZVS) are shown; [Figure 2] shows a timing diagram showing part of the ZVS technology used in the flyback power converter of Figure 1; [Figure 3] shows a timing diagram that can be used to understand the operation of the flyback power converter in Figure 1; [Figure 4] A partial block diagram and partial schematic diagram of the line voltage detection circuit used in the secondary controller of Figure 1 to determine whether the line voltage exceeds the first threshold; [Figure 5] A partial block diagram and partial schematic diagram of the output voltage detection circuit used in the secondary controller of Figure 1 to determine whether the output voltage exceeds the second threshold; [Figure 6] A partial block diagram and partial schematic diagram of the DCM detection circuit used in the secondary controller of Figure 1 to determine whether the converter is operating in the DCM; and [Figure 7] A part of the ZVS decision circuit is shown in block diagram form according to an embodiment of the present invention.

The same reference symbols are used in different drawings to indicate similar or equivalent components. Unless otherwise specified, the term "coupled" and its related verbs include direct connection and indirect electrical connection by means known in the art, and unless otherwise specified, any description of direct connection also implies the use of appropriate forms. Alternative embodiment of indirect electrical connection.

700: Part of the ZVS decision circuit

710: Line voltage detection circuit

720: Output voltage detection circuit/voltage detection circuit

730: DCM detection circuit

740: and gate

Claims (10)

A controller used in a power converter, the power converter has a flyback transformer, the flyback transformer has a primary winding switched by a primary side transistor and a secondary side The primary and secondary windings of crystal switching, the controller includes: A line voltage detection circuit for activating a high line detection signal in response to detecting that an input line voltage is greater than a first threshold; A discontinuous conduction mode detection circuit for activating a discontinuous conduction mode signal in response to detecting that the controller is operating in the discontinuous conduction mode; and A switching controller coupled to the line voltage detection circuit and the discontinuous conduction mode detection circuit for using partial zeros in response to the activation of one of the high line detection signal and the discontinuous conduction mode signal Voltage switching is used to control the primary side transistor and the secondary side transistor, and in other cases, partial zero voltage switching is not used to control the primary side transistor and the secondary side transistor. Such as the controller of claim 1, wherein the line voltage detection circuit includes: A drain voltage detection circuit for providing a drain voltage sensing signal proportional to a voltage of a drain of the secondary side transistor system conducting; An output voltage detection circuit for providing an output voltage sensing signal proportional to an output voltage of the power converter; and A comparator for comparing a difference between the drain voltage sensing signal and the output voltage sensing signal with a second threshold, The line voltage detection circuit provides the high line detection signal in response to the comparator detecting that the difference is greater than the second threshold. Such as the controller of claim 2, wherein the line voltage detection circuit further includes: A threshold voltage generating circuit having an input for receiving a trim voltage and an output for providing the second threshold based on a high-line voltage threshold and a turns ratio of the flyback transformer . For example, the controller of claim 1, wherein the discontinuous conduction mode detection circuit detects that the controller is operating in the discontinuous conduction mode in response to detecting that the following two do not overlap: the controller responds to a The control loop is used to activate a primary gate drive signal to a trigger pulse of the primary side transistor; and after one of the previous primary side gate drive signals is disabled, to one or two of the secondary side transistor One of the secondary gate drive signals is activated first. For example, the controller of claim 1, which further includes: An output voltage detection circuit for activating a high output voltage detection signal in response to detecting that an output voltage across the secondary winding is greater than a second threshold, The switching controller is further coupled to the output voltage detection circuit, and uses partial zero voltage switching in response to activation of one of the high line detection signal, the discontinuous conduction mode signal, and the high output voltage detection signal To control the primary side transistor and the secondary side transistor, and in other cases, do not use partial zero voltage switching to control the primary side transistor and the secondary side transistor. Such as the controller of request 1, where: The controller is formed in a single integrated circuit package and has a primary controller and a secondary controller, wherein the secondary controller and the primary controller are galvanically isolated and communicatively coupled to the primary controller. A power converter including: A flyback transformer, which has a primary winding and a secondary winding; A primary side transistor, which is coupled in series with the primary winding; A secondary side transistor, which is coupled in series with the secondary winding; A controller, which includes: A line voltage detection circuit for activating a high line detection signal in response to detecting that an input line voltage is greater than a first threshold; A discontinuous conduction mode detection circuit for activating a discontinuous conduction mode signal in response to detecting that the controller is operating in the discontinuous conduction mode; and A switching controller coupled to the line voltage detection circuit and the discontinuous conduction mode detection circuit for using partial zeros in response to the activation of one of the high line detection signal and the discontinuous conduction mode signal Voltage switching is used to control the primary side transistor and the secondary side transistor, and in other cases, partial zero voltage switching is not used to control the primary side transistor and the secondary side transistor. Such as the power converter of claim 7, which further includes: An output voltage detection circuit for activating a high output voltage detection signal in response to detecting that an output voltage across the secondary winding is greater than a second threshold, The switching controller is further coupled to the output voltage detection circuit, and uses partial zero voltage switching in response to activation of one of the high line detection signal, the discontinuous conduction mode signal, and the high output voltage detection signal To control the primary side transistor and the secondary side transistor, and in other cases, do not use partial zero voltage switching to control the primary side transistor and the secondary side transistor. A method for selectively operating a power converter in a partial zero-voltage switching mode. The power converter has a flyback transformer, and the flyback transformer has one-to-one switching by a primary-side transistor. The secondary winding and the primary and secondary winding switched by a secondary side transistor, the method includes: Detect an input line voltage; Detect an output voltage; Detecting an operation mode of a control loop of the power converter; In response to detecting that the input line voltage is greater than a first threshold, detecting that the output voltage is greater than a second threshold, and detecting that the operation mode is a discontinuous conduction mode, the control loop is operated in This part of the zero voltage switching mode; and In response to at least one of detecting that the input line voltage is less than the first threshold, detecting that the output voltage is less than the second threshold, and detecting that the operation mode is the discontinuous conduction mode, The control loop operates in another mode other than the partial zero voltage switching mode. The method of claim 9, wherein the operating the control loop in the partial zero voltage switching mode includes: Disable the primary side transistor; Starting the secondary side transistor after deactivating the primary side transistor; When the primary secondary side current generated in response to the activation is discharged to zero, the secondary side transistor is disabled; After the secondary-side transistor is disabled, a trigger pulse is generated in response to a secondary-side control loop using valley switching; Activating the secondary-side transistor in response to the generation of the trigger pulse, and then deactivating the secondary-side transistor at the end of a predetermined time; and Then, in response to a drain voltage of the secondary side transistor reaching a valley value, the primary side transistor is activated.

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