TWI811380B - Multilayer ceramic capacitor and manufacturing method of the same - Google Patents

Abstract

A multilayer ceramic capacitor includes: a multilayer chip in which each of dielectric layers and each of internal electrode layers are alternately stacked and the internal electrode layers are alternately exposed to two end faces; and external electrodes formed on the two end faces; wherein: a relationship “M ≥ -0.00002 × EM + 0.0012” is satisfied, when a length of end margins in a direction in which the two end faces face with each other is EM [μm] and a concentration of Mo with respect to a B site element of a main component ceramic of the end margins is M [atm%], wherein the end margin is a region, in which internal electrode layers connected to one of the external electrodes without sandwiching internal electrode layers connected to the other of the external electrode, face with each other, in the multilayer chip.

Description

Multilayer ceramic capacitor and manufacturing method thereof

The present invention relates to a multilayer ceramic capacitor and a manufacturing method thereof.

A laminated ceramic capacitor has a laminated body in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately laminated, and a pair of external electrodes formed on the surface of the laminated body so as to be electrically connected to the internal electrode layers drawn out to the surface of the laminated body. . The external electrode is plated on the base layer. It is known that hydrogen generated during the plating process is absorbed near the external electrode and then diffuses into the body, causing IR (Insulation Resistance) degradation.

Patent Document 1 describes that hydrogen generated during the plating process is absorbed into the internal electrode and reduces the dielectric layer, thereby degrading the insulation resistance. Furthermore, Patent Document 1 describes that when an internal electrode containing a noble metal as a main component is used, Ni (nickel) is added as a metal that suppresses hydrogen absorption. Patent Document 2 describes thickening the external electrode on the anode side in order to maintain moisture resistance reliability. [Prior technical literature] [Patent Document]

[Patent Document 1] Japanese Patent Application Laid-Open No. 1-80011 [Patent Document 2] Japanese Patent Application Publication No. 2015-188046

[Problem to be solved by the invention]

However, it is difficult to sufficiently suppress IR degradation by the above-mentioned techniques.

The present invention was made in view of the above-mentioned problems, and an object thereof is to provide a multilayer ceramic capacitor capable of suppressing IR degradation and a manufacturing method thereof. [Technical means to solve problems]

The laminated ceramic capacitor of the present invention is characterized by having a laminated chip in which dielectric layers and internal electrode layers mainly composed of ceramics are alternately laminated, and a plurality of the laminated internal electrode layers are alternately laminated on two opposite sides. It is formed with the end surfaces exposed and has a substantially rectangular parallelepiped shape; and a pair of external electrodes, which are formed on the two end surfaces; the pair of external electrodes have a structure in which a plating layer is formed on a base layer, and the base layer contains Ni A metal or alloy of at least any one of Cu and When the concentration of the B-site element of the component ceramic is set to M [atm%], M ≧ -0.00002 The exposed portion of the end surface facing the internal electrode layer.

In the above-mentioned multilayer ceramic capacitor, the above-mentioned plating layer may also include a Sn plating layer.

In the above-mentioned multilayer ceramic capacitor, the main component metal of the above-mentioned base layer may also be Ni.

In the above-mentioned multilayer ceramic capacitor, the above-mentioned internal electrode layer may have Ni as its main component.

In the above-mentioned multilayer ceramic capacitor, the length EM of the above-mentioned end edge may also be less than 60 μm.

In the above-mentioned laminated ceramic capacitor, the above-mentioned Mo concentration can also be used to perform ICP-MS (Inductively Coupled Plasma-Mass Spectrometry, Inductively Coupled Plasma-Mass Spectrometry) by irradiating the entire end edge area with laser in a cross-section parallel to the side surface of the laminated chip. ) obtained by analysis.

The manufacturing method of the multilayer ceramic capacitor of the present invention is characterized in that ceramic dielectric layer green sheets and conductive paste for forming internal electrodes are alternately laminated so that a plurality of laminated conductive pastes for forming internal electrodes are alternately exposed on both opposite end surfaces. , thereby forming a substantially rectangular parallelepiped-shaped ceramic laminate, and applying a metal paste in contact with the two end surfaces. The metal paste contains metal powder containing as a main component a metal or alloy containing at least one of Ni and Cu. , and Mo source, by firing the ceramic laminate coated with the metal paste, the ceramic laminate becomes a laminated wafer, the metal paste becomes a base layer, and plating is performed on the base layer, Form an external electrode including the base layer and the plating layer. Let the length of the end edge in the direction in which the two end faces face be EM [μm]. Let the end edge Mo be relative to the B-site element of the main component ceramic. When the concentration is set to M [atm%], adjust the amount of the Mo source added in the metal paste in such a way that M≧-0.00002×EM+0.0012 is established. The end edges are exposed at the same end face of the laminated wafer The internal electrode layers are opposed to each other without being separated from the internal electrode layers exposed at different end surfaces. [Effects of the invention]

According to the present invention, IR degradation can be suppressed.

Hereinafter, embodiments will be described with reference to the drawings.

(implementation form) FIG. 1 is a partially cross-sectional perspective view of a multilayer ceramic capacitor 100 according to the embodiment. Figure 2 is a cross-sectional view along line A-A in Figure 1. Figure 3 is a cross-sectional view along line B-B of Figure 1. As illustrated in FIGS. 1 to 3 , the multilayer ceramic capacitor 100 includes a multilayer wafer 10 having a substantially rectangular parallelepiped shape, and external electrodes 20 a and 20 b provided on arbitrary opposite end surfaces of the multilayer wafer 10 . Furthermore, among the four surfaces of the laminated wafer 10 other than the two end surfaces, the two surfaces other than the upper surface and the lower surface in the lamination direction are called side surfaces. The external electrodes 20 a and 20 b extend on the upper surface, the lower surface, and two side surfaces of the laminated wafer 10 in the lamination direction. Among them, the external electrodes 20a and 20b are separated from each other.

The laminated wafer 10 has a structure in which dielectric layers 11 including ceramic materials functioning as dielectrics and internal electrode layers 12 including base metal materials are alternately laminated. The edge of each internal electrode layer 12 is alternately exposed on the end surface where the external electrode 20 a is provided and the end surface where the external electrode 20 b is provided on the laminated chip 10 . Thereby, each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a structure in which a plurality of dielectric layers 11 are laminated with the internal electrode layers 12 interposed therebetween. In addition, in the laminated structure of the dielectric layer 11 and the internal electrode layer 12, the internal electrode layer 12 is arranged on the outermost layer in the lamination direction, and the upper surface and the lower surface of the laminated body are covered with the covering layer 13. The covering layer 13 mainly consists of ceramic material. For example, the main component of the material of the covering layer 13 is the same ceramic material as that of the dielectric layer 11 .

The dimensions of the multilayer ceramic capacitor 100 are, for example, length 0.25 mm, width 0.125 mm, height 0.125 mm, or length 0.4 mm, width 0.2 mm, height 0.2 mm, or length 0.6 mm, width 0.3 mm, height 0.3 mm, or length 1.0 mm , width 0.5 mm, height 0.5 mm, or length 3.2 mm, width 1.6 mm, height 1.6 mm, or length 4.5 mm, width 3.2 mm, height 2.5 mm, but are not limited to these dimensions.

The internal electrode layer 12 mainly contains base metals such as Ni (nickel), Cu (copper), and Sn (tin). As the internal electrode layer 12, noble metals such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold), or alloys containing the same can also be used. The average thickness of the internal electrode layer 12 is, for example, 1 μm or less. The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO ₃ , for example. Furthermore, the perovskite structure contains ABO _{3- α} that deviates from the stoichiometric composition. For example, as the ceramic material, BaTiO ₃ (barium titanate), CaZrO ₃ (calcium zirconate), CaTiO ₃ (calcium titanate), SrTiO ₃ (strontium titanate), and Ba _1- forming a perovskite structure can be used. _xy Ca _x Sr _y Ti _1-z Zr _z O ₃ (0≦x≦1, 0≦y≦1, 0≦z≦1), etc. The average thickness of the dielectric layer 11 is, for example, 1 μm or less.

As illustrated in FIG. 2 , the area where the internal electrode layer 12 connected to the external electrode 20 a faces the internal electrode layer 12 connected to the external electrode 20 b is the area where capacitance is generated in the multilayer ceramic capacitor 100 . Therefore, the region where capacitance is generated is called capacitance region 14 . That is, the capacitance region 14 is connected to the region where adjacent internal electrode layers 12 of different external electrodes face each other.

A region in which the internal electrode layers 12 connected to the external electrode 20 a face each other without intervening the internal electrode layer 12 connected to the external electrode 20 b is called an end edge region 15 . In addition, the internal electrode layers 12 connected to the external electrode 20b are not separated from each other by the internal electrode layers 12 connected to the external electrode 20a, and the opposing regions are also end edge regions 15. That is, the end edge region 15 is a region facing the internal electrode layer 12 connected to the same external electrode without intervening the internal electrode layer 12 connected to a different external electrode. The end edge area 15 is an area where no capacitance is generated.

As illustrated in FIG. 3 , the area from both side surfaces of the laminated wafer 10 to the internal electrode layer 12 in the laminated wafer 10 is called a side edge region 16 . That is, the side edge region 16 is a region provided so as to cover the ends of the plurality of internal electrode layers 12 laminated in the above-mentioned multilayer structure and extend to both side surfaces. The side edge area 16 is also an area where no capacitance is generated.

FIG. 4 is a cross-sectional view of the external electrode 20a, and is a partial cross-sectional view along line A-A in FIG. 1 . In addition, the hatching indicating the cross section is omitted in FIG. 4 . As illustrated in FIG. 4 , the external electrode 20 a has a structure in which a Cu plating layer 22 , a Ni plating layer 23 and a Sn plating layer 24 are formed on the base layer 21 . The base layer 21 , Cu plating layer 22 , Ni plating layer 23 and Sn plating layer 24 extend from both end surfaces of the laminated chip 10 to the upper surface, the lower surface and both side surfaces. Furthermore, in FIG. 4 , the external electrode 20 a is illustrated, and the external electrode 20 b also has the same structure.

The base layer 21 is mainly composed of a metal or alloy containing at least one of Ni and Cu. It may include a glass component for densifying the base layer 21 or a common material for controlling the sinterability of the base layer 21 . . The glass components are oxides of Ba, Sr, Ca, Zn (zinc), Al (aluminum), Si (silicon), B (boron), etc. The common material is a ceramic component, for example, the ceramic component that is the main component in the dielectric layer 11 .

In addition, the base layer 21 contains Mo (molybdenum). Since the base layer 21 contains Mo, hydrogen generated when the Cu plating layer 22 , the Ni plating layer 23 and the Sn plating layer 24 are formed can be suppressed from intruding into the internal electrode layer 12 . For example, Mo has the function of preventing hydrogen permeation. It is considered that Mo, which prevents hydrogen permeation, is contained in the base layer 21 and diffuses to the ceramic part 17 near the external electrodes 20a and 20b according to the concentration gradient. Therefore, the hydrogen permeability in the base layer 21 and the ceramic part 17 is reduced and blocked. Eliminate the intrusion path of hydrogen (exerting a blocking effect). The ceramic portion 17 refers to a region of the laminated wafer 10 closer to each end surface than an opposing region where the internal electrode layers 12 connected to different external electrodes face each other. The ceramic portion 17 includes a portion of the covering layer 13 , the entire end edge region 15 , and a portion of the side edge region 16 . If the intrusion path of hydrogen is blocked, the absorption of hydrogen into the internal electrode layer 12 is suppressed, thereby suppressing the reduction of the dielectric layer 11 . Thereby, the insulation resistance of the multilayer ceramic capacitor 100 is suppressed from decreasing. Furthermore, during the plating steps of the Cu plating layer 22 and the Ni plating layer 23, more hydrogen will be generated on the surface of the plating object. Therefore, blocking the intrusion path of hydrogen is particularly effective.

In addition, if part of Mo in the base layer 21 diffuses into the dielectric layer 11, the diffused Mo will replace the B site of the perovskite structure shown in ABO ₃ and function as a donor. Thereby, the generation of oxygen defects in the ceramic constituting the dielectric layer 11 can be suppressed. As a result, the reduction resistance of the dielectric layer 11 is improved. In addition, in this embodiment, Mo is focused as an element contained in the base layer 21, but it is not limited to this. Elements that have the effect of preventing hydrogen permeation and function as donors instead of the B position, such as Nb (niobium), Ta (tantalum), W (tungsten), etc., can also be used instead of Mo.

Furthermore, if the internal electrode layer 12 contains Ni as the main component, the hydrogen storage property of the internal electrode layer 12 becomes higher. Therefore, when the internal electrode layer 12 mainly contains Ni, it is particularly effective to suppress the intrusion of hydrogen from the external electrodes 20a and 20b. In addition, during the plating step of the Cu plating layer 22 and the Ni plating layer 23, a large amount of hydrogen is generated on the surface of the plating object. Therefore, blocking the intrusion path of hydrogen is particularly effective.

In addition, Sn has higher density. The reason is that Sn has the most densely packed structure. If the Sn plating layer 24 is provided on the base layer 21 , hydrogen is more likely to be sealed into the laminated wafer 10 side than the Sn plating layer 24 . That is, the influence of hydrogen becomes easy to occur. Therefore, when the Sn plating layer 24 is provided on the base layer 21, it is particularly effective to suppress the intrusion of hydrogen from the external electrodes 20a and 20b.

The multilayer ceramic capacitor 100 has been required to be miniaturized and increased in capacity. For this purpose, the end edge areas 15 and the side edge areas 16 are designed to be smaller. Here, as illustrated in FIG. 2 , the length EM is defined as the length of each end edge region 15 in the direction in which the end surfaces of the laminated wafer 10 face each other. There is a correlation between the number of IR degradation (the number of laminated ceramic capacitors that cause IR degradation relative to a specific number of laminated ceramic capacitors) in reliability tests (humidity load resistance test, etc.) and the length EM of the end edge region 15 . Specifically, as the end edge region 15 becomes shorter, the number of IR degradation gradually increases.

The present inventors conducted intensive research and found that if the end edge region 15 is shorter, the amount of MoO ₃ added to the external electrode forming metal paste used to form the base layer 21 is increased, causing diffusion. When the amount of Mo reaches the end edge region 15 is increased, IR degradation can be suppressed. Specifically, the present inventors found that by making the length EM [μm] of each end edge region 15 and the concentration M of Mo in the end edge region 15 relative to the B-site element of the main component ceramic (in BaTiO ₃ In this case, the Mo/Ti ratio (concentration of Mo relative to Ti) (atm%)), the following formula (1) is established, and IR degradation can be suppressed. Figure 5 shows the following formula (1). M≧-0.00002×EM+0.0012 (1)

From the viewpoint of suppressing IR degradation, it is preferable that the amount of Mo in the end edge region 15 is large. Therefore, M≧-0.00002×EM+0.0014 is preferred, and M≧-0.00002×EM+0.0016 is more preferred.

Furthermore, if the end edge region 15 is sufficiently long, IR degradation can be suppressed even if Mo is not included in the end edge region 15 . Specifically, when the length EM exceeds 60 μm, Mo may not be included in the end edge region 15 . Therefore, when the length EM is less than 60 μm, it is preferable to include Mo in the end edge region 15 .

Furthermore, the Mo/Ti ratio can be obtained by analyzing the end edge region 15 of the cross-section parallel to the side as shown in FIG. 2 by ICP-MS. For example, the Mo/Ti ratio can be obtained by performing ICP-MS analysis by irradiating laser throughout the end edge region of the cross section in Figure 2 .

Next, a method of manufacturing the multilayer ceramic capacitor 100 will be described. FIG. 6 is a diagram illustrating the flow of a manufacturing method of the multilayer ceramic capacitor 100.

(Raw material powder production steps) First, according to the purpose, a specific additive compound is added to the powder of the ceramic material that is the main component of the dielectric layer 11 . Examples of additive compounds include Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gallium), Tb (dyronium), Dy (dysprosium), Ho (鈥), Er (erbium), Tm (銩) and Yb (ytterbium)) oxides, and Co (cobalt), Ni, Li (lithium), B, Na (Sodium), K (potassium) and Si oxides or glasses. For example, first, a compound containing an additive compound is mixed with powder of a ceramic material and calcined. Next, the obtained ceramic material particles and the additive compound are wet-mixed, dried and pulverized to prepare ceramic material powder.

(Layering step) Then, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol and toluene, and a plasticizer are added to the obtained ceramic material powder, and wet mixing is performed. Using the obtained slurry, for example, by a die coating method or a doctor blade method, a strip-shaped dielectric green sheet with a thickness of 0.8 μm or less is coated on the substrate and allowed to dry.

Then, the conductive paste for internal electrode formation is printed on the surface of the dielectric green sheet by screen printing, gravure printing, etc., thereby arranging the pattern of the internal electrode layer 12 . The conductive paste for forming the internal electrode layer contains powder of the metal that is the main component of the internal electrode layer 12, a binder, a solvent, and other auxiliaries as needed. It is preferable to use binders and solvents that are different from the above-mentioned ceramic slurry. Furthermore, the ceramic material that is the main component of the dielectric layer 11 may be dispersed as a common material in the conductive paste for forming internal electrodes.

Then, the dielectric green sheet printed with the internal electrode layer pattern is punched to a specific size, and the punched dielectric green sheet is peeled off from the base material in a manner such that the internal electrode layer 12 and the dielectric layer 11 are interlaced. A specific number of layers (for example, 200 to 500 layers) are stacked in such a manner that the ends of the internal electrode layers 12 are alternately exposed at both ends in the length direction of the dielectric layer 11 and are alternately drawn out to a pair of external electrodes with different polarities. A covering sheet as the covering layer 13 is pressed onto the top and bottom of the laminated pattern forming sheet and cut into a specific wafer size (for example, 1.0 mm×0.5 mm). Thereby, a substantially rectangular parallelepiped-shaped ceramic laminated body can be obtained.

(Metal paste coating step) Next, the ceramic laminated body obtained in the lamination step is debonded in an _N2 atmosphere at 200°C to 500°C, and then metal fillers are coated on both ends of the ceramic laminated body to each side. Materials, adhesives, solvents and metal pastes containing molybdenum sources are allowed to dry. This metal paste is a metal paste for forming external electrodes.

The type, shape, etc. of the moiety are not particularly limited. For example, as the Mo source, specifically, molybdenum oxide (MoO ₂ , MoO ₃ ), molybdenum chloride (MoCl ₂ , MoCl ₃ , MoCl ₄ ), molybdenum hydroxide (Mo(OH) ₃ , Mo(OH)) can be used. ₅ ), barium molybdate (BaMoO ₄ ), ammonium molybdate ((NH ₄ ) ₆ Mo ₇ O ₂₄・4H ₂ O), molybdenum-nickel alloy, etc. Alternatively, Mo may be dissolved in a common material in advance and the common material may be used as the Mo source.

(firing step) Then, the ceramic laminate coated with the metal paste for forming external electrodes is fired at 1100 to 1300° C. for 10 minutes to 2 hours in a reducing atmosphere. In this way, a sintered body is obtained, which has the laminated wafer 10 in which the dielectric layer 11 and the internal electrode layer 12 containing the sintered body are alternately laminated, the cover layer 13 formed as the outermost layer in the vertical direction of the lamination, and the base layer. 21.

(Plating process step) Thereafter, by performing plating processing steps, the Cu plating layer 22, the Ni plating layer 23, and the Sn plating layer 24 are sequentially formed on the base layer 21. Through the above steps, the multilayer ceramic capacitor 100 is completed.

According to the manufacturing method of this embodiment, the base layer 21 contains Mo. In this case, hydrogen generated when the Cu plating layer 22 , the Ni plating layer 23 and the Sn plating layer 24 are formed can be suppressed from intruding into the internal electrode layer 12 . Thereby, the storage of hydrogen into the internal electrode layer 12 can be suppressed, and the reduction of the dielectric layer 11 can be suppressed. As a result, reduction in insulation resistance can be suppressed. In addition, if part of Mo in the base layer 21 diffuses into the dielectric layer 11, the diffused Mo will replace the B site of the perovskite structure shown in ABO ₃ and function as a donor. Thereby, the generation of oxygen defects in the ceramic constituting the dielectric layer 11 can be suppressed. As a result, the reduction resistance of the dielectric layer 11 is improved.

Alternatively, the Mo source may not be added to the metal paste before forming the external electrodes, but the Mo source may be formed by sputtering before or after the metal paste is applied, or both. film, thereby achieving the same effect through diffusion during firing.

Furthermore, during firing, Mo of the metal paste for forming external electrodes diffuses to the end edge region 15 . Therefore, in this embodiment, let the length of each end edge region 15 in the completed multilayer ceramic capacitor 100 be EM, and let the concentration of Mo in the end edge region 15 relative to the B-site element of the main component ceramic (atm When %) is set to M, the amount of the Mo source added to the metal paste for external electrode formation is adjusted so that the above formula (1) is established. Thereby, IR degradation can be suppressed. In addition to the amount of Mo source added, the firing conditions (temperature, time, etc.) can also be adjusted. [Example]

Next, a multilayer ceramic capacitor according to the embodiment is produced and its characteristics are investigated.

(Examples 1 to 6) The required additives are added to the barium titanate powder, and the mixture is thoroughly mixed and pulverized using a ball mill to obtain a dielectric material. Add organic binder and solvent to the dielectric material, and use the scraper method to make the dielectric green sheet. The coating thickness of the dielectric green sheet is set to 1.2 μm, polyvinyl butyral (PVB), etc. are used as organic binders, and ethanol, toluic acid, etc. are added as solvents. In addition, plasticizers, etc. are also added. Next, a conductive paste for forming internal electrodes containing powder of the metal as the main component of the internal electrode layer 12, a binder, a solvent, and other auxiliaries as necessary is produced. The conductive paste used to form internal electrodes uses different organic binders and solvents from the dielectric green sheets. The conductive paste for forming internal electrodes is screen-printed on the dielectric sheet. 195 sheets printed with conductive paste for forming internal electrodes were stacked, and covering sheets were laminated on top and bottom of the sheets. Thereafter, a ceramic laminate is obtained by thermocompression bonding and cut into a specific shape.

After the obtained ceramic laminate is debonded in an _N2 atmosphere, a metal filler containing Ni as the main component, a common material, a binder, a solvent, and a Mo source are coated on both end surfaces and all sides of the ceramic laminate. of metal paste and let it dry. Use MoO ₃ as the Mo source. Thereafter, the metal paste and the ceramic laminated body are simultaneously fired in a reducing atmosphere at 1100°C to 1300°C for 10 minutes to 2 hours to obtain a sintered body.

The shape and dimensions of the obtained sintered body were 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height. The sintered body is re-oxidized in an _N2 atmosphere at 800°C and then plated to form a Cu plating layer 22, a Ni plating layer 23 and a Sn plating layer 24 on the surface of the base layer 21. Thus, the multilayer ceramic capacitor 100 is obtained. 1000 samples of Examples 1 to 6 were produced respectively.

The length EM of the end edge region 15 is 70 μm. Therefore, the M value that satisfies the above equation (1) is -0.02 atm%. In Example 1, the Mo/Ti ratio of the end edge region 15 is 0.005 atm%. In Example 2, the Mo/Ti ratio of the end edge region 15 is 0.010 atm%. In Example 3, the Mo/Ti ratio of the end edge region 15 is 0.020 atm%. In Example 4, the Mo/Ti ratio of the end edge region 15 is 0.050 atm%. In Example 5, the Mo/Ti ratio of the end edge region 15 is 0.100 atm%. In Example 6, the Mo/Ti ratio of the end edge region 15 is 0.300 atm%. These Mo/Ti ratios are obtained by analyzing the end edge region 15 of the cross-section parallel to the side as shown in Figure 2 by ICP-MS. As an analysis device, ICP-MS (model 7900 manufactured by Agilent Technologies) was used. As the laser device, model NWR213 manufactured by esi Corporation is used. Set the laser spot diameter to 3 μm, set the laser irradiation energy to 7.5 J/cm ² , irradiate the laser throughout the end edge area of the cross section in Figure 2, and conduct ICP-MS analysis to obtain Mo/Ti Compare. In addition, the Mo/Ti ratio was also obtained by the same analysis method in the Examples and Comparative Examples described later.

(Examples 7 to 10 and Comparative Examples 1 and 2) A multilayer ceramic capacitor was produced under the same conditions as in Examples 1 to 6. In Examples 7 to 10 and Comparative Examples 1 and 2, the length EM of the end edge region 15 was set to 50 μm. Therefore, the M value that satisfies the above equation (1) is 0.02 atm%. In Example 7, the Mo/Ti ratio of the end edge region 15 is 0.020 atm%. In Example 8, the Mo/Ti ratio of the end edge region 15 is 0.050 atm%. In Example 9, the Mo/Ti ratio of the end edge region 15 is 0.100 atm%. In Example 10, the Mo/Ti ratio of the end edge region 15 is 0.300 atm%. In Comparative Example 1, the Mo/Ti ratio of the end edge region 15 is 0.005 atm%. In Comparative Example 2, the Mo/Ti ratio of the end edge region 15 is 0.010 atm%.

(Examples 11 to 13 and Comparative Examples 3 to 5) A multilayer ceramic capacitor was produced under the same conditions as in Examples 1 to 6. In Examples 11 to 13 and Comparative Examples 3 to 5, the length EM of the end edge region 15 was set to 35 μm. Therefore, the M value that satisfies the above equation (1) is 0.05 atm%. In Example 11, the Mo/Ti ratio of the end edge region 15 is 0.050 atm%. In Example 12, the Mo/Ti ratio of the end edge region 15 is 0.100 atm%. In Example 13, the Mo/Ti ratio of the end edge region 15 is 0.300 atm%. In Comparative Example 3, the Mo/Ti ratio of the end edge region 15 is 0.005 atm%. In Comparative Example 4, the Mo/Ti ratio of the end edge region 15 is 0.010 atm%. In Comparative Example 5, the Mo/Ti ratio of the end edge region 15 is 0.020 atm%.

(Examples 14, 15 and Comparative Examples 6 to 9) A multilayer ceramic capacitor was produced under the same conditions as in Examples 1 to 6. In Examples 14 and 15 and Comparative Examples 6 to 9, the length EM of the end edge region 15 was set to 10 μm. Therefore, the M value that satisfies the above equation (1) is 0.10 atm%. In Example 14, the Mo/Ti ratio of the end edge region 15 is 0.100 atm%. In Example 15, the Mo/Ti ratio of the end edge region 15 is 0.300 atm%. In Comparative Example 6, the Mo/Ti ratio of the end edge region 15 is 0.005 atm%. In Comparative Example 7, the Mo/Ti ratio of the end edge region 15 is 0.010 atm%. In Comparative Example 8, the Mo/Ti ratio of the end edge region 15 is 0.020 atm%. In Comparative Example 9, the Mo/Ti ratio of the end edge region 15 is 0.050 atm%.

Each of Examples 1 to 15 and Comparative Examples 1 to 9 was subjected to a withstand voltage test at temperature = 85° C., relative humidity 85%, and 10 V for 100 hours. In this case, investigate the occurrence rate of samples that become 100 MΩ or less within 60 seconds (IR defect occurrence rate). Table 1 shows the results. Furthermore, in Table 1, "M value" represents the lower limit of the Mo concentration that satisfies the above formula (1). When the above-mentioned formula (1) is established, the "expression judgment" is "○", and when the above-mentioned formula (1) is not established, the "expression judgment" is "×". [Table 1]

As shown in Table 1, in any of Examples 1 to 15, the IR degradation number was 0/1000. The reason is considered to be that since the above-mentioned formula (1) is established, the intrusion of hydrogen from the external electrodes 20a and 20b into the laminated wafer 10 can be suppressed, and the diffusion of hydrogen can be suppressed even if it has intruded. On the other hand, in any of Comparative Examples 1 to 9, the IR degradation number exceeded 0/1000. The reason for this is considered to be that since the above formula (1) does not hold, the intrusion of hydrogen from the external electrodes 20a and 20b into the laminated wafer 10 can be sufficiently suppressed, and the intruded hydrogen can be diffused.

The embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific embodiments, and various changes and modifications can be made within the scope of the gist of the present invention described in the patent application.

10‧‧‧Laminated wafer 11‧‧‧Dielectric layer 12‧‧‧Internal electrode layer 13‧‧‧Covering layer 14‧‧‧Capacitor area 15‧‧‧End edge area 16‧‧‧Side edge area 17‧‧‧Ceramics Department 20a‧‧‧External electrode 20b‧‧‧External electrode 21‧‧‧Basilar layer 22‧‧‧Cu plating layer 23‧‧‧Ni plating layer 24‧‧‧Sn plating layer 100‧‧‧Multilayer Ceramic Capacitor

Figure 1 is a partially cutaway perspective view of a multilayer ceramic capacitor. Figure 2 is a cross-sectional view along line A-A in Figure 1. Figure 3 is a cross-sectional view along line B-B of Figure 1. FIG. 4 is a cross-sectional view of the external electrode, and a partial cross-sectional view along line A-A in FIG. 1 . Figure 5 is a diagram expressing equation (1). FIG. 6 is a diagram illustrating the flow of a manufacturing method of a multilayer ceramic capacitor.

10‧‧‧Laminated wafer

11‧‧‧Dielectric layer

12‧‧‧Internal electrode layer

13‧‧‧Covering layer

20a‧‧‧External electrode

20b‧‧‧External electrode

100‧‧‧Multilayer Ceramic Capacitor

Claims (9)

A laminated ceramic capacitor, characterized by having: a laminated chip in which dielectric layers and internal electrode layers mainly composed of ceramics are alternately laminated, and a plurality of the laminated internal electrode layers are alternately exposed on both opposite end surfaces is formed in a manner and has a substantially rectangular parallelepiped shape; and a pair of external electrodes, which are formed on the two end surfaces; and the pair of external electrodes have a structure in which a plating layer is formed on a base layer, and the base layer is composed of Ni and Cu is made of at least any metal or alloy as the main component, and Mo is included. Let the length of the end edge in the direction in which the above two end faces face be EM [μm]. Let the end edge Mo be relative to the main component. When the concentration of ceramic B-site elements is set to M [atm%], M≧-0.00002×EM+0.0012 is established. The above-mentioned end edges are the internal electrode layers exposed at the same end face in the above-mentioned laminated wafer and are not exposed at different end faces. The portion facing the internal electrode layer; the concentration of Mo in the base layer is higher than the concentration of Mo in the end edge. The multilayer ceramic capacitor of claim 1, wherein the plating layer includes an Sn plating layer. The multilayer ceramic capacitor of claim 1 or 2, wherein the main component metal of the above-mentioned base layer is Ni. A laminated ceramic capacitor according to claim 1 or 2, wherein the internal electrode layer contains Ni as a main component. The multilayer ceramic capacitor of claim 1 or 2, wherein the length EM of the end edge does not reach 60 μm. The laminated ceramic capacitor of claim 1 or 2, wherein the Mo concentration is obtained by irradiating the entire end edge area with laser and performing ICP-MS analysis on a cross-section parallel to the side surface of the laminated wafer. The laminated ceramic capacitor of claim 1 or 2, wherein the base layer contains a glass component or ceramic. The laminated ceramic capacitor of claim 1 or 2, wherein the Mo contained in the base layer is molybdenum oxide. A method for manufacturing a laminated ceramic capacitor, which is characterized in that: ceramic dielectric layer green sheets and conductive paste for forming internal electrodes are alternately laminated so that a plurality of laminated conductive pastes for forming internal electrodes are alternately exposed on opposite end surfaces, A substantially rectangular parallelepiped-shaped ceramic laminate is thereby formed, and a metal paste containing a metal powder containing a metal or alloy containing at least one of Ni and Cu as a main component is applied so as to be in contact with the two end surfaces. and a Mo source, by firing the ceramic laminated body coated with the metal paste, so that the ceramic laminated body becomes a laminated wafer, the metal paste becomes a base layer, and plating is performed on the base layer, Formation includes the above-mentioned base layer and plating layer For the external electrode, let the length of the end edge in the direction in which the above-mentioned two end faces face each other be EM [μm], and let the concentration of the above-mentioned end edge Mo relative to the B-site element of the main component ceramic be M [atm%] When M≧-0.00002×EM+0.0012 is established, the amount of the Mo source added in the metal paste is adjusted so that the end edges are not separated from each other by the internal electrode layers exposed at the same end face in the laminated wafer. The portion facing the exposed internal electrode layer on the end surface.