TWI809979B - Low power consumption driver circuit for LED display driver chip, LED display driver chip and LED display device - Google Patents

Abstract

A low-power drive stage circuit for LED display driver chips, which includes: a current-to-voltage circuit with a first PMOS transistor to generate a control voltage at its gate according to the current of a certain current source, wherein the The source of the first PMOS transistor is coupled to a first supply voltage, and its drain is biased at a certain voltage; and a current output circuit has a voltage-to-current unit, and the voltage-to-current unit has a channel variable A PMOS transistor, wherein the source of the channel variable PMOS transistor is coupled to the first supply voltage, the gate is coupled to the control voltage, the drain is biased at the constant voltage, and the channel variable The PMOS transistor system determines its channel width according to a plurality of switching signals.

Description

Low-power driver circuit for LED display driver chip, LED display driver chip and LED display device

The invention relates to an LED display driving circuit, in particular to a low power consumption driving stage circuit for an LED display driving chip.

Please refer to FIG. 1a, which shows a circuit diagram of a driver stage circuit of a conventional LED display chip. As shown in FIG. 1, the driver stage circuit includes a PMOS transistor 10, a PMOS transistor 20 and an amplifier 30 to drive an LED element 40, wherein the PMOS transistor 20 and the amplifier 30 are used in the PMOS transistor 10 The drain generates a certain voltage V _X , which is approximately equal to a reference voltage V _REF , so that the PMOS transistor 10 can accurately generate an output current I _O according to a control voltage V _CNTL .

In order to save power consumption, it is generally hoped that the channel voltage drop of the PMOS transistor 10 and the PMOS transistor 20 should be as small as possible. Therefore, the value of the reference voltage V _REF is generally set to AVDD-0.2V, and AVDD is the driving stage circuit. supply voltage. In this way, the input voltage of the amplifier 30 is AVDD-0.2V, which is a high input voltage and requires NMOS as the input stage of the amplifier 30; on the other hand, in order to flow a large current, the gate voltage of the PMOS transistor 20 should be as low as possible. Low to reduce the size of the PMOS transistor 20, so that the output of the amplifier 30 must provide a large swing (with respect to the swing of the reference ground). For this reason, the amplifier 30 has two commonly used structures, one is a two-stage type, and the other is a cascaded type.

Please refer to FIG. 1 b , which shows a circuit diagram of a two-stage structure of the amplifier 30 . As shown in FIG. 1b, the amplifier 30 includes an input stage and an output stage. The input stage includes a current source (composed of NMOS transistors 33), a differential input pair (composed of NMOS transistors 31a, 31b) and a Active load (composed of PMOS transistors 32a, 32b), and the output stage includes a PMOS transistor 34a and an NMOS transistor 34b connected in series between AVDD and the reference ground to provide a large output voltage swing. However, for compensation, the working current I3 of the output stage is greater than the working current (I1, I2) of the input stage, so that the two-stage architecture consumes a lot of power.

Please refer to FIG. 1 c , which shows a circuit diagram of a cascaded structure of the amplifier 30 . As shown in Figure 1c, the amplifier 30 includes an input stage and an output stage, the input stage includes a current source (formed by NMOS transistor 36) and a differential input pair (formed by NMOS transistors 35a, 35b), and The output stage includes a stacked active load (composed of PMOS transistors 37a, 37b, 38a, and 38b) connected in series between AVDD and the reference ground, and a pair of NMOS transistors (39a, 39b) in one of the The output terminal OUT provides a large output voltage swing. Although the operating current of each stage of the cascaded amplifier is not large, it requires 6 stages of operating current (I1-I6, wherein, I5 and I6 are used to generate bias voltages VBP1 and VBN1), and its power consumption is also very high. considerable.

It is worth mentioning that in the application of an LED display, the LED display driver chip uses N output channels to drive N columns of LED units, and N is a positive integer. When N is very large, the drive of these output channels The combined power consumed by the amplifiers in the stage circuit will be very large.

In order to solve the above problems, there is an urgent need in the art for a novel low power consumption driver stage circuit.

The main purpose of the present invention is to disclose a low power consumption driving stage circuit for LED display driving chip, which can effectively reduce the power consumption of the chip by canceling the amplifier in the current output channel.

Another object of the present invention is to disclose an LED display driver chip, which can effectively reduce the chip area and power consumption of the chip by the above-mentioned low power consumption driver circuit.

Another object of the present invention is to disclose a display device, which can effectively reduce the chip area of its LED driver chip and reduce its power consumption through the above-mentioned low power consumption driving stage circuit.

In order to achieve the aforementioned purpose, a low power consumption driver stage circuit for LED display driver chips is proposed, which includes: A current-to-voltage circuit has a first PMOS transistor to generate a control voltage at its gate according to the current of a certain current source, wherein the source of the first PMOS transistor is coupled to a first supply voltage, and its The drain is biased at a certain voltage; and A current output circuit has a voltage-to-current unit, and the voltage-to-current unit has a channel-variable PMOS transistor, wherein the source of the channel-variable PMOS transistor is coupled to the first supply voltage, and the gate is Coupled with the control voltage, the drain is biased at the constant voltage, and the variable-channel PMOS transistor system determines its channel width according to a plurality of switching signals.

In one embodiment, the current-to-voltage circuit has a first bias circuit, the first bias circuit has a second PMOS transistor connected in series between a second supply voltage and a reference ground, and A first current source is used to generate the constant voltage at the gate of the second PMOS transistor according to the current of the first current source.

In one embodiment, the current output circuit has a second bias circuit, and the second bias circuit has a third PMOS transistor and a third PMOS transistor connected in series between the second supply voltage and the reference ground. The second current source is used to generate the constant voltage at the gate of the third PMOS transistor according to the current of the second current source, and the channel aspect ratio of the third PMOS transistor is equal to the channel length of the second PMOS transistor. width ratio, and the current of the second current source is equal to the current of the first current source.

In one embodiment, the second supply voltage is higher than the first supply voltage.

In one embodiment, the second supply voltage is equal to the first supply voltage, and both the second PMOS transistor and the third PMOS transistor are native PMOS transistors.

In one embodiment, the second supply voltage is equal to the first supply voltage, and bodies of the second PMOS transistor and the third PMOS transistor are respectively coupled to the reference ground through a second current source.

In one embodiment, the channel variable PMOS transistor has a plurality of fourth PMOS transistors, and the fourth PMOS transistor system determines its parallel configuration according to the switching signals to determine the channel width .

To achieve the aforementioned purpose, the present invention further proposes an LED display driver chip, which has a bias circuit and a plurality of output channels, and the bias circuit is used to bias the output channels, wherein the bias circuit And the output channel is correspondingly implemented by the current-to-voltage circuit and the current output circuit of the aforementioned low-power consumption driver circuit.

To achieve the aforementioned purpose, the present invention further provides an LED display device, which has an LED array and the aforementioned LED driver chip for driving the LED array.

In possible embodiments, the LED array can be a sub-millimeter LED array, a micro LED array or a quantum dot LED array.

In order to enable your review committee members to further understand the structure, features and purpose of the present invention, drawings and detailed descriptions of preferred specific embodiments are hereby attached.

The principle of the present invention is to effectively reduce the area and power consumption of the chip by canceling the amplifier in the current output channel of the LED display driver chip.

Please refer to FIG. 2 , which shows a circuit diagram of an embodiment of a low power consumption driver circuit for LED display driver chips of the present invention. As shown in FIG. 2 , a low power consumption driver circuit 100 has a current-to-voltage circuit 110 and a current output circuit 120 for generating an output current I _O according to a plurality of switching signals SW1˜SWn.

The current-to-voltage circuit 110 has a first PMOS transistor 111 to generate a control voltage V _Y at its gate according to a reference current I _REF generated by a certain current source 114, wherein the source of the first PMOS transistor 111 is coupled to A first supply voltage AVDD, and its drain is biased at a certain voltage V _X .

The current output circuit 120 has a voltage-to-current unit 121, and the voltage-to-current unit 121 has a channel-variable PMOS transistor, wherein the source of the channel-variable PMOS transistor is coupled to the first supply voltage AVDD, and the gate Coupled with the control voltage V _Y , the drain is biased at a constant voltage V _X , and the variable-channel PMOS transistor system determines its channel width according to the switching signals SW1~SWn.

Specifically, the current-to-voltage circuit 110 has a first bias circuit, the first bias circuit has a second PMOS transistor 112 connected in series between a second supply voltage VDD and a reference ground, and A first current source 115 is used to generate a constant voltage V _X at the gate of the second PMOS transistor 112 according to the current of the first current source 115, wherein V _X is approximately equal to VDD-V _TH , and V _TH is the second PMOS transistor The threshold voltage of the crystal 112, that is, the current I1 of the first current source 115 is very small, so that the source-gate voltage difference of the second PMOS transistor 112 is approximately equal to V _TH . In addition, the channel of a PMOS transistor 113 is coupled between the first PMOS transistor 111 and the constant current source 114, and its gate is coupled to the drain of the second PMOS transistor 112 so that the second PMOS transistor 112 A certain voltage V _Z1 is generated at the drain. In this way, the three terminals of the second PMOS transistor 112 will see three constant voltages (VDD, V _X , V _Z1 ) to lock its channel current, and the three terminals of the PMOS transistor 113 will see three constant voltages (V _X , V _Z1 , V _Y ) to lock its channel current.

In addition, the current output circuit 120 has a second bias circuit, the second bias circuit has a third PMOS transistor 122 connected in series between the second supply voltage VDD and the reference ground and a second current The source 124 is used to generate a constant voltage V _X at the gate of the third PMOS transistor 122 according to the current I1 of the second current source 124, wherein the channel aspect ratio of the third PMOS transistor 122 is equal to that of the second PMOS transistor 112 channel aspect ratio, and the current of the second current source 124 is equal to the current of the first current source 115 . In addition, the source of a PMOS transistor 123 is coupled to the voltage-to-current unit 121 and the gate of the third PMOS transistor 122, and the gate of the PMOS transistor 123 is coupled to the drain of the third PMOS transistor 122 for the third PMOS transistor 122. The drain of the PMOS transistor 122 generates a certain voltage V _Z2 . In this way, the three terminals of the third PMOS transistor 122 will see three constant voltages (VDD, V _X , V _Z2 ) to lock its channel current, and the three terminals of the voltage-to-current unit 121 will be connected to the first PMOS The three terminals of the transistor 111 also see three constant voltages (AVDD, V _Y , V _X ) so that the output current I _O is precisely proportional to the reference current I _REF .

In addition, in order to minimize the voltage difference between the constant voltage V _X and the first supply voltage AVDD to reduce the power consumption of the current output circuit 120, in a possible embodiment, the second supply voltage VDD may be higher than the first supply voltage AVDD; or The second supply voltage VDD can be equal to the first supply voltage AVDD, and the second PMOS transistor 112 and the third PMOS transistor 122 are both native PMOS transistors; or, as shown in FIG. 3, the second supply voltage VDD is equal to The first supply voltage AVDD, the second PMOS transistor 112 is coupled to the reference ground through a first current source 112a, and the body of the third PMOS transistor 122 is coupled to the reference ground through another current source 112a, wherein the current Source 112a provides a constant current I2.

In addition, please refer to FIG. 4 , which shows a circuit diagram of an embodiment of the channel-variable PMOS transistor of the voltage-to-current unit 121 in FIG. 2 . As shown in FIG. 4 , the channel-variable PMOS transistor has a plurality of fourth PMOS transistors 121a, and the fourth PMOS transistors 121a control a plurality of switches 121b according to the switching signals SW1˜SWn to determine their Parallel configuration, thus determining the channel width described.

According to the above description, the present invention further provides an LED display driver chip. Please refer to FIG. 5 , which shows a block diagram of an embodiment of the LED display driver chip of the present invention. As shown in FIG. 5 , an LED display driver chip 200 has a bias circuit 210 and a plurality of output channels 220, wherein the bias circuit 210 is used to bias the output channels 220, and the bias circuit 210 And the output channel 220 is correspondingly implemented by the current-to-voltage circuit 110 and the current output circuit 120 of the aforementioned low-power consumption driver circuit 100 .

In addition, according to the above description, the present invention further provides an LED display device. Please refer to FIG. 6 , which shows a block diagram of an embodiment of the LED display device of the present invention. As shown in FIG. 6 , an LED display device 300 has an LED array 310 and an LED display driver chip 320 for driving the LED array 310 , wherein the LED display driver chip 320 is realized by the LED display driver chip 200 . In addition, the LED array 310 can be a common-anode LED array or a common-cathode LED array, and it can be a millimeter LED array, a micro LED array or a quantum dot LED array.

With the design disclosed above, the present invention has the following advantages: 1. The low power consumption driving stage circuit for LED display driving chip of the present invention can effectively reduce the power consumption of the chip by canceling the amplifier in the current output channel. 2. The LED display driver chip of the present invention can effectively reduce the chip area and power consumption of the chip by the above-mentioned low power consumption driver circuit. 3. The display device of the present invention can effectively reduce the chip area of its LED display driver chip and reduce its power consumption by the above-mentioned low power consumption driver circuit.

What is disclosed in this case is a preferred embodiment. For example, any partial changes or modifications derived from the technical ideas of this case and easily deduced by those who are familiar with the technology are within the scope of the patent right of this case.

To sum up, regardless of the purpose, means and efficacy of this case, it shows that it is very different from the conventional technology, and its first invention is practical, and it does meet the patent requirements of the invention. I implore your review committee to understand it clearly and grant a patent as soon as possible. Society is for the Most Prayer.

10: PMOS transistor 20: PMOS transistor 30: Amplifier 31a, 31b: NMOS transistors 32a, 32b: PMOS transistors 33: NMOS transistor 34a: PMOS transistor 34b: NMOS transistor 35a, 35b: NMOS transistors 36: NMOS transistor 37a, 37b, 38a, 38b: PMOS transistors 39a, 39b: NMOS transistor 40: LED components 100: Low power consumption driver stage circuit 110: Current to voltage circuit 111: The first PMOS transistor 112: The second PMOS transistor 112a: current source 113: PMOS transistor 114: constant current source 115: the first current source 120: current output circuit 121: Voltage to current unit 121a: the fourth PMOS transistor 121b: switch 122: The third PMOS transistor 123: PMOS transistor 124: second current source 200: LED display driver chip 210: Bias circuit 220: output channel 300: LED display device 310:LED array 320: LED display driver chip

FIG. 1a shows a circuit diagram of a driver stage circuit of a conventional LED display chip. FIG. 1b shows a circuit diagram of a two-stage structure of an amplifier of the driver stage circuit of FIG. 1a. FIG. 1c is a circuit diagram of a cascaded structure of amplifiers in the driver stage circuit of FIG. 1a. FIG. 2 is a circuit diagram of an embodiment of a low power consumption driver circuit for an LED display driver chip of the present invention. FIG. 3 is a circuit diagram of an embodiment of a first bias circuit and a second bias circuit of the low power consumption driver circuit shown in FIG. 2 . FIG. 4 is a circuit diagram of an embodiment of a channel-variable PMOS transistor of the voltage-to-current unit of the low-power-consumption driving stage circuit shown in FIG. 2 . FIG. 5 shows a block diagram of an embodiment of the LED display driver chip of the present invention. FIG. 6 shows a block diagram of an embodiment of the LED display device of the present invention.

100: Low power consumption driver stage circuit

110: Current to voltage circuit

111: The first PMOS transistor

112: The second PMOS transistor

113: PMOS transistor

114: constant current source

115: the first current source

120: current output circuit

121: Voltage to current unit

122: The third PMOS transistor

123: PMOS transistor

124: second current source

Claims (9)

A low-power drive stage circuit for LED display drive chips, which includes: a current-to-voltage circuit with a first PMOS transistor to generate a control voltage at its gate according to the current of a certain current source, wherein the The source of the first PMOS transistor is coupled to a first supply voltage, and its drain is biased at a certain voltage; and a current output circuit has a voltage-to-current unit, and the voltage-to-current unit has a channel variable A PMOS transistor, wherein the source of the channel variable PMOS transistor is coupled to the first supply voltage, the gate is coupled to the control voltage, the drain is biased at the constant voltage, and the channel variable The PMOS transistor system determines its channel width according to a plurality of switching signals; wherein, the channel-variable PMOS transistor has a plurality of fourth PMOS transistors, and the fourth PMOS transistor system determines its channel width according to the switching signals. Connect to the configuration to determine the channel width described. As the low power consumption driver circuit for LED display driver chip described in item 1 of the patent scope of the application, wherein, the current-to-voltage circuit has a first bias circuit, and the first bias circuit has a serial connection A second PMOS transistor and a first current source between a second supply voltage and a reference ground are used to generate the constant voltage at the gate of the second PMOS transistor according to the current of the first current source. As the low power consumption driving stage circuit for LED display driver chip described in item 2 of the patent scope of the application, wherein, the current output circuit has a second bias circuit, and the second bias circuit has a circuit connected in series A third PMOS transistor and a second current source between the second supply voltage and the reference ground, so as to generate the constant voltage at the gate of the third PMOS transistor according to the current of the second current source voltage, the channel aspect ratio of the third PMOS transistor is equal to the channel aspect ratio of the second PMOS transistor, and the current of the second current source is equal to the current of the first current source. The low power consumption driving stage circuit for LED display driver chip as described in item 3 of the scope of patent application, wherein the second supply voltage is higher than the first supply voltage. The low power consumption driving stage circuit for LED display driver chip as described in item 3 of the scope of patent application, wherein the second supply voltage is equal to the first supply voltage, and the second PMOS transistor and the third PMOS The transistors are all native PMOS transistors. The low power consumption driving stage circuit for LED display driver chip as described in item 3 of the scope of patent application, wherein the second supply voltage is equal to the first supply voltage, and the second PMOS transistor and the third PMOS The bodies of the transistors are each coupled to the reference ground via a second current source. An LED display driver chip, which has a bias circuit and a plurality of output channels, and the bias circuit is used to bias the output channels, wherein, the bias circuit and the output channels are provided by the application The current-to-voltage circuit and the current output circuit of the low-power-consumption driving stage circuit described in any one of items 1 to 6 of the patent scope are implemented correspondingly. An LED display device, which has an LED array and the LED display driving chip as described in item 7 of the scope of the patent application for driving the LED array. The LED display device as described in item 8 of the scope of the patent application, wherein the LED array is selected from the group consisting of a submillimeter light emitting diode array, a micro light emitting diode array and a quantum dot light emitting diode array An array of display elements.

Images