TWI809638B - Double output dc-ac converter - Google Patents

Abstract

A double output DC-AC converter includes a voltage-controlled oscillator, a comparator, a gate drive circuit, a first DC-AC conversion circuit, and a second DC-AC conversion circuit. The voltage-controlled oscillator outputs a sawtooth wave. The comparator receives the sawtooth wave and a reference voltage and outputs a comparison signal. The gate drive circuit receives the comparison signal and outputs a first high-level gate control signal, a first low-level gate Control signal, a second high-level gate control signal, and a second low-level gate control signal to the first DC-AC conversion circuit and the second DC-AC conversion circuit, so that the first DC-AC conversion circuit and the second DC-AC conversion circuit outputs a first AC signal and a second AC signal.

Description

Dual Output DC-AC Converter

The invention relates to a DC-AC converter, in particular to a dual-output DC-AC converter.

A DC-AC converter is a device that converts DC power to AC power. It is often used in solar battery power generation systems, uninterruptible power systems, MRT power systems or air-conditioning systems. Among them, a full-bridge DC-AC converter is based on PWM signal The generating circuit and the gate control circuit control the power switch of the DC-AC converter, and the LC circuit at the back end generates alternating current, but in order to generate two opposite-phase alternating currents, two sets of PWM signal generating circuits and gate control circuits are required , so that the overall layout area of the DC-AC converter increases.

The main purpose of the present invention is to control two sets of DC-AC conversion circuits through a single set of comparators and gate drive circuits by outputting two sets of gate control signals with different levels by the gate drive circuit, so as to reduce the layout of the overall circuit area.

A dual-output DC-AC converter of the present invention includes a voltage-controlled oscillator, a comparator, a gate drive circuit, a first DC-AC conversion circuit and a second DC-AC conversion circuit, the voltage-controlled oscillator is used To output a sawtooth wave, the comparator is electrically connected to the voltage-controlled oscillator, the comparator receives the sawtooth wave and a reference voltage, and the comparator is used to compare the potential of the sawtooth wave and the reference signal to output a comparison signal, the The gate drive circuit is electrically connected to the comparator to receive the comparison signal, the gate drive circuit also receives a high-level power supply voltage and a high-level ground voltage, and the gate drive circuit outputs a first high-level gate control signal, a first low-level quasi-gate control signal, a second high-level quasi-gate control signal, and a second low-level quasi-gate control signal, the first DC-AC conversion circuit is electrically connected to the gate drive circuit to receiving the first high-level quasi-gate control signal and the first low-level quasi-gate control signal, and the first DC-AC conversion circuit outputs a first AC signal, and the second DC-AC conversion circuit is electrically connected to the gate The driving circuit receives the second high-level gate control signal and the second low-level gate control signal, and the second DC-AC conversion circuit outputs a second AC signal.

In the present invention, the gate drive circuit outputs the first high-level quasi-gate control signal, the first low-level quasi-gate control signal, the second high-level quasi-gate control signal and the second low-level quasi-gate control signal to The first AC-DC conversion circuit and the second AC-DC conversion circuit are controlled to provide two AC voltages and prevent the overall circuit layout from being too large.

Please refer to Figure 1, which is an embodiment of the present invention, a circuit diagram of a dual-output DC-AC converter 100, the dual-output DC-AC converter 100 includes a voltage-controlled oscillator 110, a comparator 120, a gate drive The circuit 130 , a first DC-AC conversion circuit 140 and a second DC-AC conversion circuit 150 .

The voltage-controlled oscillator 110 receives a control voltage Vc and outputs a sawtooth wave Vramp. The potential of the control voltage Vc can be used to control the oscillation frequency of the sawtooth wave Vramp. The comparator 120 is electrically connected to the voltage-controlled oscillator 110, a negative input terminal of the comparator 120 receives the sawtooth wave Vramp of the voltage-controlled oscillator 110, and a positive input terminal of the comparator 120 receives a reference signal Vref , the reference signal Vref is a sine wave, and the comparator 120 is used to compare the potentials of the sawtooth wave Vramp and the reference signal Vref to output a comparison signal Vcomp. Preferably, the comparator 120 is a hysteresis comparator, which has a better effect of suppressing noise, so as to prevent erroneous operation of the circuit.

The gate drive circuit 130 is electrically connected to the comparator 120 to receive the comparison signal Vcomp, the gate drive circuit 130 also receives a high-level power supply voltage Vhdd and a high-level ground voltage Vhgnd, and the gate drive circuit 130 outputs A first high-level quasi-gate control signal Vgh1, a first low-level quasi-gate control signal Vgl1, a second high-level quasi-gate control signal Vgh2, and a second low-level quasi-gate control signal Vgl2.

Please refer to FIG. 2, in this embodiment, the gate drive circuit 130 has a non-overlapping circuit 131, a first voltage level converter 132, a second voltage level converter 133, a first high voltage The buffer 134 , a first low voltage buffer 135 , a second high voltage buffer 136 and a second low voltage buffer 137 . The non-overlapping circuit 131 is electrically connected to the comparator 120 to receive the comparison signal Vcomp, and the non-overlapping circuit 131 outputs a first non-overlapping signal NO1 and a second non-overlapping signal NO2, the first voltage The level converter 132 is electrically connected to the non-overlapping circuit 131 to receive the first non-overlapping signal NO1, and the first voltage level converter 132 outputs a first high level non-overlapping signal H1, the first high level The quasi-non-overlapping signal H1 is output as the first high level gate control signal Vgh1 through the first high voltage buffer 134 . The first low-voltage buffer 135 is electrically connected to the non-overlapping circuit 131 to receive the first non-overlapping signal NO1, and the first low-voltage buffer 135 outputs the first low-level gate control signal Vgl1. The second voltage level converter 133 is electrically connected to the non-overlapping circuit 131 to receive the second non-overlapping signal NO2, and the second voltage level converter 133 outputs a second high-level non-overlapping signal H2, The second high-level non-overlapping signal H2 outputs the second high-level gate control signal Vgh2 through the second high-voltage buffer 136, and the second low-voltage buffer 137 is electrically connected to the non-overlapping circuit 131 to receive the second high-level non-overlapping signal H2. The non-overlapping signal NO2, and the second low voltage buffer 137 outputs the second low level gate control signal Vgl2.

Please refer to Figures 2 and 3, the non-overlapping circuit 131 has a first inverter 131a, a first inverter 131b, a second inverter 131c, a first delay unit 131d, a second inverter device 131e, a second delay unit 131f and a third inverter 131g. The first inverter 131a receives the comparison signal Vcomp, the second inverter 131c receives the inverted comparison signal Vcomp through the first inverter 131b, and an input end of the first delay unit 131d is electrically connected The first NAND gate 131a, an output terminal of the first delay unit 131d is electrically connected to the second NAND gate 131c, wherein the first delay unit 131d is composed of two inverters connected in series, and the first delay unit 131d is connected in series. The two inverters 131e are electrically connected to the output end of the first delay unit 131d, and the second inverter 131e outputs the first non-overlapping signal NO1. An input terminal of the second delay unit 131f is electrically connected to the second NAND gate 131c, an output terminal of the second delay unit 131f is electrically connected to the first NAND gate 131a, wherein the second delay unit 131f is Two inverters are connected in series, the third inverter 131g is electrically connected to the output terminal of the second delay unit 131f, and the third inverter 131g outputs the second non-overlapping signal NO2. Under this structure, the phase of the first non-overlapping signal NO1 and The first comparison signal Vcomp is the same, and the phase of the second non-overlapping signal NO2 is opposite to that of the first comparison signal Vcomp and the first non-overlapping signal NO1.

Please refer to Figures 2 and 4. In this embodiment, the first voltage level converter 132 has a transistor pair 132a, a high-level grounded transistor pair 132b, a low-level grounded transistor pair 132c and an inverse Phaser 132d. The inverter 132d receives the first non-overlapping signal NO1, and the inverter 132d outputs the inverted first non-overlapping signal, and the low-level grounded transistor pair 132c receives the first non-overlapping signal NO1 and the first non-overlapping signal of antiphase, the high-level ground transistor pair 132b is electrically connected to the low-level ground transistor pair 132c, and the high-level ground transistor pair 132b receives the high-level ground voltage Vhgnd, The transistor pair 132a is electrically connected to the high-level grounded transistor pair 132b, the transistor pair 132a receives the high-level power supply voltage Vhdd, and the transistor pair 132a outputs the first high-level non-overlapping signal H1.

Wherein, the transistor pair 132a has a first P-type power transistor M _P11 and a second P-type power transistor M _P12 , and the high-level grounded transistor pair 132b has a third P-type power transistor M _P13 and A fourth P-type power transistor M _P14 , the low-level grounded transistor pair 132c has a first N-type power transistor M _N11 and a second N-type power transistor M _N12 . The gate of the first N-type power transistor _MN11 receives the first non-overlapping signal NO1, and the gate of the second N-type power transistor _MN12 is electrically connected to the inverter 132d to receive the inverted signal. The first non-overlapping signal NO1, the sources of the first and second N-type power transistors _MN11 and _MN12 are grounded. The drain of the third P-type power transistor _MP13 is electrically connected to the drain of the first N-type power transistor _MN11 , and the drain of the fourth P-type power transistor _MP14 is electrically connected to the second N The drain of the P-type power transistor M _N12 and the gates of the third and fourth P-type power transistors _MP13 and _MP14 receive the high-level ground voltage Vhgnd. The drain of the first P-type power transistor M _P11 and the gate of the second P-type power transistor M _P12 are electrically connected to the source of the third P-type power transistor M _P13 . The gate of the transistor M _P11 and the drain of the second P-type power transistor M _P12 are electrically connected to the source of the fourth P-type power transistor M _P14 , and the first and second P-type power transistors M _P11 , The source of _MP12 receives the high-level quasi-power supply voltage Vhdd.

The circuit action of the first voltage level converter 132 is: when the first non-overlapping signal NO1 is at a high potential, the first N-type power transistor _MN11 is turned on, and the second N-type power transistor _{MN12 is} turned on. At the end, the drain of the three P-type power transistor M _P13 will be discharged to a low potential, and the potential of the source of the three P-type power transistor M _P13 is Vhgnd+Vthp, that is, the high level ground voltage Vhgnd plus P At this time, the second P-type power transistor _MP12 is turned on, so that the drain of the second P-type power transistor _MP12 is charged to the high-level power supply voltage Vhdd and output as the first A high-level non-overlapping signal H1. Conversely, when the first non-overlapping signal NO1 is at a low potential, the second N-type power transistor M _N12 is turned on, the first N-type power transistor M _N11 is turned off, and the four P-type power transistors M _P14 The drain will be discharged to a low potential, the potential of the source of the four P-type power transistors M _P14 is Vhgnd+Vthp and output as the first high-level non-overlapping signal H1, at this time, the first P-type power transistor The transistor _MP11 is turned on, so that the drain of the first P-type power transistor _MP11 is charged to the high level power supply voltage Vhdd. Thereby, the voltage level of the first non-overlapping signal NO1 can be increased from 0 and VDD to Vhgnd+Vthp and Vhdd.

Please refer to FIG. 2, the circuit structure and circuit action of the second voltage level converter 133 are the same as that of the first voltage level converter 132, the only difference is that the input signal is changed from the first non-overlapping signal to NO1 becomes the second non-overlapping signal NO2, so it will not be described again.

Please refer to FIG. 1, the first DC-AC conversion circuit 140 is electrically connected to the gate driving circuit 130 to receive the first high level gate control signal Vgh1 and the first low level gate control signal Vgl1, and the The first DC-AC conversion circuit 140 outputs a first AC signal Vop.

In this embodiment, the first DC-AC conversion circuit 140 has a first P-type power transistor M _P1 , a first N-type power transistor M _N1 , a first output inductor 141 and a first output capacitor 142. The first P-type power transistor _MP1 receives the first high-level gate control signal Vgh1, the first N-type power transistor _MN1 receives the first low-level gate control signal Vgl1, and the first output inductor 141 The first P-type power transistor M _P1 and the first N-type power transistor M _N1 are electrically connected, and the first output capacitor 142 is electrically connected to the first output inductor 141 .

Wherein, the gate of the first P-type power transistor _MP1 receives the first high-level gate control signal Vgh1, the source of the first P-type power transistor _MP1 receives the high-level power supply voltage Vhdd, and the first The drain of the P-type power transistor M _P1 is electrically connected to the drain of the first N-type power transistor _MN1 , and the gate of the first N-type power transistor _MN1 receives the first low-level quasi-gate control signal Vgl1, the source of the first N-type power transistor _MN1 is grounded, and one end of the first output inductor 141 is electrically connected to the first P-type power transistor M _P1 and the first N-type power transistor _MN1 . Drain, the other end of the first output inductor 141 is electrically connected to one end of the first output capacitor 142 to output the first AC signal Vop, and the other end of the first output capacitor 142 is grounded.

The second DC-AC conversion circuit 150 is electrically connected to the gate driving circuit 130 to receive the second high-level gate control signal Vgh2 and the second low-level gate control signal Vgl2, and the second DC-AC conversion circuit 150 Outputting a second AC signal Von.

In this embodiment, the second DC-AC conversion circuit 150 has a second P-type power transistor M _P2 , a second N-type power transistor M _N2 , a second output inductor 151 and a second output capacitor 152 , the second P-type power transistor M _P2 receives the second high-level gate control signal Vgh2, the second N-type power transistor M _N2 receives the second low-level gate control signal Vgl2, and the second output inductor 151 is electrically connected to the second P-type power transistor M _P2 and the second N-type power transistor M _N2 , and the second output capacitor 152 is electrically connected to the second output inductor 151 .

Wherein, the gate of the second P-type power transistor _MP2 receives the second high-level gate control signal Vgh2, the source of the second P-type power transistor _MP2 receives the high-level power supply voltage Vhdd, and the second The drain of the P-type power transistor M _P2 is electrically connected to the drain of the second N-type power transistor _MN2 , and the gate of the second N-type power transistor _MN2 receives the second low level gate control signal Vgl2, the source of the second N-type power transistor M _N2 is grounded, and one end of the second output inductor 151 is electrically connected to the second P-type power transistor M _P2 and the second N-type power transistor M _N2 Drain, the other end of the second output inductor 151 is electrically connected to one end of the second output capacitor 152 to output the second AC signal Von, and the other end of the second output capacitor 152 is grounded.

Through the first high-level quasi-gate control signal Vgh1, the first low-level quasi-gate control signal Vgl1, the second high-level quasi-gate control signal Vgh2, and the second low-level quasi-gate control signal Vgl2, the first DC The control of the AC conversion circuit 140 and the second DC-AC conversion circuit 150 can obtain the first AC signal Vop and the second AC signal Von which are opposite to each other, so as to achieve a single comparator 120 and the gate drive Circuit 130 outputs the effect of two alternating currents.

In the present invention, the gate driving circuit 130 outputs the first high level gate control signal Vgh1, the first low level gate control signal Vgl1, the second high level gate control signal Vgh2 and the second low level The gate control signal Vgl2 is controlled by the first AC-DC conversion circuit 140 and the second AC-DC conversion circuit 150 to provide two AC voltages and avoid the overall circuit layout from being too large.

The scope of protection of the present invention should be defined by the scope of the appended patent application. Any changes and modifications made by anyone who is familiar with this technology without departing from the spirit and scope of the present invention belong to the scope of protection of the present invention. .

100: Dual output DC-AC converter

110:Voltage Controlled Oscillator

120: Comparator

130: Gate drive circuit

131: Non-overlapping circuits

131a: The first reverse and gate

131b: the first inverter

131c: The second reverse and gate

131d: the first delay unit

131e: second inverter

131f: the second delay unit

131g: the third inverter

132: first voltage level converter

132a: Transistor pair

M _P11 : The first P-type power transistor

M _P12 : The second P-type power transistor

132b: high-level grounding transistor pair

M _P13 : the third P-type power transistor

M _P14 : The fourth P-type power transistor

132c: Low level ground transistor pair

M _N11 : the first N-type power transistor

M _N12 : the second N-type power transistor

132d: Inverter

133: second voltage level converter

134: The first high-voltage buffer

135: The first low voltage buffer

136: Second high voltage buffer

137: Second low voltage buffer

140: The first DC-AC conversion circuit

M _P1 : the first P-type power transistor

M _N1 : the first N-type power transistor

141: The first output inductance

142: The first output capacitor

150: the second DC-AC conversion circuit

M _P2 : The second P-type power transistor

M _N2 : the second N-type power transistor

151: Second output inductance

152: second output capacitor

Vramp: sawtooth wave

Vcomp: compare signal

Vhdd: High quasi-power supply voltage

Vhgnd: high level ground voltage

Vgh1: the first high-level quasi-gate control signal

Vgl1: the first low quasi-gate control signal

Vgh2: The second high quasi-gate control signal

Vgl2: second low quasi-gate control signal

Vop: first communication signal

Von: second AC signal

ON1: The first non-overlapping signal

ON2: The second non-overlapping signal

Vref: reference signal

H1: The first high-level quasi-non-overlapping signal

H2: The second highest quasi-non-overlapping signal

H1: Inverted first high-level non-overlapping signal

Figure 1: A circuit diagram of a dual-output DC-AC converter according to an embodiment of the present invention. Figure 2: A circuit diagram of a gate drive circuit according to an embodiment of the present invention. Figure 3: A circuit diagram of a non-overlapping circuit according to an embodiment of the present invention. Fig. 4: According to an embodiment of the present invention, a circuit diagram of a first voltage level converter.

100: Dual-output DC-AC converter 110: Voltage-controlled oscillator 120: Comparator 130: Gate drive circuit 140: The first DC-AC conversion circuit M _P1 : The first P-type power transistor M _N1 : The first N-type Power transistor 141: first output inductor 142: first output capacitor 150: second DC-AC conversion circuit M _P2 : second P-type power transistor M _N2 : second N-type power transistor 151: second output inductor 152 : second output capacitor Vramp: sawtooth wave Vcomp: comparison signal Vhdd: high level quasi-supply voltage Vhgnd: high level quasi-ground voltage Vgh1: first high level quasi-gate control signal Vgl1: first low level quasi-gate control signal Vgh2: second high level Quasi-gate control signal Vgl2: second low level quasi-gate control signal Vop: first AC signal Von: second AC signal Vref: reference signal

Claims (10)

A dual-output DC-AC converter, which includes: a voltage-controlled oscillator, used to output a sawtooth wave; a comparator, electrically connected to the voltage-controlled oscillator, the comparator receives the sawtooth wave and a reference voltage, and the The comparator is used to compare the potential of the sawtooth wave and the reference signal to output a comparison signal; a gate drive circuit is electrically connected to the comparator to receive the comparison signal, and the gate drive circuit receives a high-level power supply voltage and a High-level quasi-ground voltage, and the gate drive circuit outputs a first high-level quasi-gate control signal, a first low-level quasi-gate control signal, a second high-level quasi-gate control signal and a second low-level quasi-gate control signal Signal; a first DC-AC conversion circuit electrically connected to the gate drive circuit to receive the first high-level quasi-gate control signal and the first low-level quasi-gate control signal, and the first DC-AC conversion circuit Outputting a first AC signal; and a second DC-AC conversion circuit electrically connected to the gate drive circuit to receive the second high-level gate control signal and the second low-level gate control signal, and the second The DC-AC conversion circuit outputs a second AC signal, wherein the first DC-AC conversion circuit has a first P-type power transistor, a first N-type power transistor, a first output inductor and a first output capacitor , the first P-type power transistor receives the first high-level quasi-gate control signal, the first N-type power transistor receives the first low-level quasi-gate control signal, and the first output inductor is electrically connected to the first The P-type power transistor, the first N-type power transistor, and the first output capacitor are electrically connected to the first output inductor. As claimed in item 1, the dual-output DC-AC converter, wherein the comparator is a hysteresis comparator. The dual-output DC-AC converter of claim 1, wherein the first P-type power transistor The gate of the body receives the first high-level gate control signal, the source of the first P-type power transistor receives a high-level power supply voltage, and the drain of the first P-type power transistor is electrically connected to the first N The drain of the first N-type power transistor, the gate of the first N-type power transistor receives the first low-level quasi-gate control signal, the source of the first N-type power transistor is grounded, and one end of the first output inductor electrically connected to the drain of the first P-type power transistor and the first N-type power transistor, the other end of the first output inductor is electrically connected to one end of the first output capacitor, and the other end of the first output capacitor One end is grounded. The dual-output DC-AC converter as claimed in item 1, wherein the second DC-AC conversion circuit has a second P-type power transistor, a second N-type power transistor, a second output inductor and a second output capacitor , the second P-type power transistor receives the second high-level quasi-gate control signal, the second N-type power transistor receives the second low-level quasi-gate control signal, and the second output inductor is electrically connected to the second The P-type power transistor, the second N-type power transistor, and the second output capacitor are electrically connected to the second output inductor. The dual-output DC-AC converter of claim 4, wherein the gate of the second P-type power transistor receives the second high-level gate control signal, and the source of the second P-type power transistor receives a high-level power supply voltage, the drain of the second P-type power transistor is electrically connected to the drain of the second N-type power transistor, and the gate of the second N-type power transistor receives the second low level gate control signal, The source of the second N-type power transistor is grounded, one end of the second output inductor is electrically connected to the drain of the second P-type power transistor and the second N-type power transistor, and the second output inductor The other end is electrically connected to one end of the second output capacitor, and the other end of the second output capacitor is grounded. The dual-output DC-AC converter of claim 1, wherein the gate drive circuit has a non-overlapping circuit, a first voltage level converter, a second voltage level converter, a first high voltage buffer, A first low-voltage buffer, a second high-voltage buffer, and a second low-voltage buffer, the non-overlapping circuit The circuit is electrically connected to the comparator to receive the comparison signal, and the non-overlapping circuit outputs a first non-overlapping signal and a second non-overlapping signal, and the first voltage level converter is electrically connected to the non-overlapping circuit to receive the first non-overlapping signal, and the first voltage level converter outputs the first high-level gate control signal through the first high-voltage buffer, and the first low-voltage buffer is electrically connected to the non-overlapping circuit to receive the first non-overlapping signal, and the first low-voltage buffer outputs the first low-level gate control signal, and the second voltage level converter is electrically connected to the non-overlapping circuit to receive the second non-overlapping circuit overlapping signal, and the second voltage level converter outputs the second high-level gate control signal through the second high-voltage buffer, and the second low-voltage buffer is electrically connected to the non-overlapping circuit to receive the second non-overlapping circuit overlap signal, and the second low-voltage buffer outputs the second low level gate control signal. Such as the dual-output DC-AC converter of claim 6, wherein the non-overlapping circuit has a first inverter, a first inverter, a second inverter, a first delay unit, and a second inverter device, a second delay unit and a third inverter, the first inverter gate receives the comparison signal, the second inverter gate receives the comparison signal through the first inverter, and the first delay unit An input end is electrically connected to the first inverter, an output end of the first delay unit is electrically connected to the second inverter, and the second inverter is electrically connected to the output end of the first delay unit , and the second inverter outputs the first non-overlapping signal, an input end of the second delay unit is electrically connected to the second NAND gate, and an output end of the second delay unit is electrically connected to the first An NAND gate, the third inverter is electrically connected to the output end of the second delay unit, and the third inverter outputs the second non-overlapping signal. Such as the dual-output DC-AC converter of claim 6, wherein the first voltage level converter has a transistor pair, a high-level grounded transistor pair, a low-level grounded transistor pair, and an inverter, the inverter The device receives the first non-overlapping signal, and the inverter outputs the inverted first non-overlapping signal, and the low-level grounded transistor pair receives the first non-overlapping signal and the inverted first non-overlapping signal. overlapping signals, The high-level ground transistor pair is electrically connected to the low-level ground transistor pair, and the high-level ground transistor pair receives the high-level ground voltage, and the transistor pair is electrically connected to the high-level ground transistor pair, The transistor pair receives the high-level power supply voltage, and the transistor pair outputs a first high-level non-overlapping signal. Such as the dual-output DC-AC converter of claim 8, wherein the transistor pair has a first P-type power transistor and a second P-type power transistor, and the high-level grounded transistor pair has a third P-type power transistor Transistor and a fourth P-type power transistor, the low-level quasi-grounded transistor pair has a first N-type power transistor and a second N-type power transistor, and the gate of the first N-type power transistor receives The first non-overlapping signal, the gate of the second N-type power transistor is electrically connected to the inverter, the source of the first and second N-type power transistors is grounded, and the third P-type power transistor The drain of the first N-type power transistor is electrically connected to the drain of the fourth P-type power transistor, and the drain of the fourth P-type power transistor is electrically connected to the drain of the second N-type power transistor. The gate of the P-type power transistor receives the high level ground voltage, the drain of the first P-type power transistor and the gate of the second P-type power transistor are electrically connected to the source of the third P-type power transistor The gate of the first P-type power transistor and the drain of the second P-type power transistor are electrically connected to the source of the fourth P-type power transistor. The first and second P-type power transistors The source receives the high-level power supply voltage. A dual-output DC-AC converter, which includes: a voltage-controlled oscillator, used to output a sawtooth wave; a comparator, electrically connected to the voltage-controlled oscillator, the comparator receives the sawtooth wave and a reference voltage, and the The comparator is used to compare the potential of the sawtooth wave and the reference signal to output a comparison signal; a gate drive circuit is electrically connected to the comparator to receive the comparison signal, and the gate drive circuit receives a high-level power supply voltage and a High-level ground voltage, and the gate drive circuit outputs a first high Level gate control signal, a first low level gate control signal, a second high level gate control signal and a second low level gate control signal; a first DC to AC conversion circuit electrically connected to the a gate driving circuit to receive the first high-level gate control signal and the first low-level gate control signal, and the first DC-AC conversion circuit outputs a first AC signal; and a second DC-AC conversion circuit , electrically connected to the gate drive circuit to receive the second high-level gate control signal and the second low-level gate control signal, and the second DC-AC conversion circuit outputs a second AC signal, wherein the gate The drive circuit has a non-overlapping circuit, a first voltage level converter, a second voltage level converter, a first high voltage buffer, a first low voltage buffer, a second high voltage buffer and a first Two low-voltage buffers, the non-overlapping circuit is electrically connected to the comparator to receive the comparison signal, and the non-overlapping circuit outputs a first non-overlapping signal and a second non-overlapping signal, and the first voltage level is converted The device is electrically connected to the non-overlapping circuit to receive the first non-overlapping signal, and the first voltage level converter outputs the first high-level gate control signal through the first high-voltage buffer, and the first low-voltage buffer The device is electrically connected to the non-overlapping circuit to receive the first non-overlapping signal, and the first low-voltage buffer outputs the first low-level gate control signal, and the second voltage level converter is electrically connected to the non-overlapping a circuit for receiving the second non-overlapping signal, and the second voltage level converter outputs the second high-level gate control signal through the second high-voltage buffer, and the second low-voltage buffer is electrically connected to the non-overlapping The circuit receives the second non-overlapping signal, and the second low voltage buffer outputs the second low level gate control signal.

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