TWI809638B - Double output dc-ac converter - Google Patents
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本發明是關於一種直流交流轉換器,特別是關於一種雙輸出直流交流轉換器。The invention relates to a DC-AC converter, in particular to a dual-output DC-AC converter.
直流交流轉換器是一種將直流電轉換至交流電之裝置,常應用於太陽能電池發電系統、不斷電系統、捷運電力系統或空調系統中,其中,一種全橋式直流交流轉換器是以PWM訊號產生電路及閘極控制電路控制直流交流轉換器功率開關,而在後端之LC電路產生交流電,但為了產生兩個相位相反之交流電時,則需設置兩組PWM訊號產生電路及閘極控制電路,使得直流交流轉換器的整體佈局面積增加。A DC-AC converter is a device that converts DC power to AC power. It is often used in solar battery power generation systems, uninterruptible power systems, MRT power systems or air-conditioning systems. Among them, a full-bridge DC-AC converter is based on PWM signal The generating circuit and the gate control circuit control the power switch of the DC-AC converter, and the LC circuit at the back end generates alternating current, but in order to generate two opposite-phase alternating currents, two sets of PWM signal generating circuits and gate control circuits are required , so that the overall layout area of the DC-AC converter increases.
本發明的主要目的在於藉由閘極驅動電路輸出兩組位準不同之閘極控制訊號而可僅透過單一組比較器及閘極驅動電路控制兩組直流交流轉換電路,以減少整體電路的佈局面積。The main purpose of the present invention is to control two sets of DC-AC conversion circuits through a single set of comparators and gate drive circuits by outputting two sets of gate control signals with different levels by the gate drive circuit, so as to reduce the layout of the overall circuit area.
本發明的一種雙輸出直流交流轉換器包含一壓控振盪器、一比較器、一閘極驅動電路、一第一直流交流轉換電路及一第二直流交流轉換電路,該壓控振盪器用以輸出一鋸齒波,該比較器電性連接該壓控振盪器,該比較器接收該鋸齒波及一參考電壓,且該比較器用以比較該鋸齒波及該參考訊號之電位而輸出一比較訊號,該閘極驅動電路電性連接該比較器以接收該比較訊號,該閘極驅動電路並接收一高位準電源電壓及一高位準接地電壓,且該閘極驅動電路輸出一第一高位準閘極控制訊號、一第一低位準閘極控制訊號、一第二高位準閘極控制訊號及一第二低位準閘極控制訊號,該第一直流交流轉換電路,電性連接該閘極驅動電路以接收該第一高位準閘極控制訊號及該第一低位準閘極控制訊號,且該第一直流交流轉換電路輸出一第一交流訊號,該第二直流交流轉換電路電性連接該閘極驅動電路以接收該第二高位準閘極控制訊號及該第二低位準閘極控制訊號,且該第二直流交流轉換電路輸出一第二交流訊號。A dual-output DC-AC converter of the present invention includes a voltage-controlled oscillator, a comparator, a gate drive circuit, a first DC-AC conversion circuit and a second DC-AC conversion circuit, the voltage-controlled oscillator is used To output a sawtooth wave, the comparator is electrically connected to the voltage-controlled oscillator, the comparator receives the sawtooth wave and a reference voltage, and the comparator is used to compare the potential of the sawtooth wave and the reference signal to output a comparison signal, the The gate drive circuit is electrically connected to the comparator to receive the comparison signal, the gate drive circuit also receives a high-level power supply voltage and a high-level ground voltage, and the gate drive circuit outputs a first high-level gate control signal, a first low-level quasi-gate control signal, a second high-level quasi-gate control signal, and a second low-level quasi-gate control signal, the first DC-AC conversion circuit is electrically connected to the gate drive circuit to receiving the first high-level quasi-gate control signal and the first low-level quasi-gate control signal, and the first DC-AC conversion circuit outputs a first AC signal, and the second DC-AC conversion circuit is electrically connected to the gate The driving circuit receives the second high-level gate control signal and the second low-level gate control signal, and the second DC-AC conversion circuit outputs a second AC signal.
本發明藉由該閘極驅動電路輸出該第一高位準閘極控制訊號、該第一低位準閘極控制訊號、該第二高位準閘極控制訊號及該第二低位準閘極控制訊號至該第一交流直流轉換電路及該第二交流直流轉換電路進行控制,可提供兩路之交流電壓並避免整體之電路佈局的面積過大。In the present invention, the gate drive circuit outputs the first high-level quasi-gate control signal, the first low-level quasi-gate control signal, the second high-level quasi-gate control signal and the second low-level quasi-gate control signal to The first AC-DC conversion circuit and the second AC-DC conversion circuit are controlled to provide two AC voltages and prevent the overall circuit layout from being too large.
請參閱第1圖,為本發明之一實施例,一種雙輸出直流交流轉換器100的電路圖,該雙輸出直流交流轉換器100包含一壓控振盪器110、一比較器120、一閘極驅動電路130、一第一直流交流轉換電路140及一第二直流交流轉換電路150。
Please refer to Figure 1, which is an embodiment of the present invention, a circuit diagram of a dual-output DC-
該壓控振盪器110接收一控制電壓Vc並輸出一鋸齒波Vramp,該控制電壓Vc的電位大小可用以控制該鋸齒波Vramp的振盪頻率。該比較器120電性連接該壓控振盪器110,該比較器120的一負極輸入端接收該壓控振盪器110之該鋸齒波Vramp,該比較器120的一正極輸入端接收一參考訊號Vref,該參考訊號Vref為一弦波,該比較器120用以比較該鋸齒波Vramp及該參考訊號Vref的電位大小而輸出一比較訊號Vcomp。較佳的,該比較器120為一遲滯比較器,可具有較佳之抑制雜訊的功效,以防止電路的錯誤作動。
The voltage-controlled
該閘極驅動電路130電性連接該比較器120以接收該比較訊號Vcomp,該閘極驅動電路130並接收一高位準電源電壓Vhdd及一高位準接地電壓Vhgnd,且該閘極驅動電路130輸出一第一高位準閘極控制訊號Vgh1、一第一低位準閘極控制訊號Vgl1、一第二高位準閘極控制訊號Vgh2及一第二低位準閘極控制訊號Vgl2。
The
請參閱第2圖,在本實施例中,該閘極驅動電路130具有一非交疊電路131、一第一電壓位準轉換器132、一第二電壓位準轉換器133、一第一高壓緩衝器134、一第一低壓緩衝器135、一第二高壓緩衝器136及一第二低壓緩衝器137。該非交疊電路131電性連接該比較器120以接收該比較訊號Vcomp,且該非交疊電路131輸出一第一非交疊訊號NO1及一第二非交疊訊號NO2,該第一電壓
位準轉換器132電性連接該非交疊電路131以接收該第一非交疊訊號NO1,且該第一電壓位準轉換器132輸出一第一高位準非交疊訊號H1,該第一高位準非交疊訊號H1經由該第一高壓緩衝器134輸出為該第一高位準閘極控制訊號Vgh1。該第一低壓緩衝器135電性連接該非交疊電路131以接收該第一非交疊訊號NO1,且該第一低壓緩衝器135輸出該第一低位準閘極控制訊號Vgl1。該第二電壓位準轉換器133電性連接該非交疊電路131以接收該第二非交疊訊號NO2,且該第二電壓位準轉換器133輸出一第二高位準非交疊訊號H2,該第二高位準非交疊訊號H2經由該第二高壓緩衝器136輸出該第二高位準閘極控制訊號Vgh2,該第二低壓緩衝器137電性連接該非交疊電路131以接收該第二非交疊訊號NO2,且該第二低壓緩衝器137輸出該第二低位準閘極控制訊號Vgl2。
Please refer to FIG. 2, in this embodiment, the
請參閱第2及3圖,該非交疊電路131具有一第一反及閘131a、一第一反相器131b、一第二反及閘131c、一第一延遲單元131d、一第二反相器131e、一第二延遲單元131f及一第三反相器131g。該第一反及閘131a接收該比較訊號Vcomp,該第二反及閘131c經由該第一反相器131b接收反相之該比較訊號Vcomp,該第一延遲單元131d的一輸入端電性連接該第一反及閘131a,該第一延遲單元131d的一輸出端電性連接該第二反及閘131c,其中該第一延遲單元131d是由兩個反相器串接而成,該第二反相器131e電性連接該第一延遲單元131d的該輸出端,且該第二反相器131e輸出該第一非交疊訊號NO1。該第二延遲單元131f的一輸入端電性連接該第二反及閘131c,該第二延遲單元131f的一輸出端電性連接該第一反及閘131a,其中該第二延遲單元131f是由兩個反相器串接而成,該第三反相器131g電性連接該第二延遲單元131f的該輸出端,且該第三反相器131g輸出該第二非交疊訊號NO2。於此結構下,該第一非交疊訊號NO1的相位與
該第一比較訊號Vcomp相同,該第二非交疊訊號NO2的相位則與該第一比較訊號Vcomp及該第一非交疊訊號NO1相反。
Please refer to Figures 2 and 3, the
請參閱第2及4圖,在本實施例中,該第一電壓位準轉換器132具有一電晶體對132a、一高位準接地電晶體對132b、一低位準接地電晶體132c對及一反相器132d。該反相器132d接收該第一非交疊訊號NO1,且該反相器132d輸出反相之該第一非交疊訊號,該低位準接地電晶體對132c接收該第一非交疊訊號NO1及反相之該第一非交疊訊號,該高位準接地電晶體對132b電性連接該低準位接地電晶體對132c,該高位準接地電晶體對132b並接收該高位準接地電壓Vhgnd,該電晶體對132a電性連接該高位準接地電晶體對132b,該電晶體對132a接收該高位準電源電壓Vhdd,且該電晶體對132a輸出該第一高位準非交疊訊號H1。
Please refer to Figures 2 and 4. In this embodiment, the first
其中,該電晶體對132a具有一第一P型功率電晶體MP11及一第二P型功率電晶體MP12,該高位準接地電晶體對132b具有一第三P型功率電晶體MP13及一第四P型功率電晶體MP14,該低位準接地電晶體對132c具有一第一N型功率電晶體MN11及一第二N型功率電晶體MN12。該第一N型功率電晶體MN11之閘極接收該第一非交疊訊號NO1,該第二N型功率電晶體MN12之閘極電性連接該反相器132d,以接收反相之該第一非交疊訊號NO1,該第一、二N型功率電晶體MN11、MN12之源極接地。該第三P型功率電晶體MP13之汲極電性連接該第一N型功率電晶體MN11之汲極,該第四P型功率電晶體MP14之汲極電性連接該第二N型功率電晶體MN12之汲極,該第三、四P型功率電晶體MP13、MP14之閘極接收該高位準接地電壓Vhgnd。該第一P型功率電晶體MP11之汲極及該第二P型功率電晶體MP12之閘極電性連接該第三P型功率電晶體MP13之源極,該第一P型功率電晶體MP11之閘極及該第二P型功率電晶體MP12之汲極電性連接該第四P型功率電晶體MP14之源
極,該第一、二P型功率電晶體MP11、MP12之源極接收該高位準電源電壓Vhdd。
Wherein, the
該第一電壓位準轉換器132的電路作動為:當該第一非交疊訊號NO1為高電位時,該第一N型功率電晶體MN11導通,該第二N型功率電晶體MN12截止,該三P型功率電晶體MP13之汲極會放電至低電位,該三P型功率電晶體MP13之源極的電位為Vhgnd+Vthp,也就是該高位準接地電壓Vhgnd加上P型功率電晶體的門檻電壓,此時,該第二P型功率電晶體MP12導通,使得該第二P型功率電晶體MP12之汲極充電至該高位準電源電壓Vhdd並輸出為該第一高位準非交疊訊號H1。反之,當該第一非交疊訊號NO1為低電位時,該第二N型功率電晶體MN12導通,該第一N型功率電晶體MN11截止,該四P型功率電晶體MP14之汲極會放電至低電位,該四P型功率電晶體MP14之源極的電位為Vhgnd+Vthp並輸出為該第一高位準非交疊訊號H1,此時,該第一P型功率電晶體MP11導通,使得該第一P型功率電晶體MP11之汲極充電至該高位準電源電壓Vhdd。藉此,可將該第一非交疊訊號NO1的電壓位準由0及VDD提高至Vhgnd+Vthp及Vhdd。
The circuit action of the first
請參閱第2圖,該第二電壓位準轉換器133的電路結構及電路做動與該第一電壓位準轉換器132相同,差異僅在將輸入訊號由該第一非交疊訊號改NO1變為該第二非交疊訊號NO2,因此不再贅述。
Please refer to FIG. 2, the circuit structure and circuit action of the second
請參閱第1圖,該第一直流交流轉換電路140電性連接該閘極驅動電路130以接收該第一高位準閘極控制訊號Vgh1及該第一低位準閘極控制訊號Vgl1,且該第一直流交流轉換電路140輸出一第一交流訊號Vop。
Please refer to FIG. 1, the first DC-
在本實施例中,該第一直流交流轉換電路140具有一第一P型功率電晶體MP1、一第一N型功率電晶體MN1、一第一輸出電感141及一第一輸出電容142。該第一P型功率電晶體MP1接收該第一高位準閘極控制訊號Vgh1,該第一N
型功率電晶體MN1接收該第一低位準閘極控制訊號Vgl1,該第一輸出電感141電性連接該第一P型功率電晶體MP1及該第一N型功率電晶體MN1,該第一輸出電容142電性連接該第一輸出電感141。
In this embodiment, the first DC-
其中,該第一P型功率電晶體MP1之閘極接收該第一高位準閘極控制訊號Vgh1,該第一P型功率電晶體MP1之源極接收高位準電源電壓Vhdd,該第一P型功率電晶體MP1之汲極電性連接該第一N型功率電晶體MN1之汲極,該第一N型功率電晶體MN1之閘極接收該第一低位準閘極控制訊號Vgl1,該第一N型功率電晶體MN1之源極接地,該第一輸出電感141之一端電性連接該第一P型功率電晶體MP1及該第一N型功率電晶體MN1之汲極,該第一輸出電感141之另一端電性連接該第一輸出電容142之一端並輸出該第一交流訊號Vop,該第一輸出電容142之另一端接地。
Wherein, the gate of the first P-type power transistor MP1 receives the first high-level gate control signal Vgh1, the source of the first P-type power transistor MP1 receives the high-level power supply voltage Vhdd, and the first The drain of the P-type power transistor M P1 is electrically connected to the drain of the first N-type power transistor MN1 , and the gate of the first N-type power transistor MN1 receives the first low-level quasi-gate control signal Vgl1, the source of the first N-type power transistor MN1 is grounded, and one end of the
該第二直流交流轉換電路150電性連接該閘極驅動電路130以接收該第二高位準閘極控制訊號Vgh2及該第二低位準閘極控制訊號Vgl2,且該第二直流交流轉換電路150輸出一第二交流訊號Von。
The second DC-
在本實施例中,該第二直流交流轉換電路150具有一第二P型功率電晶體MP2、一第二N型功率電晶體MN2、一第二輸出電感151及一第二輸出電容152,該第二P型功率電晶體MP2接收該第二高位準閘極控制訊號Vgh2,該第二N型功率電晶體MN2接收該第二低位準閘極控制訊號Vgl2,該第二輸出電感151電性連接該第二P型功率電晶體MP2及該第二N型功率電晶體MN2,該第二輸出電容152電性連接該第二輸出電感151。
In this embodiment, the second DC-
其中,該第二P型功率電晶體MP2之閘極接收該第二高位準閘極控制訊號Vgh2,該第二P型功率電晶體MP2之源極接收高位準電源電壓Vhdd,該第
二P型功率電晶體MP2之汲極電性連接該第二N型功率電晶體MN2之汲極,該第二N型功率電晶體MN2之閘極接收該第二低位準閘極控制訊號Vgl2,該第二N型功率電晶體MN2之源極接地,該第二輸出電感151之一端電性連接該第二P型功率電晶體MP2及該第二N型功率電晶體MN2之汲極,該第二輸出電感151之另一端電性連接該第二輸出電容152之一端並輸出該第二交流訊號Von,該第二輸出電容152之另一端接地。
Wherein, the gate of the second P-type power transistor MP2 receives the second high-level gate control signal Vgh2, the source of the second P-type power transistor MP2 receives the high-level power supply voltage Vhdd, and the second The drain of the P-type power transistor M P2 is electrically connected to the drain of the second N-type power transistor MN2 , and the gate of the second N-type power transistor MN2 receives the second low level gate control signal Vgl2, the source of the second N-type power transistor M N2 is grounded, and one end of the
透過該第一高位準閘極控制訊號Vgh1、該第一低位準閘極控制訊號Vgl1、該第二高位準閘極控制訊號Vgh2及該第二低位準閘極控制訊號Vgl2對該第一直流交流轉換電路140及該第二直流交流轉換電路150的控制,可得到互為反相之該第一交流訊號Vop及該第二交流訊號Von,而達成單一個該比較器120及該閘極驅動電路130輸出兩個交流電之功效。
Through the first high-level quasi-gate control signal Vgh1, the first low-level quasi-gate control signal Vgl1, the second high-level quasi-gate control signal Vgh2, and the second low-level quasi-gate control signal Vgl2, the first DC The control of the
本發明藉由該閘極驅動電路130輸出該第一高位準閘極控制訊號Vgh1、該第一低位準閘極控制訊Vgl1號、該第二高位準閘極控制訊號Vgh2及該第二低位準閘極控制訊號Vgl2至該第一交流直流轉換電路140及該第二交流直流轉換電路150進行控制,可提供兩路之交流電壓並避免整體之電路佈局的面積過大。
In the present invention, the
本發明之保護範圍當視後附之申請專利範圍所界定者為準,任何熟知此項技藝者,在不脫離本發明之精神和範圍內所作之任何變化與修改,均屬於本發明之保護範圍。 The scope of protection of the present invention should be defined by the scope of the appended patent application. Any changes and modifications made by anyone who is familiar with this technology without departing from the spirit and scope of the present invention belong to the scope of protection of the present invention. .
100:雙輸出直流交流轉換器 100: Dual output DC-AC converter
110:壓控振盪器 110:Voltage Controlled Oscillator
120:比較器 120: Comparator
130:閘極驅動電路 130: Gate drive circuit
131:非交疊電路 131: Non-overlapping circuits
131a:第一反及閘 131a: The first reverse and gate
131b:第一反相器 131b: the first inverter
131c:第二反及閘 131c: The second reverse and gate
131d:第一延遲單元 131d: the first delay unit
131e:第二反相器 131e: second inverter
131f:第二延遲單元 131f: the second delay unit
131g:第三反相器 131g: the third inverter
132:第一電壓位準轉換器 132: first voltage level converter
132a:電晶體對 132a: Transistor pair
MP11:第一P型功率電晶體 M P11 : The first P-type power transistor
MP12:第二P型功率電晶體 M P12 : The second P-type power transistor
132b:高位準接地電晶體對 132b: high-level grounding transistor pair
MP13:第三P型功率電晶體 M P13 : the third P-type power transistor
MP14:第四P型功率電晶體 M P14 : The fourth P-type power transistor
132c:低位準接地電晶體對 132c: Low level ground transistor pair
MN11:第一N型功率電晶體 M N11 : the first N-type power transistor
MN12:第二N型功率電晶體 M N12 : the second N-type power transistor
132d:反相器 132d: Inverter
133:第二電壓位準轉換器 133: second voltage level converter
134:第一高壓緩衝器 134: The first high-voltage buffer
135:第一低壓緩衝器 135: The first low voltage buffer
136:第二高壓緩衝器 136: Second high voltage buffer
137:第二低壓緩衝器 137: Second low voltage buffer
140:第一直流交流轉換電路 140: The first DC-AC conversion circuit
MP1:第一P型功率電晶體 M P1 : the first P-type power transistor
MN1:第一N型功率電晶體 M N1 : the first N-type power transistor
141:第一輸出電感 141: The first output inductance
142:第一輸出電容 142: The first output capacitor
150:第二直流交流轉換電路 150: the second DC-AC conversion circuit
MP2:第二P型功率電晶體 M P2 : The second P-type power transistor
MN2:第二N型功率電晶體 M N2 : the second N-type power transistor
151:第二輸出電感 151: Second output inductance
152:第二輸出電容 152: second output capacitor
Vramp:鋸齒波 Vramp: sawtooth wave
Vcomp:比較訊號 Vcomp: compare signal
Vhdd:高位準電源電壓 Vhdd: High quasi-power supply voltage
Vhgnd:高位準接地電壓 Vhgnd: high level ground voltage
Vgh1:第一高位準閘極控制訊號 Vgh1: the first high-level quasi-gate control signal
Vgl1:第一低位準閘極控制訊號 Vgl1: the first low quasi-gate control signal
Vgh2:第二高位準閘極控制訊號 Vgh2: The second high quasi-gate control signal
Vgl2:第二低位準閘極控制訊號 Vgl2: second low quasi-gate control signal
Vop:第一交流訊號 Vop: first communication signal
Von:第二交流訊號 Von: second AC signal
ON1:第一非交疊訊號 ON1: The first non-overlapping signal
ON2:第二非交疊訊號 ON2: The second non-overlapping signal
Vref:參考訊號 Vref: reference signal
H1:第一高位準非交疊訊號 H1: The first high-level quasi-non-overlapping signal
H2:第二高位準非交疊訊號 H2: The second highest quasi-non-overlapping signal
H1:反相之第一高位準非交疊訊號 H1: Inverted first high-level non-overlapping signal
第1圖:依據本發明之一實施例,一雙輸出直流交流轉換器之電路圖。 第2圖:依據本發明之一實施例,一閘極驅動電路之電路圖。 第3圖:依據本發明之一實施例,一非交疊電路之電路圖。 第4圖:依據本發明之一實施例,一第一電壓位準轉換器之電路圖。 Figure 1: A circuit diagram of a dual-output DC-AC converter according to an embodiment of the present invention. Figure 2: A circuit diagram of a gate drive circuit according to an embodiment of the present invention. Figure 3: A circuit diagram of a non-overlapping circuit according to an embodiment of the present invention. Fig. 4: According to an embodiment of the present invention, a circuit diagram of a first voltage level converter.
100:雙輸出直流交流轉換器 110:壓控振盪器 120:比較器 130:閘極驅動電路 140:第一直流交流轉換電路 M P1:第一P型功率電晶體 M N1:第一N型功率電晶體 141:第一輸出電感 142:第一輸出電容 150:第二直流交流轉換電路 M P2:第二P型功率電晶體 M N2:第二N型功率電晶體 151:第二輸出電感 152:第二輸出電容 Vramp:鋸齒波 Vcomp:比較訊號 Vhdd:高位準電源電壓 Vhgnd:高位準接地電壓 Vgh1:第一高位準閘極控制訊號 Vgl1:第一低位準閘極控制訊號 Vgh2:第二高位準閘極控制訊號 Vgl2:第二低位準閘極控制訊號 Vop:第一交流訊號 Von:第二交流訊號 Vref:參考訊號 100: Dual-output DC-AC converter 110: Voltage-controlled oscillator 120: Comparator 130: Gate drive circuit 140: The first DC-AC conversion circuit M P1 : The first P-type power transistor M N1 : The first N-type Power transistor 141: first output inductor 142: first output capacitor 150: second DC-AC conversion circuit M P2 : second P-type power transistor M N2 : second N-type power transistor 151: second output inductor 152 : second output capacitor Vramp: sawtooth wave Vcomp: comparison signal Vhdd: high level quasi-supply voltage Vhgnd: high level quasi-ground voltage Vgh1: first high level quasi-gate control signal Vgl1: first low level quasi-gate control signal Vgh2: second high level Quasi-gate control signal Vgl2: second low level quasi-gate control signal Vop: first AC signal Von: second AC signal Vref: reference signal
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TW371382B (en) * | 1996-10-24 | 1999-10-01 | Nec Corp | Circuit and method for driving piezoelectric transformer |
WO2008032424A1 (en) * | 2006-09-15 | 2008-03-20 | Mitsubishi Electric Corporation | Dc/dc power converter |
TW201106594A (en) * | 2009-08-10 | 2011-02-16 | Richtek Technology Corp | Control circuit and method for a buck-boost power converter |
CN112087135A (en) * | 2020-07-31 | 2020-12-15 | 西安电子科技大学 | Multi-mode modulation chip applied to LLC converter |
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TW371382B (en) * | 1996-10-24 | 1999-10-01 | Nec Corp | Circuit and method for driving piezoelectric transformer |
WO2008032424A1 (en) * | 2006-09-15 | 2008-03-20 | Mitsubishi Electric Corporation | Dc/dc power converter |
TW201106594A (en) * | 2009-08-10 | 2011-02-16 | Richtek Technology Corp | Control circuit and method for a buck-boost power converter |
CN112087135A (en) * | 2020-07-31 | 2020-12-15 | 西安电子科技大学 | Multi-mode modulation chip applied to LLC converter |
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