TWI807553B - A manufacturing method of memory device including semiconductor element - Google Patents

Abstract

A N⁺layer 11a which is connected to a source line SL located at both ends of Si pillars 12a to 12d standing in the vertical direction, N⁺layers 13a, 13c which are connected to a bit line BL1, N⁺layers 13b and 13d which are connected to a bit line BL2, a TiN layer 18a which is connected to a metal plate line PL1 that surrounds a gate HfO₂ layer 17 surrounding the Si pillars 12a to 12d and is connected between the Si pillars 12a and 12b, a TiN layer 18b which is connected to a plate line PL2 connected between the Si pillars 12c and 12d, a TiN layer 26b which is connected to a word line WL1 that surrounds a gate HfO₂ layer 17b surrounding the Si pillars 12a to 12d and is connected between the Si pillars 12a, 12b, and a TiN layer 26b which is connected to a word line WL2 connected between the Si pillars 12c and 12d are formed on a substrate 10. Voltages applied to the source line SL, the plate lines PL1, PL2, the word lines WL1, WL2, and the bit lines BL1, BL2 are controlled so as to perform a data holding operation of holding a hole group generated due to the impact ionization phenomenon in the Si pillars 12a to 12b, and a data erase operation of removing the hole group from the Si pillars 12a to 12d.

Description

Method for manufacturing memory device including semiconductor element

The invention relates to a manufacturing method of a memory device including a semiconductor element.

In recent years, in the development of LSI (Large Scale Integration, large-scale integrated circuit) technology, there is a demand for high density and high performance of memory components.

In a common planar MOS transistor, its channel extends horizontally along the upper surface of the semiconductor substrate. In contrast, the channel of the SGT (Surrounding Gate Transistor; Surrounding Gate Transistor) extends in a direction perpendicular to the upper surface of the semiconductor substrate (for example, refer to Patent Document 1 and Non-Patent Document 1). Therefore, compared with planar MOS transistors, SGT can achieve higher density of semiconductor devices. Using this SGT as a selection transistor, DRAM (Dynamic Random Access Memory, dynamic random access memory, dynamic random access memory, for example, refer to non-patent literature 2) connected with capacitors, PCM (Phase Change Memory, phase change memory, for example, referring to non-patent literature 3), RRAM (Resistive Random Access Memory, resistive random access memory, referring to non-patent literature 4), and the direction of the spin magnetic moment is changed by current. variable resistance High densification such as MRAM (Magnetoresistive Random Access, magnetoresistive random access memory. For example, refer to Non-Patent Document 5). In addition, there is also a DRAM memory cell composed of one MOS transistor without a capacitor (see Non-Patent Document 7). This case relates to a dynamic flash memory that can only be composed of MOS transistors without resistance variable elements, capacitors, etc.

FIG. 7 shows the writing operation of the aforementioned DRAM memory cell composed of a MOS transistor without a capacitor, FIG. 8 shows the problems in the operation, and FIG. 9 shows the reading operation (refer to non-patent documents 7 to 10).

FIG. 7 shows the writing operation of a DRAM memory cell. Fig. 7(a) shows the "1" writing state. Here, the memory cell is formed on an SOI (Silicon on Insulator, silicon-on-insulator) substrate 100, the source N ⁺ layer 103 is connected to the source line SL, the drain N ⁺ layer 104 is connected to the bit line BL, and the gate conductor layer 105 is connected to the word line WL. The memory cell of DRAM. In addition, the directly below the floating body 102 is in contact with the SiO ₂ layer 101 of the SOI substrate. When writing "1" into a memory cell constituted by one MOS transistor 110a, the MOS transistor 110a is operated in a linear region. That is, the channel 107 for electrons extending from the source N ⁺ layer 103 has a pinch point 108 in it and does not reach the drain N ⁺ layer 104 to which the bit line is connected. In this way, if both the bit line BL connected to the drain N ⁺ layer 104 and the word line WL connected to the gate conductor layer 105 are set to a high voltage, and the gate voltage is about 1/2 of the drain voltage to operate the MOS transistor 110a, then the electric field intensity becomes maximum at the pinch point 108 near the drain N ⁺ layer 104. As a result, the accelerated electrons flowing from the source N ⁺ layer 103 toward the drain N ⁺ layer 104 collide with the Si lattice, and electron-hole pairs are generated due to the kinetic energy lost at that point (impact ionization phenomenon). Most of the generated electrons (not shown) reach the drain N ⁺ layer 104 . In addition, a very small portion of extremely hot electrons passes through the gate oxide film 109 to reach the gate conductor layer 105 . Moreover, the electric hole 106 generated at the same time charges the floating body 102 . At this time, since the floating body 102 is P-type Si, the generated holes contribute to the increment of majority carriers. The floating body 102 is filled with the generated holes 106 so that the voltage of the floating body 102 is higher than that of the source N ⁺ layer 103 to be above Vb, and further generated holes will discharge the source N ⁺ layer 103 . Here, Vb is the built-in voltage of the PN junction between the source N ⁺ layer 103 and the floating body 102 of the P layer, about 0.7V. FIG. 7( b ) shows the situation that the floating body 102 has been saturated charged by the generated electric hole 106 .

Next, the writing operation of "0" in the memory cell 110 will be described using FIG. 7( c ). For the common selected word line WL, the memory cell 110 a written with “1” and the memory cell 110 b written with “0” exist randomly. FIG. 7( c ) shows the situation of rewriting from the written state of "1" to the written state of "0". When “0” is written, the voltage of the bit line BL is set as a negative bias, and the PN junction between the drain N ⁺ layer 104 and the floating body 102 of the P layer is set as a positive bias. As a result, the hole 106 generated in the floating body 102 in the previous cycle flows to the drain N ⁺ layer 104 connected to the bit line BL. If the writing operation ends, the state of two memory cells of the memory cell 110a shown in FIG. 7( b) filled with the generated electric hole 106 and the memory cell 110b shown in FIG. 7( c) that the generated electric hole has been discharged will be obtained. The potential of the floating body 102 of the memory cell 110a filled with the holes 106 is higher than that of the floating body 102 without any generated holes. Therefore, the threshold voltage of the memory cell 110a is lower than the threshold voltage of the memory cell 110b, as shown in FIG. 7( d ).

Next, problems in the operation of such a memory cell composed of one MOS transistor will be described using FIG. 8 . As shown in Figure 8(a), the capacitance C _FB of the floating body 102 is the sum of the capacitance C _WL , the junction capacitance C _SL , and the junction capacitance C _BL , which is expressed as

C _FB =C _WL +C _BL +C _SL (1)

To represent. Wherein, the capacitor C _WL is the capacitor between the gate connected to the word line and the floating body 102 . The junction capacitance C _SL is the junction capacitance of the PN junction between the source N ⁺ layer 103 connected to the source line and the floating body 102 . The junction capacitance C _BL is the junction capacitance of the PN junction between the source N ⁺ layer 104 connected to the bit line and the floating body 102 . Therefore, if the word _line voltage V _WL oscillates during writing, the voltage of the floating _body 102 which becomes the memory node ₍ contact) of the memory cell will also be affected by it, and a situation as shown _{in FIG .} Its voltage variation △V _FB to

△V _FB =V _FB1 -V _FB2

=C _WL /(C _WL +C _BL +C _SL )×C _ProgWL (2)

To represent.

Here, β=C _WL /(C _WL +C _BL +C _SL ) (3)

To express, β is called the coupling rate. In this type of memory unit, the contribution ratio of C _WL is relatively large, for example, C _WL : C _BL : C _SL =8:1:1. At this time, β=0.8. For example, if the word line is 5V during writing and becomes 0V after writing, the floating body 102 will suffer oscillation noise of 5V×β=4V due to the capacitive coupling between the word line and the floating body 102 . Therefore, there is a problem in that the difference margin of the potential difference between the "1" potential and the "0" potential of the floating body at the time of writing cannot be sufficiently obtained.

Figure 9 shows the reading action. FIG. 9(a) shows the writing state of "1", and Fig. 9(b) shows the writing state of "0". However, actually, even if Vb is written into the floating body 102 by writing "1", when the word line returns to 0V due to the completion of writing, the floating body 102 will be lowered to a negative bias. When "0" is written, since the bias becomes more negative, the difference margin of the potential difference between "1" and "0" cannot be sufficiently increased at the time of writing. For this DRAM memory cell, such a small difference in motion becomes a serious problem. Furthermore, there is also a problem of increasing the density of the DRAM memory cells. In addition, there are also memory devices that use two MOS transistors on an SOI (Silicon on Insulator) layer to form a memory cell (for example, refer to Patent Documents 4 and 5). In these devices, the N ⁺ layer that distinguishes the floating body channel of the two MOS transistors and becomes the source or drain is connected to the insulating layer and formed. By connecting the N ⁺ layer to the insulating layer, the floating body channels of the two MOS transistors are electrically separated. Therefore, the voltage of the separated floating body channel in which the hole group belonging to the signal charge is stored changes greatly as shown in equation (2) by the pulse voltage applied to the gate electrode of each MOS transistor as described above. Therefore, there is a problem that the difference margin of the potential difference between "1" and "0" at the time of writing cannot be sufficiently increased.

[Prior Art Literature]

[Patent Document]

Patent Document 1: Japanese Patent Application Laid-Open No. 2-188966

Patent Document 2: Japanese Patent Application Laid-Open No. 3-171768

Patent Document 3: Japanese Patent No. 3957774

Patent Document 4: US2008/0137394A1

Patent Document 5: US2003/0111681A1

[Non-patent literature]

【0001】

Non-Patent Document 1: Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol.38, No.3, pp.573-578 (1991)

Non-Patent Document 2: H. Chung, H. Kim, H. Kim, K. Kim, S. Kim, K. Dong, J. Kim, Y.C. Oh, Y. Hwang, H. Hong, G. Jin, and C. Chung: “4F2 DRAM Cell with Vertical Pillar Transistor(VPT),” 2011 Proceeding of the European Solid-State Device Research Confer ence, (2011)

Non-Patent Document 3: H. S. Philip Wong, S. Raoux, S. Kim, Jiale Liang, J. R. Reifenberg, B. Rajendran, M. Asheghi and K. E. Goodson: “Phase Change Memory,” Proceeding of IEEE, Vol.98, No 12, December, pp.2201-2227 (2010)

Non-Patent Document 4: T. Tsunoda, K .Kinoshita, H. Noshiro, Y. Yamazaki, T. Iizuka, Y. Ito, A. Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, and Y. Sugiyama: “Low Power and high Speed Switching of Ti-doped NiO ReRAM under the Unipol ar Voltage Source of less than 3V,” IEDM (2007)

Non-Patent Document 5: W. Kang, L. Zhang, J. Klein, Y. Zhang, D. Ravelosona, and W. Zhao: “Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology,” IEEE Transaction on Electron Devices, pp.1-9 (2015)

Non-Patent Document 6: M. G. Ertosum, K. Lim, C. Park, J. Oh, P. Kirsch, and K. C. Saraswat : “Novel Capacitorless Single-Transistor Charge-Trap DRAM (1T CT DRAM) Utilizing Electron,” IEEE Electron Device Letter, Vol. 31, No.5, pp.405-40 7 (2010)

Non-Patent Document 7: J. Wan, L. Rojer, A. Zaslavsky, and S. Critoloveanu: “A Compact Capacitor-Less High-Speed DRAM Using Field Effect-Controlled Charge Regeneration,” Electron Device Letters, Vol. 35, No.2, pp.179-181 (2012)

Non-Patent Document 8: T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi: “Memory design using a one-transistor gain cell on SOI,” IEEE JSSC, vol.37, No.11, pp1510-1522 (2002).

Non-Patent Document 9: T. Shino, N. Kusunoki, T. Higashi, T. Ohsawa, K. Fujita, K. Hatsuda, N. Ikumi, F. Matsuoka, Y. Kajitani, R. Fukuda, Y. Watanabe, Y. Minami, A. Sakamoto, J. Nishimura, H. Nakajima, M. Morikado, K. Ino h, T. Hamamoto, A. Nitayama: “Floating Body RAM Technology and its Scalability to 32nm Node and Beyond,” IEEE IEDM (2006).

Non-Patent Document 10: E. Yoshida: "A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory," IEEE IEDM (2006).

Non-Patent Document 11: J.Y. Song, W. Y. Choi, J. H. Park, J. D. Lee, and B-G. Park: “Design Optimization of Gate-All-Around (GAA) MOSFETs,” IEEE Trans. Electron Devices, vol. 5, no. 3, pp.186-191, May 2006.

Non-Patent Document 12: N. Loubet, et al.: “Stacked Nanosheet Gate-All-Around Transistor to Enable Scaling Beyond FinFET,” 2017 IEEE Symposium on VLSI Technology Digest of Technical Papers, T17-5, T230-T231, June 2017.

Non-Patent Document 13: H. Jiang, N. Xu, B. Chen, L. Zeng1, Y. He, G. Du, X. Liu and X. Zhang: “Experimental investigation of self heating effect (SHE) in multiple-fin SOI FinFETs,” Semicond. Sci. Technol. 29 (2014) 115021 (7pp ).

Non-Patent Document 14: E. Yoshida, and T. Tanaka: "A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory," IEEE Transactions on Electron Devices, Vol. 53, No. 4, pp. 69 2-697, Apr. 2006.

In a transistor-type DRAM (gain unit) without a capacitor in a memory device using SGT, the capacitive coupling between the word line and the SGT substrate of the floating body is relatively large. When the potential of the word line oscillates when data is read or written, there will be a problem that it will be directly regarded as noise transmitted to the SGT substrate. As a result, problems of misreading and misrewriting of memory data are caused. However, it is difficult to realize the practical application of a one-transistor DRAM (gain unit) without a capacitor. Therefore, it is necessary to solve the above problems and increase the density of memory cells.

In order to solve the above-mentioned problems, the present invention provides a method of manufacturing a memory device comprising a columnar semiconductor element. The memory device is to perform: a data retention operation, which is to control the voltage applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region, and to maintain the hole group formed by the impact free phenomenon or the drain leakage current caused by the gate in any one or each of the first semiconductor pillar, the second semiconductor pillar, the third semiconductor pillar, and the fourth semiconductor pillar; and the data erasing operation. Controlling the voltage applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region to remove the hole group from any or each of the first to fourth semiconductor pillars; the manufacturing method has the following steps:

The step of forming the first semiconductor column and the second semiconductor column, and the third semiconductor column and the fourth semiconductor column on the substrate, wherein the first semiconductor column and the second semiconductor column stand in a vertical direction and are arranged adjacently in the first direction when viewed from above, and the third semiconductor column and the fourth semiconductor column are arranged adjacently in a second direction parallel to the first direction;

a step of forming a first insulating layer surrounding the aforementioned first to fourth semiconductor pillars;

The step of forming the aforementioned first gate conductor layer and the aforementioned second gate conductor layer, the aforementioned first gate conductor layer surrounds the aforementioned first insulating layer, and in the vertical direction, its upper surface is located below the aforementioned first to fourth semiconductor columns, and in the aforementioned first direction, in the aforementioned The first semiconductor column is connected with the aforementioned second semiconductor column, and the aforementioned second gate conductor layer is connected between the aforementioned third semiconductor column and the aforementioned fourth semiconductor column in the aforementioned second direction;

Etching the first gate conductor layer in the vertical direction and the first insulating layer above the second gate conductor layer, and forming a first gate insulating layer at the bottom of the first to fourth semiconductor pillars;

A step of forming a second gate insulating layer in a vertical direction in contact with the first gate insulating layer and surrounding the side surfaces of the first to fourth semiconductor pillars;

The step of forming the third gate conductor layer and the fourth gate conductor layer, the third gate conductor layer surrounds the second gate insulating layer, and in the vertical direction, its upper surface is located below the tops of the first to fourth semiconductor pillars, and is connected between the first semiconductor pillar and the second semiconductor pillar in the first direction, and is separated from the first gate conductor layer in the vertical direction, the fourth gate conductor layer is connected between the third semiconductor pillar and the fourth semiconductor pillar arranged in the second direction, and in the vertical direction separated from the aforementioned second gate conductor layer;

Before or after forming the first to fourth semiconductor pillars, a step of forming the first impurity region connected to the bottom of the second semiconductor pillar, the third semiconductor pillar, and the fourth semiconductor pillar;

A step of forming the aforementioned second impurity region on each of the tops of the aforementioned first to fourth semiconductor columns before or after forming the aforementioned first to fourth semiconductor columns; and

The step of forming a first wiring conductor layer and a second wiring conductor layer, the first wiring conductor layer is connected to the second impurity region on the top of the first semiconductor pillar and the third semiconductor pillar, the second wiring conductor layer is connected to the second impurity region on the top of the second semiconductor pillar and the fourth semiconductor pillar.

In the above method of manufacturing a memory device comprising a columnar semiconductor element, when viewed from above, the first length between the two outer perimeter lines of the first gate insulating layer surrounding the first semiconductor column and the second semiconductor column and the intersection point of the first line connecting the center of the first semiconductor column and the aforementioned second semiconductor column and the first length between the two points of intersection between the two outer perimeter lines of the aforementioned second gate insulating layer surrounding the first semiconductor column and the aforementioned third semiconductor column and the second line connecting the center of the first semiconductor column and the aforementioned third semiconductor column The second length between the two points is smaller;

The aforementioned second length is greater than twice the third length of the thickness of the aforementioned first gate conductor layer located on the aforementioned second line and surrounding the aforementioned first semiconductor pillar;

The aforementioned first length is smaller than twice the aforementioned third length.

In the above method of manufacturing a memory device comprising a columnar semiconductor element, the following steps are further included:

After forming the first gate insulating layer, forming a first conductor layer whose upper surface is positioned vertically to be the upper ends of the first gate conductor layer and the second gate conductor layer on the outer periphery of the first gate insulating layer;

The step of forming a first mask material layer, a second mask material layer and a third mask material layer, the first mask material layer is located on the top of the first to fourth semiconductor pillars, the second mask material layer surrounds the sides of the first to fourth semiconductor pillars, and is connected between the first semiconductor pillar and the second semiconductor pillar, and the third mask material layer is connected between the third semiconductor pillar and the fourth semiconductor pillar, and is separated from the second mask material layer; and

Using the first mask material layer, the second mask material layer and the third mask material layer as masks, etching the first conductor layer to form the first gate conductor layer and the second gate conductor layer.

In the above method of manufacturing a memory device including a columnar semiconductor element, the following steps are further included: after forming the second gate insulating layer, forming a second conductor layer whose upper surface is located near the lower end of the second impurity region in the vertical direction on the outer periphery of the second gate insulating layer; The layers surround the side surfaces of the first to fourth semiconductor pillars and are connected between the first semiconductor pillar and the second semiconductor pillar, the fifth mask material layer is connected between the third semiconductor pillar and the fourth semiconductor pillar; and using the first mask material layer, the fourth mask material layer and the fifth mask material layer as masks, etching the second conductor layer to form the third gate conductor layer and the fourth gate conductor layer.

In the above method of manufacturing a memory device comprising a columnar semiconductor element, the following steps are further included: for the aforementioned first to fourth semiconductor columns with the first masking material layer formed on the top, after forming the aforementioned first gate insulating layer, on the outer peripheral portion of the aforementioned first gate insulating layer, a step of forming a third conductive layer whose upper surface is located in the vertical direction near the middle position of the aforementioned first to fourth semiconductor columns; removing the aforementioned first gate insulating layer above the aforementioned third conductive layer, and forming a second insulating layer on the aforementioned second insulating layer; layer, a step of forming a fourth conductor layer whose upper surface is close to the lower end of the aforementioned second impurity region in the vertical direction; The step of forming a sixth mask material layer and a seventh mask material layer in a separate manner, the sixth mask material layer is formed to surround the sides of the first and second semiconductor columns on the fourth conductor layer, and is connected between the first semiconductor column and the second semiconductor column, the seventh mask material layer is formed to surround the sides of the third and fourth semiconductor columns on the fourth conductor layer, and is connected between the third semiconductor column and the fourth semiconductor column; and the first mask material layer, the sixth mask material layer, and the seventh mask material layer as a mask, etching the third conductor layer, the second insulating layer and the fourth conductor layer to form the first gate conductor layer, the second gate conductor layer, the third gate conductor layer and the fourth gate conductor layer.

In the above method of manufacturing a memory device including a columnar semiconductor element, the wiring connected to the first impurity region is a source line, the wiring connected to the second impurity region is a bit line, and if one of the wirings connected to the first gate conductor layer and the second gate conductor layer and the wiring connected to the third gate conductor layer and the fourth gate conductor layer is a word line, the other is a first drive control line; to selectively perform the aforementioned data erasing operation and the aforementioned data holding operation.

In the above method of manufacturing a memory device including pillar-shaped semiconductor elements, the first gate capacitance between the first gate conductor layer and the first to fourth semiconductor pillars is formed to be larger than the second gate capacitance between the second gate conductor layer and the first to fourth semiconductor pillars.

In the above method of manufacturing a memory device including a columnar semiconductor element, when viewed from above, a first hole is formed between the third gate conductor layer and the fourth gate conductor layer.

In the above method of manufacturing a memory device including columnar semiconductor elements, a second hole is formed between the first wiring conductor layer and the second wiring conductor layer.

In the above method of manufacturing a memory device including a columnar semiconductor element, the second insulating layer is formed by the second gate insulating layer connected to the first to fourth semiconductor columns.

1,10: Substrate

2, 12a, 12b, 12c, 12d: Si column

3a, 3b, 11, 11a, 13, 13a, 13b, 13c, 13d: N ⁺ layers

4a: The first gate insulating layer

4b: The second gate insulating layer

5a: The first gate conductor layer

5b: The second gate conductor layer

6: Insulation layer

7: Channel area

7a: First channel region (first channel Si layer)

7b: Second channel region (second channel Si layer)

9: Dynamic flash memory unit

12: P layer

14a, 14b, 14c, 14d: mask material layer

17, 17a, 17b, 33, 33a, 33b: HfO ₂ layers

18, 18a, 18b, 18c, 18d, 26a, 26b, 34, 34a, 34b: TiN layer

20, 20a, 20b, 23, 29: SiO ₂ layers

21a, 21b, 27a, 27b, 36a, 36b: SiN layer

30a, 30b, 30c, 30d: contact holes

31a: conductor layer of bit line BL1

31aa, 31ab, 31ac, 31ba, 31bb, 31bc, 31ca, 31cb, 31cc, 34a, 34b, 34c: empty holes

31b: conductor layer of bit line BL2

100: SOI substrate

101: SiO ₂ layers

102: floating body

103: Source N ⁺ layer

104: drain N ⁺ layer

105: gate conductor layer

106: electric hole

107: channel

108: pinch point

109:Gate oxide film

110: memory unit

110a: memory unit (MOS transistor)

110b: memory unit

BL: bit line

BL1: bit line

BL2: bit line

PL: metal plate line

PL1: Metal plate line

PL2: Metal plate line

SL: source line

WL: character line

WL1: word line

WL2: word line

C _FB : capacitance

C _WL : Capacitance

C _PL : Capacitance

C _SL : junction capacitance

C _BL : junction capacitance

V _WL : word line voltage

V _FB : the voltage of the floating body

L1, L2, L3: Length

FIG. 1 is a structural diagram of a memory device with SGT in the first embodiment.

FIG. 2 is a diagram for explaining the erase operation mechanism of the memory device with SGT in the first embodiment.

FIG. 3 is a diagram for explaining the writing operation mechanism of the memory device having the SGT in the first embodiment.

FIG. 4A is a diagram for explaining the read operation mechanism of the memory device with SGT in the first embodiment.

FIG. 4B is a diagram for explaining the read operation mechanism of the memory device with SGT in the first embodiment.

FIG. 5A is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5B is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5C is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5D is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5E is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5F is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5G is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5H is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5I is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 5J is a diagram for explaining the manufacturing method of the memory device with SGT in the first embodiment.

FIG. 6A is a diagram illustrating a method of manufacturing a memory device having an SGT according to the second embodiment.

FIG. 6B is a diagram illustrating a method of manufacturing a memory device having an SGT in the second embodiment.

FIG. 6C is a diagram for explaining the manufacturing method of the memory device with SGT in the second embodiment.

FIG. 7 is a diagram for explaining problems in the operation of a conventional DRAM memory cell without a capacitor.

FIG. 8 is a diagram for explaining problems in the operation of a conventional DRAM memory cell without a capacitor.

FIG. 9 is a diagram showing a reading operation of a conventional DRAM memory cell without a capacitor.

A memory device including a semiconductor element (hereinafter referred to as a dynamic flash memory) of the present invention will be described below with reference to the drawings.

(first implementation type)

The structure and operation mechanism of the dynamic flash memory unit of the first embodiment of the present invention will be described using FIG. 1 to FIG. 5 . The structure of a dynamic flash memory cell will be described using FIG. 1 . In addition, the data erasing mechanism is described using FIG. 2 , the data writing mechanism is described using FIG. 3 , and the data writing mechanism is described using FIGS. 4A and 4B . A method of manufacturing a dynamic flash memory will be described using FIG. 5 .

FIG. 1 shows the structure of the dynamic flash memory unit of the first embodiment of the present invention. In the upper and lower positions of the Si pillars 2 with p-type or i-type (intrinsic) conductivity formed on the substrate 1 (hereinafter, silicon semiconductor pillars are referred to as "Si pillars"), there are formed N ⁺ layers 3a and 3b (hereinafter, semiconductor regions containing high-concentration donor impurities are referred to as "N ⁺ layers") where one becomes a source and the other becomes a drain. The portion that becomes the Si column 2 between the N ⁺ layers 3 a and 3 b of the source and drain becomes the channel region 7 . A first gate insulating layer 4 a and a second gate insulating layer 4 b are formed to surround the channel region 7 . The first gate insulating layer 4a and the second gate insulating layer 4b are respectively connected to or close to the N ⁺ layers 3a and 3b which become the source and drain. A first gate conductor layer 5a and a second gate conductor layer 5b are formed to surround the first gate insulating layer 4a and the second gate insulating layer 4b, respectively. Moreover, the first gate conductor layer 5 a and the second gate conductor layer 5 b are separated by the insulating layer 6 . Moreover, the channel region 7 of the part of the Si column 2 between the N ⁺ layers 3a, 3b is composed of the first channel Si layer 7a surrounded by the first gate insulating layer 4a and the second channel Si layer 7b surrounded by the second gate insulating layer 4b. Thereby, a dynamic flash memory cell 9 composed of N ⁺ layers 3a and 3b serving as source and drain, a channel region 7, a first gate insulating layer 4a, a second gate insulating layer 4b, a first gate conductor layer 5a, and a second gate conductor layer 5b is formed. Moreover, the N ⁺ layer 3a that becomes the source is connected to the source line SL, the N ⁺ layer 3b that becomes the drain is connected to the bit line BL, the first gate conductor layer 5a is connected to the metal plate line (plate line) PL, and the second gate conductor layer 5b is connected to the word line WL. Preferably, the gate capacitance of the first gate conductor layer 5a connected to the metal plate line PL is larger than the gate capacitance of the second gate conductor layer 5b connected to the word line WL.

Here, in FIG. 1, the gate length of the first gate conductor layer 5a is greater than the gate length of the second gate conductor layer 5b, so that the gate capacitance of the first gate conductor layer 5a connected to the metal plate line PL is greater than the gate capacitance of the second gate conductor layer 5b connected to the word line WL. However, in addition, the gate length of the first gate conductor layer 5a may not be greater than the gate length of the second gate conductor layer 5b, but the film thickness of each gate insulating layer is changed so that the film thickness of the gate insulating layer of the first gate insulating layer 4a is smaller than the film thickness of the gate insulating layer of the second gate insulating layer 4b. In addition, the dielectric constant of the material of each gate insulating layer can also be changed, so that the dielectric constant of the gate insulating layer of the first gate insulating layer 4a is greater than that of the second gate insulating layer 4b. In addition, the lengths of the gate conductor layers 5a and 5b, the film thicknesses of the gate insulating layers 4a and 4b, and the dielectric constant can be combined arbitrarily so that the gate capacitance of the first gate conductor layer 5a connected to the metal plate line PL is greater than the gate capacitance of the second gate conductor layer 5b connected to the word line WL.

Referring to FIG. 2, the erasing action mechanism will be described. The channel region 7 between the N ⁺ layers 3a, 3b is electrically separated from the substrate to form a floating body. FIG. 2( a ) shows the state that the hole group 11 generated by impact ionization in the previous cycle accumulates in the channel region 7 before the erasing operation. And, as shown in FIG. 2( b ), during the erasing operation, the voltage of the bit line BL is set to the negative voltage V _ERA . Here, V _ERA is -3V, for example. As a result, the PN junction between the source N ⁺ layer 3 a connected to the source line SL and the channel region 7 is positively biased regardless of the value of the initial potential of the channel region 7 . As a result, the hole group 11 accumulated in the channel region 7 generated by impact ionization in the previous cycle is sucked into the N ⁺ layer 3 a of the source portion, and the potential V _FB of the channel region 7 becomes V _FB =V _ERA +Vb. Here, Vb is the built-in voltage of the PN junction, which is about 0.7V. Therefore, when V _ERA =-3V, the potential of the channel region 7 becomes -2.3V. This value becomes the potential state of the channel region 7 in the erased state. Therefore, if the potential of the channel region 7 of the floating body becomes a negative voltage, the threshold voltage of the N-channel MOS transistor of the dynamic flash memory unit 9 will become higher due to the substrate bias effect. Thereby, as shown in FIG. 2( c ), the threshold voltage of the second gate conductor layer 5 b connected to the word line WL becomes higher. The erased state of the channel area 7 becomes logical memory data "0". In addition, it is also possible to use GIDL (Gate Induced Drain Leakage, Gate Induced Drain Leakage) current (for example, refer to Non-Patent Document 14) to generate electron and hole pairs during the writing of "1", and fill the floating body FB with the generated hole groups.

FIG. 3 shows the writing operation of the dynamic flash memory unit of the first embodiment of the present invention. As shown in FIG. 3(a), for example 0V is input to the N ⁺ layer 3a connected to the source line SL, for example 3V is input to the N ⁺ layer 3b connected to the bit line BL, for example 2V is input to the first gate conductor layer 5a connected to the metal plate line PL, and for example 5V is input to the second gate conductor layer 5b connected to the word line WL. As a result, as shown in FIG. 3(a), an inversion layer 12a is formed on the inner periphery of the first gate conductor layer 5a connected to the metal plate line PL, and the first N-channel MOS transistor region having the first gate conductor layer 5a operates in a saturation region. As a result, pinch points 13 exist in the inversion layer 12a on the inner periphery of the first gate conductor layer 5a connected to the metal plate line PL. On the other hand, the second N-channel MOS transistor region having the second gate conductor layer 5b connected to the word line WL operates in the linear region. As a result, there is no pinch point on the inner periphery of the second gate conductor layer 5b connected to the word line WL, and the inversion layer 12b is formed on the entire surface. The inversion layer 12b formed entirely under the second gate conductor layer 5b connected to the word line WL operates as a substantial drain of the second N-channel MOS transistor region having the second gate conductor layer 5b. As a result, the electric field becomes maximum at the junction region of the channel region 7 between the first N-channel MOS transistor region having the first gate conductor layer 5a connected in series and the second N-channel MOS transistor region having the second gate conductor layer 5b, and impact ionization occurs in this region. Since this region is the region on the source side viewed from the second N-channel MOS transistor region having the second gate conductor layer 5b connected to the word line WL, this phenomenon is called the source side impact free phenomenon. By this source-side impact ionization phenomenon, electrons flow from the N ⁺ layer 3 a connected to the source line SL toward the N ⁺ layer 3 b connected to the bit line. The accelerated electrons hit lattice Si atoms to generate electron-hole pairs by their kinetic energy. Part of the generated electrons will flow to the first gate conductor layer 5a and the second gate conductor layer 5b, but most of them will flow to the N ⁺ layer 3b (not shown) connected to the bit line BL.

Furthermore, in FIG. 3 , as shown in FIG. 3( b ), the generated hole group 11 is the majority carrier of the channel region 7 and charges the channel region 7 to a positive bias. Since the N ⁺ layer 3 a connected to the source line SL is 0 V, the channel region 7 is charged to the built-in voltage Vb (about 0.7 V) of the PN junction between the N ⁺ layer 3 a connected to the source line SL and the channel region 7 . When the channel region 7 is charged with positive bias voltage, the threshold voltages of the first N-channel MOS transistor region and the second N-channel MOS transistor region will become lower due to the substrate bias effect. Thus, as shown in FIG. 3( c ), the threshold voltage of the second N-channel MOS transistor region connected to the second channel region 7 b of the word line WL becomes lower. The write state of this channel area 7 is assigned to logical memory data "1".

Here, during the writing operation, the second boundary region between the first impurity layer and the first channel semiconductor layer or the third boundary region between the second impurity layer and the second channel semiconductor layer can be used instead of the above-mentioned boundary region 7 between the first N-channel MOS transistor region with the first gate conductor layer 5a and the second N-channel MOS transistor region with the second gate conductor layer 5b, to generate electron and hole pairs by impacting ion phenomenon or GIDL current, and charge the channel region 7 with the generated hole group 11.

4A and 4B are diagrams for explaining the reading operation of the dynamic flash memory unit of the first embodiment of the present invention. As shown in (a) of FIG. 4A , when the channel region 7 is charged to the built-in voltage Vb (about 0.7V), the threshold voltage of the N-channel MOS transistor will decrease due to the substrate bias effect. Assign this status to logical memory data "1". As shown in (b) of FIG. 4A , when the selected memory block is in the erase state “0” before writing, the floating voltage V _FB in the channel region 7 becomes V _ERA +Vb. The writing state "1" is randomly memorized by the writing operation. As a result, logical memory data of logic "0" and "1" are created for the word line WL. As shown in (c) of FIG. 4A , using the difference between the two threshold voltages for the word line WL, reading can be performed with a sense amplifier.

In FIG. 4B, (d) of FIG. 4B is a structural diagram illustrating the relationship between the gate capacitances of the first gate conductor layer 5a and the second gate conductor layer 5b during the reading operation of the dynamic flash memory unit of the first embodiment of the present invention. The gate capacitance of the second gate conductor layer 5b connected to the word line WL is preferably designed to be smaller than the gate capacitance of the first gate conductor layer 5a connected to the metal plate line PL. As shown in (d) of FIG. 4B , the length in the vertical direction of the first gate conductor layer 5a connected to the metal plate line PL is greater than the length in the vertical direction of the second gate conductor layer 5b connected to the word line WL, and the gate capacitance of the second gate conductor layer 5b connected to the word line WL is smaller than the capacitance of the first gate conductor layer 5a connected to the metal plate line PL. (e) of FIG. 4B shows the equivalent circuit of one unit of the dynamic flash memory unit of (d) of FIG. 4B. Furthermore. (f) of FIG. 4B shows the coupling capacitance relationship of the dynamic flash memory unit. Here, C _WL is the capacitance of the second gate conductor layer 5b, C _PL is the capacitance of the first gate conductor layer 5a, C _BL is the junction capacitance of the PN junction between the N ⁺ layer 3b of the drain and the second channel region 7b, and _CSL is the junction capacitance of the PN junction between the N ⁺ layer 3a of the source and the first channel region 7a. As shown in (g) of FIG. 4B , when the voltage applied to the word line WL fluctuates, its operation becomes noise and affects the channel region 7 . The potential variation ΔV _FB of the channel region 7 at this time becomes ΔV _FB =C _WL /(C _PL +C _WL +C _BL +C _SL )×V _ReadWL . Here, V _ReadWL is an oscillation potential at the time of reading the word line WL. From equation (1) shown in (g), it can be seen that if the contribution rate of C _WL is reduced compared to the overall capacitance C _PL +C _WL +C _BL +C _SL of the channel region 7 , then ΔV _FB becomes smaller. C _BL +C _SL is the junction capacitance of the PN junction. To increase the junction capacitance, for example, the diameter of the Si pillar 2 can be increased. However, this is not ideal for miniaturization of memory cells. In this regard, by making the length in the vertical direction of the first gate conductor layer 5a connected to the metal plate line PL longer than the length in the vertical direction of the second gate conductor layer 5b connected to the word line WL, ΔV _FB can be made smaller without reducing the density of memory cells when viewed from above.

5A to 5H show the manufacturing method of the dynamic flash memory unit of this embodiment. In each figure, (a) is a plan view, (b) is a sectional view along the X-X' line of (a), and (c) is a sectional view along the Y-Y' line of (a).

As shown in FIG. 5A , on a substrate 10 (an example of a "substrate" in the scope of the patent application), an N ⁺ layer 11 (an example of the "first impurity region" in the scope of the patent application), a P layer 12 made of Si, and an N ⁺ layer 13 are formed from below. In addition, circular mask material layers 14a, 14b, 14c, and 14d (an example of the "first mask material layer" in the scope of the patent application) are formed. Here, the substrate 10 may be formed of SOI, single or plural layers of Si, or other semiconductor materials, and may also be a well layer composed of an N layer or a single or plural layers of a P layer.

Next, as shown in FIG. 5B, using the mask material layers 14a to 14d as masks, N⁺layer 13, P layer 12, and N⁺The upper part of layer 11 is etched, while the N⁺Formed on the layer 11a are Si columns 12a (an example of the "first semiconductor column" in the scope of the patent application), 12b (an example of the "second semiconductor column" in the scope of the patent application), 12c (an example of the "third semiconductor column" in the scope of the patent application), 12d (not shown, an example of the "fourth semiconductor column" in the scope of the patent application), N⁺Layers 13a, 13b, 13c, and 13d (not shown) (each an example of the "second impurity region" in the scope of the patent application).

Next, as shown in FIG. 5C , a gate insulating layer HfO ₂ layer 17 (an example of the "first insulating layer" in the scope of the patent application) is formed covering the entirety using, for example, ALD (Atomic Layer Deposition) method. Furthermore, a TiN layer (not shown) that will become the gate conductor layer is formed covering the whole, and polished to the upper surface position by CMP (Chemical Mechanical Polishing) to become the upper surface of the mask material layers 14a to 14d. Furthermore, the TiN layer is etched by RIE (Reactive Ion Etching, Reactive Ion Etching) until the upper surface position in the vertical direction is located near the middle position of the Si pillars 12a to 12d to form the TiN layer 18 (an example of the "first conductor layer" in the scope of the patent application). Here, if it can function as a gate insulating layer, the HfO ₂ layer 17 may be another insulating layer composed of a single layer or a plurality of layers. Furthermore, as long as it has the function of a gate conductor layer, the TiN layer 18 may use the other conductor layer which consists of a single layer or a plurality of layers. In addition, the position of the upper surface of the TiN layer 18 in the vertical direction is preferably etched higher than the middle position of the Si pillars 12a to 12d.

Next, as shown in FIG. 5D, an SiO ₂ layer 20 whose upper surface position is located near the lower end of the N ⁺ layers 13a to 13d is formed. Furthermore, a silicon nitride (SiN) layer (not shown) is entirely covered, and is polished by CMP until the upper surface positions become the upper surface positions of the mask material layers 14a to 14d. Furthermore, SiN is etched by the RIE method, whereby Si pillars 12a, 12b are connected and Si pillars 12c, 12d are connected, and Si pillars 12a, 12c are separated, and Si pillars 12b, 12d are separated on the side surfaces of N ⁺ layers 13a to 13d and mask material layers 14a to 14d. An example of the "third masking material layer" in the range). When Si pillars 12a to 12d are sufficiently separated along XX' and YY' directions in plan view, SiN layers 21a and 21b are formed to surround Si pillars 12a to 12d with equal width. The length of this equal width is L3 as shown in figure (a) (an example of the "third length" in the scope of the patent application). As shown in Figure (a), if the length L1 (an example of the "first length" of the scope of the patent application) between the intersection point of the outer peripheral line of the HfO _layer 17 surrounding the Si pillars 12a, 12b and the XX' line is smaller than twice L3, then the SiN layer 21a can be formed continuously between the Si pillars 12a and 12b. Similarly, the SiN layer 21b can be formed continuously between the Si pillars 12c and 12d. Also, as shown in Figure (a), if the length L2 (an example of the "second length" of the scope of the patent application) between the intersection point of the outer peripheral line of the HfO _layer 17 surrounding the Si pillars 12a, 12c and the YY' line is greater than twice L3, then the SiN layers 21a, 21b can be formed separately between the Si pillars 12a, 12c, and between the Si pillars 12b, 12d.

Next, as shown in FIG. 5E, the SiO layer ₂₀ and the TiN layer 18 are etched using the SiN layers 21a, 21b and the mask material layers 14a to 14d as masks to form the SiO layer _20a and the TiN layer 18a surrounding the Si pillars 12a and 12b (an example of the "first gate conductor layer" in the scope of the patent application), and form the SiO layer 20b and the TiN layer ₁ surrounding the Si pillars 12c and 12d. 8b (also an example of the "first gate conductor layer" in the scope of the patent application together with the TiN layer 18a). Furthermore, the SiN layers 21a, 21b and the SiO ₂ layers 20a, 20b are removed.

Next, as shown in FIG. 5F , the SiO ₂ layer 23 (an example of the "second insulating layer" in the scope of the patent application) is formed so that the upper surface position becomes the upper surface of the TiN layers 18a, 18b.

Next, as shown in FIG. 5G , the HfO 2 layer 17 higher than the SiO ₂ layer 23 is etched to form an HfO ₂ layer _17a (an example of the "first gate insulating layer" in the scope of the patent application). Furthermore, an HfO ₂ layer 17b (an example of the "second gate insulating layer" in the scope of the patent application) is formed on the whole. Furthermore, the whole is covered with a TiN layer (not shown) by CVD. Furthermore, the TiN layer is etched by the CMP method and the RIE method until the position of the upper surface becomes near the lower end of the N ⁺ layers 13a and 13d. Furthermore, by the same method as that of forming SiN layers 21a, 21b in FIG. 5D, a SiN layer 27a (an example of the "fourth mask material layer" in the scope of the patent application) that surrounds and connects the sides of the N ⁺ layers 13a, 13b and the mask material layers 14a, 14b is formed. Similarly, a SiN layer 27b (an example of the "fifth mask material layer" in the scope of the patent application) is formed to surround and connect the side surfaces of the N ⁺ layers 13c and 13d and the mask material layers 14c and 14d. Furthermore, using the SiN layers 27a and 27b as masks, the TiN layer is etched to form TiN layers 26a (an example of the "third gate conductor layer" in the scope of the patent application) and 26b (an example of the "fourth gate conductor layer" in the scope of the patent application).

Next, as shown in FIG. 5H, a SiO2 layer 29 including holes 31aa, 31ab, 31ac, 31ba, 31bb, 31bc, 31ca, 31cb, and 31cc (an example of the " _first hole" in the scope of the patent application) is formed between and around the side surfaces of the TiN layers 26a, 26b and the SiN layers 27a, 27b. Figure (d) is a sectional view along the X1-X1' line of Figure (a) (the same is true in Figure 5I). Here, the upper end positions of the holes 31aa, 31ab, 31ac, 31ba, 31bb, 31bc, 31ca, 31cb, 31cc are formed lower than the upper end positions of the TiN layers 26a, 26b shown by the dotted lines in FIG.

Next, as shown in FIG. 5I, the mask material layers 14a to 14d are etched to form contact holes 30a, 30b, 30c, and 30d.

Next, as shown in FIG. 5J , the conductor layer 31a of the bit line BL1 connected to the N ⁺ layers 13a and 13c through the contact holes 30a and 30c (an example of the "first wiring conductor layer" in the scope of the patent application) and the conductor layer 31b of the bit line BL2 connected to the N ⁺ layers 13b and 13d through the contact holes 30b and 30d (an example of the "second wiring conductor layer" in the scope of the patent application) are formed. Furthermore, between the conductor layer 31a of the bit line BL1 and the conductor layer 31b of the bit line BL2, a _SiO2 layer 29 including holes 34a, 34b, and 34c (an example of the "second hole" in the scope of the patent application) is formed. Thereby, a dynamic flash memory is formed on the substrate 10 . TiN layers 26a, 26b serve as conductor layers for word lines WL1, WL2, TiN layers 18a, 8b serve as conductor layers for metal plate lines PL1, PL2, and N ⁺ layer 11a serves as a conductor layer for source lines SL.

Here, in FIG. 1, the vertical length of the first gate conductor layer 5a connected to the metal plate line PL is greater than the vertical length of the second gate conductor layer 5b connected to the word line WL so that C _PL >C _WL is preferable. However, as long as the metal plate line PL is added, the coupling ratio (C _WL /(C _PL +C _WL +C _BL +C _SL )) of the word line WL to the capacitive coupling of the channel region 7 becomes smaller. As a result, the potential variation ΔV _FB of the channel region 7 of the floating body becomes smaller.

2 shows an erase operation, FIG. 3 shows a write operation, and FIG. 4 shows examples of voltages applied to source line SL, plate line PL, word line WL, and bit line BL in a read operation. However, if the various basic operations of erasing, writing, and reading can be obtained, the parameters for these source lines SL, metal plate lines PL, word lines WL, and bit lines BL can also be changed. Apply voltage. In addition, in FIG. 1, in the channel region 7 of the portion surrounded by the insulating layer 6 in the vertical direction, the potential distributions of the first channel region 7a and the second channel region 7b are formed in a continuous manner. Thereby, the first channel region 7 a and the second channel region 7 b of the channel region 7 are connected in the vertical direction by the region surrounded by the insulating layer 6 .

In addition, as shown in FIG. 5A, the N ⁺ layer 11a in FIG. 5J is formed before the step of forming Si pillars 12a to 12d. On the other hand, it may also be formed in a step after forming the Si pillars 12a to 12d, for example. Likewise, N ⁺ layers 13a to 13d in FIG. 5J are formed using N ⁺ layer 13 formed before the step of forming Si pillars 12a to 12d. On the other hand, the N ⁺ layers 13a to 13d may also be formed, for example, in a step after forming the Si pillar TiN layers 26a, 26b.

In addition, in this embodiment, the Si pillars 12 a to 12 d are arranged in a square lattice in a plan view, but they may also be arranged in an oblique lattice. When arranged in a diagonal lattice, the Si pillars (not shown) connected to the Si pillars 12a and 12b are arranged in a zigzag shape along the XX' line. Similarly, the Si pillars (not shown) connected to the Si pillars 12c and 12d are arranged in a zigzag shape along the XX' line. At this time, the relationship of L1 , L2 , and L3 in FIG. 5D can be maintained even in a zigzag configuration. The same applies to other embodiments of the present invention.

In addition, in FIG. 5I, the holes 31aa, 31ab, 31ac, 31ba, 31bb, 31bc, 31ca, 31cb, and 31cc are formed independently of each other. On the other hand, the distance between the Si pillars 12a, 12c and the distance between the Si pillars 12b, 12d may be increased, and the holes 31aa, 31ab, 31ac may be connected, the holes 31ba, 31bb, 31bc may be connected, and the holes 31ca, 31cb, 31cc may be connected.

In addition, as shown in FIG. 5G, the insulation between the TiN layer 18a and the TiN layer 26a is achieved by the SiO ₂ layer 23 covering the TiN layer 18a and the HfO ₂ layer 17b of the gate insulating layer. On the other hand, the insulation between the TiN layer 18a and the TiN layer 26a may be formed only by the HfO ₂ layer 17b.

This implementation type provides the following features.

(Feature 1)

In the dynamic flash memory cell of this embodiment, the N ⁺ layers 3a and 3b serving as the source and drain, the channel region 7, the first gate insulating layer 4a, the second gate insulating layer 4b, the first gate conductor layer 5a, and the second gate conductor layer 5b are all formed in a columnar shape. In addition, the N ⁺ layer 3a that becomes the source is connected to the source line SL, the N ⁺ layer 3b that becomes the drain is connected to the bit line BL, the first gate conductor layer 5a is connected to the metal plate line PL, and the second gate conductor layer 5b is connected to the word line WL. The dynamic flash memory cell has a structure in which the gate capacitance of the first gate conductor layer 5a connected to the metal plate line PL is greater than the gate capacitance of the second gate conductor layer 5b connected to the word line WL. In the dynamic flash memory unit, the first gate conductor layer and the second gate conductor layer are stacked vertically. Therefore, even if the gate capacitance of the first gate conductor layer 5a connected to the metal plate line PL is greater than the gate capacitance of the second gate conductor layer 5b connected to the word line WL, the area of the memory cell does not increase when viewed from above. In this way, high performance and high density of the dynamic flash memory unit can be realized at the same time.

(Feature 2)

When paying attention to the first gate conductor layer 5a connected to the metal plate line PL of the dynamic flash memory unit of the first embodiment of the present invention, it can be seen that there are five functions of the following (1) to (5).

(1) When a dynamic flash memory cell performs writing and reading operations, the voltage of the word line WL will oscillate up and down. At this time, the metal plate line PL is responsible for reducing the capacitive coupling ratio between the word line WL and the channel region 7 . As a result, the voltage oscillation of the word line WL can be significantly suppressed The influence of the voltage change of the channel region 7 during the occasion. Thereby, the threshold voltage difference of the SGT transistor of the word line WL displaying logic "0" and "1" can be increased. This results in an enlargement of the operating differential margin of the dynamic flash memory cell.

(2) When the dynamic flash memory cell performs erasing, writing, and reading operations, the first gate conductor layer 5a connected to the metal plate line PL and the second gate conductor layer 5b connected to the word line WL function as the gate of the SGT transistor. When the current flows from the bit line BL to the source line SL, the short channel effect (Short Channel Effect) of the SGT transistor can be suppressed. In this way, the short channel effect can be suppressed by the first gate conductor layer 5 a connected to the metal plate line PL. Thereby, improvement of the data retention characteristic can be aimed at.

(3) When the writing operation of the dynamic flash memory unit starts, the hole group gradually accumulates in the channel region 7, and the threshold voltage of the first MOS transistor with the metal plate line PL and the second MOS transistor with the word line WL decreases. At this time, since the threshold voltage of the first MOS transistor having the metal plate line PL is lowered, the shock dissociation phenomenon during the write operation will be promoted. Thereby, the metal plate line PL can generate a positive feedback action during writing, and speed-up of the writing operation can be achieved.

(4) In the dynamic flash memory cell in which "1" has been written, the threshold voltage of the first MOS transistor having the metal plate line PL is lowered. As a result, when a positive bias is applied to the metal plate line PL, an inversion layer is always formed on the inner periphery of the first gate conductor layer 5a connected to the metal plate line PL. As a result, the electron layer staying in the inversion layer formed on the inner periphery of the first gate conductor layer 5a connected to the metal plate line PL becomes a conductor wave barrier layer. In this way, the disturbance noise from the surroundings of the dynamic flash memory cells that have been written with “1” can be shielded.

(5) During the writing operation of the dynamic flash memory cell, photons are generated due to the impact ionization phenomenon. The generated photons are repeatedly reflected by the first gate conductor layer 5a and the second gate conductor layer 5b, And move toward the vertical direction of the Si column 2 . At this time, the metal plate line PL has a light-shielding effect on photons, so that the photons generated during writing will not destroy the data of the adjacent memory cells in the horizontal direction.

(feature three)

As shown in Figure 5D and Figure 5E, by making the length L1 between the intersection of the outer perimeter of the HfO layer ₁₇ surrounding the Si columns 12a, 12b and the XX' line less than twice the width L3 of the SiN layer 21a, 21b on the YY' line, and making the length L2 between the intersection of the outer perimeter of the HfO _layer 17 surrounding the Si columns 12a, 12c and the YY' line greater than twice L3, Si The N layer 21a is connected between the Si pillars 12a and 12b and is formed separately between the Si pillars 12a and 12c. Similarly, the SiN layer 21b can be connected between the Si pillars 12c and 12d and can be formed separately between the Si pillars 12a and 12c. SiN layers 21a, 21b are formed in self-alignment with respect to Si pillars 12a to 12d. Therefore, the metal plate lines PL formed using the SiN layers 21a, 21b as etching masks and the TiN layers 18a, 18b which are gate conductor layers are formed in self-alignment with respect to the Si pillars 12a to 12d. By forming the TiN layers 18a and 18b by self-alignment in this way, high densification of the dynamic flash memory can be achieved. Furthermore, when forming the TiN layers 18a and 18b, since a mask pattern in the lithography step is unnecessary, the cost of the mask used can be reduced.

(feature four)

As shown in FIG. 5G , the TiN layer 26a belonging to the word line WL and being the gate conductor layer is formed to be connected between the Si pillars 12a, 12b by being separated from the TiN layer 26b and self-aligned with respect to the Si pillars 12a, 12b. Likewise, the TiN layer 26b is formed in connection between the Si pillars 12c, 12d by being separated from the TiN layer 26a and self-aligned with respect to the Si pillars 12c, 12d. Thereby, high densification of the dynamic flash memory can be achieved. Furthermore, the formation of the TiN layers 26a, 26b does not require a mask pattern in the lithography step similarly to the formation of the TiN layers 18a, 18b, so the mask pattern used can be optimized. low cost. Furthermore, TiN layers 26a, 26b which are gate conductor layers belonging to word line WL overlap TiN layers 18a, 18b which are gate conductor layers belonging to metal plate line PL in plan view. Thereby, high densification of the dynamic flash memory can be achieved.

The manufacturing method of the dynamic flash memory of the second embodiment is shown using FIG. 6A to FIG. 6C. (a) is a top view, (b) is a sectional view along the line X-X' of (a), and (c) is a sectional view along the line Y-Y' of (a).

The steps shown in FIGS. 5A to 5C are performed. Next, as shown in FIG. 6A, the HfO ₂ layer 17 that is higher than the upper surface of the TiN layer 18 in the vertical direction is removed to form an HfO ₂ layer 17a. Furthermore, the HfO ₂ layer 33 is formed on the whole. Furthermore, the whole is covered with a TiN layer (not shown), and the upper surface thereof is polished by CMP until it becomes the upper surface of the mask material layers 14a to 14d. Furthermore, the TiN layer 34 is formed by etching up to the position of the upper surface to the vicinity of the lower ends of the N ⁺ layers 13a to 13d by the RIE method.

Next, as shown in FIG. 6B , the entire surface is covered with a silicon nitride (SiN layer) layer (not shown), and polished by CMP until the upper surface positions become the upper surface positions of the mask material layers 14a to 14d. Furthermore, by etching the SiN layer by the RIE method, SiN layers 36a, 36b connected between Si pillars 12a, 12b and Si pillars 12c, 12d and separated between Si pillars 12a, 12c and Si pillars 12b, 12d are formed on the side surfaces of N ⁺ layers 13a to 13d and mask material layers 14a to 14d.

Next, as shown in FIG. 6C, using the SiN layers 36a, 36b and the mask material layers 14a to 14d as masks, the TiN layer 34, the HfO layer 33, and the TiN layer 18 are etched to form TiN layers 18c, 18d, _34a , 34b, and _HfO layers 33a, 33b. Thereafter, the same steps as those in FIG. 5H and FIG. 5I are performed. Thereby, a dynamic flash memory is formed on the substrate 10 similarly to the first embodiment.

This implementation type provides the following features.

The manufacturing method of the dynamic flash memory shown in FIG. 5 is to respectively form the TiN layers 18a, 18b belonging to the metal plate line PL and being the gate conductor layer and the TiN layers 26a, 26b belonging to the word line WL and being the gate conductor layer. In contrast, in this embodiment, as shown in FIG. 6C , the TiN layer 34 , the HfO _layer 33 , and the TiN layer 18 are etched together using the SiN layers 36 a, 36 b and the mask material layers 14 a to 14 d as masks to form the TiN layers 18 c and 18 d belonging to the metal plate line PL and being the gate conductor layer and the TiN layers 34 a and 34 b belonging to the word line WL and being the gate conductor layer. Thereby, it is easy to manufacture the dynamic flash memory.

(other implementation types)

In addition, in the present invention, the Si columns 2, 12a to 12d are formed, but semiconductor columns formed of other semiconductor materials may also be used. The same applies to other embodiments of the present invention.

In addition, the N ⁺ layers 3 a , 3 b , 11 , and 13 in the first embodiment can also be formed of Si or other semiconductor material layers containing donor impurities. In addition, the N ⁺ layers 3a, 3b, 11, 13 can also be formed of different semiconductor material layers. In addition, these forming methods can form the N ⁺ layer by epitaxial crystal growth method or other methods. The same applies to other embodiments of the present invention.

In addition, if the mask material layers 14a to 14d _shown in FIG. 5A are materials that meet the purpose of the present invention such as _SiO2 layer, aluminum oxide ( _Al2O3 , also known as AlO) layer, SiN layer, etc., other materials including organic materials or inorganic materials composed of single or multiple layers can also be used. The same applies to other embodiments of the present invention.

In addition, the thickness and shape of the mask material layers 14a to 14d shown in FIG. 5A are changed according to polishing by CMP method, etching and cleaning by RIE method. This change is not limited as long as it meets the purpose of the present invention. The same applies to other embodiments of the present invention.

In addition, in the first embodiment, the TiN layers 18a and 18b are used as the metal plate line PL and the gate conductor layer 5a connected to the metal plate line PL. On the other hand, instead of the TiN layers 18a and 18b, a single layer or a plurality of conductive material layers may be used in combination. Similarly, in the first embodiment, the TiN layers 26a and 26b are used as the word line WL and the gate conductor layer 5b connected to the word line WL. On the other hand, instead of the TiN layers 18a and 18b, a single layer or a plurality of conductive material layers may be used in combination. The same applies to other embodiments of the present invention.

In addition, SiN layers 21a, 21b, _SiO2 layers 20a, 20b shown in FIG. 5D and SiN layers 27a, 27b shown in FIG. 5G are used to form etching mask layers for TiN layers 18a, 18b, 26a, 26b. The SiN layers 21a, 21b, 27a, 27b and the SiO ₂ layers 20a, 20b can also use single or multiple layers of other material layers if they can achieve the function of the etching mask in this embodiment. The same applies to other embodiments of the present invention.

In addition, in the second embodiment, the _HfO2 layers 17a, 33 used as gate insulating layers are formed to surround the Si pillars 12a to 12d as the gate insulating layers, but other material layers composed of a single layer or a plurality of layers can also be used. The same applies to other embodiments of the present invention.

In addition, in the first embodiment, the shape of the Si pillars 12a to 12d is circular when viewed from above. However, the shape of the Si pillars 12a to 12d in plan view may be circular, elliptical, or elongated in one direction. Furthermore, even with the area separate from the dynamic flash memory cell In the logic circuit region formed separately, Si pillars having different shapes when viewed from above may be mixedly formed on the logic circuit region according to the logic circuit design. The same applies to other embodiments of the present invention.

In addition, in FIG. 1 , the first gate conductor layer 5 a can be divided into two or more conductor electrodes as metal plate wires, which can be operated synchronously or asynchronously with the same driving voltage or different driving voltages. Similarly, the second gate conductor layer 5b can be divided into two or more conductor electrodes, which are used as the conductor electrodes of the word lines, respectively, and operate synchronously or asynchronously with the same driving voltage or different driving voltages. Even so, dynamic flash memory will work. At this time, in FIG. 5D and FIG. 5E, by etching the TiN layer 18, the TiN layer 18 surrounding the SiN layers 21a, 21b is divided into two TiN layers along the Y-Y' line direction in a plan view, and the TiN layer 18 surrounding the SiN layers 21c, 21d is divided into two TiN layers along the Y-Y' line direction. In this case, the SiN layers 21a, 21b and the SiN layers 21c, 21d may be formed by connecting TiN layers in plan view. Similarly, in FIG. 5G, each of TiN layer 26a, 26b may be divided and formed. The same applies to other embodiments of the present invention.

In addition, in the first embodiment, the source line SL is negatively biased during the erasing operation, thereby removing the hole group in the channel region 7 belonging to the floating body FB. However, the bit line BL can also be set to a negative bias instead of the source line SL, or both the source line SL and the bit line BL can be set to a negative bias to perform the erasing operation. The same applies to other embodiments of the present invention.

In addition, in the operation described using FIG. 2 , FIG. 3 , and FIG. 4 , a fixed voltage of, for example, 2 V may be applied to the voltage V _ErasePL of the metal plate line PL regardless of each operation mode. In addition, the voltage V _ErasePL of the metal plate line PL can be applied, eg, 0 V, only during erasing.

Various implementation forms and changes can be made to the present invention without departing from the broad spirit and scope of the present invention. In addition, the above-mentioned implementation forms are used to illustrate an embodiment of the present invention, and are not intended to limit the scope of the present invention. The above-described embodiments and modifications can be combined arbitrarily. In addition, even if a part of the constituent requirements of the said embodiment is excluded as needed, it is also included in the scope of the technical idea of this invention.

[industrial availability]

According to the manufacturing method of the memory device using SGT of the present invention, the dynamic flash memory of the memory device using the high-density and high-performance SGT can be obtained.

10: Substrate

11a, 13a, 13b, 13c: N ⁺ layers

12a, 12b, 12c: Si column

17a, 17b, 33: HfO ₂ layers

18a, 18b, 26a, 26b: TiN layer

23,29: SiO ₂ layers

27a, 27b: SiN layer

30a, 30b, 30c, 30d: contact holes

31a: conductor layer of bit line BL1

31b: conductor layer of bit line BL2

34a, 34b, 34c: empty hole

BL1: bit line

BL2: bit line

PL1: Metal plate line

PL2: Metal plate line

SL: source line

WL1: word line

WL2: word line

Claims (10)

A manufacturing method of a memory device including a columnar semiconductor element, the memory device is performed: a data holding operation is to control the voltage applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region and the second impurity region, and the hole group formed by the impact free phenomenon or the drain leakage current caused by the gate is kept in any or each of the first semiconductor pillar, the second semiconductor pillar, the third semiconductor pillar and the fourth semiconductor pillar; and the data erasing operation is controlled for the first gate. The electrode conductor layer, the aforementioned second gate conductor layer, the aforementioned third gate conductor layer, the aforementioned fourth gate conductor layer, the aforementioned first impurity region, and the aforementioned second impurity region apply a voltage to remove the hole group from any or each of the aforementioned first to fourth semiconductor columns; the aforementioned manufacturing method has the following steps: forming the aforementioned first semiconductor column and the aforementioned second semiconductor column, the aforementioned third semiconductor column and the aforementioned fourth semiconductor column on a substrate, wherein the aforementioned first semiconductor column and the second semiconductor column stand in the vertical direction, and are adjacently grounded in the first direction when viewed from above Configuration, the third semiconductor column and the fourth semiconductor column are adjacently arranged in the second direction parallel to the first direction; the step of forming the first insulating layer surrounding the first semiconductor column to the fourth semiconductor column; the step of forming the first gate conductor layer and the second gate conductor layer, the first gate conductor layer surrounds the first insulating layer, and in the vertical direction, its upper surface is located below the first semiconductor column to the fourth semiconductor column, and is connected between the first semiconductor column and the second semiconductor column in the first direction. The aforementioned third semiconductor column in the aforementioned second direction is connected to the aforementioned fourth semiconductor column; Etching the aforementioned first gate conductor layer in the vertical direction and the aforementioned first insulating layer above the aforementioned second gate conductor layer, and forming a first gate insulating layer at the bottom of the aforementioned first to fourth semiconductor pillars; a step of forming a second gate insulating layer in a vertical direction in contact with the aforementioned first gate insulating layer and surrounding the side surfaces of the first to fourth semiconductor pillars; forming the aforementioned third gate conductor layer and the aforementioned fourth gate conductor layer, wherein the aforementioned third gate conductor layer surrounds the aforementioned second gate insulating layer, And in the vertical direction, its upper surface position is located below the tops of the first to fourth semiconductor columns, and is connected between the first semiconductor column and the second semiconductor column in the first direction, and is separated from the first gate conductor layer in the vertical direction, and the fourth gate conductor layer is connected between the third semiconductor column and the fourth semiconductor column arranged in the second direction, and is separated from the second gate conductor layer in the vertical direction; The step of forming the first impurity region connected to the bottom of the fourth semiconductor pillar; the step of forming the second impurity region on each of the tops of the first to fourth semiconductor pillars before or after forming the first to fourth semiconductor pillars; and the step of forming a first wiring conductor layer and a second wiring conductor layer. The manufacturing method of a memory device comprising a columnar semiconductor element as described in Claim 1, wherein, when viewed from above, the two outer peripheral lines of the first gate insulating layer surrounding the first semiconductor column and the second semiconductor column and the two peripheral lines connecting the first semiconductor column and the second The first length between two opposite points of the intersection of the first line at the center of the semiconductor pillar is smaller than the second length between the two opposite points of the intersection of the second line connecting the center of the first semiconductor pillar and the center of the third semiconductor pillar. times smaller. The method for manufacturing a memory device comprising a columnar semiconductor element as described in Claim 2 comprises the following steps: after forming the first gate insulating layer, forming a first conductor layer whose upper surface is positioned vertically on the upper end of the first gate conductor layer and the second gate conductor layer on the outer periphery of the first gate insulating layer; Surrounding the sides of the first to fourth semiconductor pillars, and connecting between the first semiconductor pillar and the second semiconductor pillar, the third mask material layer is connected between the third semiconductor pillar and the fourth semiconductor pillar, and separated from the second mask material layer; and using the first mask material layer, the second mask material layer and the third mask material layer as masks, etching the first conductor layer to form the first gate conductor layer and the second gate conductor layer. The method for manufacturing a memory device comprising a columnar semiconductor element as described in Claim 2 comprises the following steps: After forming the second gate insulating layer, forming a second conductor layer whose upper surface is vertically located near the lower end of the second impurity region on the outer periphery of the second gate insulating layer; forming a first mask material layer, a fourth mask material layer, and a fifth mask material layer in a manner separated from each other, the first mask material layer is on the second conductor layer and is located on the top of the first to fourth semiconductor pillars, the fourth mask material layer surrounds the sides of the first to fourth semiconductor pillars, and is formed between the first semiconductor pillars and the first semiconductor pillars. The second semiconductor pillars are connected, the fifth mask material layer is connected between the third semiconductor pillar and the fourth semiconductor pillar; and using the first mask material layer, the fourth mask material layer and the fifth mask material layer as masks, etching the second conductor layer to form the third gate conductor layer and the fourth gate conductor layer. The method for manufacturing a memory device comprising a columnar semiconductor element as described in Claim 2 comprises the following steps: for the aforementioned first to fourth semiconductor columns with a first mask material layer formed on the top, after forming the first gate insulating layer, forming a third conductor layer whose upper surface is located near the middle of the first to fourth semiconductor columns in the vertical direction on the outer periphery of the aforementioned first gate insulating layer; removing the aforementioned first gate insulating layer above the third conductor layer, and forming a second insulating layer on the aforementioned third conductor layer; A step of forming a fourth conductor layer whose upper surface is close to the lower end of the second impurity region in the vertical direction on the second insulating layer; a step of forming a sixth mask material layer and a seventh mask material layer in a manner separated from each other, the sixth mask material layer is formed to surround the first and second semiconductor layers on the fourth conductor layer The side surface of the conductor column is connected between the first semiconductor column and the second semiconductor column, the seventh mask material layer is formed to surround the sides of the third and fourth semiconductor columns on the fourth conductor layer, and is connected between the third semiconductor column and the fourth semiconductor column; and using the first mask material layer, the sixth mask material layer and the seventh mask material layer as masks, the third conductor layer, the second insulating layer and the fourth conductor layer are etched to form the first gate conductor layer, the second gate conductor layer, the aforementioned first gate conductor layer, the aforementioned second gate conductor layer, Steps of the third gate conductor layer and the aforementioned fourth gate conductor layer. The method for manufacturing a memory device including a columnar semiconductor element as described in Claim 1, wherein the wiring connected to the first impurity region is a source line, the wiring connected to the second impurity region is a bit line, and if one of the wiring connecting the first gate conductor layer and the second gate conductor layer, and the wiring connecting the third gate conductor layer and the fourth gate conductor layer is a word line, the other is a first drive control line; The voltage applied to the word line selectively performs the data erasing operation and the recording data retention operation. The method of manufacturing a memory device comprising a columnar semiconductor element as described in claim 1, wherein the first gate capacitance between the first gate conductor layer and the first to fourth semiconductor pillars is formed to be larger than the second gate capacitance between the second gate conductor layer and the first to fourth semiconductor pillars. The method of manufacturing a memory device including a columnar semiconductor element as claimed in Claim 1, wherein, when viewed from above, a first hole is formed between the third gate conductor layer and the fourth gate conductor layer. The method of manufacturing a memory device including a columnar semiconductor element according to claim 1, wherein a second hole is formed between the first wiring conductor layer and the second wiring conductor layer. The method for manufacturing a memory device including a columnar semiconductor element as claimed in claim 5, wherein the second insulating layer is formed by the second gate insulating layer connected to the first to fourth semiconductor columns.

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