TWI805691B - Etch stop layer-based approaches for conductive via fabrication and structures resulting therefrom - Google Patents

Abstract

Etch stop layer-based approaches for via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer, wherein each of the plurality of conductive lines has a bulk portion including a metal and has an uppermost surface including the metal and a non-metal. A hardmask layer is on the plurality of conductive lines and on an uppermost surface of the ILD layer, and includes a first hardmask component on and aligned with the uppermost surface of the plurality of conductive lines, and a second hardmask component on and aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of one of the plurality of conductive lines, the portion having a composition different than the uppermost surface including the metal and the non-metal.

Description

Etch stop layer based approach for conductive via fabrication and resulting structures

Embodiments of the present invention are in the field of semiconductor structures and processing, and in particular, etch stop layer based approaches for conductive via fabrication, and resulting structures.

The scaling of features in integrated circuits has been the driving force behind the growing semiconductor industry for the past few decades. Scaling to smaller and smaller features enables an increased density of functional units on the limited surface of a semiconductor wafer. For example, shrinking the size of transistors allows an increased number of memory or logic devices to be combined on a chip, resulting in the manufacture of products of increased capacity. However, the desire for more and more capacity is not without problems. The need to optimize the performance of each device is becoming more and more important.

Integrated circuits typically include conductive microelectronic structures, known in the art as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias are usually formed by a lithographic process. Typically, a photoresist layer can be spin-coated over the dielectric layer, the photoresist layer can be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer can be developed to form Openings are in the photoresist layer. Next, openings for vias can be etched in the dielectric layer by using the openings in the photoresist layer as etch masks. This opening is called a via opening. Finally, the via opening may be filled with one or more metals or other conductive materials to form the via.

The size and spacing of vias have been significantly reduced in the past, and are expected to continue to decrease significantly in the future, for at least some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.). One measure of the size of a via is the critical dimension of the via opening. One measure of spacing between vias is via pitch. Via pitch represents the center-to-center distance between the nearest adjacent vias.

There are several challenges inherent in patterning very small vias at very small pitches by such lithographic processes, especially when the pitch is on the order of 70-90 nanometers (nm) or smaller and/or When the critical dimension of the via opening is about 35 nm or less. One of these challenges is that the overlap between the via and the interconnect above, and the overlap between the via and the interconnect positioned below typically need to be controlled to a high tolerance on the order of a quarter of the via pitch. As via pitch scales get smaller, overlap tolerances tend to shrink at a faster rate than their lithography tools can keep up.

Another of these challenges is that the critical dimensions of via openings generally tend to shrink faster than the resolution capabilities of lithographic scanners. There are shrinking techniques to shrink the critical dimensions of via openings. However, the amount of scaling is often limited by the minimum via pitch, and the ability to shrink the process sufficiently free from optical proximity correction (OPC) without significantly compromising line width roughness (LWR) and/or critical Dimensional Uniformity (CDU).

Yet another of these challenges is that the LWR and/or CDU characteristics of the photoresist typically need to be improved as the CD of the via opening decreases to maintain the same overall fraction of the CD budget. However, the LWR and/or CDU characteristics of most current photoresists have not improved as rapidly as the CD reduction of via openings.

A further such challenge is that very small via pitches generally tend to be below the resolution capabilities of even extreme ultraviolet (EUV) lithography scanners. As a result, often several different lithography masks can be used, which tends to increase cost. At some point, if the pitch continues to decrease, it may not be possible (even with multiple masks) to print these very small pitch via openings using an EUV scanner.

Therefore, there is a need to improve the field of back-end metallization fabrication techniques for fabricating metal vias.

and

Description: Etch stop layer based approach for conductive via fabrication and resulting structures. In the following description, numerous specific details are set forth, such as specific integration and states of materials, in order to provide a thorough understanding of embodiments of the invention. It will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other instances, well-known features, such as IC layouts, have not been described in detail so as not to unnecessarily obscure embodiments of the invention. Furthermore, it should be understood that the various embodiments shown in the figures thereof are illustrative representations and are not necessarily drawn to scale.

Certain terms may also be used in the following description for reference purposes only and thus are not intended to be limiting. For example, terms such as "higher," "lower," "above," and "below" refer to directions in the figure to which the reference applies. Terms such as "front", "rear", "rear", and "side" describe the orientation and/or position of a portion of a component within a constant (but arbitrary) frame of reference by which the component in question is described The text and related graphics become clear. This term may include the words explicitly mentioned above, derivatives thereof, and words of similar import.

One or more embodiments described herein relate to methods of using etch stop layers for directed self-polymerization (DSA) or selective growth to enable fabrication of self-aligned interconnects. Embodiments may address or implement one or more of etch stop layers, directed self-polymerization, selective deposition, self-alignment, or the use of fine-pitch patterned interconnects. Embodiments may be implemented to provide improved via short tolerance by utilizing "colored" self-alignment through selective deposition, followed by directed self-polymerization (e.g., for 10nm and smaller technology nodes) . In one embodiment, an etch stop layer is implemented for pattern replication based via self-alignment.

According to one or more embodiments of the present invention, an etch stop layer is implemented for multicolor integration. To provide context, color schemes for common interconnect metals such as Co, Co alloys, Ni, Ni alloys, and Cu and Cu alloys can suffer from severe metal corrosion during dry etching, especially if the color material is based on In the case of metal oxides (eg, HfOx, ZrOx). Corrosion during dry etching may be due to the oxidizing nature of the etch gas BCl ₃ and/or Cl based by-products or fluorine containing etch gas. Pretreatment of interconnect metal can be used to inhibit or stop etch attack altogether, but with resulting high via resistance values. Embodiments of the present invention may rely on specific surface treatments, which modify the metal surface so that corrosion is inhibited. The etch resistant surface is then modified or removed upon completion or performance of via metallization, which provides a post metallized interconnect stack with corrosion resistance during etch and low via resistance values.

In certain embodiments, the interconnect metal is disposed prior to metal oxide hard mask deposition to enhance corrosion resistance. Treatment may include oxidation and/or silane/ _NH3 treatment to form metal silicide, metal silicide/nitride. Metals have adequate corrosion resistance during metal oxide etching. Pre-processing layers are removed (eg metal oxide reduction, metal/silicide/nitride through etch) before vias are placed. The result is the ability to provide corrosion resistance during etch and low via resistance post-metallization (eg, in the locations where the vias sit).

To provide further background, etch stop caps for conductive interconnects, such as high quality oxides, metal silicides, metal germanides, or metal borides, are formed on the conductive interconnects prior to metal oxide deposition. The metal surface can be treated with an ammonia plasma to fix silicon and/or germanium and/or boron to the surface and form a self-separating etch stop. Once the via opening is placed, the handling layer is removed (eg, regular etch through etch, reduction in the case of oxide, physical sputtering, etc.). In one embodiment, the resulting structure includes very unique features in which the interconnect material includes a unique pre-processing layer everywhere except where the vias are located (ie, where the via resistance values need to be low in the location). In another aspect, embodiments may include the fabrication of a bilayer of metal oxide and an etch stop layer (eg, silicon oxide, nitride, etc.). The bilayer system acts as an etch stop layer during metal oxide etch removal and can be selectively removed during via placement.

More generally, one or more embodiments relate to a method for fabricating metal lines and associated conductive vias. Conductive vias or vias (as defined) are used to land on the previous metal pattern. In this way, the embodiments described herein enable a more robust interconnect fabrication scheme because constraints on lithographic equipment are relaxed. This interconnect fabrication scheme can be used to save many alignments/exposures, and can be used to reduce overall process operations and processing time, compared to that required using conventional means to pattern such features. Other advantages may include improved yield, or protection from shorts to miswires.

In a first example approach based on the use of the same type of conductive lines and etch stop layers, FIGS. 1A-1F illustrate cross-sectional views of portions of integrated circuit layers representing a process involving interconnects for back-end-of-line (BEOL) The various operations in the method of fabricating the etch stop layer and forming the self-aligned conductive via are according to the embodiments of the present invention.

Referring to FIG. 1A , a starting structure 100 is provided as a starting point for fabricating a new metallization layer. The starting structure 100 includes an interlayer dielectric (ILD) layer 104 disposed on a substrate 102 . As described below, the ILD layer may be disposed over an underlying metallization layer formed over the substrate 102 . Trenches are formed in ILD layer 104 and filled with a conductive layer (or layers) to provide conductive lines 106 (and, in some cases, corresponding conductive vias 108 ). In one embodiment, trenches for conductive lines 106 are formed in ILD layer 104 using a pitch division patterning process flow. Non-limiting examples of such pitch division schemes are described in more detail below in association with FIGS. 5A , 5B, and 6 . It should be understood that the following process operations described below may or may not involve pitch division first. In either case, but especially when pitch division is also used, embodiments may enable continuous scaling of the pitch of the metal layer beyond the resolving capabilities of state-of-the-art lithography equipment. In one embodiment, the conductive line 106 includes a copper fill material in a titanium nitride or tantalum nitride barrier liner. In another embodiment, Co (or an alloy of Co, such as CoWB) is used. In one embodiment, at least a portion of the conductive line 106 (eg, copper fill) is formed using an electroplating process.

Referring to FIG. 1B , the conductive line 106 has a bulk portion comprising a metallic species (or metal). In one embodiment, the metal is selected from the group consisting of cobalt, copper, tungsten and nickel. The conductive wire is processed to form a modified conductive wire 110 having an uppermost surface 114 . The uppermost surface 114 includes metal and non-metal species (or non-metal). In one embodiment, treating the plurality of conductive lines 106 includes exposing the plurality of conductive lines 106 to sources of ammonia and non-metals. In one embodiment, the non-metal is selected from the group consisting of oxygen, silicon, germanium and boron. It should be understood that in addition to protecting the metal of modified conductive lines 110 during subsequent processing steps, uppermost surface 114 may also assist in the selective deposition of hard mask materials, particularly "color" hard mask materials.

Referring to FIG. 1C, a hard mask layer 116 is formed over the structure of FIG. 1B. The hard mask layer 116 includes a first hard mask component 118 and a second hard mask component 120 . A first hard mask element is formed on and aligned with the uppermost surface 114 of the conductive lines 110 . A second hard mask feature 120 is formed on and aligned with the exposed surface of the ILD layer 104 . In one embodiment, the hard mask layer 116 having the first hard mask element 118 and the second hard mask element 120 is formed using directed self-polymerization or selective deposition to finally form the first hard mask Two distinct, alternating regions of the mask element 118 and the second hard mask element 120 . In one such embodiment, the directed self-polymerization or selective deposition approach is enhanced by using the uppermost surface 114 (different from the surface using the conductive lines 110). In one embodiment, the materials of the first hard mask element 118 and the second hard mask element 120 exhibit different etch selectivities from each other. As described in more detail below, directed self-polymerization or selective growth may be used to selectively individually align the first hard mask component 118 and the second hard mask component 120 to the dielectric and metal surfaces.

In the first general embodiment, to finally form the first hard mask feature 118 and the second hard mask feature 120, a directed self polymerization (DSA) block copolymer deposition and polymer polymerization process is performed. In one embodiment, a DSA block copolymer is coated on the surface and annealed to separate the polymer into a first block and a second block. In one embodiment, the first polymer block preferentially adheres to the exposed surface of the ILD layer 104 . The second polymer block is adhered to the uppermost surface 114 of the conductive line 110 .

In one embodiment, block copolymer molecules are polymer molecules formed by covalently joining chains of monomers. In a dual block copolymer, there are two different types of monomers, and these different types of monomers are predominantly included in two different blocks or adjacent sequences of monomers. The block copolymer molecules shown include blocks of the first polymer and blocks of the second polymer. In one embodiment, the blocks of the first polymer consist essentially of chains of covalently linked monomers A (e.g., A-A-A-A-A...), while the blocks of the second polymer consist essentially of covalently linked monomers A chain of body B (eg, B-B-B-B-B...). Monomers A and B may represent any of the different types of monomers used in block copolymers known in the art. For example, monomer A can represent a monomer used to form polystyrene, and monomer B can represent a monomer used to form polymethylmethacrylate (PMMA), or vice versa, although the present invention The scope is not so limited. In other embodiments, there may be more than two blocks. Furthermore, in other embodiments, each of the blocks may comprise a different type of monomer (eg, each block itself may be a copolymer). In one embodiment, the blocks of the first polymer and the blocks of the second polymer are covalently bonded together. The blocks of the first polymer and the blocks of the second polymer may be about the same length, or one block may be significantly longer than the other.

In one embodiment, phase separation of block copolymers is implemented as described in more detail below. In one such embodiment, DSA brushes (such as small polystyrene or PMMA fragments of controlled molecular weight with thiol or nitrile or OH end groups) are first formed on the surface to facilitate this phase separation. In certain such embodiments, such a brush layer is covalently adhered to the metal or ILD surface and then directs the block copolymer to polymerize over the metal and ILD grating.

In general, blocks of block copolymers (eg, blocks of a first polymer and blocks of a second polymer) can each have different chemical properties. For example, one of the blocks may be relatively hydrophobic (eg, water-repelling) while the other may be relatively hydrophilic (water-absorbing). At least conceptually, one of the zones may be relatively more like oil while the other may be relatively more like water. Such differences in chemical properties between different block polymers (whether hydrophilic-hydrophobic differences or otherwise) may cause the block copolymer molecules to self-polymerize. For example, self-polymerization can be based on microphase separation of polymer blocks. Conceptually, this can be analogous to the phase separation of oil and water which are usually immiscible. Similarly, differences in hydrophilicity between polymer blocks (e.g., one block is relatively hydrophobic and another block is relatively hydrophilic) may cause similar microphase separations, where different polymer regions Blocks try to "separate" from each other because they don't like each other chemically.

However, in one embodiment, since the polymer blocks are covalently bonded to each other, they cannot be completely separated on the macroscopic scale. Conversely, polymer blocks of a given type tend to separate or aggregate from polymer blocks of other molecules of the same type in very small (eg, nano-sized) regions or phases. The particular size and shape of the domains or microphases typically depends at least in part on the relative lengths of the polymer blocks. In one embodiment, for example, in a two-block copolymer, if the blocks are approximately the same length, a grid-like pattern of alternating first and second polymer lines results.

In one embodiment, the first polymer/second polymer grating is first applied as an unpolymerized segmental copolymer layer portion comprising, for example, segments applied by brushing or other coating process Copolymer material. Unpolymerized morphology refers to one in which (at the moment of deposition) the block copolymer has not yet substantially phase separated and/or self-polymerized to form nanostructures. In this unpolymerized form, the block polymer molecules are quite highly randomized, having a relatively high degree of random orientation and positioning. The unpolymerized block copolymer layer portion can be applied in a number of different ways. For example, block copolymers can be dissolved in a solvent and then spin-coated onto the surface. Alternatively, the unpolymerized block copolymer may be sprayed, dipped, dipped, or otherwise coated or applied onto the surface. Other means of applying block copolymers, and other means known in the art for applying similar organic coatings, could potentially be used. The unpolymerized layer may then form the polymerized block copolymer layer portion, for example, by microphase separation and/or self-polymerization of the unpolymerized block copolymer layer portion. Microphase separation and/or self-polymerization occurs through the reconfiguration and/or reorientation of the block copolymer molecules, and in particular the reconfiguration and/or reorientation of the different polymer blocks of the block copolymer molecules.

In such an embodiment, an annealing treatment may be applied to the unpolymerized block copolymer to initiate, accelerate, increase, or enhance the quality of microphase separation and/or self-polymerization. In certain embodiments, the annealing treatment can include a treatment operable to increase the temperature of the block copolymer. An example of such a treatment is baking the layer, heating the layer in an oven or over a heat lamp, applying infrared radiation to the layer, or applying heat to or increasing the temperature of the layer. The desired temperature increase will generally be sufficient to significantly accelerate the rate of microphase separation and/or self-polymerization of the block polymer without damaging the block copolymer or any other important material or structure of the integrated circuit substrate. Typically, the heating range may be from about 50°C to about 300°C, or from about 75°C to about 250°C, without exceeding the thermal degradation limits of the block copolymer or integrated circuit substrate. Heating or annealing can help provide energy to the block copolymer molecules to make them more mobile/elastic to increase the rate and/or improve the quality of microphase separation. This microphase separation or reconfiguration/repositioning of the block copolymer molecules can lead to self-polymerization to form extremely small (eg, nanoscale) structures. Self-polymerization can occur under the influence of surface energy, molecular affinity, and other surface-related and chemically-related forces.

In any event, in certain embodiments, self-polymerization of block copolymers (whether based on hydrophobic-hydrophilic differences or not) can be used to form extremely small periodic structures (e.g., precisely spaced nanoscale structures or Wire). In some embodiments, it can be used to form nanoscale wires or other nanoscale structures.

Referring again to FIG. 1C , in the case of a DSA process, in the first embodiment, the first hard mask feature 118 and the second hard mask feature 120 are the second and first block polymers, respectively. However, in the second embodiment, the second and first block polymers are each sequentially replaced with the material of the first hard mask component 118 and the second hard mask component 120 , respectively. In one such embodiment, a selective etch and deposition process is used to replace the second and first bulk polymers with the material of the first hard mask feature 118 and the second hard mask feature 120 , respectively.

In the second general embodiment, in order to finally form the first hard mask element 118 and the second hard mask element 120, a selective growth process is used instead of the DSA method. In one such embodiment, the material of the second hard mask component 120 is grown over exposed portions of the ILD layer 104 . A second (different) material of the first hard mask element 118 is grown over the uppermost surface 114 of the conductive line 110 . In one embodiment, the selective growth is by a dep-etch-dep-etch (deposition-etch-deposition-etch) method for both the first hard mask element 118 and the second hard mask element 120 materials to achieve, resulting in multiple layers of each of the materials. Such an approach may be ideal over conventional selective growth techniques, which can form "mushroom-top" films. Mushroom top film growth propensity can be reduced by an alternating deposition/etch/deposition (dep-etch-dep-etch) approach. In another embodiment, a film is selectively deposited on the metal, followed by a different film selectively deposited on the ILD (or vice versa), and repeated several times to create a sandwich-like stack. In another embodiment, two materials are grown simultaneously in a reaction chamber (eg, by CVD-style processes), which are selectively grown on exposed regions of the underlying substrate.

As described in more detail below, in one embodiment, the resulting structure of FIG. 1C enables improved via short tolerance when later via layers are fabricated on the structure of FIG. 1C. In one embodiment, improved short circuit tolerance is achieved because fabricating the structure with alternating "color" hard mask elements reduces the risk of vias shorting to the wrong metal line. In one embodiment, self-alignment is achieved because alternating color hard mask elements are self-aligned to the underlying surface, including the uppermost surface 114 of alternating ILD layers 104 and conductive lines 110 . In certain embodiments, the first hard mask feature 118 and the second hard mask feature 120 are different materials such as, but not limited to, SiO ₂ , Al-doped SiO ₂ , SiN, SiC, SiCN, SiCON. , or metal oxides (such as AlOx, HfOx, ZrOx, TiOx).

Referring to FIG. 1D , a second interlayer dielectric (ILD) layer 122 is formed over the structure of FIG. 1C . Openings 124 are formed in the second ILD layer 122 . In one embodiment, openings 124 are formed in locations selected for conductive via fabrication of the next level of metallization. With respect to conventional via location options, the opening 124 may (in one embodiment) have a relatively relaxed width compared to the width of the corresponding conductive line 110 on which the conductive via will ultimately be formed. For example, in a particular embodiment, the width (W) of opening 124 has a dimension of approximately 3/4 the pitch of conductive lines 110 . This accommodation for relatively wider via openings 124 can relax constraints on the lithography process used to form the openings 124 . In addition, the tolerance for misalignment can also be increased.

Referring to FIG. 1E , one of the first hard mask elements 118 is selected for removal (eg, by a selective etch process) to form an opening 127 . In this case, the exposed portion of the first hard mask element 118 is removed, which is selective to the exposed portion of the second hard mask element 120 . In one embodiment, the exposed portions of the first hard mask feature 118 are removed selectively to the exposed portions of the second hard mask feature 120 using a selective dry or plasma etch process. In another embodiment, the exposed portions of the first hard mask element 118 are removed selectively to the exposed portions of the second hard mask element 120 using a selective wet etch process.

Referring again to FIG. 1E , removal of the one of the first hard mask elements 118 forms an opening in the hard mask layer 116 that exposes a portion of one of the plurality of metal lines 110 . In one embodiment, the exposed portion of the one of the plurality of metal lines 110 is modified to remove (or at least substantially remove) non-metal from the uppermost surface 114 of the exposed portion of the one of the plurality of metal lines 110 . The resulting modified exposed portions 115 associated with selected respective underlying conductive lines 110 may be referred to as chemically reduced regions having increased conductivity relative to the uppermost surface 114 . Thus, in one embodiment, modifying the exposed portion of the one of the plurality of metal lines 110 includes leaving the metal of the uppermost surface 114 (eg, as portion 115 ). In certain embodiments, an H ₂ -based plasma is used to remove non-metallic species from exposed portions of the uppermost surface 114 of the corresponding selected conductive lines 110 .

FIG. 1F illustrates the structure of FIG. 1E following fabrication of vias in the next layer. Conductive vias 128 are formed in openings 127 of FIG. 1E . The conductive via 128 is located on the modified exposed portion 115 of the one of the plurality of metal lines 110 and is (in one embodiment) electrically connected to the modified exposed portion 115 . In one embodiment, the conductive via 128 is in electrical contact with the modified exposed portion 115 without shorting to one of the adjacent or adjacent uppermost surface 114 /conductive line 110 pair. In certain embodiments, a portion of the conductive via 128 is disposed on one or more exposed portions of the second hard mask component 120, as depicted in FIG. 1F. In one embodiment, improved short circuit tolerance is achieved.

Referring again to FIG. 1F , in an exemplary illustrative embodiment, an integrated circuit structure includes a plurality of conductive lines 110 in an interlayer dielectric (ILD) layer 104 over a substrate 102 . Each of the plurality of conductive lines 110 has a bulk portion comprising metal and has an uppermost surface 114 comprising metal and non-metal. The hard mask layer 126 is located on the plurality of conductive lines 110 and on the uppermost surface of the ILD layer 104 . The hard mask layer 126 includes a first hard mask element 118 on and aligned with the uppermost surface 114 of the plurality of conductive lines 110, and a second hard mask element 120 on and aligned with a region of the uppermost surface of the ILD layer 104. . In one embodiment, the compositions of the first 118 and the second 120 hard mask elements are different from each other. Conductive vias 128 are located in openings in hard mask layer 126 and over a portion 115 of one of plurality of conductive lines 110 that has a different composition than its uppermost surface 114, which includes metals and non-metals.

In one embodiment, the non-metal is selected from the group consisting of oxygen, silicon, germanium and boron. In one embodiment, the metal is selected from the group consisting of cobalt, copper, tungsten and nickel. In one embodiment, the first hard mask feature 118 is a metal oxide selected from the group consisting of AlOx, HfOx, ZrOx and TiOx.

In one embodiment, the portion 115 of the one of the plurality of conductive lines is substantially coplanar with the uppermost surface 114 having metal and non-metal. In one embodiment, the first hard mask element 118 is confined to the uppermost surface 114 of the plurality of conductive lines 110, as shown. However, in another embodiment (not shown), the first hard mask element 118 extends onto the uppermost surface of the ILD layer 104 .

In one embodiment, the uppermost surface 114 of the plurality of conductive lines 110 has an uppermost surface that is substantially coplanar with the uppermost surface of the ILD layer 104 , as shown in FIG. 1F . In one embodiment, the first hard mask element 118 has an uppermost surface that is substantially coplanar with the uppermost surface of the second hard mask element 120 , as shown in FIG. 1F . In one embodiment, the integrated circuit structure further includes a second ILD layer 122 on the hard mask layer 126 . The conductive via 128 is further located in the opening of the second ILD layer 122 . In one such embodiment, the openings of the second ILD layer have a width approximately equal to the 3/4 pitch of the plurality of conductive lines 110 . In one embodiment, one of the plurality of conductive lines 110 is coupled to the underlying conductive via structure 108, as shown in FIG. 1F. In one such embodiment, the underlying conductive via structure 108 is connected to an underlying metallization layer of an integrated circuit structure (not shown).

In another form, FIGS. 1E'-1F' illustrate cross-sectional views of a portion of an integrated circuit layer showing another method involving etch stop layers and self-aligned conductive vias for back-end-of-line (BEOL) interconnect fabrication. Each operation in the hole forming method is according to the embodiment of the present invention.

Referring to FIG. 1E', one of the first hard mask elements 118 is selected for removal (eg, by a selective etch process) to form opening 127'. In this case, the exposed portion of the first hard mask element 118 is removed, which is selective to the exposed portion of the second hard mask element 120 . In one embodiment, the exposed portions of the first hard mask feature 118 are removed selectively to the exposed portions of the second hard mask feature 120 using a selective dry or plasma etch process. In another embodiment, the exposed portions of the first hard mask element 118 are removed selectively to the exposed portions of the second hard mask element 120 using a selective wet etch process.

Referring again to FIG. 1E', removal of the one of the first hard mask elements 118 forms an opening in the hard mask layer 116 that exposes a portion of one of the plurality of metal lines 110'. In one embodiment, the exposed portion of the one of the plurality of metal lines 110' is etched to remove the uppermost surface 114 of the exposed portion of the one of the plurality of metal lines 110'. The resulting modified recessed portion 115' is associated with the selected corresponding underlying conductive line 110'. Therefore, in one embodiment, modifying the exposed portion of the one of the plurality of metal lines 110' further includes removing the metal of the uppermost surface 114 to form the recessed portion 115' of the one of the plurality of metal lines 110'.

FIG. 1F' illustrates the structure of FIG. 1E' following fabrication of vias in the next layer. A conductive via 128' is formed in opening 127' of FIG. 1E'. The conductive via 128' is located on the recessed portion 115' of the one of the plurality of metal lines 110' and is (in one embodiment) electrically connected to the one of the plurality of conductive lines 110'. In one embodiment, the conductive via 128' electrically contacts the one of the plurality of conductive lines 110' without shorting to one of the adjacent or adjacent uppermost surface 114/conductive line 110 pairs. In certain embodiments, a portion of the conductive via 128' is disposed on one or more exposed portions of the second hard mask component 120, as depicted in FIG. 1F'. In one embodiment, improved short circuit tolerance is achieved.

Referring again to FIG. 1F', in an exemplary illustrative embodiment, an integrated circuit structure includes a plurality of conductive lines 110 in an interlayer dielectric (ILD) layer 104 over a substrate 102. Referring to FIG. Each of the plurality of conductive lines 110 has a bulk portion comprising metal and has an uppermost surface 114 comprising metal and non-metal. The hard mask layer 126 is located on the plurality of conductive lines 110 and on the uppermost surface of the ILD layer 104 . The hard mask layer 126 includes a first hard mask element 118 on and aligned with the uppermost surface 114 of the plurality of conductive lines 110, and a second hard mask element 120 on and aligned with a region of the uppermost surface of the ILD layer 104. . In one embodiment, the compositions of the first 118 and the second 120 hard mask elements are different from each other. Conductive vias 128 are located in openings of hard mask layer 126 and over recesses of plurality of conductive lines 110', for example, at location 115'.

In one embodiment, the non-metal is selected from the group consisting of oxygen, silicon, germanium and boron. In one embodiment, the metal is selected from the group consisting of cobalt, copper, tungsten and nickel. In one embodiment, the first hard mask feature 118 is a metal oxide selected from the group consisting of AlOx, HfOx, ZrOx and TiOx.

In one embodiment, the recessed portion 115' of the one of the plurality of conductive lines 110' is recessed relative to the uppermost surface 114 having metal and non-metal, as shown. In one embodiment, the first hard mask element 118 is confined to the uppermost surface 114 of the plurality of conductive lines 110, as shown. However, in another embodiment (not shown), the first hard mask element 118 extends onto the uppermost surface of the ILD layer 104 .

In one embodiment, the uppermost surface 114 of the plurality of conductive lines 110 has an uppermost surface that is substantially coplanar with the uppermost surface of the ILD layer 104, as shown in FIG. 1F'. In one embodiment, the first hard mask element 118 has an uppermost surface that is substantially coplanar with the uppermost surface of the second hard mask element 120, as shown in FIG. 1F'. In one embodiment, the integrated circuit structure further includes a second ILD layer 122 on the hard mask layer 126 . The conductive via 128' is further located in the opening of the second ILD layer 122. In one such embodiment, the openings of the second ILD layer have a width approximately equal to the 3/4 pitch of the plurality of conductive lines 110/110'. In one embodiment, one of the plurality of conductive lines 110 is coupled to the underlying conductive via structure 108, as shown in FIG. 1F'. In one such embodiment, the underlying conductive via structure 108 is connected to an underlying metallization layer of an integrated circuit structure (not shown).

In a second example approach based on the use of different "colored" etch stop layers, Figures 2A-2C illustrate cross-sectional views of portions of integrated circuit layers representing another method involved in back-end-of-line (BEOL) interconnect fabrication. Each operation in the method of forming the etch stop layer and the self-aligned conductive via is according to another embodiment of the present invention.

Referring to FIG. 2A , a starting structure 200 includes a plurality of alternating first 110A and second 110B conductive lines formed in an interlayer dielectric (ILD) layer 104 over a substrate 102 . A plurality of first handling surfaces 114A are formed on corresponding ones of the first conductive lines 110A. A plurality of second handling surfaces 114B are formed on corresponding ones of the second conductive lines 110B. In one embodiment, the composition of the plurality of second treatment surfaces 114B is different from that of the plurality of first treatment surfaces 114A. A hard mask layer 216 is formed on the first plurality of handle surfaces 114A, on the second plurality of handle surfaces 114B, and on the uppermost surface of the ILD layer 104 . The hard mask layer 216 includes a first hard mask component 220 over and aligned with the first plurality of handling surfaces 114A, and a second hard mask component 218 over and aligned with the second plurality of handling surfaces 114B. In one embodiment, the compositions of the first 220 and the second 218 hard mask elements are different from each other.

In one embodiment, the starting structure 200 is fabricated by patterning the hard mask and ILD layers and then metallizing half the total number of metal trenches (eg, alternating ones of the trenches), leaving The other half of the population is open until subsequent metallization processes are performed on the other half of the population. This approach allows the possibility of different compositions of alternating lines. For example, in one embodiment, the metallization layer ultimately includes conductive interconnects of alternating, different first and second compositions. However, in another embodiment, metal lines 110A and 110B are fabricated from substantially the same material.

In one embodiment, to obtain the different compositions of the alternating treated surfaces 114A and 114B, two separate treatment processes (eg, different non-metallic treatments) are used to manufacture the first 114A and second 114B treated surface types. In one embodiment, the hard mask layer 216 having the first hard mask element 220 and the second hard mask element 218 is formed using directed self-polymerization or selective deposition to finally form the first hard mask Two distinct, alternating regions of the mask element 220 and the second hard mask element 218 . In one such embodiment, the directed self-polymerization or selective deposition approach is enhanced by using the handling surfaces 114A and 114B individually (different from the surface using the corresponding conductive lines 110A and 110B). In one embodiment, the materials of the first hard mask element 220 and the second hard mask element 218 exhibit different etch selectivities from each other. Directed self-polymerization or selective growth may be used to selectively align the first hard mask component 220 and the second hard mask component 218 to the respective materials of the first handling surface 114 and the second handling surface 114B.

Referring to FIG. 2B, a second interlayer dielectric (ILD) layer 222 is formed over the structure of FIG. 2A. Openings 224 are formed in the second ILD layer 222 . In one embodiment, openings 224 are formed in locations selected for conductive via fabrication of the next level of metallization. With respect to conventional via location options, the opening 224 may (in one embodiment) have a relatively relaxed width compared to the width of the corresponding conductive line 110B on which the conductive via will ultimately be formed. For example, in a particular embodiment, the width (W) of opening 224 has a dimension that is approximately 1.5 times the pitch of conductive lines 110A/110B. This accommodation for relatively wider via openings 224 can relax constraints on the lithography process used to form openings 224 . In addition, the tolerance for misalignment can also be increased.

FIG. 2C illustrates the structure of FIG. 2B following fabrication of the next layer of vias. One of the second hard mask features 218 is selected for removal (eg, by a selective etch process). In this case, the exposed portion of the second hard mask element 218 is removed, which is selective to the exposed portion of the first hard mask element 220 . In one embodiment, the exposed portions of the second hard mask element 218 are removed selectively to the exposed portions of the first hard mask element 220 using a selective wet etch process. In another embodiment, the exposed portions of the second hard mask feature 218 are removed selectively to the exposed portions of the first hard mask feature 220 using a selective dry or plasma etch process.

Referring again to FIG. 2C , removal of the one of the first hard mask elements 218 forms an opening in the hard mask layer 216 that exposes a portion of one of the plurality of metal lines 110B. In one embodiment, the exposed portion of the one of the plurality of metal lines 110B is modified to remove (or at least substantially remove) non-metal from the uppermost surface 114B of the exposed portion of the one of the plurality of metal lines 110B. The resulting modified exposed portions 115 associated with selected respective underlying conductive lines 110B may be referred to as chemically reduced regions having increased conductivity relative to the uppermost surface 114B. Thus, in one embodiment, modifying the exposed portion of the one of the plurality of metal lines 110B includes leaving the metal of the uppermost surface 114B (eg, as portion 115 ). In certain embodiments, an H ₂ -based plasma is used to remove non-metallic species from exposed portions of the uppermost surface 114B of the corresponding selected conductive line 110B.

Conductive vias 228 are then formed in openings 224 and in regions where a selected one of second hard mask elements 218 has been removed. The conductive vias 228 are in electrical contact with a corresponding one of the second etch stop layer 114B of the second conductive lines 110B. In one embodiment, the conductive vias 228 electrically contact the modified exposed portion 115 of the respective one of the second conductive lines 110B without shorting to the adjacent or adjacent one of the first conductive lines 110A. In certain embodiments, a portion of the conductive via 228 is disposed on one or more exposed portions of the first hard mask component 220, as depicted in FIG. 2C. Then, in one embodiment, improved short circuit tolerance is achieved.

Referring again to FIG. 2C , in an exemplary illustrative embodiment, an integrated circuit structure includes a plurality of alternating first 110A and second 110B conductive lines in an interlayer dielectric (ILD) layer 104 on a substrate 102 . In one embodiment, as described below in relation to FIG. 3 , a plurality of alternating first 110A and second 110B conductive lines are formed along the same direction of the back-end-of-line (BEOL) metallization layer.

The resulting structure, such as that described in connection with Figures 1F, 1F' or 2C, can then be used as a basis for forming subsequent metal lines/vias and ILD layers. Alternatively, the structure of Figures 1F, 1F' or 2C may represent the final metal interconnect layer in an integrated circuit. It should be understood that the above-described process operations may be performed in alternate orders, that not every operation need be performed and/or additional process operations may be performed. Although the foregoing methods of fabricating metallization layers (or portions of metallization layers) of BEOL metallization layers (eg, FIGS. 1A-1F , 1E'-1F', or 2A-2C) have been described in detail for select operations, It should be understood that additional or intermediate operations in its manufacture may include standard microelectronics fabrication procedures such as lithography, etching, thin film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, etch stop layers use of planarization stop layers, and/or any other related actions associated with the manufacture of microelectronic components.

3 illustrates a plan view of a portion of an integrated circuit layer showing operations in a method involving etch stop layer and self-aligned conductive via formation for back end of line (BEOL) interconnect fabrication, in accordance with the practice of the present invention example.

Referring to FIG. 3, first 118 and second 120 hard mask components are shown in this view. An opening 300 in one of the first 118 hard mask components is shown to reveal the modified exposed portion 115 . It should be understood that opening 300 may represent an opening for conductive via 128, 128' or 228 of Figures 1F, 1F' or 2C, respectively. Thus, in one embodiment, selective removal of one of the hard mask components over a selected line does not reveal the complete underlying line, but only a portion of the line where via formation will occur. In one embodiment, only the portion of one of the first 118 hard mask elements exposed by an opening, such as opening 124 or opening 224, is removed along one of the lines. It should be further understood that FIG. 3 represents an embodiment in which the plurality of conductive lines 106/110 (FIGS. 1A-1F, or 1E'-1F') are formed along the same direction of the back-end-of-line (BEOL) metallization layer; or A plurality of alternating first 110A and second 110B conductive lines ( FIGS. 2A-2C ) are formed along the same direction of the back-end-of-line (BEOL) metallization layer.

In another form, FIGS. 4A-4C illustrate cross-sectional views of portions of integrated circuit layers representing another method involving etch layers and self-aligned conductive via formation for back-end-of-line (BEOL) interconnect fabrication. Each operation in the method is according to the embodiment of the present invention.

Referring to FIG. 4A , a hard mask layer 416 is formed over a structure including a plurality of conductive lines 410 in the ILD layer 404 . The hard mask layer 416 includes a first hard mask component 418 and a second hard mask component 420 . The first hard mask element 418 is a double-layer hard mask element that includes a lower etch stop portion 414 and an upper portion. A first hard mask element 418 is formed on and aligned with the uppermost surface of the conductive lines 410 . A second hard mask feature 120 is formed on and aligned with the exposed surface of the ILD layer 404 . In one embodiment, the hard mask layer 416 having the first hard mask element 418 and the second hard mask element 420 is formed using directed self-polymerization or selective deposition to finally form the first hard mask Two distinct, alternating regions of mask element 418 and second hard mask element 420 . In one embodiment, the materials of the first hard mask element 418 and the second hard mask element 420 exhibit different etch selectivities from each other.

Referring to FIG. 4B, a second interlayer dielectric (ILD) layer 422 is formed over the structure of FIG. 4A. Openings 424 are formed in the second ILD layer 422 . In one embodiment, openings 424 are formed in locations selected for conductive via fabrication of the next level of metallization. Relative to conventional via location options, opening 424 may (in one embodiment) have a relatively relaxed width compared to the width of corresponding conductive line 410 on which the conductive via will ultimately be formed. For example, in a particular embodiment, the width (W) of opening 424 has a dimension of approximately 3/4 the pitch of conductive lines 410 . This accommodation for relatively wider via openings 424 can relax constraints on the lithography process used to form the openings 424 . In addition, the tolerance for misalignment can also be increased.

Referring to FIG. 4C, one of the first hard mask features 418 is selected for removal (eg, by a selective etch process). In this case, the exposed portion of the first hard mask element 418 is removed, which is selective to the exposed portion of the second hard mask element 420 . In one embodiment, the exposed portions of the first hard mask feature 418 are removed selectively to the exposed portions of the second hard mask feature 420 using a selective dry or plasma etch process. In another embodiment, the exposed portions of the first hard mask element 418 are removed selectively to the exposed portions of the second hard mask element 420 using a selective wet etch process.

Referring again to FIG. 4C , removal of the one of the first hard mask elements 418 forms an opening in the hard mask layer 416 to form a patterned hard mask layer 426 exposing one of the plurality of metal lines 410 part of the person. A conductive via 428 is formed in the opening. Conductive vias 428 are those that electrically contact selected conductive lines 410 without shorting to adjacent or adjacent ones of conductive lines 410 . In certain embodiments, a portion of the conductive via 428 is disposed on one or more exposed portions of the second hard mask component 420, as depicted in FIG. 4C. In one embodiment, improved short circuit tolerance is achieved.

Referring again to FIG. 4C , in an embodiment, an integrated circuit structure includes a plurality of conductive lines 410 in an interlayer dielectric (ILD) layer 404 on a substrate 402 . The hard mask layer 426 is located on the plurality of conductive lines 410 and on the uppermost surface of the ILD layer 404 . The hard mask layer 426 includes a first hard mask element 418 on and aligned with the uppermost surface of the plurality of conductive lines 410 . The second hard mask element 420 is located on and aligned with a region of the uppermost surface of the ILD layer 404 . The composition of the first 418 and the second 420 hard mask components are different from each other. The first hard mask component 418 includes a lower etch stop layer 414 and an upper layer different from the lower etch stop layer 414 . A conductive via 428 is located in an opening in the hard mask layer 426 and over a portion of one of the plurality of conductive lines 410 .

In one embodiment, the etch stop layer 414 under the first hard mask element 418 is selected from the group consisting of SiOx and SiNx. The upper layer of the first hard mask feature 418 is a metal oxide selected from the group consisting of AlOx, HfOx, ZrOx and TiOx.

In one embodiment, the first hard mask element 418 is limited to the uppermost surface of the plurality of conductive lines 410, as shown. In another embodiment (not shown), the first hard mask element 418 extends onto the uppermost surface of the ILD layer 404 .

In one embodiment, a portion of the conductive via 428 is located on a portion of the second hard mask element 420 of the hard mask layer 426 . In one embodiment, the first hard mask element 418 has an uppermost surface that is substantially coplanar with the uppermost surface of the second hard mask element 420, as shown.

The above-described embodiments can be implemented to enable strong self-alignment and mitigation of edge layout issues that would otherwise compromise conventional patterning. Embodiments may be implemented to enable integration of DSA and selective deposition. Embodiments may be implemented to enable robust interconnect reliability and low via/contact resistance.

It should be understood that embodiments are applicable to DSA, selective deposition, or "traditional" top-down methods for coloring. In one example, the example process scheme involves: recessing metal by etching, surface treatment of metal (eg, oxidation, silane, borane treatment) to form materials such as material 114 , coloring materials (eg, AlOx, TiOx, HfOx, ZrOx) fill the recessed portion of the metal line, and finally polish or planarize. The final structure can be the same or similar to structures fabricated using DSA or selective deposition.

It should be understood that embodiments involving coloring with DSA may be accompanied by distinctive features in the final product. Such distinctive features can be in the guard ring as well as in the cutting lane.

In one embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of (or includes) a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (eg, silicon dioxide (SiO ₂ )), silicon nitrides (eg, silicon nitride (Si ₃ N ₄ )), silicon doped Doped oxides, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. This interlayer dielectric material can be formed by conventional techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In one embodiment, as also used throughout this specification, the metal line or interconnect line material (and via material) is composed of one or more metal or other conductive structures. A common example is a structure using copper lines and which may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of several metals. For example, metal interconnect lines may include barrier layers, stacks of different metals or alloys, and the like. Thus, the interconnect lines may be a single layer of material, or may be formed from several layers, including conductive liner and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form the interconnect lines. In one embodiment, the interconnection line is composed of a barrier layer and a conductive filling material. In one embodiment, the barrier layer is a tantalum or tantalum nitride layer, or a combination thereof. In one embodiment, the conductive filling material is a material such as (but not limited to) Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof . Interconnect lines are sometimes also (in the art) referred to as traces, wires, wires, metal, metal lines, or just interconnects.

In one embodiment, as also used throughout this specification, the hard mask material (and in some instances the etch stop layer) is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask materials may be used for different regions to provide growth or etch selectivities that are different from each other and from the underlying dielectric below the metal layer. In some embodiments, the hard mask layer includes a layer of silicon nitride (eg, silicon nitride) or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials such as silicon carbide. In another embodiment, the hard mask material includes metals. For example, a hard mask or other overlying material may include a layer of titanium or other metal nitride (eg, titanium nitride). Potentially smaller amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, other hard mask layers known in the art may be used depending on the particular implementation. The hard mask layer can be formed by CVD, PVD, or by other deposition methods.

It should be understood that the layers and materials described in connection with Figures 1A-1F, 1E'-1F', 2A-2C, 3, and 4A-4C are typically formed on an underlying semiconductor substrate or structure (such as an underlying device layer of an integrated circuit) on or above. In one embodiment, the underlying semiconductor substrate represents a typical workpiece object used to fabricate integrated circuits. Semiconductor substrates often include wafers or other pieces of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, monocrystalline silicon, polycrystalline silicon, and silicon-on-insulator (SOI), and similar substrates formed from other semiconductor materials. Semiconductor substrates (depending on the stage of manufacture) often include transistors, integrated circuits, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Again, the structures depicted in Figures 1F, 1F', 2C or 4C can be fabricated on the underlying lower level interconnect layers.

As described above, the patterned features may be patterned in a raster-like pattern with lines, holes or trenches spaced at a constant pitch and having a constant width. Patterns can be fabricated, for example, by halving the pitch or quartering the pitch. In one example, a capping film, such as a polysilicon film, is patterned using a lithography and etch process (which may involve, for example, spacer-based quadruple patterning (SBQP) or pitch reduction by a factor of four). patterned. It should be understood that the grating pattern of lines can be fabricated by a variety of methods including 193nm immersion lithography (i193), extreme ultraviolet (EUV) and/or electron beam direct writing (EBDW) lithography, directed self-polymerization, and the like. In other embodiments, the pitch need not be constant, nor the width.

In one embodiment, pitch division technique is used to increase line density. In a first example, halving the pitch can be implemented to double the linear density of the resulting grating structure. 5A illustrates a cross-sectional view of the starting structure after deposition (but before patterning) of a hard mask material layer formed subsequent to an interlayer dielectric (ILD) layer. 5B illustrates a cross-sectional view of the structure of FIG. 5A following patterning by a pitch-halved hard mask layer.

Referring to FIG. 5A , a starting structure 500 has a hard mask material layer 504 formed on an interlayer dielectric (ILD) layer 502 . A patterned mask 506 is disposed over the hard mask material layer 504 . The patterned mask 506 has spacers 508 formed along the sidewalls of its features (lines), on the hard mask material layer 504 .

Referring to FIG. 5B , the hard mask material layer 504 is patterned in a half-pitch manner. Specifically, patterning mask 506 is removed first. The resulting pattern of spacers 508 has twice the density of mask 506, or half its pitch or features. The pattern of spacers 508 is transferred to hard mask material layer 504, eg, by an etching process, to form patterned hard mask 510, as shown in FIG. 5B. In one such embodiment, the patterned hard mask 510 is formed with a grating pattern of unidirectional lines. The grating pattern of the patterned hard mask 510 may be a close pitch grating structure. For example, tight pitches may not be directly achievable by conventional lithography techniques. Even, although not shown, the original pitch can be reduced to a quarter by a second round of spacer mask patterning. Thus, the raster-like pattern of the patterned hard mask 510 of FIG. 5B may have hard mask lines spaced at a constant pitch and having a constant width relative to each other. The resulting dimensions may be much smaller than the critical dimensions of the lithography techniques employed. Thus, blank films can be processed using lithography and etching (which can involve, for example, spacer-based double patterning (SBDP) or pitch half, or spacer-based quadruple patterning (SBQP) or pitch quartered) to be patterned.

It should be understood that other pitch division methods can also be implemented. For example, FIG. 6 illustrates a cross-sectional view in a spacer-based sixfold patterning (SBSP) process scheme involving a factor of six pitch division. Referring to FIG. 6 , in operation (a), the sacrificial pattern X after lithography, thinning and etching processes is shown. In operation (b), spacers A and B are shown after deposition and etching. In operation (c), the pattern of operation (b) after spacer A removal is shown. In operation (d), the pattern of operation (c) after spacer C deposition is shown. In operation (e), the pattern of operation (d) after spacer C etch is shown. In operation (f), a pitch/6 pattern is obtained after sacrificial pattern X removal and spacer B removal.

In one embodiment, lithography is performed using 193nm immersion lithography (i193), EUV and/or EBDW lithography, and the like. Positive or negative tone resists can be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topographic mask, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topography masking portion is a carbon hard mask (CHM) layer and the anti-reflective coating is a silicon ARC layer.

In another aspect, one or more embodiments described herein relate to the fabrication of semiconductor devices, such as PMOS and NMOS device fabrication. For example, the approaches described herein may be implemented to fabricate self-aligned gate contacts used in a metal oxide semiconductor (MOS) device. As an example of a completed device, Figure 7A illustrates a cross-sectional view of a non-planar semiconductor device with self-aligned gate contacts, in accordance with an embodiment of the present invention. Figure 7B illustrates a plan view taken along the a-a' axis of the semiconductor device of Figure 7A, in accordance with an embodiment of the present invention.

Referring to FIG. 7A , semiconductor structure or device 700 includes non-planar active regions (eg, fin structures including protruding fin portion 704 and sub-fin region 705 ) formed from substrate 702 (and within isolation region 706 ). Gate line 708 is disposed over protruding portion 704 of the non-planar active region and over a portion of isolation region 706 . As shown, the gate line 708 includes a gate electrode 750 and a gate dielectric layer 752 . In one embodiment, the gate line 708 may also include a dielectric capping layer 754 . Gate contact 714 , and overlying gate contact via 716 are also seen from this perspective, along with overlying metal interconnect 760 , which are all disposed in interlevel dielectric stack or layer 770 . Also seen in the perspective view of FIG. 7A, gate contact 714 is (in one embodiment) disposed over isolation region 706, but not over the non-planar active region. According to an embodiment of the present invention, the dielectric cap layer 754 is a self-aligned or colored hard mask layer, as described above. In one such embodiment, the dielectric cap layer 754 is formed on the treated surface 799 , such as the surface described above in association with the uppermost surface 114 . A gate contact 714 is formed on the modified portion 777 of the treated surface 799 in the opening formed in the dielectric cap layer 754 .

Referring to FIG. 7B , gate line 708 is shown disposed over protruding fin portion 704 . The source and drain regions 704A and 704B of the protruding fin portion 704 can be seen from this perspective view. In one embodiment, source and drain regions 704A and 704B are doped portions of the original material protruding from fin portion 704 . In another embodiment, the material of the protruding fin portion 704 is removed and replaced with another semiconductor material, such as by epitaxial deposition. In either case, source and drain regions 704A and 704B may extend below the level of dielectric layer 706 , ie, into sub-fin region 705 .

In one embodiment, the semiconductor structure or device 700 is a non-planar device such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region consists of or is formed as a three-dimensional body. In one such embodiment, the gate electrode stack of gate line 708 surrounds at least a top surface and a pair of sidewalls of the three-dimensional body.

The substrate 702 can be composed of a semiconductor material that can withstand the manufacturing process and in which charge migration is possible. In one embodiment, substrate 702 is a bulk substrate made of a layer of crystalline silicon, silicon/germanium, or germanium doped with charge carriers such as, but not limited to, phosphorous, arsenic, boron, or combinations thereof. composition to form the active region 704 . In one embodiment, the concentration of silicon in bulk substrate 702 is greater than 97%. In another embodiment, the bulk substrate 702 consists of an epitaxial layer grown on top of a separate crystalline substrate, eg, a silicon epitaxial layer grown on top of a boron-doped bulk silicon monocrystalline substrate. The bulk substrate 702 may alternatively be composed of Group III-V materials. In one embodiment, bulk substrate 702 is composed of Group III-V materials such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, arsenide Indium Gallium, Aluminum Gallium Arsenide, Indium Gallium Phosphide, or combinations thereof. In one embodiment, the bulk substrate 702 is composed of a III-V material with charge carrier dopant impurity atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

Isolation region 706 may be composed of a material suitable for ultimately electrically isolating (or facilitating isolating) the permanent gate structure from the underlying bulk substrate or from an active region formed in the underlying bulk substrate, such as Isolate the active area of the fin. For example, in one embodiment, isolation region 706 is formed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

Gate line 708 may consist of a gate electrode stack including gate dielectric layer 752 and gate electrode layer 750 . In one embodiment, the gate electrode 750 of the gate electrode stack is composed of a metal gate, and the gate dielectric layer 752 is composed of a high-K material. For example, in one embodiment, the gate dielectric layer 752 is composed of a material such as (but not limited to) hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, Tantalum, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. Furthermore, a portion of the gate dielectric layer may include a layer of native oxide formed from the top layers of the substrate 702 . In one embodiment, the gate dielectric layer consists of a top high-k portion and a lower portion (composed of an oxide of semiconductor material). In one embodiment, the gate dielectric layer 752 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride.

In one embodiment, the gate electrode layer 750 of the gate line 708 is composed of a metal layer, such as (but not limited to) metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium , titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-work function setting fill material formed over the metal work function setting layer. The gate electrode layer can be composed of a P-type work function metal or an N-type work function metal, and the transistor will be a PMOS or NMOS transistor. In some embodiments, the gate electrode layer may include a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for gate electrodes include (but are not limited to) hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, and titanium carbide , tantalum carbide, and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode with a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may include a "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may be only a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In a further embodiment of the invention, the gate electrode may comprise a combination of U-shaped structures and planar, non-U-shaped structures. For example, a gate electrode may include one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.

In one embodiment, treated surface 799 is composed of materials such as those described above in connection with treated surface 114 . For example, the treated surface 799 may include a metal, such as the bulk metal of the gate electrode fill (eg, copper, cobalt, nickel, tungsten, etc.), and a non-metal, such as boron, silicon, germanium, or oxygen. Modified portion 777 may be a converted or reduced region where, for example, non-metals have been removed, or at least substantially removed. Alternatively, although not depicted, modified portion 777 is an etched or recessed region. In one embodiment, the dielectric cap layer 754 is composed of a material such as that described above in connection with the hard mask component 118 , 120 , 218 or 220 .

The spacer associated with the gate electrode stack may be composed of a material suitable to ultimately electrically isolate (or facilitate isolating) the permanent gate structure from adjacent conductive contacts, such as self-aligned contacts . For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

The gate contact 714 and the upper gate contact via 716 may be formed of a conductive material. In one embodiment, one or more contacts or vias are composed of metal species. Metal species can be pure metals, such as tungsten, nickel, or cobalt; or can be alloys, such as metal-metal alloys or metal-semiconductor alloys (eg, such as silicide materials). According to another embodiment of the present invention, the gate contact 714 is a self-aligned gate contact.

In one embodiment (although not shown), providing structure 700 involves forming a contact pattern that aligns substantially perfectly with an existing gate pattern while avoiding the use of a lithography with an extremely stringent registration budget. step. In one such embodiment, this approach enables the use of an inherently highly selective wet etch (eg, relative to conventionally practiced dry or plasma etch) to create contact openings. In one embodiment, the contact pattern is formed by utilizing an existing gate pattern combined with contact plug lithography. In one such embodiment, this approach enables the elimination of the need for critical lithography operations (as used in conventional approaches) to create the contact pattern. In one embodiment, the trench contact grid is not separately patterned, but is formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed subsequent to gate grating patterning but prior to gate grating dicing.

Furthermore, the gate stack structure 708 can be fabricated by a replacement gate process. In this approach, dummy gate material such as polysilicon or silicon nitride pillar material can be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being done from an earlier process. In one embodiment, the dummy gate is removed by dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and removed by a dry etching process including the use of SF ₆ . In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a wet etch process including the use of aqueous NH ₄ OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and removed by a wet etch process including aqueous phosphoric acid.

In one embodiment, one or more of the approaches described herein basically consider a dummy and replacement gate process combined with a dummy and replacement contact process to obtain structure 700 . In one such embodiment, the replacement contact process is performed after the replacement gate process to allow high temperature annealing of at least a portion of the permanent gate stack. For example, in certain such embodiments, annealing of at least a portion of the permanent gate structure (eg, after the gate dielectric layer is formed) is performed at a temperature greater than about 600 degrees Celsius. Annealing is performed prior to the formation of permanent contacts.

Referring again to FIG. 7A, the semiconductor structure or device 700 is configured to place the gate contact above the isolation region. Such a configuration can be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of a gate electrode formed over an active region. Typically, before (eg, in addition to) forming a gate contact structure (such as a via) over the active portion of the gate and in the same layer as the trench contact via (eg, in addition), one of the present invention Or more embodiments include a trench contact process using gate alignment first. Such a process may be implemented to form trench contact structures for semiconductor structure fabrication, eg, for integrated circuit fabrication. In one embodiment, trench contact patterns are formed to align with existing gate patterns. In contrast, conventional approaches generally involve an additional lithography process, with a lithographic contact pattern closely aligned to the existing gate pattern, combined with selective contact etching. For example, a conventional process may include patterning of a separately patterned poly (gate) grid with contact features.

It should be understood that not all aspects of the above processes need to be implemented to fall within the spirit and scope of the embodiments of the present invention. For example, in one embodiment, dummy gates need not have been formed before making gate contacts over the active portion of the gate stack. The gate stacks described above may actually be permanent gate stacks, as originally formed. Also, the processes described herein can be used to fabricate one or more semiconductor devices. The semiconductor device can be a type of device such as a transistor. For example, in one embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Meanwhile, in one embodiment, the semiconductor device has a three-dimensional architecture, such as a triple-gate device, a dual-gate device with independent access, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at the 10 nanometer (10 nm) or smaller technology node.

The embodiments disclosed herein can be used to fabricate many different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memory can be fabricated. In addition, integrated circuits or other microelectronic devices may be used in a variety of electronic devices known in the art. For example, in computer systems (eg, desktops, laptops, servers), mobile phones, personal electronic devices, and so on. Integrated circuits can be coupled to bus bars and other components in the system. For example, a processor may be coupled to memory, a chipset, etc. by one or more busses. Each processor, memory, chipset can potentially be fabricated using the methods disclosed herein.

FIG. 8 illustrates a computing device 800 according to an embodiment of the present invention. Computing device 800 contains circuit board 802 . The circuit board 802 may include several components including, but not limited to, a processor 804 and at least one communication chip 806 . Processor 804 is physically and electrically coupled to circuit board 802 . In some embodiments, at least one communication chip 806 is also physically and electrically coupled to the circuit board 802 . In a further embodiment, the communication chip 806 is part of the processor 804 .

Depending on its application, computing device 800 may include other components, which may or may not be physically and electrically coupled to circuit board 802 . These other components include (but are not limited to) volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chip group, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyro, speaker, Cameras, and mass storage devices (such as hard drives, compact discs (CD), digital discs (DVD), etc.).

Communication chip 806 enables wireless communication for transfer of data to and from computing device 800 . The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that communicate data through the use of modulated electromagnetic radiation through non-solid media. The term does not imply that its associated device does not contain any wiring, although in some embodiments it might not. The communication chip 806 may implement any of several wireless standards or protocols, including (but not limited to) Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocol designated as 3G, 4G, 5G, and above. Computing device 800 may include a plurality of communication chips 806 . For example, the first communication chip 806 can be dedicated to short-distance wireless communication, such as Wi-Fi and Bluetooth; and the second communication chip 806 can be dedicated to longer-distance wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE , Ev-DO and others.

Processor 804 of computing device 800 includes an integrated circuit die packaged within processor 804 . In some embodiments of the invention, the integrated circuit die of the processor includes one or more structures, such as etch stop layers and corresponding conductive vias, constructed in accordance with implementations of the embodiments of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from a register and/or memory to convert that electronic data into a form that can be stored in the register and/or memory other electronic materials.

The communication chip 806 also includes integrated circuit die packaged within the communication chip 806 . According to another embodiment of the present invention, the IC die of the communication chip includes one or more structures, such as etch stop layers and corresponding conductive vias, which are constructed according to the implementation of the embodiments of the present invention.

In a further embodiment, another component included within computing device 800 may comprise an integrated circuit die including one or more structures, such as etch stop layers and corresponding conductive vias, in accordance with implementations of the present invention Example implementation built.

In various embodiments, the computing device 800 can be a laptop computer, a small notebook computer, a notebook computer, a thin notebook computer, a smart phone, a tablet, a personal digital assistant (PDA), an ultralight mobile PC, a mobile phone , desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further embodiments, computing device 800 may be any other electronic device that processes data.

Figure 9 illustrates an inserter 900 that includes one or more embodiments of the present invention. The interposer 900 is an intermediate substrate for bridging the first substrate 902 to the second substrate 904 . The first substrate 902 can be, for example, an integrated circuit die. The second substrate 904 can be, for example, a memory module, a computer motherboard, or other integrated circuit die. Typically, the purpose of the interposer 900 is to extend a connection to a wider pitch or to reroute a connection to a different connection. For example, interposer 900 may couple an integrated circuit die to a ball grid array (BGA) 906 , which may subsequently be coupled to a second substrate 904 . In some embodiments, the first and second bases 902 / 904 are mounted to opposite sides of the interposer 900 . In other embodiments, the first and second bases 902 / 904 are mounted to the same side of the interposer 900 . And in a further embodiment, three or more substrates are interconnected via the interposer 900 .

Interposer 900 may be formed from epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In further embodiments, the interposer may be formed of alternative hard or resilient materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other III-V or IV materials.

The interposer may include metal interconnects 908 and vias 910 including, but not limited to, through-silicon vias (TSVs) 912 . Inserter 900 may further include embedded devices 914, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, inductors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on interposer 900 . According to embodiments of the present invention, the apparatus or process disclosed herein may be used in the manufacture of interposer 900 .

Accordingly, embodiments of the present invention include etch stop layer based approaches for conductive via fabrication, and resulting structures

Example Embodiment 1: An integrated circuit structure includes a plurality of conductive lines in an interlayer dielectric (ILD) layer above a substrate, wherein each of the plurality of conductive lines has a bulk portion comprising metal and has a structure comprising metal and non-conductive lines. The top surface of the metal. A hard mask layer is located on the plurality of conductive lines and on the uppermost surface of the ILD layer, the hard mask layer includes a first hard mask component on and aligned with the uppermost surface of the plurality of conductive lines, and a second hard mask element on and aligned with the region of the uppermost surface of the ILD layer, the composition of the first hard mask element and the second hard mask element are different from each other. A conductive via is located in the opening in the hard mask layer and on a portion of one of the plurality of conductive lines that has a different composition than the uppermost surface thereof including the metal and the non-metal.

Example Embodiment 2: The integrated circuit structure of Example Embodiment 1, wherein the non-metal is selected from the group consisting of oxygen, silicon, germanium and boron.

Example Embodiment 3: The integrated circuit structure of Example Embodiment 1 or 2, wherein the metal is selected from the group consisting of cobalt, copper, tungsten and nickel.

Example Embodiment 4: The integrated circuit structure of Example Embodiments 1, 2 or 3, wherein the first hard mask feature is a metal oxide selected from the group consisting of AlOx, HfOx, ZrOx and TiOx.

Example Embodiment 5: The integrated circuit structure of Example Embodiment 1, 2, 3 or 4, wherein the portion of the one of the plurality of conductive lines is substantially coplanar with the uppermost surface comprising the metal and the non-metal .

Example Embodiment 6: The integrated circuit structure of Example Embodiment 1, 2, 3 or 4, wherein the portion of the one of the plurality of conductive lines is recessed below the uppermost surface including the metal and the non-metal.

Example Embodiment 7: The integrated circuit structure of Example Embodiments 1, 2, 3, 4, 5 or 6, wherein the first hard mask element is confined to the uppermost surface of the plurality of conductive lines.

Example Embodiment 8: The integrated circuit structure of Example Embodiments 1, 2, 3, 4, 5, or 6, wherein the first hard mask element extends onto the uppermost surface of the ILD layer.

Example Embodiment 9: The integrated circuit structure of Example Embodiments 1, 2, 3, 4, 5, 6, 7, or 8, wherein a portion of the conductive via is located in the second hard mask of the hard mask layer part of the component.

Example Embodiment 10: The integrated circuit structure of Example Embodiments 1, 2, 3, 4, 5, 6, 7, 8, or 9, wherein the first hard mask element has an uppermost The uppermost surface where the surfaces are substantially coplanar.

Example Embodiment 11: The integrated circuit structure of Example Embodiments 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10, further comprising a second ILD layer over the hard mask layer, wherein The conductive via is further in the opening of the second ILD layer.

Example Embodiment 12: The integrated circuit structure of Example Embodiments 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, or 11, wherein one of the plurality of conductive lines is coupled to an underlying conductive via structure, the underlying conductive via structure is connected to the underlying metallization layer of the integrated circuit structure.

Example Embodiment 13: An integrated circuit structure includes a plurality of conductive lines in an interlayer dielectric (ILD) layer above a substrate. A hard mask layer is located on the plurality of conductive lines and on the uppermost surface of the ILD layer, the hard mask layer includes a first hard mask component on and aligned with the uppermost surface of the plurality of conductive lines, and a second hard mask element on and aligned with the region of the uppermost surface of the ILD layer, the composition of the first hard mask element and the second hard mask element are different from each other, and the first hard mask element The mask component includes a lower etch stop layer and an upper layer different from the lower etch stop layer. A conductive via is located in the opening in the hard mask layer and over a portion of one of the plurality of conductive lines.

Example Embodiment 14: The integrated circuit structure of Example Embodiment 13, wherein the lower etch stop layer is selected from the group consisting of SiOx and SiNx, and wherein the upper layer of the first hard mask element is selected from the group consisting of AlOx, Metal oxides of the group consisting of HfOx, ZrOx and TiOx.

Example Embodiment 15: The integrated circuit structure of Example Embodiment 13 or 14, wherein the first hard mask element is limited to the uppermost surface of the plurality of conductive lines.

Example Embodiment 16: The integrated circuit structure of Example Embodiment 13 or 14, wherein the first hard mask element extends onto the uppermost surface of the ILD layer.

Example Embodiment 17: The integrated circuit structure of Example Embodiment 13, 14, 15 or 16, wherein a portion of the conductive via is located on a portion of the second hard mask element of the hard mask layer.

Example Embodiment 18: The integrated circuit structure of Example Embodiments 13, 14, 15, 16, or 17, wherein the first hard mask element has an uppermost surface that is substantially coplanar with an uppermost surface of the second hard mask element .

Example Embodiment 19: The integrated circuit structure of Example Embodiments 13, 14, 15, 16, 17, or 18, further comprising a second ILD layer on the hard mask layer, wherein the conductive via is further on the In the opening of the second ILD layer.

Example Embodiment 20: The integrated circuit structure of Example Embodiments 13, 14, 15, 16, 17, 18, or 19, wherein one of the plurality of conductive lines is coupled to an underlying conductive via structure, the underlying conductive via structure is connected to the underlying metallization layer of the integrated circuit structure.

Example Embodiment 21: A method of fabricating an integrated circuit structure comprising forming a plurality of conductive lines in an interlayer dielectric (ILD) layer over a substrate, wherein each of the plurality of conductive lines has a bulk portion comprising metal. The method also includes processing the plurality of conductive lines to form an uppermost surface that includes metal and non-metal. The method also includes forming a hard mask layer on the plurality of conductive lines and on the uppermost surface of the ILD layer, the hard mask layer including a first hard mask layer on and aligned with the uppermost surface of the plurality of conductive lines. A mask element, and a second hard mask element over and aligned with a region of the uppermost surface of the ILD layer, the first hard mask element and the second hard mask element are different in composition from each other. The method also includes forming an opening in the hard mask layer to expose a portion of one of the plurality of metal lines. The method also includes modifying the exposed portion of the one of the plurality of metal lines to remove the non-metal from the uppermost surface of the exposed portion of the one of the plurality of metal lines. The method also includes forming a conductive via in the opening in the hard mask layer and on the modified exposed portion of the one of the plurality of conductive lines.

Example Embodiment 22: The method of Example Embodiment 21, wherein modifying the exposed portion of the one of the plurality of metal lines includes leaving the metal of the uppermost surface.

Example Embodiment 23: The method of Example Embodiment 21, wherein modifying the exposed portion of the one of the plurality of metal lines comprises removing the metal of the uppermost surface to form a recessed portion of the one of the plurality of metal lines .

Example Embodiment 24: The method of Example Embodiment 21, 22, or 23, wherein treating the plurality of conductive lines comprises exposing the plurality of conductive lines to ammonia and a nonmetal selected from the group consisting of oxygen, silicon, germanium, and boron source.

Example Embodiment 25: The method of Example Embodiment 21, 22, 23, or 24, wherein forming the hard mask layer includes using a Directed Self-Aggregation (DSA) method or a selective growth method.

100‧‧‧start structure 102‧‧‧base 104‧‧‧Interlayer dielectric (ILD) layer 106‧‧‧conductive wire 108‧‧‧conductive via 110, 110'‧‧‧Modified conductive thread 110A‧‧‧The first conductive wire 110B‧‧‧Second conductive wire 114‧‧‧top surface 114A‧‧‧First Disposal Surface 114B‧‧‧Second Disposal Surface 115‧‧‧exposed part 115’‧‧‧Concave part 116‧‧‧hard mask layer 118‧‧‧The first hard mask component 120‧‧‧Second Hard Mask Assembly 122‧‧‧Second interlayer dielectric (ILD) layer 124‧‧‧opening 126‧‧‧hard mask layer 127, 127’‧‧‧opening 128, 128’‧‧‧Conductive vias 200‧‧‧start structure 216‧‧‧hard mask layer 218‧‧‧Second Hard Mask Component 220‧‧‧The first hard mask component 222‧‧‧Second interlayer dielectric (ILD) layer 224‧‧‧opening 228‧‧‧conductive via 300‧‧‧openings 402‧‧‧base 404‧‧‧interlayer dielectric (ILD) layer 410‧‧‧conductive wire 414‧‧‧Lower etching stop part 416‧‧‧hard mask layer 418‧‧‧The first hard mask component 420‧‧‧Second Hard Mask Assembly 422‧‧‧Second interlayer dielectric (ILD) layer 424‧‧‧opening 426‧‧‧patterned hard mask layer 428‧‧‧Conductive Via 500‧‧‧start structure 502‧‧‧interlayer dielectric (ILD) layer 504‧‧‧hard mask material layer 506‧‧‧patterned mask 508‧‧‧Spacer 510‧‧‧patterned hard mask 700‧‧‧semiconductor structure or device 702‧‧‧base 704‧‧‧Protruding fin part 704A, 704B‧‧‧source and drain regions 705‧‧‧sub-fin area 706‧‧‧Quarantine area 708‧‧‧gate line 714‧‧‧gate contact 716‧‧‧Upper gate contact via hole 750‧‧‧gate electrode 752‧‧‧gate dielectric layer 754‧‧‧Dielectric capping layer 760‧‧‧Metal interconnection above 770‧‧‧interlayer dielectric stack or layer 777‧‧‧Modified part 799‧‧‧treated surface 800‧‧‧computing device 802‧‧‧circuit board 804‧‧‧processor 806‧‧‧communication chip 900‧‧‧Interposer 902‧‧‧First Foundation 904‧‧‧Second Foundation 906‧‧‧Ball Grid Array (BGA) 908‧‧‧Metal interconnection 910‧‧‧through hole 912‧‧‧Through Silicon Via (TSV) 914‧‧‧Embedded device

1A-1F illustrate cross-sectional views of portions of integrated circuit layers representing operations in a method involving etch stop layer and self-aligned conductive via formation for back end of line (BEOL) interconnect fabrication, According to the embodiment of the present invention.

1E'-1F' illustrate cross-sectional views of portions of integrated circuit layers showing one of another methods involving etch stop layer and self-aligned conductive via formation for back end of line (BEOL) interconnect fabrication. Each operation is according to the embodiment of the present invention.

2A-2C illustrate cross-sectional views of portions of integrated circuit layers representing operations in another method involving etching layers and self-aligned conductive via formation for back-end-of-line (BEOL) interconnect fabrication, According to the embodiment of the present invention.

3 illustrates a plan view of a portion of an integrated circuit layer showing operations in a method involving etch stop layer and self-aligned conductive via formation for back end of line (BEOL) interconnect fabrication, in accordance with the practice of the present invention example.

4A-4C illustrate cross-sectional views of portions of integrated circuit layers representing operations in another method involving etching layers and self-aligned conductive via formation for back-end-of-line (BEOL) interconnect fabrication, According to the embodiment of the present invention.

5A illustrates a cross-sectional view of a starting structure after deposition (but before patterning) of a hard mask material layer formed subsequent to an interlayer dielectric (ILD) layer, in accordance with an embodiment of the present invention.

5B illustrates a cross-sectional view of the structure of FIG. 5A subsequent to patterning by a half-pitch hard mask layer, in accordance with an embodiment of the present invention.

6 illustrates a cross-sectional view in a spacer-based sixfold patterning (SBSP) process scheme involving factor-of-six pitch division, according to an embodiment of the present invention.

Figure 7A illustrates a cross-sectional view of a non-planar semiconductor device with self-aligned gate contacts, in accordance with an embodiment of the present invention.

Figure 7B illustrates a plan view taken along the a-a' axis of the semiconductor device of Figure 7A, in accordance with an embodiment of the present invention.

Figure 8 illustrates a computing device, according to an implementation of an embodiment of the present invention.

Figure 9 is an interposer implementing one or more embodiments of the present invention.

102‧‧‧base

104‧‧‧Interlayer dielectric (ILD) layer

108‧‧‧conductive via

110‧‧‧Modified conductive thread

114‧‧‧top surface

115‧‧‧exposed part

118‧‧‧The first hard mask component

120‧‧‧Second Hard Mask Assembly

122‧‧‧Second interlayer dielectric (ILD) layer

126‧‧‧hard mask layer

128‧‧‧conductive vias

Claims (25)

An integrated circuit structure comprising: a plurality of conductive lines in an interlayer dielectric (ILD) layer above a substrate, wherein each of the plurality of conductive lines has a bulk portion comprising the metal and has a the uppermost surface of the plurality of conductive lines and a hard mask layer on the uppermost surface of the ILD layer, the hard mask layer includes a first hard mask layer on and aligned with the uppermost surface of the plurality of conductive lines a mask element, and a second hard mask element on and aligned with a region of the uppermost surface of the ILD layer, the first hard mask element and the second hard mask element having compositions different from each other; and A conductive via in the opening in the hard mask layer and on a portion of one of the plurality of conductive lines having a composition different from the uppermost surface thereof including the metal and the non-metal. Such as the integrated circuit structure of claim 1, wherein the non-metal is selected from the group consisting of oxygen, silicon, germanium and boron. Such as the integrated circuit structure of claim 1 or 2, wherein the metal is selected from the group consisting of cobalt, copper, tungsten and nickel. The integrated circuit structure of claim 1 or 2, wherein the first hard mask element is a metal oxide selected from the group consisting of AlOx, HfOx, ZrOx and TiOx. As for the integrated circuit structure of claim 1 or 2, the part of the one of the plurality of conductive lines is substantially coplanar with the uppermost surface including the metal and the non-metal. For the integrated circuit structure of claim 1 or 2, wherein the part of the one of the plurality of conductive lines is recessed below the uppermost surface including the metal and the non-metal. The integrated circuit structure of claim 1 or 2, wherein the first hard mask element is limited to the uppermost surface of the plurality of conductive lines. The integrated circuit structure of claim 1 or 2, wherein the first hard mask element extends to the uppermost surface of the ILD layer. According to the integrated circuit structure of claim 1 or 2, a part of the conductive via is located on a part of the second hard mask element of the hard mask layer. The integrated circuit structure of claim 1 or 2, wherein the first hard mask element has an uppermost surface that is substantially coplanar with the uppermost surface of the second hard mask element. For the integrated circuit structure of item 1 or 2 of the scope of the patent application, it further includes Including: a second ILD layer over the hard mask layer, wherein the conductive via is further in the opening of the second ILD layer. Such as the integrated circuit structure of claim 1 or 2, wherein one of the plurality of conductive lines is coupled to the lower conductive via structure, and the lower conductive via structure is connected to the lower metallization of the integrated circuit structure layer. An integrated circuit structure comprising: a plurality of conductive lines in an interlayer dielectric (ILD) layer on a substrate; a hard mask layer on the plurality of conductive lines and on the uppermost surface of the ILD layer, the hard mask layer comprising a first hard mask element on and aligned with the uppermost surface of the plurality of conductive lines, and a second hard mask element on and aligned with a region of the uppermost surface of the ILD layer, the The composition of the first hard mask element and the second hard mask element are different from each other, and the first hard mask element includes a lower etch stop layer and a layer above the lower etch stop layer, the lower etch stop layer is confined to the uppermost surface of the plurality of conductive lines; and a conductive via in an opening in the hard mask layer and over a portion of one of the plurality of conductive lines. Such as the integrated circuit structure of claim 13, wherein the lower etch stop layer is selected from the group consisting of SiOx and SiNx, and wherein the upper layer of the first hard mask element is selected from the group consisting of AlOx, HfOx, ZrOx and Metal oxides of the group consisting of TiOx. The integrated circuit structure of claim 13 or 14, wherein the first hard mask element is limited to the uppermost surface of the plurality of conductive lines. The integrated circuit structure of claim 13 or 14, wherein the first hard mask element extends to the uppermost surface of the ILD layer. The integrated circuit structure of claim 13 or 14, wherein a portion of the conductive via is located on a portion of the second hard mask element of the hard mask layer. The integrated circuit structure of claim 13 or 14, wherein the first hard mask element has an uppermost surface substantially coplanar with an uppermost surface of the second hard mask element. The integrated circuit structure of claim 13 or 14 further includes: a second ILD layer on the hard mask layer, wherein the conductive via is further in the opening of the second ILD layer. Such as the integrated circuit structure of claim 13 or 14, wherein one of the plurality of conductive lines is coupled to a lower conductive via structure, and the lower conductive via structure is connected to the lower metallization of the integrated circuit structure layer. A method of fabricating an integrated circuit structure, the method comprising: forming a plurality of conductive lines in an interlayer dielectric (ILD) layer over a substrate, wherein each of the plurality of conductive lines has a bulk portion comprising metal; processing the A plurality of conductive lines to form the uppermost surface comprising the metal and non-metal; forming a hard mask layer on the plurality of conductive lines and on the uppermost surface of the ILD layer, the hard mask layer included in the plurality of conductive lines a first hard mask element on and aligned with an uppermost surface, and a second hard mask element on and aligned with a region of the uppermost surface of the ILD layer, the first hard mask element and the second hard mask element The composition of the hard mask components is different from each other; forming an opening in the hard mask layer to expose a portion of one of the plurality of metal lines; modifying the exposed portion of the one of the plurality of metal lines to obtain from the removing the non-metal from the uppermost surface of the exposed portion of the one of the plurality of metal lines; and forming a conductive via in the opening in the hard mask layer and in the via of the one of the plurality of conductive lines Modify the exposed part. The method of claim 21, wherein modifying the exposed portion of the one of the plurality of metal lines includes leaving the metal of the uppermost surface. The method of claim 21, wherein modifying the exposed portion of the one of the plurality of metal lines includes removing the metal of the uppermost surface to form a recessed portion of the one of the plurality of metal lines. The method of claim 21, 22 or 23, wherein treating the plurality of conductive wires includes exposing the plurality of conductive wires to ammonia and a nonmetal selected from the group consisting of oxygen, silicon, germanium and boron source. The method of claim 21, 22 or 23, wherein forming the hard mask layer includes using Directed Self-Aggregation (DSA) or selective growth.

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