TWI805623B - Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication - Google Patents

Fin trim isolation with single gate spacing for advanced integrated circuit structure fabrication Download PDF

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TWI805623B
TWI805623B TW107134935A TW107134935A TWI805623B TW I805623 B TWI805623 B TW I805623B TW 107134935 A TW107134935 A TW 107134935A TW 107134935 A TW107134935 A TW 107134935A TW I805623 B TWI805623 B TW I805623B
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Taiwan
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fin
gate
layer
dielectric
fins
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TW107134935A
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Chinese (zh)
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TW201935614A (en
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百榮 何
克里斯多福 奧斯
麥可 哈頓朵夫
塔何 甘尼
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美商英特爾股份有限公司
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H01L29/7854—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection with rounded corners

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Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins, individual ones of the plurality of fins along a first direction. A plurality of gate structures is formed over the plurality of fins, individual ones of the gate structures along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of one of the plurality of gate structures is removed to expose a portion of each of the plurality of fins. The exposed portion of each of the plurality of fins is removed. An insulating layer is formed in locations of the removed portion of each of the plurality of fins.

Description

用於先進積體電路結構製造之具有單閘極間隙的鰭部修整隔離技術Fin Trimmed Isolation Technology with Single Gate Gap for Fabrication of Advanced Integrated Circuit Structures 相關技術的交互參考： Cross-references for related technologies:

本發明主張2017年11月30日提出申請之美國臨時申請案號62/593,149，標題為「先進積體電路結構製造(ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION)」的優先權，其整體內容在此做為參考資料而被併入本文中。 This application claims priority to U.S. Provisional Application No. 62/593,149, filed November 30, 2017, entitled "ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION", the entire contents of which are hereby incorporated by reference data are incorporated into this article.

本發明之實施例係有關先進積體電路結構製造，尤其有關10奈米節點和更小的積體電路結構製造及其所得結構的技術領域。 Embodiments of the present invention relate to the technical field of fabrication of advanced integrated circuit structures, particularly those at the 10nm node and smaller, and the resulting structures.

過去幾十年來，積體電路之特徵的按比例縮放(scaling)一直是不斷成長之半導體工業背後的驅動力。 按比例縮減到愈來愈小的特徵致使能夠增加半導體晶片之有限面積(real estate)上功能性單元的密度。例如，縮小(shrinking)電晶體尺寸允許晶片上數量增加之記憶體或邏輯裝置的併合，導致製造產品具有增加的容量。然而，更多容量(ever-more)的驅動不是沒有問題的。使各裝置的性能最佳化的需求變得愈來愈重要。 The scaling of features in integrated circuits has been the driving force behind the growing semiconductor industry for the past few decades. Scaling to smaller and smaller features enables an increase in the density of functional units on a limited real estate of a semiconductor wafer. For example, shrinking transistor dimensions allows the incorporation of increased numbers of memory or logic devices on a chip, resulting in manufactured products with increased capacity. However, ever-more drives are not without problems. The need to optimize the performance of each device is becoming more and more important.

習知製造過程和目前已知製造過程的變化性可能會限制使它們進一步延伸到10奈米節點或次10奈米節點範圍的可能性。因此，未來科技節點所需之功能性組件的製造在目前的製造過程上可能需要新方法的導入或新技術的整合，或者取代目前的製造過程。 The variability of conventional and currently known fabrication processes may limit the possibility of extending them further into the 10nm node or sub-10nm node range. Therefore, the manufacture of functional components required by future technology nodes may require the introduction of new methods or the integration of new technologies in the current manufacturing process, or replace the current manufacturing process.

本發明的實施例係在先進積體電路結構製造的領域中，尤其是在10奈米節點和更小的積體電路結構製造及其所得結構的技術領域中。在一範例中，方法包含形成複數個鰭部，該複數個鰭部之個別的一些沿著第一方向。複數個閘極結構被形成在該複數個鰭部之上，該複數個閘極結構之個別的一些沿著與該第一方向正交的第二方向。電介質材料結構被形成在該複數個閘極結構之相鄰的一些之間。該複數個閘極結構之其中一個閘極結構的部位被去除以使該複數個鰭部之各者的部位暴露出。該複數個鰭部之各者的露出部位被去除。絕緣層被形成在該複數個鰭部之各者的去除部位的位置中。 Embodiments of the present invention are in the field of advanced integrated circuit structure fabrication, particularly in the art of 10 nanometer node and smaller integrated circuit structure fabrication and resulting structures. In one example, the method includes forming a plurality of fins, individual ones of the plurality of fins are along a first direction. A plurality of gate structures are formed on the plurality of fins, individual ones of the plurality of gate structures are along a second direction orthogonal to the first direction. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. Portions of one of the plurality of gate structures are removed to expose portions of each of the plurality of fins. Exposed portions of each of the plurality of fins are removed. An insulating layer is formed in the location of the removed portion of each of the plurality of fins.

100:起始結構 100: Starting structure

102:層間電介質(ILD)層 102: Interlayer dielectric (ILD) layer

104:硬遮罩材料層 104: Hard mask material layer

106:圖案化後的遮罩 106: Patterned mask

108:間隔層 108: spacer layer

110:圖案化後的硬遮罩 110: Hard mask after patterning

200:間距四等分法 200: Spacing Quarters

202:光阻特徵 202: Photoresist features

204:第一骨幹(BB1)特徵 204: First Backbone (BB1) Features

206:第一間隔層(SP1)特徵 206: Features of the first spacer layer (SP1)

206’:變薄的第一間隔層特徵 206': Thinned first spacer layer feature

208:第二骨幹(BB2)特徵 208: Second Backbone (BB2) Features

210:第二間隔層(SP2)特徵 210: Second spacer layer (SP2) features

250:半導體鰭部 250: Semiconductor fins

300:合併鰭部間距四等分法 300:Combined Fin Spacing Quartering Method

302:光阻特徵 302: Photoresist features

304:第一骨幹(BB1)特徵 304: First Backbone (BB1) Features

306:第一間隔層(SP1)特徵 306: Features of the first spacer layer (SP1)

306’:變薄的第一間隔層特徵 306': Thinned first spacer layer feature

308:第二骨幹(BB2)特徵 308: Second Backbone (BB2) Features

310:第二間隔層(SP2)特徵 310: Second spacer layer (SP2) features

350:半導體鰭部 350: semiconductor fins

352:第一複數個半導體鰭部 352: first plurality of semiconductor fins

353:相鄰的個別半導體鰭部 353: adjacent individual semiconductor fins

354:第二複數個半導體鰭部 354: second plurality of semiconductor fins

355:相鄰的個別半導體鰭部 355: adjacent individual semiconductor fins

356,367:最接近的半導體鰭部 356, 367: closest semiconductor fins

402:圖案化後的硬遮罩層 402: Hard mask layer after patterning

404:半導體層 404: semiconductor layer

406:鰭部 406: fins

408:剩餘的鰭部殘材 408:Remaining fin residual material

502:鰭部 502: fins

502A:下鰭部部位(子鰭部) 502A: Lower fin part (female fin part)

502B:上鰭部部位 502B: Upper fin part

504:第一絕緣層 504: the first insulating layer

506:第二絕緣層 506: Second insulating layer

508:電介質填充材料 508: Dielectric Filling Material

552:第一鰭部 552: first fin

552A:下鰭部部位 552A: lower fin part

552B:上鰭部部位 552B: Upper fin part

554:肩部特徵 554: Shoulder features

562:第二鰭部 562: second fin

562A:下鰭部部位 562A: lower fin part

562B:上鰭部部位 562B: Upper fin part

564:肩部特徵 564: Shoulder Features

574:第一絕緣層 574: The first insulating layer

574A:第一末端部位 574A: first end site

574B:第二末端部位 574B: second terminal site

576:第二絕緣層 576: Second insulating layer

578:電介質填充材料 578: Dielectric Filling Materials

578A:上表面 578A: upper surface

602:鰭部 602: fins

602A:露出之上鰭部部位 602A: Exposing the upper fin part

604:第一絕緣層 604: first insulating layer

606:第二絕緣層 606: Second insulating layer

608:電介質填充材料 608: Dielectric filling material

702:鰭部 702: fins

702A:下鰭部部位 702A: lower fin part

702B:上鰭部部位 702B: Upper fin part

704:絕緣結構 704: Insulation structure

706:閘極結構 706:Gate structure

706A:犧牲閘極電介質層 706A: Sacrificial gate dielectric layer

706B:犧牲閘極 706B:Sacrificial gate

706C:硬遮罩 706C: Hard mask

708:電介質材料 708: Dielectric materials

710:硬遮罩材料 710:Hard mask material

712:凹入的硬遮罩材料 712:Recessed hard mask material

714:圖案化後的電介質材料 714: Dielectric material after patterning

714A:第一電介質間隔層 714A: first dielectric spacer layer

714B:第一電介質間隔層 714B: first dielectric spacer layer

714C:第二電介質間隔層 714C: second dielectric spacer layer

704A:第一部位 704A: First part

704A’:第二部位 704A': second part

704A”:第三部位 704A": the third part

910:嵌入的源極或汲極結構 910: Embedded source or drain structure

910A:底部表面 910A: Bottom surface

910B:頂部表面 910B: top surface

920:永久性閘極堆疊 920:Permanent Gate Stack

922:閘極電介質層 922: gate dielectric layer

924:第一閘極層 924: the first gate layer

926:閘極填充材料 926:Gate filling material

930:殘餘的多晶矽部位 930: Residual polysilicon parts

1000:積體電路結構 1000: integrated circuit structure

1001:塊狀矽基板 1001: bulk silicon substrate

1002:第一複數個半導體鰭部 1002: first plurality of semiconductor fins

1004:源極或汲極結構 1004: source or drain structure

1006:絕緣結構 1006: Insulation structure

1008:導電性接觸 1008: Conductive contact

1052:第二複數個半導體鰭部 1052: second plurality of semiconductor fins

1054:源極或汲極結構 1054: source or drain structure

1058:導電性接觸 1058: Conductive contact

1100:積體電路結構 1100: Integrated circuit structure

1102:第一鰭部 1102: first fin

1104:第一磊晶源極或汲極結構 1104: the first epitaxial source or drain structure

1104A:底部 1104A: Bottom

1104B:頂部 1104B: top

1105:外形 1105: shape

1108:第一導電電極 1108: first conductive electrode

1152:第二鰭部 1152: second fin

1154:第三磊晶源極或汲極結構 1154: The third epitaxial source or drain structure

1158:第二導電電極 1158: second conductive electrode

1201:矽基板 1201: Silicon substrate

1202:鰭部 1202: fins

1202A:下鰭部部位 1202A: lower fin part

1202B:上鰭部部位 1202B: Upper fin part

1204:電介質間隔層 1204: dielectric spacer

1204A:頂部表面 1204A: top surface

1206:凹入的鰭部 1206: Recessed fins

1208:磊晶源極或汲極結構 1208: Epitaxial source or drain structure

1208A:下部部位 1208A: lower part

1210:導電電極 1210: conductive electrode

1210A:導電性阻障層 1210A: Conductive barrier layer

1210B:導電性填充材料 1210B: Conductive Filling Material

1302:鰭部 1302: fins

1304:第一方向 1304: first direction

1306:柵格 1306: grid

1307:間隙 1307: gap

1308:第二方向 1308: the second direction

1310:鰭部 1310: fins

1312:切割部 1312: Cutting Department

1402:鰭部 1402: fins

1404:第一方向 1404: first direction

1406:閘極結構 1406:Gate structure

1408:第二方向 1408: Second direction

1410:電介質材料結構 1410: Dielectric Material Structure

1412:部位 1412: part

1414:部位 1414: parts

1416:光刻窗口 1416: Photolithographic window

1418:寬度 1418: width

1420:切割區域 1420: cutting area

1502:矽鰭部 1502: Silicon fin

1504:第一鰭部部位 1504: first fin part

1506:第二鰭部部位 1506: second fin part

1508:相對寬的切割部 1508: Relatively wide cutting section

1510:電介質填充材料 1510: Dielectric Filling Material

1512:閘極線 1512: gate line

1514:閘極電介質及閘極電極堆疊 1514: Gate Dielectric and Gate Electrode Stack

1516:電介質蓋層 1516: Dielectric Capping

1518:側壁間隔層 1518: side wall spacer

X,Y:寬度 X, Y: width

1600:積體電路結構 1600: Integrated circuit structure

1602:矽鰭部 1602: Silicon fins

1604:第一鰭部部位 1604: First fin part

1606:第二鰭部部位 1606: Second fin part

1608:相對窄的切割部 1608: relatively narrow cutting section

1610:電介質填充材料 1610: Dielectric Filling Material

1611:中心 1611: center

1612:閘極線 1612: gate line

1612A:第一閘極結構 1612A: First gate structure

1612B:第二閘極結構 1612B: Second gate structure

1612C:第三閘極結構 1612C: The third gate structure

1613A,1613B,1613C:中心 1613A, 1613B, 1613C: center

1614:閘極電介質及閘極電極堆疊 1614: Gate Dielectric and Gate Electrode Stack

1616:電介質蓋層 1616: Dielectric Capping

1618:側壁間隔層 1618: side wall spacer

1620:殘餘的間隔層材料 1620: Residual spacer material

1622:具有三條不作用閘極線的區域 1622: Region with three inactive gate lines

1650:第一方向 1650: First Direction

1652:第二方向 1652: Second direction

1660:閘極電極 1660: gate electrode

1662:高k閘極電介質層 1662: High-k gate dielectric layer

1664A:第一磊晶半導體區域 1664A: first epitaxial semiconductor region

1664B:第二磊晶半導體區域 1664B: second epitaxial semiconductor region

1664C:第三磊晶半導體區域 1664C: The third epitaxial semiconductor region

1680:鰭部 1680: fins

1682:基板 1682: Substrate

1684:鰭部末端或寬廣的鰭部切割部 1684: Fin tip or broad fin cut

1686:局部切割部 1686: Partial cutting department

1688:作用閘極電極 1688: Function gate electrode

1690:電介質插塞 1690: Dielectric plug

1692:電介質插塞 1692: Dielectric plug

1694:磊晶的源極或汲極區域 1694: Epitaxy source or drain region

1700:半導體鰭部 1700: Semiconductor fins

1700A:下鰭部部位 1700A: lower fin part

1700B:上鰭部部位 1700B: Upper fin part

1702:下面的基板 1702: Substrate below

1704:絕緣結構 1704: Insulation structure

1706A,1706B,1706C,1706D:局部鰭部隔離切割部 1706A, 1706B, 1706C, 1706D: partial fin isolation cut

1710:第一鰭部部位 1710: First fin part

1712:第二鰭部部位 1712:Second fin part

1800:第一半導體鰭部 1800: First semiconductor fin

1803A:下鰭部部位 1803A: lower fin part

1800B:上鰭部部位 1800B: Upper fin part

1802:第二半導體鰭部 1802: Second semiconductor fin

1802A:下鰭部部位 1802A: lower fin part

1802B:上鰭部部位 1802B: Upper fin part

1804:絕緣結構 1804: Insulation structure

1806:鰭部末端或寬廣的鰭部切割部 1806: Fin tip or broad fin cut

1808:局部切割部 1808: Partial cutting department

1810:殘餘部位 1810: Remnants

1820:切割深度 1820: Depth of cut

1900:鰭部 1900: fins

1902:基板 1902: Substrate

1904:鰭部末端或寬廣的鰭部切割部 1904: Fin tip or broad fin cut

1906:作用閘極電極位置 1906: Action gate electrode position

1908:假性閘極電極位置 1908: False Gate Electrode Position

1910:磊晶的源極或汲極區域 1910: Epitaxy source or drain regions

1912:層間電介質材料 1912: Interlayer Dielectric Materials

1920:開口 1920: opening

2000:鰭部 2000: Fins

2002:基板 2002: Substrate

2004:局部切割部 2004: Partial Cutting Department

2006:作用閘極電極位置 2006: The location of the active gate electrode

2008:假性閘極電極位置 2008: False Gate Electrode Position

2010:磊晶的源極或汲極區域 2010: Epitaxy source or drain region

2012:層間電介質材料 2012: Interlayer Dielectric Materials

2020:開口 2020: opening

2100:起始結構 2100: Starting structure

2102:第一鰭部 2102: first fin

2104:基板 2104: Substrate

2106:鰭部末端 2106: fin end

2108:第一作用閘極電極位置 2108: First action gate electrode position

2110:第一假性閘極電極位置 2110: First false gate electrode position

2112:磊晶的N型源極或汲極區域 2112: N-type source or drain region of epitaxy

2114:層間電介質材料 2114: interlayer dielectric material

2122:第二鰭部 2122: Second fin

2126:鰭部末端 2126: fin end

2128:第二作用閘極電極位置 2128: second action gate electrode position

2130:第二假性閘極電極位置 2130: Second pseudo-gate electrode position

2132:磊晶的P型源極或汲極區域 2132: Epitaxy P-type source or drain region

2134:層間電介質材料 2134: interlayer dielectric material

2136:開口 2136: opening

2140:材料襯墊 2140: material liner

2142:保護冠層 2142: Protective Canopy

2144:硬遮罩材料 2144: Hard mask material

2146:光刻遮罩或遮罩堆疊 2146: Lithographic mask or mask stack

2148:第二材料襯墊 2148: second material liner

2150:第二硬遮罩材料 2150: second hard mask material

2152:絕緣填充材料 2152: insulating filling material

2154:凹入的絕緣填充材料 2154: Recessed insulating filler material

2156:第三材料襯墊 2156: third material liner

2302:半導體鰭部 2302: Semiconductor fins

2304:基板 2304: Substrate

2308A:淺的電介質插塞 2308A: Shallow Dielectric Plug

2308B:深的電介質插塞 2308B: Deep Dielectric Plug

2308C:深的電介質插塞 2308C: Deep Dielectric Plug

2308D:NMOS插塞 2308D: NMOS plug

2308E:NMOS插塞 2308E: NMOS plug

2308F:PMOS插塞 2308F: PMOS plug

2308G:PMOS插塞 2308G: PMOS plug

2350:伸張應力誘發氧化物層 2350: Tensile stress induced oxide layer

2400:半導體鰭部 2400: Semiconductor fins

2402,2404:末端 2402, 2404: end

2450:半導體鰭部 2450: Semiconductor fins

2452,2454:末端 2452, 2454: end

2502:鰭部 2502: fins

2504:第一方向 2504: first direction

2506:閘極結構 2506:Gate structure

2508:第二方向 2508: Second direction

2510:電介質材料結構 2510: Dielectric Material Structure

2512:部位 2512: parts

2513:部位 2513: parts

2520:切割區域 2520: cutting area

2530:絕緣結構 2530: Insulation structure

2600A,2600B,2600C:部位 2600A, 2600B, 2600C: parts

2602:溝槽隔離結構 2602: Trench isolation structure

2602A:第一絕緣層 2602A: The first insulating layer

2602B:第二絕緣層 2602B: Second insulating layer

2602C:絕緣填充材料 2602C: insulating filling material

2700A,2700B:積體電路結構 2700A, 2700B: integrated circuit structure

2702:第一矽鰭部 2702: first silicon fin

2703:第一方向 2703: first direction

2704:第二矽鰭部 2704: second silicon fin

2706:絕緣材料 2706: insulating material

2708:閘極線 2708: Gate line

2708A:第一側 2708A: First side

2708B:第二側 2708B: second side

2708C:第一末端 2708C: first end

2708D:第二末端 2708D: second end

2709:第二方向 2709:Second direction

2710:中斷 2710: interrupt

2712:電介質插塞 2712: Dielectric plug

2714:溝槽接觸 2714: Groove contact

2715:位置 2715: location

2716:電介質間隔層 2716: dielectric spacer

2718:第二溝槽接觸 2718: Second trench contact

2719:位置 2719: location

2720:第二電介質間隔層 2720: second dielectric spacer layer

2722:高k閘極電介質層 2722: High-k gate dielectric layer

2724:閘極電極 2724: gate electrode

2726:電介質蓋層 2726: Dielectric Capping

2752:第一矽鰭部 2752: first silicon fin

2753:第一方向 2753: first direction

2754:第二矽鰭部 2754: second silicon fin

2756:絕緣材料 2756: insulating material

2758:閘極線 2758: gate line

2758A:第一側 2758A: First side

2758B:第二側 2758B: second side

2758C:第一末端 2758C: first end

2758D:第二末端 2758D: second end

2759:第二方向 2759:Second direction

2760:中斷 2760: interrupt

2762:電介質插塞 2762: Dielectric plug

2764:溝槽接觸 2764: Groove contact

2765:位置 2765: location

2766:電介質間隔層 2766: dielectric spacer

2768:第二溝槽接觸 2768: Second trench contact

2769:位置 2769:location

2770:第二電介質間隔層 2770: second dielectric spacer

2772:高k閘極電介質層 2772: High-k gate dielectric layer

2774:閘極電極 2774: gate electrode

2776:電介質蓋層 2776: Dielectric Capping

2802:閘極線 2802: Gate line

2804:結構 2804: structure

2806:假性閘極電極 2806: False gate electrode

2808:電介質蓋部 2808: Dielectric cover

2810:電介質間隔層 2810: dielectric spacer

2812:電介質材料 2812: Dielectric material

2814:遮罩 2814: mask

2816:縮減後的電介質間隔層 2816: Reduced Dielectric Spacers

2818:腐蝕後的電介質材料部位 2818: Dielectric material parts after corrosion

2820:剩餘之假性閘極材料 2820: Remaining dummy gate material

2822:硬遮罩 2822: hard mask

2830:電介質插塞 2830: Dielectric plug

2902:鰭部 2902: fins

2902A:上鰭部部位 2902A: Upper fin part

2902B:下鰭部部位 2902B: lower fin part

2902C:頂部 2902C: top

2902D:側壁 2902D: side wall

2904:半導體基板 2904: Semiconductor substrate

2906:隔離結構 2906: Isolation structure

2906A:第二絕緣材料 2906A: Second insulating material

2906B:第二絕緣材料 2906B: Second insulating material

2906C:絕緣材料 2906C: insulating material

2907:頂部表面 2907: Top surface

2908:半導體材料 2908: Semiconductor materials

2910:閘極電介質層 2910: Gate Dielectric Layer

2911:中介之額外的閘極電介質層 2911: Additional gate dielectric layer for intermediary

2912:閘極電極 2912: gate electrode

2912A:功函數層 2912A: work function layer

2912B:導電性填充金屬層 2912B: Conductive Fill Metal Layer

2916:第一源極或汲極區域 2916: The first source or drain region

2918:第二源極或汲極區域 2918: Second source or drain region

2920:第一電介質間隔層 2920: First Dielectric Spacer

2922:第二電介質間隔層 2922: Second Dielectric Spacer

2924:絕緣蓋部 2924: Insulation cover

3000:鰭部 3000: fins

3000A:下鰭部部位 3000A: lower fin part

3000B:上鰭部部位 3000B: Upper fin part

3000C:頂部 3000C: top

3000D:側壁 3000D: side wall

3002:半導體基板 3002: Semiconductor substrate

3004:隔離結構 3004: isolation structure

3004A,3004B:第二絕緣材料 3004A, 3004B: second insulating material

3004C:絕緣材料 3004C: insulating material

3005:頂部表面 3005: top surface

3006:佔位件閘極電極 3006: placeholder gate electrode

3008:方向 3008: direction

3010:氧化部位 3010: oxidation site

3012:部位 3012: part

3014:閘極電介質層 3014: gate dielectric layer

3016:永久性閘極電極 3016: permanent gate electrode

3016A:功函數層 3016A: work function layer

3016B:導電性填充金屬層 3016B: Conductive filled metal layer

3018:絕緣閘極蓋層 3018: Insulated gate cap

3100:積體電路結構 3100: Integrated circuit structure

3102:閘極結構 3102: gate structure

3102A:鐵電或反鐵電多晶材料層 3102A: Ferroelectric or antiferroelectric polycrystalline material layer

3102B:導電層 3102B: conductive layer

3102C:閘極填充層 3102C: Gate fill layer

3103:非晶電介質層 3103: Amorphous dielectric layer

3104:基板 3104: Substrate

3106:半導體通道結構 3106: Semiconductor channel structure

3108:源極區 3108: source region

3110:汲極區 3110: Drain area

3112:源極或汲極接觸 3112: Source or drain contact

3112A:阻障層 3112A: barrier layer

3112B:導電性溝槽填充材料 3112B: Conductive trench fill material

3114:層間電介質層 3114: interlayer dielectric layer

3116:閘極電介質間隔層 3116: gate dielectric spacer

3149:位置 3149: location

3150:積體電路結構 3150: Integrated circuit structure

3152:閘極結構 3152: gate structure

3152A:鐵電或反鐵電多晶材料層 3152A: Ferroelectric or antiferroelectric polycrystalline material layer

3152B:導電層 3152B: conductive layer

3152C:閘極填充層 3152C: gate fill layer

3153:非晶電介質層 3153: Amorphous dielectric layer

3154:基板 3154: Substrate

3156:半導體通道結構 3156: Semiconductor channel structure

3158:突起的源極區域 3158: Protruding source region

3160:突起的汲極區域 3160: raised drain region

3162:源極或汲極接觸 3162: Source or drain contact

3162A:阻障層 3162A: barrier layer

3162B:導電性溝槽填充材料 3162B: Conductive trench fill material

3164:層間電介質層 3164: interlayer dielectric layer

3166:閘極電介質間隔層 3166: gate dielectric spacer

3199:位置 3199: location

3200:半導體鰭部 3200: Semiconductor fins

3204:作用閘極線 3204: Action gate line

3206:假性閘極線 3206: false gate line

3208:間隙 3208: Clearance

3251,3252,3253,3254:源極或汲極區域 3251, 3252, 3253, 3254: source or drain region

3260:基板 3260: Substrate

3262:半導體鰭部 3262: Semiconductor fins

3264:作用閘極線 3264: Action gate line

3266:假性閘極線 3266: false gate line

3268:嵌入的源極或汲極結構 3268: Embedded source or drain structure

3270:電介質層 3270: dielectric layer

3272:閘極電介質結構 3272: Gate Dielectric Structure

3274:功函數閘極電極部 3274: work function gate electrode part

3276:填充閘極電極部 3276: filling the gate electrode part

3278:電介質覆蓋層 3278: Dielectric Overlay

3280:電介質間隔層 3280: dielectric spacer

3297:溝槽接觸材料 3297: Trench contact material

3298:鐵電或反鐵電多晶材料層 3298: Layers of ferroelectric or antiferroelectric polycrystalline materials

3299:非晶氧化物層 3299: Amorphous oxide layer

3300:半導體作用區域 3300: semiconductor active area

3302:第一NMOS裝置 3302: first NMOS device

3304:第二NMOS裝置 3304: Second NMOS device

3306:閘極電介質層 3306: gate dielectric layer

3308:第一閘極電極導電層 3308: first gate electrode conductive layer

3310:閘極電極導電填充 3310: Gate Electrode Conductive Fill

3312:區域 3312:Area

3320:半導體作用區域 3320: semiconductor active area

3322:第一PMOS裝置 3322: First PMOS device

3324:第二PMOS裝置 3324:Second PMOS device

3326:閘極電介質層 3326: gate dielectric layer

3328:第一閘極電極導電層 3328: first gate electrode conductive layer

3330:閘極電極導電填充 3330: Gate Electrode Conductive Fill

3332:區域 3332:Area

3350:半導體作用區域 3350: semiconductor active area

3352:第一NMOS裝置 3352: First NMOS device

3354:第二NMOS裝置 3354: Second NMOS device

3356:閘極電介質層 3356: gate dielectric layer

3358:第一閘極電極導電層 3358: first gate electrode conductive layer

3359:第二閘極電極導電層 3359: second gate electrode conductive layer

3360:閘極電極導電填充 3360: Gate Electrode Conductive Fill

3370:半導體作用區域 3370: semiconductor active area

3372:第一PMOS裝置 3372: First PMOS device

3374:第二PMOS裝置 3374:Second PMOS device

3376:閘極電介質層 3376: gate dielectric layer

3378A:閘極電極導電層 3378A: Gate electrode conductive layer

3378B:閘極電極導電層 3378B: Gate electrode conductive layer

3380:閘極電極導電填充 3380: Gate Electrode Conductive Fill

3400:半導體作用區域 3400: semiconductor active area

3402:第一NMOS裝置 3402: First NMOS device

3403:第三NMOS裝置 3403: Third NMOS device

3404:第二NMOS裝置 3404: Second NMOS device

3406:閘極電介質層 3406: gate dielectric layer

3408:第一閘極電極導電層 3408: first gate electrode conductive layer

3409:第二閘極電極導電層 3409: second gate electrode conductive layer

3410:閘極電極導電填充 3410: Gate Electrode Conductive Fill

3412:區域 3412:Area

3420:半導體作用區域 3420: semiconductor active area

3422:第一PMOS裝置 3422: First PMOS device

3423:第三PMOS裝置 3423: Third PMOS device

3424:第二PMOS裝置 3424:Second PMOS device

3426:閘極電介質層 3426: gate dielectric layer

3428A:閘極電極導電層 3428A: Gate electrode conductive layer

3428B:閘極電極導電層 3428B: gate electrode conductive layer

3430:閘極電極導電填充 3430: Gate Electrode Conductive Fill

3432:區域 3432:Area

3450:半導體作用區域 3450: semiconductor active area

3452:第一NMOS裝置 3452: First NMOS device

3453:第三NMOS裝置 3453: Third NMOS device

3454:第二NMOS裝置 3454:Second NMOS device

3456:閘極電介質層 3456: gate dielectric layer

3458:第一閘極電極導電層 3458: first gate electrode conductive layer

3459:第二閘極電極導電層 3459: second gate electrode conductive layer

3460:閘極電極導電填充 3460: Gate Electrode Conductive Fill

3462:區域 3462:Area

3470:半導體作用區域 3470: semiconductor active area

3472:第一PMOS裝置 3472: First PMOS device

3473:第三PMOS裝置 3473: Third PMOS device

3474:第二PMOS裝置 3474:Second PMOS device

3476:閘極電介質層 3476: gate dielectric layer

3478A:閘極電極導電層 3478A: Gate electrode conductive layer

3478B:閘極電極導電層 3478B: Gate electrode conductive layer

3480:閘極電極導電填充 3480: Gate Electrode Conductive Fill

3482:區域 3482:Area

3502:第一半導體鰭部 3502: First Semiconductor Fin

3504:第二半導體鰭部 3504: Second semiconductor fin

3506:閘極電介質層 3506: gate dielectric layer

3508:P型金屬層 3508: P-type metal layer

3509:部位 3509: parts

3510:N型金屬層 3510: N-type metal layer

3512:導電填充金屬層 3512: Conductive fill metal layer

3602:第一半導體鰭部 3602: first semiconductor fin

3604:第二半導體鰭部 3604: Second semiconductor fin

3606:閘極電介質層 3606: gate dielectric layer

3608:第一P型金屬層 3608: The first P-type metal layer

3609:部位 3609: part

3610:第二P型金屬層 3610: Second P-type metal layer

3611:接縫 3611: seam

3612:導電填充金屬層 3612: Conductive fill metal layer

3614:N型金屬層 3614: N-type metal layer

3700:積體電路結構 3700: Integrated circuit structure

3702:半導體基板 3702: Semiconductor substrate

3704:N井區域 3704: N well area

3706:第一半導體鰭部 3706: First Semiconductor Fins

3708:P井區域 3708:P well area

3710:第二半導體鰭部 3710: Second semiconductor fin

3712:溝槽隔離結構 3712: Trench isolation structure

3714:閘極電介質層 3714: gate dielectric layer

3716:導電層 3716: conductive layer

3718:p型金屬閘極層 3718: p-type metal gate layer

3719:頂部表面 3719: top surface

3720:n型金屬閘極層 3720: n-type metal gate layer

3721:頂部表面 3721: top surface

3722:層間電介質(ILD)層 3722: interlayer dielectric (ILD) layer

3724:開口 3724: opening

3726:側壁 3726: side wall

3730:導電填充金屬層 3730: Conductive fill metal layer

3732:熱或化學氧化物層 3732: thermal or chemical oxide layer

3800:基板 3800: Substrate

3802:層間電介質(ILD)層 3802: interlayer dielectric (ILD) layer

3804:第一半導體鰭部 3804: First Semiconductor Fin

3806:第二半導體鰭部 3806: Second semiconductor fin

3808:開口 3808: opening

3810:閘極電介質層 3810: gate dielectric layer

3811:熱或化學氧化物層 3811: thermal or chemical oxide layer

3812:溝槽隔離結構 3812: Trench isolation structure

3814:導電層 3814: conductive layer

3815:圖案化後導電層 3815: conductive layer after patterning

3816:p型金屬閘極結構 3816:p-type metal gate structure

3817:p型金屬閘極層 3817: p-type metal gate layer

3818:電介質蝕刻停止層 3818: Dielectric etch stop layer

3819:圖案化後的電介質蝕刻停止層 3819: Dielectric etch stop layer after patterning

3820:遮罩 3820: mask

3822:n型金屬閘極層 3822: n-type metal gate layer

3824:側壁 3824: side wall

3826:導電填充金屬層 3826: Conductive fill metal layer

3902:第一閘極結構 3902: The first gate structure

3903:電介質側壁間隔層 3903: Dielectric sidewall spacer

3904:第一鰭部 3904: first fin

3906:絕緣材料 3906: insulating material

3908:第一源極或汲極區域 3908: The first source or drain region

3910:第二源極或汲極區域 3910: Second source or drain region

3952:第二閘極結構 3952:Second gate structure

3953:電介質側壁間隔層 3953: Dielectric Sidewall Spacers

3954:第二鰭部 3954:Second fin

3958:第三源極或汲極區域 3958: Third source or drain region

3960:第四源極或汲極區域 3960: Fourth source or drain region

3962:第二金屬矽化物層 3962:Second Metal Silicide Layer

3902A:第一側 3902A: First side

3902B:第二側 3902B: Second side

3904A:頂部 3904A: top

3952A:第一側 3952A: First side

3952B:第二側 3952B: Second side

3954A:頂部 3954A: top

3970:第三溝槽接觸結構 3970: The third trench contact structure

3972:第四溝槽接觸結構 3972: The fourth trench contact structure

4000:積體電路結構 4000: Integrated circuit structure

4002:鰭部 4002: fins

4004:閘極電介質層 4004: gate dielectric layer

4006:閘極電極 4006: gate electrode

4006A:第一側 4006A: First side

4006B:第二側 4006B: second side

4008:共形導電層 4008: Conformal conductive layer

4010:導電填充 4010: conductive filling

4012:電介質蓋部 4012: Dielectric cover

4013:電介質間隔層 4013: dielectric spacer

4014:第一半導體源極或汲極區域 4014: first semiconductor source or drain region

4016:第二半導體源極或汲極區域 4016: Second semiconductor source or drain region

4018:第一溝槽接觸結構 4018: The first trench contact structure

4020:第二溝槽接觸結構 4020: Second trench contact structure

4022:U型金屬層 4022: U-shaped metal layer

4024:T型金屬層 4024: T-shaped metal layer

4026:第三金屬層 4026: the third metal layer

4028:第一溝槽接觸介層 4028: First trench contact via

4030:第二溝槽接觸介層 4030: Second trench contact via

4032:金屬矽化物層 4032: metal silicide layer

4050:積體電路結構 4050: Integrated circuit structure

4052:鰭部 4052: fins

4054:閘極電介質層 4054: gate dielectric layer

4056:閘極電極 4056: gate electrode

4056A:第一側 4056A: First side

4056B:第二側 4056B: second side

4058:共形導電層 4058: Conformal conductive layer

4060:導電填充 4060: conductive filling

4062:電介質蓋部 4062: Dielectric cover

4063:電介質間隔層 4063: dielectric spacer

4064:第一半導體源極或汲極區域 4064: first semiconductor source or drain region

4065:凹部 4065: concave part

4066:第二半導體源極或汲極區域 4066: Second semiconductor source or drain region

4067:凹部 4067: concave part

4068:第一溝槽接觸結構 4068: First Trench Contact Structure

4070:第二溝槽接觸結構 4070: Second Trench Contact Structure

4072:U型金屬層 4072: U-shaped metal layer

4074:T型金屬層 4074: T-shaped metal layer

4076:第三金屬層 4076: the third metal layer

4078:第一溝槽接觸介層 4078: First trench contact via

4080:第二溝槽接觸介層 4080: Second trench contact via

4082:金屬矽化物層 4082: metal silicide layer

4100:半導體結構 4100: Semiconductor Structures

4102:閘極結構 4102: gate structure

4102A:閘極電介質層 4102A: gate dielectric layer

4102B:功函數層 4102B: work function layer

4102C:閘極填充 4102C: Gate Fill

4104:基板 4104: Substrate

4108:源極區域 4108: source region

4110:汲極區域 4110: drain area

4112:源極或汲極接觸 4112: Source or drain contact

4112A:高純度金屬層 4112A: High-purity metal layer

4112B:導電性溝槽填充材料 4112B: Conductive trench fill material

4114:層間電介質層 4114: interlayer dielectric layer

4116:閘極電介質間隔層 4116: gate dielectric spacer

4149:表面 4149: surface

4150:半導體結構 4150: Semiconductor Structures

4152:閘極結構 4152: gate structure

4152A:層間電介質層 4152A: interlayer dielectric layer

4152B:功函數層 4152B: work function layer

4152C:閘極填充 4152C: Gate Fill

4154:基板 4154: Substrate

4158:源極區域 4158: source region

4160:汲極區域 4160: drain area

4162:源極或汲極接觸 4162: Source or drain contact

4162A:高純度金屬層 4162A: High-purity metal layer

4162B:導電性溝槽填充材料 4162B: Conductive trench fill material

4164:層間電介質層 4164: interlayer dielectric layer

4166:閘極電介質間隔層 4166: gate dielectric spacer

4199:表面 4199: surface

4200:半導體鰭部 4200: Semiconductor fins

4204:作用閘極線 4204: Action gate line

4206:假性閘極線 4206: False gate line

4208:間隙 4208: Clearance

4251:第一半導體源極或汲極區域 4251: first semiconductor source or drain region

4252:第二半導體源極或汲極區域 4252: Second semiconductor source or drain region

4253:第三半導體源極或汲極區域 4253: Third semiconductor source or drain region

4254:第四半導體源極或汲極區域 4254: Fourth semiconductor source or drain region

4300:基板 4300: Substrate

4302:半導體鰭部 4302: Semiconductor fins

4304:作用閘極線 4304: Action gate line

4306:假性閘極線 4306: False gate line

4308:源極或汲極結構 4308: source or drain structure

4310:電介質層 4310: dielectric layer

4312:閘極電介質層 4312: gate dielectric layer

4314:功函數閘極電極部 4314: work function gate electrode part

4316:填充閘極電極部 4316: filling the gate electrode part

4318:電介質覆蓋層 4318: Dielectric Overlay

4320:電介質間隔層 4320: dielectric spacer

4332:開口 4332: opening

4332:腐蝕後之嵌入的源極或汲極結構 4332: Embedded source or drain structure after etching

4334:溝槽接觸 4334: Groove contact

4336:金屬接觸層 4336: metal contact layer

4336A:第一半導體源極或汲極結構 4336A: The first semiconductor source or drain structure

4336B:位置 4336B: location

4338:導電性填充材料 4338: Conductive Filling Material

4400:基板 4400: Substrate

4402:鰭部 4402: fins

4404:溝槽隔離材料 4404: Trench isolation material

4406:嵌入的源極或汲極結構 4406: Embedded source or drain structure

4408:溝槽接觸 4408: Groove contact

4410:電介質層 4410: dielectric layer

4412:金屬接觸層 4412: metal contact layer

4414:導電性填充材料 4414: Conductive Filling Material

4500:積體電路結構 4500: Integrated circuit structure

4502,4502A:鰭部 4502, 4502A: fins

4504:第一方向 4504: first direction

4506:閘極結構 4506: gate structure

4508:第二方向 4508: Second direction

4510:電介質側壁間隔層 4510: Dielectric sidewall spacer

4512:溝槽接觸結構 4512: trench contact structure

4514A,4514B:接觸插塞 4514A, 4514B: contact plug

4516:下電介質材料 4516: lower dielectric material

4516A,4516B:接觸插塞 4516A, 4516B: contact plug

4518:上硬遮罩材料 4518: Upper hard mask material

4520:下導電結構 4520: lower conductive structure

4522:電介質蓋部 4522: Dielectric cover

4524:閘極電極 4524: gate electrode

4526:閘極電介質層 4526: gate dielectric layer

4528:電介質蓋部 4528: Dielectric cover

4602:鰭部 4602: fins

4604:第一方向 4604: first direction

4606:擴散區域 4606: Diffusion area

4608:閘極結構 4608: gate structure

4609:犧牲或假性閘極堆疊和電介質間隔層 4609: Sacrificial or Dummy Gate Stacks and Dielectric Spacers

4610:第二方向 4610: Second direction

4612:犧牲材料結構 4612:Sacrificial material structure

4614,4614’:接觸插塞 4614, 4614’: contact plug

4616:下電介質材料 4616: lower dielectric material

4618:硬遮罩材料 4618: Hard mask material

4620:開口 4620: opening

4622:溝槽接觸結構 4622: trench contact structure

4624:上硬遮罩材料 4624: Upper hard mask material

4626:下導電結構 4626: lower conductive structure

4628:電介質蓋部 4628: Dielectric cover

4630:永久性閘極結構 4630: Permanent gate structure

4632:永久性閘極電介質層 4632: Permanent gate dielectric layer

4634:永久性閘極電極層或堆疊 4634: Permanent Gate Electrode Layer or Stack

4636:電介質蓋部 4636: Dielectric cover

4700A,4700B:半導體結構或裝置 4700A, 4700B: Semiconductor structures or devices

4702:基板 4702: Substrate

4704:擴散或作用區域 4704: Diffusion or Area of Effect

4704C:非平面擴散或作用區域 4704C: non-planar diffusion or area of action

4706:隔離區域 4706: Quarantine area

4708A,4708B,4708C:閘極線 4708A, 4708B, 4708C: gate line

4710A,4710B:溝槽接觸 4710A, 4710B: groove contact

4712A,4712B:溝槽接觸介層 4712A, 4712B: Trench Contact Via

4714:閘極接觸 4714: Gate contact

4716:上覆的閘極接觸介層 4716:Overlying gate contact via

4750:閘極電極 4750: gate electrode

4752:閘極電介質層 4752: gate dielectric layer

4754:電介質蓋層 4754: Dielectric Capping

4760:上覆的金屬互連部 4760: Overlying Metal Interconnects

4770:層間電介質堆疊或層 4770: Interlayer Dielectric Stacks or Layers

4800A,4800B:半導體結構或裝置 4800A, 4800B: Semiconductor structures or devices

4802:基板 4802: Substrate

4804:擴散或作用區域 4804: Diffusion or Area of Effect

4804B:非平面擴散或作用區域 4804B: non-planar diffusion or area of action

4806:隔離區域 4806: Isolation area

4808A,4808B,4808C:閘極線 4808A, 4808B, 4808C: gate line

4810A,4810B:溝槽接觸 4810A, 4810B: Groove contact

4812A,4812B:溝槽接觸介層 4812A, 4812B: Trench Contact Via

4816:閘極接觸介層 4816: gate contact via

4850:閘極電極 4850: gate electrode

4852:閘極電介質層 4852: gate dielectric layer

4854:電介質蓋層 4854: Dielectric Capping

4860:上覆的金屬互連部 4860: Overlying Metal Interconnects

4870:層間電介質堆疊或層 4870: Interlayer Dielectric Stacks or Layers

4900:半導體結構 4900: Semiconductor Structures

4902:基板 4902: Substrate

4908A-E:閘極堆疊結構 4908A-E: Gate stack structure

4910A-C:溝槽接觸 4910A-C: Groove contact

4911A-C:凹入的溝槽接觸 4911A-C: Recessed trench contacts

4920:電介質間隔層 4920: Dielectric Spacer

4922:絕緣蓋層 4922: insulating cover

4924:絕緣蓋層 4924: insulating cover

4930:層間電介質(ILD) 4930: Interlayer Dielectric (ILD)

4932:硬遮罩 4932: hard mask

4934:金屬(0)溝槽 4934: metal (0) groove

4936:開口 4936: opening

5000:積體電路結構 5000: Integrated circuit structure

5002:半導體基板或鰭部 5002: Semiconductor substrates or fins

5004:閘極線 5004: Gate line

5005:閘極堆疊 5005: gate stack

5006:閘極絕緣蓋層 5006: gate insulating cover layer

5008:電介質間隔層 5008: dielectric spacer

5010:溝槽接觸 5010: groove contact

5011:導電接觸結構 5011: Conductive contact structure

5012:溝槽接觸絕緣蓋層 5012: trench contact insulating cover

5014:閘極接觸介層 5014: Gate contact via

5016:溝槽接觸介層 5016: Trench contact via

5100A,5100B,5100C:積體電路結構 5100A, 5100B, 5100C: integrated circuit structure

5102:鰭部 5102: fins

5102A:頂部 5102A: top

5104:第一閘極電介質層 5104: first gate dielectric layer

5106:第二閘極電介質層 5106: Second gate dielectric layer

5108:第一閘極電極 5108: first gate electrode

5109A:共形導電層 5109A: Conformal Conductive Layer

5109B:導電性填充材料 5109B: Conductive Filling Material

5110:第二閘極電極 5110: second gate electrode

5112:第一側 5112: first side

5114:第二側 5114: second side

5117A,5117B:底部表面 5117A, 5117B: bottom surface

5118:頂部表面 5118: top surface

5120:第一電介質間隔層 5120: first dielectric spacer layer

5122:第二電介質間隔層 5122: second dielectric spacer

5124:半導體源極或汲極區域 5124: Semiconductor source or drain region

5126:溝槽接觸結構 5126: trench contact structure

5128:絕緣蓋部 5128: Insulation cover

5128A,5128B,5128C:底部表面 5128A, 5128B, 5128C: bottom surface

5130:導電結構 5130: conductive structure

5132:凹部 5132: concave part

5134:U形金屬層 5134: U-shaped metal layer

5136:T形金屬層 5136: T-shaped metal layer

5138:第三金屬層 5138: the third metal layer

5140:金屬矽化物層 5140: metal silicide layer

5150:導電介層 5150: conductive interlayer

5152:開口 5152: opening

5154:腐蝕部位 5154: corrosion site

5160:導電介層 5160: conductive interlayer

5162:開口 5162: opening

5164:腐蝕部位 5164: corrosion site

5170:電短路的接觸 5170: Electrically Shorted Contacts

5200:半導體結構或裝置 5200: Semiconductor structures or devices

5208A-5208C:閘極結構 5208A-5208C: gate structure

5210A,5210B:溝槽接觸 5210A, 5210B: Groove contact

5250:半導體結構或裝置 5250: Semiconductor structures or devices

5258A-5258C:閘極結構 5258A-5258C: gate structure

5260A,5260B:溝槽接觸 5260A, 5260B: groove contact

5290:溝槽接觸介層 5290: Trench contact via

5300:起始結構 5300: Starting structure

5302:基板或鰭部 5302: Substrate or fin

5304:閘極堆疊 5304: gate stack

5306:閘極電介質層 5306: gate dielectric layer

5308:共形導電層 5308: Conformal conductive layer

5310:導電填充材料 5310: Conductive Filling Material

5312:熱或化學氧化物層 5312: thermal or chemical oxide layer

5314:電介質間隔層 5314: dielectric spacer

5316:層間電介質(ILD)層 5316: interlayer dielectric (ILD) layer

5318:遮罩 5318: mask

5320:開口 5320: opening

5322:凹洞 5322: pit

5324:凹入的閘極堆疊 5324: Recessed Gate Stack

5326:第一絕緣層 5326: The first insulating layer

5328:第一部位 5328: the first part

5330:絕緣閘極蓋部結構 5330: Insulated Gate Cap Structure

5330A,5330B,5330C,5330D:材料 5330A, 5330B, 5330C, 5330D: Material

5332,5332A,5332B,5332C:接縫 5332, 5332A, 5332B, 5332C: seams

5402:骨幹特徵 5402: Backbone feature

5404,5404’:第一間隔層特徵 5404,5404': first interval layer features

5406:第二間隔層特徵 5406:Second spacer layer feature

5407:互補區域 5407: complementary area

5408:溝槽 5408: Groove

5500:積體電路結構 5500: Integrated circuit structure

5502:基板 5502: Substrate

5504:層間電介質(ILD)層 5504: interlayer dielectric (ILD) layer

5506,5506S,5506C,5506B:導電互連線 5506, 5506S, 5506C, 5506B: Conductive interconnection wire

5508:導電阻障層 5508: conductive barrier layer

5510:導電填充材料 5510: Conductive Filling Material

5550:積體電路結構 5550: Integrated circuit structure

5552:基板 5552: Substrate

5554:第一層間電介質(ILD)層 5554: First interlayer dielectric (ILD) layer

5556:第一複數條導電互連線 5556: first plurality of conductive interconnect lines

5558:導電阻障層 5558: conductive barrier layer

5560:導電填充材料 5560: Conductive Filling Material

5574:第二層間電介質(ILD)層 5574: Second interlayer dielectric (ILD) layer

5576:第二複數條導電互連線 5576: second plurality of conductive interconnect lines

5578:導電阻障層 5578: Conductive barrier layer

5580:導電填充材料 5580: Conductive Filling Material

5600:積體電路結構 5600: Integrated circuit structure

5602:基板 5602: Substrate

5604:第一層間電介質(ILD)層 5604: First interlayer dielectric (ILD) layer

5606:第一複數條導電互連線 5606: first plurality of conductive interconnecting lines

5606A:導電互連線 5606A: Conductive Interconnecting Wire

5607:下面的介層 5607: Interposer below

5608:第一導電阻障層 5608: first conductive barrier layer

5610:第一導電填充材料 5610: First Conductive Filling Material

5614:第二ILD層 5614: Second ILD layer

5616:第二複數條導電互連線 5616: second plurality of conductive interconnecting lines

5616A:導電互連線 5616A: Conductive Interconnecting Wire

5617:下面的介層 5617: Interposer below

5618:第二導電阻障層 5618: second conductive barrier layer

5620:第二導電填充材料 5620: Second conductive filling material

5622:蝕刻停止層 5622: etch stop layer

5650:積體電路結構 5650: Integrated circuit structure

5652:基板 5652: Substrate

5654:第一層間電介質(ILD)層 5654: First interlayer dielectric (ILD) layer

5656:第一複數條導電互連線 5656: first plurality of conductive interconnect lines

5656A:導電互連線 5656A: Conductive Interconnecting Wire

5657:下面的介層 5657: Interposer below

5658:第一導電阻障層 5658: first conductive barrier layer

5660:第一導電填充材料 5660: First Conductive Filling Material

5664:第二ILD層 5664: Second ILD layer

5666:第二複數條導電互連線 5666: Second plurality of conductive interconnect lines

5666A:導電互連線 5666A: Conductive Interconnecting Wires

5667:下面的介層 5667: Interposer below

5668:第二導電阻障層 5668: Second conductive barrier layer

5670:第二導電填充材料 5670: Second Conductive Filling Material

5672:蝕刻停止層 5672: etch stop layer

5700:互連線 5700: interconnection line

5701:電介質層 5701: dielectric layer

5702:導電阻障材料 5702: Conductive barrier material

5704:導電填充材料 5704: Conductive Filling Material

5706:外層 5706: outer layer

5708:內層 5708: inner layer

5720:互連線 5720:Interconnection line

5721:電介質層 5721: dielectric layer

5722:導電阻障材料 5722: Conductive barrier material

5724:導電填充材料 5724: Conductive Filling Material

5730:導電蓋層 5730: Conductive cover

5740:互連線 5740: Interconnect

5741:電介質層 5741: dielectric layer

5742:導電阻障材料 5742: Conductive barrier material

5744:導電填充材料 5744: Conductive Filling Material

5746:外層 5746: Outer layer

5748:內層 5748: inner layer

5750:導電蓋層 5750: Conductive cover

5752:位置 5752: location

5800:積體電路結構 5800: Integrated circuit structure

5801:基板 5801: Substrate

5802:第一層間電介質(ILD)層 5802: First interlayer dielectric (ILD) layer

5804:第一複數條導電互連線 5804: first plurality of conductive interconnecting lines

5806:第一導電阻障層 5806: first conductive barrier layer

5808:第一導電填充材料 5808: The first conductive filling material

5812:第二ILD層 5812: Second ILD layer

5814,5814A,5814B:第二複數條導電互連線 5814, 5814A, 5814B: second plurality of conductive interconnecting lines

5819:第一導電介層 5819: first conductive via layer

5822:第三ILD層 5822: The third ILD layer

5824:第三複數條導電互連線 5824: A third plurality of conductive interconnecting lines

5826:第二導電阻障層 5826: second conductive barrier layer

5828:第二導電填充材料 5828: Second conductive filling material

5829:第二導電介層 5829: second conductive via layer

5832:第四ILD層 5832: The fourth ILD layer

5834,5834A,5834B:第四複數條導電互連線 5834, 5834A, 5834B: fourth plurality of conductive interconnecting lines

5839:第三導電介層 5839: The third conductive via layer

5842:第五ILD層 5842: fifth ILD layer

5844,5844A,5844B:第五複數條導電互連線 5844, 5844A, 5844B: fifth pluralities of conductive interconnecting lines

5849:第四導電介層 5849: The fourth conductive via layer

5852:第六ILD層 5852: Sixth ILD layer

5854,5854A:第六複數條導電互連線 5854, 5854A: Sixth plurality of conductive interconnecting lines

5859:第五導電介層 5859: fifth conductive via layer

5890:蝕刻停止層 5890: etch stop layer

5898:第一方向 5898:First direction

5899:第二方向 5899:Second direction

5900:積體電路結構 5900: Integrated circuit structure

5902:基板 5902: Substrate

5904:層間電介質(ILD)層 5904: interlayer dielectric (ILD) layer

5906:導電介層 5906: conductive interlayer

5908:第一溝槽 5908: first groove

5910:導電互連線 5910: Conductive Interconnecting Wires

5912:第二溝槽 5912: second groove

5913:開口 5913: opening

5914:第一導電阻障層 5914: first conductive barrier layer

5916:第二導電阻障層 5916: Second conductive barrier layer

5918:第三導電阻障層 5918: Third conductive barrier layer

5920:導電填充材料 5920: Conductive Filling Material

5922:導電蓋層 5922: Conductive cover

5924,5926:位置 5924,5926: Location

5950:第二導電互連線 5950: Second Conductive Interconnect Line

5952:第二ILD層 5952: Second ILD layer

5954:導電填充材料 5954: Conductive Filling Material

5956:導電蓋層 5956: Conductive cover

5958:蝕刻停止層 5958: etch stop layer

5960:開口 5960: opening

6000:積體電路結構 6000: Integrated circuit structure

6002:基板 6002: Substrate

6004:層間電介質(ILD)層 6004: interlayer dielectric (ILD) layer

6006:導電互連線 6006: Conductive interconnecting wires

6006A:導電互連線 6006A: Conductive Interconnecting Wires

6007:下面的介層 6007: Interposer below

6008:上表面 6008: upper surface

6010:上表面 6010: upper surface

6012:蝕刻停止層 6012: etch stop layer

6014:最上部位 6014: the top part

6016:最下部位 6016: The lowest part

6018:導電介層 6018: Conductive interlayer

6020:開口 6020: opening

6022:第二ILD層 6022: Second ILD layer

6024:中心 6024: center

6026:中心 6026: center

6028:阻障層 6028: barrier layer

6030:導電填充材料 6030: conductive filling material

6100:積體電路結構 6100: Integrated circuit structure

6102:基板 6102: Substrate

6104:層間電介質(ILD)層 6104: interlayer dielectric (ILD) layer

6106:導電互連線 6106: Conductive interconnecting wires

6106A:導電互連線 6106A: Conductive Interconnecting Wires

6107:下面的介層 6107: Interposer below

6108:上表面 6108: upper surface

6110:上表面 6110: upper surface

6112:蝕刻停止層 6112: etch stop layer

6114:最下部位 6114: the lowest part

6116:最上部位 6116: the top part

6118:導電介層 6118: conductive interlayer

6120:開口 6120: opening

6122:第二ILD層 6122: Second ILD layer

6124:中心 6124: center

6126:中心 6126: center

6128:阻障層 6128: barrier layer

6130:導電填充材料 6130: Conductive Filling Material

6200:金屬化層 6200: metallization layer

6202:金屬線 6202: metal wire

6203:下面的介層 6203: Interposer below

6204:電介質層 6204: dielectric layer

6205:線端或插塞 6205: wire end or plug

6206:線溝槽 6206: line groove

6208:介層溝槽 6208: via trench

6210:硬遮罩層 6210: hard mask layer

6212:線溝槽 6212: line groove

6214:介層溝槽 6214: via trench

6216:單一大的曝光 6216: Single large exposure

6300:在下面的金屬化層 6300: on the underlying metallization layer

6302:層間電介質(ILD)材料層 6302: interlayer dielectric (ILD) material layer

6304:上部部位 6304: upper part

6306:線溝槽 6306: line groove

6308:介層溝槽 6308: via trench

6310:下部部位 6310: lower part

6312:金屬線 6312: metal wire

6314:犧牲材料 6314: sacrificial material

6315:硬遮罩 6315: hard mask

6316:開口 6316: opening

6318,6318’:電介質插塞 6318,6318': Dielectric plugs

6320:上表面 6320: upper surface

6322:上表面 6322: upper surface

6324:導電材料 6324: Conductive material

6324A:第一部位 6324A: the first part

6324B:第二部位 6324B: the second part

6324C:第三部位 6324C: The third part

6328:第二導電介層 6328: Second conductive via layer

6330:第三溝槽 6330: the third groove

6318A:底部 6318A: Bottom

6350:積體電路結構 6350: Integrated circuit structure

6400:大約垂直的接縫 6400: approximately vertical seam

6450:積體電路結構 6450: Integrated Circuit Structure

6452:基板 6452: Substrate

6454:第一層間電介質(ILD)層 6454: First interlayer dielectric (ILD) layer

6456:第一複數條導電互連線 6456: first plurality of conductive interconnecting lines

6456A:第一導電阻障襯墊 6456A: First conductive barrier liner

6456B:第一導電填充材料 6456B: The first conductive filling material

6458:電介質插塞 6458: Dielectric plug

6464:第二ILD層 6464: Second ILD layer

6466:第二複數條導電互連線 6466: Second Plurality of Conductive Interconnect Lines

6466A:第二導電阻障襯墊 6466A: Second conductive barrier liner

6466B:第二導電填充材料 6466B: Second conductive filling material

6468:部位 6468: part

6470:類似層 6470: similar layer

6480:類似層 6480: similar layer

6500:代表性14奈米(14nm)佈局 6500: Representative 14-nanometer (14nm) layout

6502:位元單元 6502: bit unit

6504:閘極或多晶線 6504: Gate or polyline

6506:金屬1(M1)線 6506: Metal 1 (M1) wire

6600:代表性10奈米(10nm)佈局 6600: Representative 10-nanometer (10nm) layout

6602:位元單元 6602: bit unit

6604:閘極或多晶線 6604: Gate or polyline

6606:金屬1(M1)線 6606: Metal 1 (M1) wire

6700:單元佈局 6700: Cell Layout

6702:N-擴散 6702: N-diffusion

6704:P-擴散 6704:P-diffusion

6706:溝槽接觸 6706: Groove contact

6708:閘極接觸 6708: Gate contact

6710:接觸介層 6710: contact interposer

6800:單元佈局 6800: Cell Layout

6802:N-擴散 6802: N-Diffusion

6804:P-擴散 6804:P-diffusion

6806:溝槽接觸 6806: Groove contact

6808:閘極介層 6808: gate interlayer

6810:溝槽接觸介層 6810: Trench contact via

6900:單元佈局 6900: Cell Layout

6902:金屬0(M0)線 6902: Metal 0 (M0) line

6904:介層0結構 6904: Interposer 0 structure

7000:單元佈局 7000: Unit layout

7002:金屬0(M0)線 7002: Metal 0 (M0) line

7004:介層0結構 7004: Interposer 0 structure

7102:位元單元佈局 7102: Bit cell layout

7104:閘極線 7104: gate line

7106:溝槽接觸線 7106: grooved contact wire

7108:NMOS擴散區域 7108: NMOS diffusion area

7110:PMOS擴散區域 7110: PMOS diffusion area

7112:NMOS通過閘電晶體 7112: NMOS Pass Gate Transistor

7114:NMOS下拉電晶體 7114: NMOS pull-down transistor

7116:NMOS上拉電晶體 7116: NMOS pull-up transistor

7118:字線(WL) 7118: word line (WL)

7120,7126:內部節點 7120,7126: internal nodes

7122:位元線(BL) 7122: bit line (BL)

7124:位元線橫槓(BLB) 7124: Bit Line Bar (BLB)

7128:SRAM VCC 7128: SRAM VCC

7130:VSS 7130:VSS

7202A,7202B:基板 7202A, 7202B: Substrate

7204A,7204B:閘極線 7204A, 7204B: gate line

7206A,7206B:金屬1(M1)互連部 7206A, 7206B: Metal 1 (M1) Interconnect

7300A,7300B,7300C,7300D:單元 7300A, 7300B, 7300C, 7300D: unit

7302A,7302B,7302C,7302D:閘極(多晶)線 7302A, 7302B, 7302C, 7302D: gate (polycrystalline) line

7304A,7304B,7304C,7304D:金屬1(M1)線 7304A, 7304B, 7304C, 7304D: Metal 1 (M1) wire

7400:塊級多晶柵格 7400: Block-Level Polycrystalline Grid

7402:閘極線 7402: gate line

7404:方向 7404: direction

7406,7408:單元佈局界線 7406,7408: Unit layout boundaries

7500,7600,7700:佈局 7500, 7600, 7700: Layout

7800:積體電路結構 7800: Integrated circuit structure

7802:半導體鰭部 7802: Semiconductor fins

7804:基板 7804: Substrate

7805:頂部表面 7805: top surface

7806:第一末端 7806: first end

7807:一對側壁 7807: a pair of side walls

7808:第二末端 7808: second end

7810:金屬電阻器層 7810: Metal Resistor Layer

7810A,7810B,7810C,7810D:金屬電阻器層部位 7810A, 7810B, 7810C, 7810D: metal resistor layer part

7810E:有腳的特徵 7810E: Features with feet

7812:層 7812: layer

7814:隔離層 7814: isolation layer

7902:骨幹模板結構 7902: Backbone template structure

7904:側壁間隔層 7904: side wall spacer

7906:區域 7906:Area

8400,8402,8404,8406,8408,8410:位置 8400,8402,8404,8406,8408,8410: location

8600:基板 8600: Substrate

8601:光刻遮罩結構 8601: Photolithographic mask structure

8602:圖案化後的吸收層 8602: Absorbing layer after patterning

8604:上層 8604: upper layer

8606:圖案化後的移位器層 8606: Patterned shifter layer

8608:上部表面 8608: upper surface

8610:晶粒中區域 8610: In-grain area

8612:最上表面 8612: the top surface

8614:最上表面 8614: the top surface

8620:框架區域 8620: frame area

8630:晶粒框架介面區域 8630: Grain frame interface area

8640:雙層堆疊 8640: double stack

8700:計算裝置 8700: computing device

8702:板 8702: board

8704:處理器 8704: Processor

8706:通訊晶片 8706: communication chip

8800:中介層 8800: Interposer

8802:第一基板 8802: First Substrate

8804:第二基板 8804: second substrate

8806:球狀柵格陣列(BGA) 8806: Ball Grid Array (BGA)

8808:金屬互連 8808: Metal Interconnect

8810:金屬通孔 8810: Metal Via

8812:矽穿孔(TSV) 8812: Through Silicon Via (TSV)

8814:嵌入式裝置 8814: Embedded device

8900:行動計算平台 8900: Mobile Computing Platform

8905:顯示螢幕 8905: display screen

8910:晶片級數(SoC)或封裝組件級整合系統 8910: System on Chip (SoC) or Package Level Integration

8911:控制器 8911: Controller

8913:電池 8913: battery

8915:功率管理積體電路(PMIC) 8915: Power Management Integrated Circuit (PMIC)

8920:擴大的視圖 8920: Expanded view

8925:RF(無線)積體電路(RFIC) 8925: RF (wireless) integrated circuit (RFIC)

8960:板 8960: board

8977:封裝裝置 8977: Packaging device

9000:設備 9000: equipment

9002:晶粒 9002: grain

9004:金屬化墊塊 9004: metallized spacer

9006:封裝組件基板 9006: Packaging component substrate

9008:連接 9008: connect

9010:焊球 9010: solder ball

9012:底部填充材料 9012: Underfill material

990:頂部表面 990: top surface

4923:區域 4923:Area

圖1A繪示接著形成在層間電介質(ILD)層上的硬遮罩(hardmask)材料層的沉積之後(但是在圖案化之前)，起始結構的剖面視圖。 1A shows a cross-sectional view of a starting structure after subsequent deposition of a layer of hardmask material formed on an interlayer dielectric (ILD) layer (but before patterning).

圖1B繪示接著在藉由間距二等分法(pitch halving)來圖案化硬遮罩之後，圖1A之結構的剖面視圖。 1B shows a cross-sectional view of the structure of FIG. 1A followed by patterning the hard mask by pitch halving.

圖2A係依據本發明的一實施例，用來製造半導體鰭部之間距四等分法(pitch quartering approach)的示意圖。 FIG. 2A is a schematic diagram of a pitch quartering approach for manufacturing semiconductor fins according to an embodiment of the present invention.

圖2B繪示依據本發明的一實施例，使用間距四等分法所製造之半導體鰭部的剖面視圖。 2B illustrates a cross-sectional view of a semiconductor fin fabricated using pitch quartering, according to an embodiment of the present invention.

圖3A係依據本發明的一實施例，用來製造半導體鰭部之合併(merged)鰭部間距四等分法的示意圖。 3A is a schematic diagram of a merged fin pitch quartering method for fabricating semiconductor fins according to an embodiment of the present invention.

圖3B繪示依據本發明的一實施例，使用合併鰭部間距四等分法所製造之半導體鰭部的剖面視圖。 3B illustrates a cross-sectional view of a semiconductor fin fabricated using a merged fin pitch quartering method according to an embodiment of the present invention.

圖4A到4C係依據本發明的一實施例，代表製造複數個半導體鰭部的方法中之各種操作的剖面視圖。 4A-4C are cross-sectional views representing various operations in a method of fabricating a plurality of semiconductor fins in accordance with one embodiment of the present invention.

圖5A繪示依據本發明的一實施例，由三層的溝槽隔離結構所分開之一對半導體鰭部的剖面視圖。 5A illustrates a cross-sectional view of a pair of semiconductor fins separated by a three-layer trench isolation structure in accordance with an embodiment of the present invention.

圖5B繪示依據本發明的另一實施例，由另一個三層溝槽隔離結構所分開之另一對半導體鰭部的剖面視圖。 5B illustrates a cross-sectional view of another pair of semiconductor fins separated by another three-layer trench isolation structure according to another embodiment of the present invention.

圖6A到6D繪示依據本發明的一實施例，製造三層溝槽隔離結構之各種操作的剖面視圖。 6A to 6D illustrate cross-sectional views of various operations for fabricating a three-layer trench isolation structure in accordance with an embodiment of the present invention.

圖7A到7E繪示依據本發明的一實施例，在製造積體電路結構之方法中各種操作之有角度的三維剖面視圖。 7A-7E illustrate angled three-dimensional cross-sectional views of various operations in a method of fabricating an integrated circuit structure in accordance with one embodiment of the present invention.

圖8A到8F繪示依據本發明的一實施例，針對製造積體電路結構之方法中的各種操作，沿著圖7E的a到a’軸線所取出之略微突出(projected)的剖面視圖。 8A to 8F illustrate slightly projected cross-sectional views taken along the a to a' axis of FIG. 7E for various operations in a method of fabricating an integrated circuit structure in accordance with an embodiment of the present invention.

圖9A繪示依據本發明的一實施例，針對包含永久性閘極堆疊和磊晶的源極或汲極區域之積體電路結構，沿著圖7E的a到a’軸線所取出之略微突出的剖面視圖。 9A shows a slight protrusion taken along the a to a' axis of FIG. 7E for an integrated circuit structure including a permanent gate stack and an epitaxial source or drain region according to an embodiment of the present invention. section view.

圖9B繪示依據本發明的一實施例，針對包含磊晶的源極或汲極區域和多層的溝槽隔離結構之積體電路結構，沿著圖7E的b到b’軸線所取出的剖面視圖。 9B shows a cross-section taken along the b to b' axis of FIG. 7E for an integrated circuit structure including epitaxial source or drain regions and multilayer trench isolation structures according to an embodiment of the present invention. view.

圖10繪示依據本發明的一實施例，在源極或汲極位置所取出之積體電路結構的剖面視圖。 FIG. 10 shows a cross-sectional view of an integrated circuit structure taken out at the source or drain position according to an embodiment of the present invention.

圖11繪示依據本發明的一實施例，在源極或汲極位置所取出之另一積體電路結構的剖面視圖。 11 shows a cross-sectional view of another integrated circuit structure taken out at the source or drain position according to an embodiment of the present invention.

圖12A到12D繪示依據本發明的一實施例，在源極或汲極位置所取出且代表製造積體電路結構之製造中各種操作的剖面視圖。 12A-12D illustrate cross-sectional views taken at the source or drain location and representing various operations in the fabrication of an integrated circuit structure in accordance with an embodiment of the present invention.

圖13A及13B繪示依據本發明的一實施例，代表使具有多個閘極間隙之鰭部圖案化用以形成局部隔離結構之方法中各種操作的平面視圖。 13A and 13B illustrate plan views representing various operations in a method of patterning a fin with multiple gate gaps to form local isolation structures in accordance with an embodiment of the present invention.

圖14A到14D繪示依據本發明的另一實施 例，代表使具有單一閘極間隙之鰭部圖案化用以形成局部隔離結構之方法中各種操作的平面視圖。 14A to 14D illustrate another implementation according to the present invention Example, plan view representing various operations in a method of patterning a fin with a single gate gap to form a local isolation structure.

圖15繪示依據本發明的一實施例，具有帶有多個閘極間隙之鰭部用於局部隔離之積體電路結構的剖面視圖。 15 illustrates a cross-sectional view of an integrated circuit structure having fins with multiple gate gaps for local isolation in accordance with an embodiment of the present invention.

圖16A繪示依據本發明的另一實施例，具有帶有單一閘極間隙之鰭部用於局部隔離之積體電路結構的剖面視圖。 16A shows a cross-sectional view of an integrated circuit structure having fins with a single gate gap for partial isolation according to another embodiment of the present invention.

圖16B繪示依據本發明的一實施例，顯示其中鰭部隔離結構可以被形成來取代閘極電極之位置的剖面視圖。 16B is a cross-sectional view showing locations where fin isolation structures may be formed in place of gate electrodes in accordance with an embodiment of the present invention.

圖17A到17C繪示依據本發明的一實施例，使用鰭部修整隔離法所製造之鰭部切割部(fin cut)的各種深度可能性。 17A to 17C illustrate various depth possibilities for fin cuts fabricated using fin trim isolation methods in accordance with one embodiment of the present invention.

圖18繪示依據本發明的一實施例，沿著a到a’軸線所取下，顯示鰭部內之鰭部切割部的深度(depth of local)對鰭部切割部之較寬廣位置之可能選項的平面視圖和對應的剖面視圖。 Figure 18 is a diagram taken along the a to a' axis showing possible options for the depth of local fin cuts within the fin versus the wider location of the fin cuts in accordance with an embodiment of the present invention The plan view and the corresponding section view.

圖19A及19B繪示依據本發明的一實施例，在選擇位於鰭部的末端(其具有寬廣的切割部)處之鰭部末端應力源(stressor)位置的方法中之各種操作的剖面視圖。 19A and 19B illustrate cross-sectional views of various operations in a method of selecting a fin tip stressor location at a fin tip (with a broad cut) in accordance with an embodiment of the present invention.

圖20A及20B繪示依據本發明的一實施例，在選擇鰭部的末端(其具有局部的切割部)處之鰭部末端應力源位置的方法中之各種操作的剖面視圖。 20A and 20B illustrate cross-sectional views of various operations in a method of selecting a fin tip stressor location at a fin tip having a localized cutout, in accordance with an embodiment of the present invention.

圖21A到21M繪示依據本發明的一實施例，在製造具有差異化(differentiated)鰭部末端電介質插塞(plug)之積體電路結構的方法中之各種操作的剖面視圖。 21A-21M illustrate cross-sectional views of various operations in a method of fabricating an integrated circuit structure with differentiated fin-tip dielectric plugs in accordance with an embodiment of the present invention.

圖22A到22D繪示依據本發明的一實施例，PMOS鰭部末端應力源電介質插塞之代表性結構的剖面視圖。 22A-22D illustrate cross-sectional views of representative structures of PMOS fin end stressor dielectric plugs in accordance with one embodiment of the present invention.

圖23A繪示依據本發明的另一實施例，具有鰭部末端應力誘發(stress-inducing)特徵之另一半導體結構的剖面視圖。 23A illustrates a cross-sectional view of another semiconductor structure with fin end stress-inducing features according to another embodiment of the present invention.

圖23B繪示依據本發明的另一實施例，具有鰭部末端應力誘發特徵之另一半導體結構的剖面視圖。 23B is a cross-sectional view of another semiconductor structure with fin end stress inducing features according to another embodiment of the present invention.

圖24A繪示依據本發明的一實施例，具有伸張單軸應力(tensile uniaxial stress)之鰭部之有角度的視圖。 Figure 24A shows an angled view of a fin with tensile uniaxial stress, according to one embodiment of the present invention.

圖24B繪示依據本發明的一實施例，具有壓縮單軸應力(compressive uniaxial stress)之鰭部之有角度的視圖。 Figure 24B shows an angled view of a fin with compressive uniaxial stress, according to one embodiment of the present invention.

圖25A及25B繪示依據本發明的一實施例，代表使具有單閘極間隙之鰭部圖案化用以形成局部(local)隔離結構於選擇閘極線切割位置中的方法中之各種操作的平面視圖。 25A and 25B illustrate representations of various operations in a method of patterning a fin with a single gate gap for forming local isolation structures in selected gate line cut locations in accordance with an embodiment of the present invention. plan view.

圖26A到26C繪示依據本發明的一實施例，針對圖25B之結構的各種區域，關於用於多晶切割部(poly cut)和鰭部修整隔離(FTI)局部鰭部切割部以及僅用於多晶 切割部之位置的電介質插塞的各種可能性的剖面視圖。 26A to 26C illustrate, for various regions of the structure of FIG. 25B , local fin cuts for poly cut and fin trim isolation (FTI) and only Yu polycrystalline Cross-sectional views of various possibilities for the dielectric plug at the location of the cutout.

圖27A繪示依據本發明的一實施例，具有帶有延伸進閘極線之電介質間隔層中的電介質插塞之閘極線切割部的積體電路結構的平面視圖和對應的剖面視圖。 27A shows a plan view and corresponding cross-sectional view of an integrated circuit structure with gate line cutouts with dielectric plugs extending into the gate line's dielectric spacer, in accordance with an embodiment of the present invention.

圖27B繪示依據本發明的另一實施例，具有帶有延伸出閘極線之電介質間隔層外的電介質插塞之閘極線切割部的積體電路結構的平面視圖和對應的剖面視圖。 27B shows a plan view and corresponding cross-sectional view of an integrated circuit structure with a gate line cutout with a dielectric plug extending beyond the dielectric spacer layer of the gate line, according to another embodiment of the present invention.

圖28A到28F繪示依據本發明的另一實施例，在製造積體電路結構之方法中各種操作的剖面視圖，該積體電路結構具有帶有電介質插塞之閘極線切割部，該電介質插塞具有延伸出閘極線之電介質間隔層外的上部部位和延伸進閘極線之電介質間隔層中的下部部位。 28A to 28F illustrate cross-sectional views of various operations in a method of fabricating an integrated circuit structure having gate line cuts with dielectric plugs according to another embodiment of the present invention. The plug has an upper portion extending out of the dielectric spacer layer of the gate line and a lower portion extending into the dielectric spacer layer of the gate line.

圖29A到29C繪示依據本發明的一實施例，在永久閘極堆疊之底部部位具有剩餘之假性閘極材料之積體電路結構的平面視圖和對應的剖面視圖。 29A-29C illustrate a plan view and corresponding cross-sectional views of an integrated circuit structure with dummy gate material remaining at the bottom portion of the permanent gate stack in accordance with one embodiment of the present invention.

圖30A到30D繪示依據本發明的另一實施例，在製造積體電路結構之方法中各種操作的剖面視圖，該積體電路結構在永久閘極堆疊之底部部位具有剩餘之假性閘極材料。 30A through 30D illustrate cross-sectional views of various operations in a method of fabricating an integrated circuit structure having a dummy gate remaining at the bottom portion of the permanent gate stack in accordance with another embodiment of the present invention. Material.

圖31A繪示依據本發明的一實施例，具有鐵電或反鐵電閘極電介質結構之半導體裝置的剖面視圖。 31A shows a cross-sectional view of a semiconductor device with a ferroelectric or antiferroelectric gate dielectric structure, according to an embodiment of the present invention.

圖31B繪示依據本發明的另一實施例，具有鐵電或反鐵電閘極電介質結構之另一半導體裝置的剖面視圖。 31B shows a cross-sectional view of another semiconductor device with a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present invention.

圖32A繪示依據本發明的另一實施例，在一對半導體鰭部之上的複數條閘極線的平面視圖。 32A shows a plan view of a plurality of gate lines over a pair of semiconductor fins according to another embodiment of the present invention.

圖32B繪示依據本發明的一實施例，沿著圖32A之a到a’軸線所取下的剖面視圖。 Figure 32B shows a cross-sectional view taken along the a to a' axis of Figure 32A according to an embodiment of the present invention.

圖33A繪示依據本發明的一實施例，基於調變的摻雜而具有差異化的電壓臨界值的一對NMOS裝置和基於調變的摻雜而具有差異化的電壓臨界值的一對PMOS裝置的剖面視圖。 33A illustrates a pair of NMOS devices with differentiated voltage thresholds based on modulated doping and a pair of PMOS devices with differentiated voltage thresholds based on modulated doping, according to an embodiment of the present invention. Sectional view of the device.

圖33B繪示依據本發明的另一實施例，基於調變的閘極電極結構而具有差異化的電壓臨界值的一對NMOS裝置和基於調變的閘極電極結構而具有差異化的電壓臨界值的一對PMOS裝置的剖面視圖。 33B illustrates a pair of NMOS devices with differentiated voltage thresholds based on modulated gate electrode structures and differentiated voltage thresholds based on modulated gate electrode structures according to another embodiment of the present invention. Cross-sectional view of a pair of PMOS devices.

圖34A繪示依據本發明的一實施例，基於差異化之閘極電極結構和調變的摻雜而具有差異化的電壓臨界值之三個一組(triplet)的NMOS裝置和基於差異化之閘極電極結構和調變的摻雜而具有差異化的電壓臨界值之三個一組的PMOS裝置的剖面視圖。 FIG. 34A illustrates triplet NMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping and differentiated NMOS devices based on an embodiment of the present invention. Cross-sectional view of a trio of PMOS devices with differential voltage thresholds due to gate electrode structure and modulated doping.

圖34B繪示依據本發明的另一實施例，基於差異化之閘極電極結構和調變的摻雜而具有差異化的電壓臨界值之三個一組的NMOS裝置和基於差異化之閘極電極結構和調變的摻雜而具有差異化的電壓臨界值之三個一組的PMOS裝置的剖面視圖。 34B illustrates a triplet of NMOS devices with differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping, and differentiated gate-based NMOS devices according to another embodiment of the present invention. Cross-sectional view of a trio of PMOS devices with differentiated voltage thresholds by electrode structure and modulated doping.

圖35A到35D繪示依據本發明的另一實施例，在製造NMOS裝置之方法中各種操作的剖面視圖，該 NMOS裝置基於差異化之閘極電極結構而具有差異化的電壓臨界值。 35A to 35D illustrate cross-sectional views of various operations in a method of fabricating an NMOS device according to another embodiment of the present invention. NMOS devices have differentiated voltage thresholds based on differentiated gate electrode structures.

圖36A到36D繪示依據本發明的另一實施例，在製造PMOS裝置之方法中各種操作的剖面視圖，該PMOS裝置基於差異化之閘極電極結構而具有差異化的電壓臨界值。 36A to 36D illustrate cross-sectional views of various operations in a method of fabricating a PMOS device having differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present invention.

圖37繪示依據本發明的一實施例，具有P/N接面之積體電路結構的剖面視圖。 FIG. 37 shows a cross-sectional view of an integrated circuit structure with a P/N junction according to an embodiment of the present invention.

圖38A到38H繪示依據本發明的一實施例，在使用雙金屬閘極置換閘極處理流程來製造積體電路結構之方法中各種操作的剖面視圖。 38A through 38H illustrate cross-sectional views of various operations in a method of fabricating an integrated circuit structure using a dual metal gate replacement gate process flow, in accordance with an embodiment of the present invention.

圖39A到39H繪示依據本發明的一實施例，代表在製造以雙矽化物為基礎的積體電路之方法中各種操作的剖面視圖。 39A through 39H illustrate cross-sectional views representing various operations in a method of fabricating a dual-silicide-based integrated circuit in accordance with an embodiment of the present invention.

圖40A繪示依據本發明的一實施例，具有用於NMOS裝置之溝槽接觸的積體電路結構的剖面視圖。 40A shows a cross-sectional view of an integrated circuit structure with trench contacts for NMOS devices, in accordance with one embodiment of the present invention.

圖40B繪示依據本發明的另一實施例，具有用於PMOS裝置之溝槽接觸的積體電路結構的剖面視圖。 40B shows a cross-sectional view of an integrated circuit structure with trench contacts for a PMOS device according to another embodiment of the present invention.

圖41A繪示依據本發明的一實施例，具有源極或汲極區域上之導電接觸之半導體裝置的剖面視圖。 Figure 41A illustrates a cross-sectional view of a semiconductor device with conductive contacts on source or drain regions in accordance with one embodiment of the present invention.

圖41B繪示依據本發明的一實施例，具有突起的源極和汲極區域上之導電接觸之另一半導體裝置的剖面視圖。 41B illustrates a cross-sectional view of another semiconductor device with conductive contacts on raised source and drain regions in accordance with an embodiment of the present invention.

圖42繪示依據本發明的一實施例，在一對半 導體鰭部之上的複數條閘極線的平面視圖。 Fig. 42 shows according to an embodiment of the present invention, in a pair of halves Plan view of gate lines over conductor fins.

圖43A到43C繪示依據本發明的一實施例，針對製造積體電路結構之方法中的各種操作，沿著圖42的a到a’軸線所取出的剖面視圖。 43A to 43C illustrate cross-sectional views taken along the a to a' axes of FIG. 42 for various operations in a method of fabricating an integrated circuit structure in accordance with an embodiment of the present invention.

圖44繪示依據本發明的一實施例，針對一積體電路結構，沿著圖42的b到b’軸線所取出的剖面視圖。 FIG. 44 shows a cross-sectional view taken along the axis b to b' of FIG. 42 for an integrated circuit structure according to an embodiment of the present invention.

圖45A和45B繪示依據本發明的一實施例，分別為包含具有硬遮罩材料於其上之溝槽接觸插塞的積體電路結構的平面視圖和對應的剖面視圖。 45A and 45B illustrate a plan view and corresponding cross-sectional views, respectively, of an integrated circuit structure including trench contact plugs with hard mask material thereon, in accordance with an embodiment of the present invention.

圖46A到46D繪示依據本發明的一實施例，代表製造包含具有硬遮罩材料形成於其上之溝槽接觸插塞之積體電路結構的方法中之各種操作的剖面視圖。 46A-46D illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure including trench contact plugs having hard mask material formed thereon in accordance with an embodiment of the present invention.

圖47A繪示半導體裝置的平面視圖，該半導體裝置具有閘極接觸被設置在閘極電極的非作用部位之上。圖47B繪示非平面型半導體裝置的剖面視圖，該非平面型半導體裝置具有閘極接觸被設置在閘極電極的非作用部位之上。 47A shows a plan view of a semiconductor device with a gate contact disposed over an inactive portion of a gate electrode. 47B shows a cross-sectional view of a non-planar semiconductor device with a gate contact disposed over an inactive portion of the gate electrode.

圖48A繪示依據本發明的一實施例，半導體裝置的平面視圖，該半導體裝置具有閘極接觸介質被設置在閘極電極的作用部位之上。圖48B繪示依據本發明的一實施例，非平面型半導體裝置的剖面視圖，該非平面型半導體裝置具有閘極接觸介層被設置在閘極電極的作用部位之上。 48A illustrates a plan view of a semiconductor device having a gate contact dielectric disposed over the active portion of the gate electrode, in accordance with an embodiment of the present invention. 48B is a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over the active portion of the gate electrode, according to an embodiment of the present invention.

圖49A到49D繪示依據本發明的一實施例， 代表製造具有閘極接觸結構設置在閘極的作用部位之上的半導體結構的方法中之各種操作的剖面視圖。 49A to 49D illustrate an embodiment according to the present invention, Cross-sectional views representing various operations in a method of fabricating a semiconductor structure having a gate contact structure disposed over an active site of a gate.

圖50繪示依據本發明的一實施例，具有包含上覆的絕緣蓋層之溝槽接觸的積體電路結構的平面視圖及對應的剖面視圖。 50 shows a plan view and corresponding cross-sectional views of an integrated circuit structure with trench contacts including an overlying insulating cap layer, in accordance with an embodiment of the present invention.

圖51A到51F繪示依據本發明的一實施例，各種積體電路結構的剖面視圖，其各自具有包含上覆的絕緣蓋層之溝槽接觸並且具有包含上覆的絕緣蓋層之閘極堆疊。 51A to 51F illustrate cross-sectional views of various integrated circuit structures, each having a trench contact including an overlying insulating cap and having a gate stack including an overlying insulating cap, in accordance with an embodiment of the present invention. .

圖52A繪示依據本發明的另一實施例，具有設置在閘極的作用部分之上的閘極接觸介層之另一半導體裝置的平面視圖。 52A illustrates a plan view of another semiconductor device having a gate contact via disposed over an active portion of the gate, in accordance with another embodiment of the present invention.

圖52B繪示依據本發明的另一實施例，具有耦合一對溝槽接觸的閘極接觸介層之另一半導體裝置的平面視圖。 52B illustrates a plan view of another semiconductor device having a gate contact via coupling a pair of trench contacts according to another embodiment of the present invention.

圖53A到53E繪示依據本發明的一實施例，代表製造具有帶有覆蓋之絕緣蓋層的閘極堆疊之積體電路結構的方法中之各種操作的剖面視圖。 53A-53E illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having a gate stack with an overlying insulating cap layer in accordance with an embodiment of the present invention.

圖54為依據本發明的一實施例，用來製作用於互連結構之溝槽的間距四等分法的示意圖。 54 is a schematic diagram of a pitch quartering method used to fabricate trenches for interconnect structures according to an embodiment of the present invention.

圖55A繪示依據本發明的一實施例，使用間距四等分方案所製作之金屬化層的剖面視圖。 Figure 55A shows a cross-sectional view of a metallization layer fabricated using a pitch quartering scheme in accordance with one embodiment of the present invention.

圖55B繪示依據本發明的一實施例，在使用間距四等分方案所製作之金屬層上方之使用間距二等分方 案所製作之金屬層的剖面視圖。 FIG. 55B illustrates the use of pitch bisecting squares above a metal layer fabricated using the pitch quartering scheme, in accordance with one embodiment of the present invention. A cross-sectional view of the fabricated metal layer.

圖56A繪示依據本發明的一實施例，積體電路結構的剖面視圖，該積體電路結構具有帶有金屬線組成的金屬化層係在帶有不同金屬線組成的金屬化層上方。 56A illustrates a cross-sectional view of an integrated circuit structure having a metallization layer with a metal line composition over a metallization layer with a different metal line composition, in accordance with an embodiment of the present invention.

圖56B繪示依據本發明的一實施例，積體電路結構的剖面視圖，該積體電路結構具有帶有金屬線組成的金屬化層係耦合至帶有不同金屬線組成的金屬化層。 56B illustrates a cross-sectional view of an integrated circuit structure having a metallization layer with a metal line composition coupled to a metallization layer with a different metal line composition in accordance with an embodiment of the present invention.

圖57A到57C繪示依據本發明的一實施例，具有各種襯墊和導電覆蓋結構配置之個別互連線的剖面視圖。 Figures 57A-57C illustrate cross-sectional views of individual interconnect lines with various pad and conductive cap structure configurations in accordance with one embodiment of the present invention.

圖58繪示依據本發明的一實施例，積體電路結構的剖面視圖，該積體電路結構具有帶有金屬線組成和間距的四個金屬化層係在帶有不同金屬線組成和較小間距的兩個金屬化層上方。 58 illustrates a cross-sectional view of an integrated circuit structure having four metallization layers with wire compositions and spacings with different wire compositions and smaller metallization layers in accordance with one embodiment of the present invention. spacer above the two metallization layers.

圖59A到59D繪示依據本發明的一實施例，具有底部導電層之各種互連線和介層配置的剖面視圖。 59A to 59D illustrate cross-sectional views of various interconnect and via configurations with bottom conductive layers in accordance with one embodiment of the present invention.

圖60A到60D繪示依據本發明的一實施例，針對BEOL金屬化層之凹入線形貌之結構配置的剖面視圖。 60A-60D illustrate cross-sectional views of structural configurations for concave line topography of BEOL metallization layers in accordance with one embodiment of the present invention.

圖61A到61D繪示依據本發明的一實施例，針對BEOL金屬化層之階梯線(stepped line)形貌之結構配置的剖面視圖。 61A-61D illustrate cross-sectional views of structural configurations for stepped line topography of BEOL metallization layers according to one embodiment of the present invention.

圖62A繪示依據本發明的一實施例，沿著金屬化層之平面視圖的a-a’軸線所取出之平面視圖和對應的 剖面視圖。 Figure 62A shows a plan view taken along the a-a' axis of a plan view of a metallization layer and the corresponding Section view.

圖62B繪示依據本發明的一實施例，線端或插塞的剖面視圖。 Figure 62B shows a cross-sectional view of a wire end or plug according to one embodiment of the present invention.

圖62C繪示依據本發明的一實施例，線端或插塞的另一剖面視圖。 Figure 62C illustrates another cross-sectional view of a wire end or plug in accordance with one embodiment of the present invention.

圖63A到63F繪示依據本發明的一實施例，代表插塞最後處理方案中之各種操作的平面視圖和對應的剖面視圖。 63A-63F illustrate plan views and corresponding cross-sectional views representing various operations in a plug finishing scheme, in accordance with one embodiment of the present invention.

圖64A繪示依據本發明的一實施例，具有接縫於其中之導電線插塞的剖面視圖。 Figure 64A illustrates a cross-sectional view of a conductive thread plug having seams therein, in accordance with one embodiment of the present invention.

圖64B繪示依據本發明的一實施例，包含導電線插塞在下金屬線位置處之金屬化層堆疊的剖面視圖。 64B shows a cross-sectional view of a metallization layer stack including conductive line plugs at lower metal line locations in accordance with one embodiment of the present invention.

圖65繪示記憶單元(memory cell)之單元佈局(cell layout)的第一視圖。 FIG. 65 shows a first view of a cell layout of a memory cell.

圖66繪示依據本發明的一實施例，針對具有內部節點跨接線之記憶單元之單元佈局的第一視圖。 Figure 66 shows a first view of a cell layout for a memory cell with internal node jumpers in accordance with an embodiment of the present invention.

圖67繪示記憶單元之單元佈局的第二視圖。 Figure 67 shows a second view of the cell layout of a memory cell.

圖68繪示依據本發明的一實施例，針對具有內部節點跨接線之記憶單元之單元佈局的第二視圖。 Figure 68 shows a second view of a cell layout for a memory cell with internal node jumpers in accordance with an embodiment of the present invention.

圖69繪示記憶單元之單元佈局的第三視圖。 Figure 69 shows a third view of the cell layout of a memory cell.

圖70繪示依據本發明的一實施例，針對具有內部節點跨接線之記憶單元之單元佈局的第三視圖。 Figure 70 shows a third view of a cell layout for a memory cell with internal node jumpers in accordance with an embodiment of the present invention.

圖71A和71B分別繪示依據本發明的一實施例，針對6個電晶體(6T)靜態隨機存取記憶體(SRAM)的位 元單元佈局和示意圖。 FIGS. 71A and 71B respectively illustrate a bit for a 6-transistor (6T) static random access memory (SRAM) according to an embodiment of the present invention. Metacell layout and schematic.

圖72繪示依據本發明的一實施例，針對相同標準單元之兩個不同佈局的剖面視圖。 Figure 72 shows a cross-sectional view of two different layouts for the same standard cell, according to an embodiment of the present invention.

圖73繪示依據本發明的一實施例，表示偶(even(E))或奇(odd(O))名稱之四個不同單元配置的平面視圖。 Figure 73 shows a plan view of four different cell configurations representing even (E) or odd (O) designations, in accordance with an embodiment of the present invention.

圖74繪示依據本發明的一實施例，塊級多晶柵格(poly grid)的平面視圖。 FIG. 74 illustrates a plan view of a block-level poly grid, according to an embodiment of the present invention.

圖75繪示依據本發明的一實施例，基於具有不同版本之標準單元的代表性可接受(通過(pass))佈局。 Figure 75 illustrates a representative acceptable (pass) layout based on standard cells having different versions, according to one embodiment of the present invention.

圖76繪示依據本發明的一實施例，基於具有不同版本之標準單元的代表性不可接受(未通過(fail))佈局。 Figure 76 illustrates a representative unacceptable (fail) layout based on standard cells having different versions, in accordance with one embodiment of the present invention.

圖77繪示依據本發明的一實施例，基於具有不同版本之標準單元的另一代表性可接受(通過)佈局。 Figure 77 illustrates another representative acceptable (passed) placement based on standard cells with different versions, in accordance with an embodiment of the present invention.

圖78繪示依據本發明的一實施例，以鰭部為基礎之薄膜電阻器結構的局部切割平面視圖和對應的剖面視圖，其中，該剖面視圖係沿著局部切割平面視圖的a到a’軸線所取下的。 78 shows a partial cut plan view and corresponding cross-sectional view of a fin-based thin film resistor structure according to an embodiment of the present invention, wherein the cross-sectional view is along a to a' of the partial cut plan view. axis removed.

圖79至83繪示依據本發明的一實施例，代表製作以鰭部為基礎之薄膜電阻器結構的方法中之各種操作的平面視圖和對應的剖面視圖。 79-83 illustrate plan views and corresponding cross-sectional views representing various operations in a method of fabricating a fin-based thin film resistor structure in accordance with an embodiment of the present invention.

圖84繪示依據本發明的一實施例，以鰭部為基礎之薄膜電阻器結構的平面視圖，該結構具有針對陽極 或陰極電極接觸的各種代表性位置。 Figure 84 illustrates a plan view of a fin-based thin film resistor structure with an anode for the anode, in accordance with an embodiment of the present invention. or various representative locations of cathode electrode contacts.

圖85A至85D繪示依據本發明的一實施例，用以製作以鰭部為基礎之精密電阻器的各種鰭部幾何形狀的平面視圖。 85A-85D illustrate plan views of various fin geometries used to fabricate fin-based precision resistors in accordance with one embodiment of the present invention.

圖86繪示依據本發明的一實施例，光刻遮罩結構的剖面視圖。 Figure 86 illustrates a cross-sectional view of a photolithographic mask structure in accordance with one embodiment of the present invention.

圖87繪示依據本發明的一個實作的計算裝置。 Figure 87 illustrates a computing device according to one implementation of the present invention.

圖88繪示包含本發明的一或更多個實施例的中介層。 Figure 88 depicts an interposer incorporating one or more embodiments of the present invention.

圖89為依據本發明的一實施例，使用依據本文中所述之一或多個製程所製作或者包含本文中所述之一或多個特徵的積體電路(IC)之行動計算平台。 FIG. 89 illustrates a mobile computing platform using an integrated circuit (IC) fabricated according to one or more of the processes described herein or incorporating one or more of the features described herein, in accordance with an embodiment of the present invention.

圖90繪示依據本發明的一實施例，覆晶安裝之晶粒的剖面視圖。 FIG. 90 illustrates a cross-sectional view of a flip-chip mounted die in accordance with one embodiment of the present invention.

說明先進積體電路結構製造。在下面的說明中，提出許多特定的細節，諸如特定的整合及材料制度(regime)，以便提供本發明之實施例的透徹了解。本發明的實施例可以在沒有這些特定細節的情況下被實踐對於習於此技藝者而言將會是明顯的。在其他的例子中，諸如積體電路設計等之眾所周知的特徵不做詳細的說明，以便不致不必要地模糊了本發明的實施例。此外，將可領會到， 圖形中所顯示的各種實施例為說明性代表，而且不需要按比例來繪出。 Describes the fabrication of advanced integrated circuit structures. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the invention. It will be apparent to one skilled in the art that embodiments of the invention can be practiced without these specific details. In other instances, well-known features, such as integrated circuit designs, have not been described in detail in order not to unnecessarily obscure embodiments of the invention. Furthermore, it will be appreciated that The various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

下面的詳細說明本質上僅為說明性的，而且並不想要限定標的物的實施例或者此等實施例的應用及使用。如同本文中所使用的，「代表性」字詞意謂著「用作為範例、實例、或圖例」。本文中所說明作為代表例的任何施行並不需要被建構為比其他施行更佳或更有利。此外，沒有任何想要被前面的技術領域、先前技術、發明內容、或者下面的實施方式中所提出的任何明確或隱含的理論限制的意圖或想法。 The following detailed description is merely illustrative in nature and is not intended to limit the subject embodiments or the application and uses of such embodiments. As used herein, the word "representative" means "serving as an example, instance, or illustration." Any implementation described herein as representative is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention or idea to be bound by any expressed or implied theory presented in the preceding technical field, prior art, brief summary, or the following embodiments.

本說明書包含提到「一個實施例」或「一實施例」。用語「在一個實施例中」或「在一實施例中」的出現不需要指的是同一個實施例。可以用任何與本發明一致的適當方式來組合特別的特徵、結構、或特性。 This specification contains reference to "one embodiment" or "an embodiment." The appearances of the phrase "in one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with the invention.

術語。下面的段落提供在本發明中所發現之術語的定義或上下文(包含附加的申請專利範圍)。 the term. The following paragraphs provide definitions or context for terms found in this disclosure (including appended claims).

「包括(comprising)」。此術語係開放式的(open-ended)。如同在申請專利範圍中所使用的，此術語並不排除(foreclose)其他的結構或操作。 "comprising". This term is open-ended. As used in the claims, this term does not foreclose other structures or operations.

「組構成」。各種單元或組件可以被敘述或主張為「組構成」實施一任務或諸任務。在這樣的上下文中，「組構成」被用來意味著藉由表示該等單元或組件包含在操作期間實施那些任務之結構的結構。因此，該單元或組件可以被說成是被組構成實施任務，即使是該特定的單元或 組件目前並未正在操作(例如，並未開啟或作用中)。敘述一單元或電路或組件被「組構成」實施一或多項任務係明確地打算對於該單元或組件不援引35 U.S.C.§112，第6段。 "Composition". Various units or components may be described or claimed to be "composed" to perform a task or tasks. In such context, "composed of" is used to mean structure by denoting that such units or components comprise structure for performing those tasks during operation. Accordingly, the unit or component may be said to be composed to perform a task, even if the particular unit or The component is not currently operating (eg, not turned on or active). A statement that a unit or circuit or component is "constituted" to perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112, paragraph 6, with respect to that unit or component.

「第一」、「第二」等等。如同本文中所使用的，這些術語被用來標示名詞出現的先後，但是並不隱含任何類型的排序(例如，空間、時間、邏輯、等等)。 "First", "Second" and so on. As used herein, these terms are used to indicate the order in which nouns occur, but do not imply any type of ordering (eg, spatial, temporal, logical, etc.).

「耦合」。下面的說明係指元件或節點或特徵被「耦合」在一起。如同本文中所使用的，除非有明確地陳述，否則「耦合」意謂著一個元件或節點或特徵被直接或間接地連結到另一個元件或節點或特徵(或者與另一個元件或節點或特徵相連通)，而且不需要是機械式地。 "coupling". The description below refers to elements or nodes or features being "coupled" together. As used herein, unless expressly stated otherwise, "coupled" means that one element or node or feature is directly or indirectly connected to another element or node or feature (or with another element or node or feature). connected), and need not be mechanical.

除此之外，某些術語也可以僅為了參考的目的而被使用於下面的說明中，因而不想要被限定。例如，諸如「較高(upper)」、「較低(lower)」、「之上」、「之下」等術語係指做出該參考之圖形中的方向。諸如「前面」、「背面」、「後面」、「側面」、「外側」、「內側」等術語說明在一致但任意的參考系統(frame of reference)內該組件之部位的定向或位置或者定向和位置兩者，而參照說明討論中之該組件的上下文及相關圖形以使該參考系統清楚明確。如此術語可包含上面明確提及的字詞、其衍生詞、以及類似引入的字詞。 In addition, certain terms may also be used in the following description for reference purposes only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", "beneath" and the like refer to directions in the figure to which reference is made. Terms such as "front", "rear", "rear", "side", "outer", "inner", etc. describe the orientation or position or orientation of the part of the component within a consistent but arbitrary frame of reference Both, and location, reference is made to the context and associated figures illustrating the component in question for clarity of this reference system. Such terms may include the words explicitly mentioned above, derivatives thereof, and words of similar import.

「抑止(inhibit)」。如同本文中所使用的，抑止被用來說明使功效縮減或最小化。當組件或特徵被敘述為抑止動作、運動、或條件時，其可完全地防止結果、 後果、或未來狀態。除此之外，「抑止」也可以指其可能發生之結果、效能、或效果的縮小或減輕。因此，當組件、元件或特徵被稱作為抑止結果或狀態時，其不需要完全防止或消除該結果或狀態。 "Inhibit". As used herein, inhibition is used to describe curtailing or minimizing efficacy. When a component or feature is described as inhibiting an action, motion, or condition, it completely prevents the result, Consequences, or future states. In addition, "inhibition" can also refer to the reduction or alleviation of its possible results, potency, or effects. Thus, when a component, element or feature is referred to as inhibiting a result or condition, it need not completely prevent or eliminate that result or condition.

本文中所述之實施例可以針對前段(front-end-of-line(FEOL))半導體處理及結構。FEOL為積體電路(IC)製造的第一部分，其中，個別裝置(例如，電晶體、電容器、電阻器、等等)被圖案化於半導體基板或半導體層中。FEOL通常涵蓋到達(但不包含)金屬互連層之沉積前的任何操作步驟。接著在最終的FEOL操作之後，結果典型為具有隔離之電晶體(例如，沒有任何配線)的晶圓。 Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication in which individual devices (eg, transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or semiconductor layer. FEOL generally covers any operational steps up to, but not including, the deposition of metal interconnect layers. Then after the final FEOL operation, the result is typically a wafer with isolated transistors (eg, without any wiring).

本文中所述之實施例可以針對後段(back-end-of-line(BEOL))半導體處理及結構。BEOL為IC製造的第二部分，其中，個別裝置(例如，電晶體、電容器、電阻器、等等)和晶圓上的配線互連，例如，金屬化層或諸層。BEOL包含用晶片-到-封裝組件連接的接觸、絕緣層(電介質)、金屬層(metal level)、和接合點(bonding site)。在製造階段的BEOL部分中，接觸(墊塊)、互連配線、通孔(via)、和電介質結構被形成。對於現代的IC製程，10個以上的金屬層可以被添加於BEOL中。 Embodiments described herein may be directed to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC fabrication in which individual devices (eg, transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, eg, metallization layers or layers. A BEOL consists of contacts, insulating layers (dielectrics), metal levels, and bonding sites that are connected with the die-to-package assembly. In the BEOL portion of the fabrication stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added in BEOL.

下面所述之實施例可以應用於FEOL處理及結構、BEOL處理及結構、或者FEOL和BEOL兩者的處理及結構。特別是，雖然代表性處理方案(scheme)可以使用FEOL處理方案(scenario)來予以例舉，但是此等方法也可 以應用到BEOL處理。同樣地，雖然代表性處理方案可以使用BEOL處理方案來予以例舉，但是此等方法也可以應用到FEOL處理。 The embodiments described below can be applied to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processes and structures. In particular, while representative treatment scenarios may be exemplified using FEOL treatment scenarios, such approaches may also to be applied to BEOL processing. Likewise, while representative treatment protocols may be exemplified using BEOL treatment protocols, such methods may also be applied to FEOL treatments.

間距分割(pitch division)處理及圖案化方案可以被施行來致能本文中所述的實施例，或者可以被包含作為本文中所述之實施例的部分。間距分割圖案化典型上指的是間距二等分法、間距四等分法等等。間距分割方案可以應用於FEOL處理、BEOL處理、或者FEOL(裝置)和BEOL(金屬化)處理兩者。依據本文中所述的一或更多個實施例，光刻(optical lithography)首先被施行來以預先定義的間距列印單向的(unidirectional)線(例如，不是嚴格單向的就是主要是單向的)。間距分割處理然後被施行為增加線密度的技術。 Pitch division processing and patterning schemes may be implemented to enable the embodiments described herein, or may be included as part of the embodiments described herein. Pitch division patterning is typically referred to as pitch bisection, pitch quartering, and the like. The pitch division scheme can be applied to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. In accordance with one or more embodiments described herein, optical lithography is first performed to print unidirectional lines (e.g., either strictly unidirectional or predominantly unidirectional) at a predefined pitch. towards). Pitch division processing is then performed as a technique to increase line density.

在一實施例中，用於鰭部、閘極線、金屬線、ILD線或硬遮罩線的術語「光柵結構(grating structure)」在本文中被用來指緊密的間距光柵結構。在一個這樣的實施例中，直接經由選擇到的光刻無法達成緊密的間距。例如，基於選擇到的光刻的圖案可以首先被形成，但是該間距可以藉由使用間隔層遮罩(spacer mask)圖案化而被二等分，如同習知技術中所已知者。更甚者，原來的間距可以藉由第二輪的間隔層遮罩圖案化而被四等分。因此，本文中所述之光柵狀(grating-like)圖案可以具有以實質上一致的間距來間隔開且具有實質上一致的寬度的金屬線、ILD線或硬遮罩線。例如，在有些實施例中， 間距變化將會在百分之十以內，並且寬度變化將會在百分之十以內，而且在有些實施例中，間距變化將會在百分之五以內，並且寬度變化將會在百分之五以內。圖案可以藉由間距二等分法或間距四等分法、或者其他的間距分割方法來予以製造。在一實施例中，該光柵不需要是單一間距。 In one embodiment, the term "grating structure" for fins, gate lines, metal lines, ILD lines or hard mask lines is used herein to refer to a close pitch grating structure. In one such embodiment, tight pitches cannot be achieved directly via selective photolithography. For example, a pattern based on selected lithography can be formed first, but the spacing can be bisected by patterning using a spacer mask, as is known in the art. Furthermore, the original pitch can be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern described herein may have metal lines, ILD lines, or hard mask lines spaced at a substantially uniform pitch and having a substantially uniform width. For example, in some embodiments, The pitch variation will be within ten percent and the width variation will be within ten percent, and in some embodiments the pitch variation will be within five percent and the width variation will be within Within five. Patterns can be produced by pitch bisecting or pitch quartering, or other pitch division methods. In one embodiment, the grating need not be of a single pitch.

在第一範例中，間距二等分法可以被施行來使製造之光柵結構的線密度加倍。圖1A繪示形成在層間電介質(ILD)層上的硬遮罩材料層的沉積之後(但是在圖案化之前)，起始結構的剖面視圖。圖1B繪示接著在藉由間距二等分法來圖案化硬遮罩之後，圖1A之結構的剖面視圖。 In a first example, pitch bisection can be implemented to double the linear density of the fabricated grating structure. 1A shows a cross-sectional view of a starting structure after deposition of a layer of hard mask material formed on an interlayer dielectric (ILD) layer (but before patterning). FIG. 1B shows a cross-sectional view of the structure of FIG. 1A followed by patterning the hard mask by pitch bisecting.

參照圖1A，起始結構100具有形成在層間電介質(ILD)層102上的硬遮罩材料層104。圖案化後的遮罩106係設置在硬遮罩材料層104之上。圖案化後的遮罩106具有沿著其特徵(線)的側壁形成在硬遮罩材料層104上的間隔層(spacer)108。 Referring to FIG. 1A , a starting structure 100 has a hard mask material layer 104 formed on an interlayer dielectric (ILD) layer 102 . A patterned mask 106 is disposed over the hard mask material layer 104 . The patterned mask 106 has spacers 108 formed on the hard mask material layer 104 along the sidewalls of its features (lines).

參照圖1B，硬遮罩材料層104係以間距二等分法來予以圖案化。明確地說，圖案化後的遮罩106首先被去除，間隔層108的結果圖案已經使密度加倍，或者使遮罩106的間距或特徵二等分。藉由蝕刻處理來將間隔層108的圖案轉移至硬遮罩材料層104，以形成圖案化後的硬遮罩110，如同圖1B中所描述者。在一個這樣的實施例中，圖案化後的硬遮罩110係形成有具有單向線的光柵圖案。圖案化後的硬遮罩110之光柵圖案可以是緊密的間距 光柵結構。例如，直接經由選擇到的光刻技術可能無法達成緊密的間距。更甚者，雖然未顯示出，原來的間距可以藉由第二輪的間隔層遮罩圖案化而被四等分。因此，圖1B之圖案化後的硬遮罩110之光柵狀圖案可以具有相對於彼此以恆定的間距來予以間隔開且具有恆定的寬度的硬遮罩線。所達成的該等尺寸可以遠小於所使用之光刻技術的臨界尺寸。 Referring to FIG. 1B , the layer of hard mask material 104 is patterned by pitch bisecting. In particular, the patterned mask 106 is first removed and the resulting pattern of the spacer layer 108 has doubled the density, or bisected the pitch or features of the mask 106 . The pattern of the spacer layer 108 is transferred to the hard mask material layer 104 by an etching process to form a patterned hard mask 110 as described in FIG. 1B . In one such embodiment, the patterned hard mask 110 is formed with a grating pattern having unidirectional lines. The grating pattern of the patterned hard mask 110 can be a tight pitch Grating structure. For example, tight pitches may not be achievable directly via selected photolithographic techniques. Furthermore, although not shown, the original pitch can be quartered by a second round of spacer mask patterning. Thus, the raster-like pattern of the patterned hard mask 110 of FIG. 1B may have hard mask lines spaced at a constant pitch relative to each other and having a constant width. The dimensions achieved can be much smaller than the critical dimensions of the photolithography techniques used.

因此，對於前段(FEOL)或後段(BEOL)，或者前、後段兩者的整合方案，毯覆(blanket)膜可以使用光刻和蝕刻處理來予以圖案化，而光刻和蝕刻處理可能涉及，例如，基於間隔層的雙重圖案化(SBDP)或間距二等分法，或者基於間隔層的四重圖案化(SBQP)或間距四等分法。將可領會到其他的間距分割法也可以被施行。在任何情況下，在一實施例中，柵格佈局(gridded layout)可以藉由選擇到的光刻法來予以製造，諸如193nm浸沒式光刻法(193i)。間距分割可以被施行來使柵格佈局中的線密度增加n倍(a factor of n)。以193i光刻法再加上「n」倍的間距分割之柵格佈局形成可以被定名為193i+P/n間距分割法。在一個這樣的實施例中，193nm浸沒式縮放可以用有成本效益的(cost effective)間距分割法而被延伸許多世代。 Thus, for front-end-of-line (FEOL) or back-end-of-line (BEOL), or both, the blanket film can be patterned using photolithography and etch processes that may involve, For example, spacer-based double patterning (SBDP) or pitch bisection, or spacer-based quadruple patterning (SBQP) or pitch quartering. It will be appreciated that other pitch division methods may also be implemented. In any case, in one embodiment, a gridded layout may be fabricated by selected photolithography, such as 193nm immersion photolithography (193i). Spacing splits can be performed to increase the line density in a grid layout by a factor of n. The grid layout formed by 193i lithography plus "n" times of pitch division can be named as 193i+P/n pitch division method. In one such embodiment, 193nm immersion scaling can be extended for many generations with cost effective pitch division.

在積體電路裝置的製作方面，諸如三閘極電晶體的多閘極電晶體隨著裝置尺寸持續縮小而已經變得更加普遍。三閘極電晶體通常不是被製造於塊狀矽基板上就 是被製造於絕緣體上覆矽(silicon-on-insulator)基板上。在有些例子中，塊狀矽基板由於其較低成本以及與現有高生產(high-yielding)的塊狀矽基板基礎設施的相容性而係較佳的。 In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more common as device dimensions continue to shrink. Tri-gate transistors are usually not fabricated on bulk silicon substrates It is fabricated on a silicon-on-insulator substrate. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-yielding bulk silicon substrate infrastructure.

然而，縮小多閘極電晶體並非沒有後果的。因為微電子電路的這些基本建構方塊(building block)的尺寸被縮減，而且因為在給定區域中所製造之基本建構方塊的數量增加，所以對用來製造這些建構方塊之半導體製程的限制已經變成勢所難擋了(overwhelming)。 However, shrinking multi-gate transistors is not without consequences. As the size of these basic building blocks of microelectronic circuits has been reduced, and as the number of basic building blocks fabricated in a given area has increased, constraints on the semiconductor processes used to fabricate these building blocks have become Overwhelming.

依據本發明的一或更多個實施例，間距四等分法被施行來圖案化半導體層以形成半導體鰭部。在一或更多個實施例中，合併鰭部間距四等分法被施行。 In accordance with one or more embodiments of the present invention, pitch quartering is performed to pattern the semiconductor layer to form semiconductor fins. In one or more embodiments, merging fin pitch quartering is performed.

圖2A為依據本發明的一實施例，用來製造半導體鰭部之間距四等分法200的示意圖。圖2B繪示依據本發明的一實施例，使用間距四等分法所製造之半導體鰭部的剖面視圖。 FIG. 2A is a schematic diagram of a quartering method 200 for manufacturing semiconductor fin pitches according to an embodiment of the present invention. 2B illustrates a cross-sectional view of a semiconductor fin fabricated using pitch quartering, according to an embodiment of the present invention.

參照圖2A，在操作(a)處，光阻層(PR)被圖案化而形成光阻特徵202。光阻特徵202可以使用標準的光刻處理技術來予以圖案化，諸如193浸沒式光刻法。在操作(b)處，光阻特徵202被用來圖案化諸如絕緣層或電介質硬遮罩層的材料層，以形成第一骨幹(BB1)特徵204。第一間隔層(SP1)特徵206然後被形成鄰接第一骨幹特徵204的側壁。在操作(c)處，第一骨幹特徵204被去除而僅剩下第一間隔層特徵206餘留著。在去除第一骨幹特徵204之前或 期間，第一間隔層特徵206可以被薄化而形成變薄的第一間隔層特徵206’，如同圖2A中所描述者。此薄化可以被實施於BB1(特徵204)去除之前(如同所描述者)或之後，視BB2特徵(208，說明於下)所需之間隙及尺寸調整(sizing)而定。在操作(d)處，第一間隔層特徵206或變薄的第一間隔層特徵206’被用來圖案化諸如絕緣層或電介質硬遮罩層的材料層，以形成第二骨幹(BB2)特徵208。第二間隔層(SP2)特徵210然後被形成鄰接第二骨幹特徵208的側壁。在操作(e)處，第二骨幹特徵208被去除而僅剩下第二間隔層特徵210餘留著。餘留的第二間隔層特徵210然後可以被用來圖案化半導體層，以提供相較於初始之圖案化後的光阻特徵202具有間距經四等分後之尺寸的複數個半導體鰭部。做為範例，參照圖2B，諸如由塊狀矽層所形成之矽鰭部的複數個半導體鰭部250係使用第二間隔層特徵210作為用於該圖案化(例如，乾式或電漿蝕刻圖案化)的遮罩來予以形成。在圖2B的範例中，複數個半導體鰭部250基本上從頭到尾具有相同的間距和間隙。 Referring to FIG. 2A , at operation (a), a photoresist layer (PR) is patterned to form photoresist features 202 . The photoresist features 202 can be patterned using standard photolithographic processing techniques, such as 193 immersion photolithography. At operation (b), photoresist features 202 are used to pattern a layer of material, such as an insulating layer or a dielectric hard mask layer, to form first backbone ( BB1 ) features 204 . A first spacer ( SP1 ) feature 206 is then formed adjacent to the sidewall of the first backbone feature 204 . At operation (c), the first backbone feature 204 is removed leaving only the first spacer layer feature 206 remaining. Before removing the first backbone feature 204 or During this time, the first spacer feature 206 may be thinned to form a thinned first spacer feature 206', as depicted in FIG. 2A. This thinning can be performed before BB1 (feature 204) removal (as described) or after removal, depending on the clearance and sizing required for BB2 feature (208, described below). At operation (d), the first spacer feature 206 or the thinned first spacer feature 206' is used to pattern a layer of material such as an insulating layer or a dielectric hard mask layer to form a second backbone (BB2) Feature 208. A second spacer ( SP2 ) feature 210 is then formed adjacent to the sidewall of the second backbone feature 208 . At operation (e), the second backbone feature 208 is removed leaving only the second spacer layer feature 210 remaining. The remaining second spacer features 210 may then be used to pattern the semiconductor layer to provide a plurality of semiconductor fins having a pitched quarticed dimension compared to the initially patterned photoresist features 202 . As an example, referring to FIG. 2B, a plurality of semiconductor fins 250, such as silicon fins formed from a bulk silicon layer, use second spacer features 210 as the patterning (e.g., dry or plasma etch pattern) for the patterning. ) mask to be formed. In the example of FIG. 2B , the plurality of semiconductor fins 250 have substantially the same pitch and gap throughout.

可領會到初始圖案化後的光阻特徵間之間隙可以被修改以改變間距四等分處理的結構結果。在一範例中，圖3A為依據本發明的一實施例，用來製造半導體鰭部之合併鰭部間距四等分法300的示意圖。圖3B繪示依據本發明的一實施例，使用合併鰭部間距四等分法所製造之半導體鰭部的剖面視圖。 It can be appreciated that the gaps between photoresist features after initial patterning can be modified to alter the structural outcome of the pitch quartering process. In one example, FIG. 3A is a schematic diagram of a merged fin pitch quartering method 300 for fabricating semiconductor fins according to an embodiment of the present invention. 3B illustrates a cross-sectional view of a semiconductor fin fabricated using a merged fin pitch quartering method according to an embodiment of the present invention.

參照圖3A，在操作(a)處，光阻層(PR)被圖 案化而形成光阻特徵302。光阻特徵302可以使用標準的光刻處理技術(諸如，193浸沒式光刻法)，但是用最終可以與需要來產生均勻的間距倍增(multiplied)圖案的設計規則相干擾的間隙(例如，被稱為次設計規則空間的間隙)來予以圖案化。在操作(b)處，光阻特徵302被用來圖案化諸如絕緣層或電介質硬遮罩層的材料層，以形成第一骨幹(BB1)特徵304。第一間隔層(SP1)特徵306然後被形成鄰接第一骨幹特徵304的側壁。但是，和圖2A中所繪示的方案相反，有些相鄰的第一間隔層特徵306為合併的間隔層特徵做為更緊密的光阻特徵302的結果。在操作(c)處，第一骨幹特徵304被去除而僅剩下第一間隔層特徵306餘留著。在去除第一骨幹特徵304之前或之後，有些第一間隔層特徵306可以被薄化而形成變薄的第一間隔層特徵306’，如同圖3A中所描述者。在操作(d)處，第一間隔層特徵306和變薄的第一間隔層特徵306’被用來圖案化諸如絕緣層或電介質硬遮罩層的材料層，以形成第二骨幹(BB2)特徵308。第二間隔層(SP2)特徵310然後被形成鄰接第二骨幹特徵308的側壁。但是，在BB2特徵308為合併的特徵的位置，諸如在圖3A中央的BB2特徵308處，第二間隔層不被形成。在操作(e)處，第二骨幹特徵308被去除而僅剩下第二間隔層特徵310餘留著。餘留的第二間隔層特徵310然後可以被用來圖案化半導體層，以提供相較於初始之圖案化後的光阻特徵302具有間距經四等分後之尺寸的複數個半導體鰭部。 Referring to FIG. 3A, at operation (a), the photoresist layer (PR) is patterned patterned to form photoresist features 302 . The photoresist features 302 can use standard photolithographic processing techniques (such as 193 immersion lithography), but with gaps that can ultimately interfere with the design rules needed to produce uniform pitch multiplied (multiplied) patterns (e.g., by Gaps called sub-design rule spaces) to be patterned. At operation (b), photoresist features 302 are used to pattern a material layer, such as an insulating layer or a dielectric hard mask layer, to form first backbone ( BB1 ) features 304 . A first spacer ( SP1 ) feature 306 is then formed adjacent to the sidewall of the first backbone feature 304 . However, contrary to the scheme depicted in FIG. 2A , some of the adjacent first spacer features 306 are the result of the merged spacer features as the photoresist features 302 that are closer together. At operation (c), the first backbone feature 304 is removed leaving only the first spacer layer feature 306 remaining. Before or after removing the first backbone feature 304, some of the first spacer layer features 306 may be thinned to form a thinned first spacer layer feature 306', as depicted in FIG. 3A. At operation (d), the first spacer feature 306 and the thinned first spacer feature 306' are used to pattern a material layer, such as an insulating layer or a dielectric hard mask layer, to form a second backbone (BB2) Feature 308. A second spacer ( SP2 ) feature 310 is then formed adjacent to the sidewall of the second backbone feature 308 . However, where BB2 feature 308 is a merged feature, such as at BB2 feature 308 in the center of FIG. 3A , the second spacer layer is not formed. At operation (e), the second backbone feature 308 is removed leaving only the second spacer layer feature 310 remaining. The remaining second spacer features 310 may then be used to pattern the semiconductor layer to provide a plurality of semiconductor fins having a pitched quartiered dimension compared to the initially patterned photoresist features 302 .

做為範例，參照圖3B，諸如由塊狀矽層所形成之矽鰭部的複數個半導體鰭部350係使用第二間隔層特徵310作為用於該圖案化(例如，乾式或電漿蝕刻圖案化)的遮罩來予以形成。但是，在圖3B的範例中，該複數個半導體鰭部350具有變化的間距和間隙。此種合併鰭部間隔層圖案化法可以被施行，以基本上消除鰭部出現在複數個鰭部之圖案的某些位置。因此，如同參照圖2A及2B所說明的，在某些位置中合併第一間隔層特徵306允許基於兩個第一骨幹特徵304來製造六或四個鰭部，其典型上產生8個鰭部。在一個範例中，板內的鰭部具有比藉由以均勻的間距來產生鰭部而後切除不需要的鰭部所正常允許之間距更緊密的間距，雖然後者方法仍然可以依據本文中所述的實施例來予以施行。 As an example, referring to FIG. 3B, a plurality of semiconductor fins 350, such as silicon fins formed from a bulk silicon layer, use second spacer features 310 as the patterning (e.g., dry or plasma etched pattern) for the patterning. ) mask to be formed. However, in the example of FIG. 3B, the plurality of semiconductor fins 350 have varying pitches and gaps. Such combined fin spacer patterning can be performed to substantially eliminate the presence of fins in certain locations of the pattern of fins. Thus, as explained with reference to FIGS. 2A and 2B, incorporation of the first spacer feature 306 in certain locations allows six or four fins to be fabricated based on two first backbone features 304, which typically results in 8 fins. . In one example, the fins within the board have a closer pitch than would normally be allowed by creating the fins at a uniform pitch and then cutting off the unneeded fins, although the latter approach can still be based on the Examples are implemented.

在一代表性實施例中，參照圖3B，積體電路結構，第一複數個半導體鰭部352沿著第一方向(y，進入頁面中)具有最長的尺寸。第一複數個半導體鰭部352之相鄰的個別半導體鰭部353在與該第一方向y正交的第二方向(x)上彼此間隔開第一數量(S11)。第二複數個半導體鰭部354沿著該第一方向y具有最長的尺寸。第二複數個半導體鰭部354之相鄰的個別半導體鰭部355在該第二方向上彼此間隔開第一數量(S1)。第一複數個半導體鰭部352和第二複數個半導體鰭部354之最接近的半導體鰭部356和357分別在第二方向x上彼此間隔開第二數量(S2)。在一實施例中，第二數量S2大於第一數量S1但是小於第一數量S1的兩 倍。在另一實施例中，第二數量S2大於第一數量S1的兩倍。 In a representative embodiment, referring to FIG. 3B , the integrated circuit structure, the first plurality of semiconductor fins 352 has a longest dimension along a first direction (y, into the page). Adjacent individual semiconductor fins 353 of the first plurality of semiconductor fins 352 are spaced apart from each other by a first amount in a second direction (x) orthogonal to the first direction y ( S11 ). The second plurality of semiconductor fins 354 has the longest dimension along the first direction y. Adjacent individual semiconductor fins 355 of the second plurality of semiconductor fins 354 are spaced apart from each other by a first amount ( S1 ) in the second direction. The closest semiconductor fins 356 and 357 of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are spaced apart from each other by a second amount ( S2 ) in the second direction x, respectively. In one embodiment, the second number S2 is greater than the first number S1 but less than two times the first number S1 times. In another embodiment, the second number S2 is greater than twice the first number S1.

在一個實施例中，第一複數個半導體鰭部352和第二複數個半導體鰭部354包含矽。在一個實施例中，第一複數個半導體鰭部352和第二複數個半導體鰭部354與下面的(underlying)單晶矽基板係連續的。在一個實施例中，第一複數個半導體鰭部352和第二複數個半導體鰭部354之個別的一些沿著該第二方向x，從該第一複數個半導體鰭部352和該第二複數個半導體鰭部354之個別的一些的頂部到底部具有向外漸細(tapering)的側壁。在一個實施例中，第一複數個半導體鰭部352具有正好五個半導體鰭部，且第二複數個半導體鰭部354具有正好五個半導體鰭部。 In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 comprise silicon. In one embodiment, the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are continuous with the underlying monocrystalline silicon substrate. In one embodiment, individual ones of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 move along the second direction x from the first plurality of semiconductor fins 352 and the second plurality of Individual ones of the semiconductor fins 354 have sidewalls that taper outwardly from top to bottom. In one embodiment, the first plurality of semiconductor fins 352 has exactly five semiconductor fins and the second plurality of semiconductor fins 354 has exactly five semiconductor fins.

在另一個代表性實施例中，參照圖3A和3B，製造積體電路結構的方法包含形成第一主要骨幹結構304(左BB1)和第二主要骨幹結構304(右BB1)。主要間隔層結構306被形成鄰接第一主要骨幹結構304(左BB1)和第二主要骨幹結構304(右BB1)的側壁。第一主要骨幹結構304(左BB1)和第二主要骨幹結構304(右BB1)之間的主要間隔層結構306被合併。第一主要骨幹結構(左BB1)和第二主要骨幹結構(右BB1)被去除，而且第一、第二、第三和第四次要骨幹結構308被設置。第二和第三次要骨幹結構(例如，中央對的次要骨幹結構308)被合併。次要間隔層結構310被形成鄰接第一、第二、第三和第四次要骨幹結構308 的側壁。第一、第二、第三和第四次要骨幹結構308然後被去除。然後以次要間隔層結構310來使半導體材料圖案化而形成半導體鰭部350於半導體材料中。 In another representative embodiment, referring to FIGS. 3A and 3B , a method of fabricating an integrated circuit structure includes forming a first main backbone structure 304 (left BB1 ) and a second main backbone structure 304 (right BB1 ). The main bay structure 306 is formed adjacent to the sidewalls of the first main backbone structure 304 (left BB1 ) and the second main backbone structure 304 (right BB1 ). The main bay structure 306 between the first main backbone structure 304 (left BB1 ) and the second main backbone structure 304 (right BB1 ) is merged. The first main backbone structure (left BB1) and the second main backbone structure (right BB1) are removed, and first, second, third and fourth secondary backbone structures 308 are provided. The second and third secondary backbone structures (eg, the central pair of secondary backbone structures 308) are merged. A secondary spacer structure 310 is formed adjacent to the first, second, third and fourth secondary backbone structures 308 side wall. The first, second, third and fourth secondary backbone structures 308 are then removed. The semiconductor material is then patterned with the secondary spacer structure 310 to form semiconductor fins 350 in the semiconductor material.

在一個實施例中，以第一主要骨幹結構和第二主要骨幹結構之間的次設計規則間隙來圖案化第一主要骨幹結構304(左BB1)和第二主要骨幹結構304(右BB1)。在一個實施例中，半導體材料包含矽。在一個實施例中，半導體鰭部350之個別的一些沿著該第二方向x，從半導體鰭部350之個別的一些的頂部到底部具有向外漸細的側壁。在一個實施例中，半導體鰭部350與下面的單晶矽基板係連續的。在一個實施例中，以次要間隔層結構310來使半導體材料圖案化包含形成第一複數個半導體鰭部352，其沿著第一方向y具有最長的尺寸，其中，該第一複數個半導體鰭部352之相鄰的個別半導體鰭部在與該第一方向y正交的第二方向x上彼此間隔開第一數量S1。第二複數個半導體鰭部354係形成沿著該第一方向y具有最長的尺寸，其中，該第二複數個半導體鰭部354之相鄰的個別半導體鰭部在該第二方向x上彼此間隔開第一數量S1。第一複數個半導體鰭部352和第二複數個半導體鰭部354之最接近的半導體鰭部356和357分別在第二方向x上彼此間隔開第二數量S2。在一實施例中，第二數量S2大於第一數量S1。在一個這樣的實施例中，第二數量S2小於第一數量S1的兩倍。在另一個這樣的實施例中，第二數量S2大於第一數量S1的兩倍但是小於第一數量S1的三倍。在一實施例中，第一複 數個半導體鰭部352具有正好五個半導體鰭部，且第二複數個半導體鰭部254具有正好五個半導體鰭部，如同圖3B所描述的。 In one embodiment, the first major backbone structure 304 (left BB1 ) and the second major backbone structure 304 (right BB1 ) are patterned with a minor design rule gap between the first major backbone structure and the second major backbone structure. In one embodiment, the semiconductor material includes silicon. In one embodiment, individual ones of the semiconductor fins 350 have sidewalls that taper outwards from the top to the bottom of the individual ones of the semiconductor fins 350 along the second direction x. In one embodiment, the semiconductor fins 350 are continuous with the underlying monocrystalline silicon substrate. In one embodiment, patterning the semiconductor material with the secondary spacer structure 310 includes forming a first plurality of semiconductor fins 352 having a longest dimension along a first direction y, wherein the first plurality of semiconductor fins 352 has a longest dimension along a first direction y, wherein the first plurality of semiconductor fins 352 Adjacent individual semiconductor fins of the fins 352 are spaced apart from each other by a first amount S1 in a second direction x orthogonal to the first direction y. The second plurality of semiconductor fins 354 are formed to have the longest dimension along the first direction y, wherein adjacent individual semiconductor fins of the second plurality of semiconductor fins 354 are spaced from each other in the second direction x Open the first quantity S1. The closest semiconductor fins 356 and 357 of the first plurality of semiconductor fins 352 and the second plurality of semiconductor fins 354 are respectively spaced apart from each other by a second amount S2 in the second direction x. In an embodiment, the second quantity S2 is greater than the first quantity S1. In one such embodiment, the second number S2 is less than twice the first number S1. In another such embodiment, the second number S2 is greater than twice but less than three times the first number S1 . In one embodiment, the first Plurality of semiconductor fins 352 has exactly five semiconductor fins, and second plurality of semiconductor fins 254 has exactly five semiconductor fins, as depicted in FIG. 3B .

在另一態樣中，可領會到鰭部修整過程，其中，鰭部去除被實施作為合併鰭部法的替代方案，鰭部可以被修整(去除)於硬遮罩圖案化期間或者藉由實際地去除該鰭部。做為後一方法的範例，圖4A到4C為依據本發明的一實施例，代表製造複數個半導體鰭部的方法中之各種操作的剖面視圖。 In another aspect, a fin trim process can be envisioned where fin removal is performed as an alternative to the combined fin method, the fins can be trimmed (removed) during hard mask patterning or by actual remove the fin. As an example of the latter method, FIGS. 4A-4C are cross-sectional views representing various operations in a method of fabricating a plurality of semiconductor fins, in accordance with one embodiment of the present invention.

參照圖4A，圖案化後的硬遮罩層402被形成在半導體層404(諸如，塊狀單晶矽層)之上。參照圖4B，鰭部406然後被形成在半導體層404中，例如藉由乾式或電漿蝕刻製程。參照圖4C，選擇鰭部406被去除，例如使用遮罩和蝕刻製程。在所顯示的範例中，鰭部406的其中一個被去除並且可以留下剩餘的(remnant)鰭部殘材(stub)408，如同圖4C所描述的。在這樣的”鰭部修整最終(fin trim last)”方法中，硬遮罩402整個被圖案化來提供光柵結構而不需要去除或修改個別特徵。鰭部總數(population)不被修改直到鰭部被製造之後為止。 Referring to FIG. 4A, a patterned hard mask layer 402 is formed over a semiconductor layer 404, such as a bulk monocrystalline silicon layer. Referring to FIG. 4B , fins 406 are then formed in semiconductor layer 404 , such as by a dry or plasma etch process. Referring to FIG. 4C , select fins 406 are removed, eg, using a mask and etch process. In the example shown, one of the fins 406 is removed and a remnant fin stub 408 may be left, as depicted in FIG. 4C . In such a "fin trim last" approach, the entire hard mask 402 is patterned to provide a grating structure without removing or modifying individual features. The fin population is not modified until after the fins are fabricated.

在另一態樣中，多層溝槽隔離區域，其可以被稱為淺溝槽隔離(STI)結構，可以被施行於半導體鰭部之間。在一實施例中，多層STI結構被形成在塊狀矽基板中所形成的矽鰭部之間來定義矽鰭部的子鰭部區域。 In another aspect, multilayer trench isolation regions, which may be referred to as shallow trench isolation (STI) structures, may be implemented between semiconductor fins. In one embodiment, a multi-layer STI structure is formed between silicon fins formed in a bulk silicon substrate to define sub-fin regions of the silicon fins.

對於鰭部或基於三閘極的電晶體，希望使用 塊狀矽。然而，有一個問題在於該裝置之作用(active)矽鰭部部位下的區域(子鰭部)(例如，閘極控制區域或HSi)正在減少或者沒有閘極控制。因此，如果源極或汲極區域係在HSi點或者在HSi點之下，則漏洩通路可以存在於整個子鰭部區域中。其可以是針對適當的裝置操作，子鰭部區域中的漏洩通路(leakage pathway)應該被控制的情況。 For fin or tri-gate based transistors it is desirable to use bulk silicon. However, there is a problem that the area under the active silicon fin portion of the device (sub-fin) (eg, gate control area or HSi) is decreasing or has no gate control. Therefore, if the source or drain region is at or below the HSi point, a leakage path can exist throughout the sub-fin region. It may be the case that leakage pathways in the sub-fin region should be controlled for proper device operation.

解決上面問題的其中一種方法已經涉及了井佈植操作的使用，其中，子鰭部區域被重度摻雜(例如，遠大於2E18/cm3)，其切斷(shut off)子鰭部漏洩，但是也導致鰭部中的大量摻雜。環形佈植(halo implant)的添加進一步增加了鰭部摻雜，使得線端(end of line)的鰭部係摻雜以高位準(例如，大於約1E18/cm3)。 One of the approaches to address the above problem has involved the use of well implant operations where the sub-fin region is heavily doped (eg, much greater than 2E18/cm 3 ), which shuts off the sub-fin leakage, However, this also results in substantial doping in the fins. The addition of halo implants further increases the fin doping such that the fins at the end of line are doped at high levels (eg, greater than about 1E18/cm 3 ).

另一種方法涉及經由子鰭部摻雜所提供的摻雜，但不需要將相同的摻雜位準傳送進鰭部的HSi部位中。製程可能涉及選擇性地摻雜塊狀矽晶圓上所製造之三閘極或FinFET電晶體的子鰭部區域，例如藉由三閘極摻雜玻璃子鰭部向外擴散(out-diffusion)。例如，選擇性地摻雜三閘極或FinFET電晶體的子鰭部區域可以減緩子鰭部漏洩，且同時使鰭部摻雜保持低。使固態摻雜源(例如，p型及n型摻雜的氧化物、氮化物、或碳化物)結合入電晶體製程流程中，其係在從鰭部側壁凹入之後，將井摻雜傳送進子鰭部區域中，且同時使鰭部本體保持相對未被摻雜。 Another approach involves doping provided via sub-fin doping, but does not require delivering the same doping level into the HSi sites of the fin. The process may involve selectively doping the sub-fin regions of tri-gate or FinFET transistors fabricated on bulk silicon wafers, for example by out-diffusion of tri-gate doped glass sub-fins . For example, selectively doping the sub-fin regions of tri-gate or FinFET transistors can slow down sub-fin leakage while keeping the fin doping low. Incorporating solid-state dopant sources (e.g., p-type and n-type doped oxides, nitrides, or carbides) into the transistor process flow, after recessing from the fin sidewalls, transfers the well doping into the in the sub-fin region while leaving the fin body relatively undoped.

因而，製程方案可包含在鰭部蝕刻之後使用沉積在鰭部上的固態源摻雜層(例如，摻雜硼的氧化物)。 稍後，在溝槽填充和研磨之後，摻雜層和溝槽填充材料一起被凹入來界定裝置的鰭部高度(HSi)。該操作從HSi之上的鰭部側壁去除摻雜層。因此，摻雜層僅沿著子鰭部區域中的鰭部側壁出現，其確保摻雜放置(placement)的精確控制。在驅入式退火(drive-in anneal)之後，高摻雜被限制於子鰭部區域，在HSi之上鰭部的相鄰區域(其構成電晶體的通道區域)中快速地轉變到低摻雜。通常，對NMOS鰭部摻雜施行硼矽酸鹽玻璃(BSG)，而對PMOS鰭部摻雜施行磷矽酸鹽玻璃(PSG)或砷矽酸鹽玻璃(AsSG)層。在一個範例中，此種P型固態摻雜劑源層為具有硼濃度約在0.1到10重量百分比(weight%)之範圍中的BSG層。在另一個範例中，此種N型固態摻雜劑源層為分別具有磷或砷濃度約在0.1到10重量百分比(weight%)之範圍中的PSG層或AsSG層。氮化矽覆蓋層(capping layer)可以被包含在摻雜層上，而且二氧化矽或氧化矽填充材料然後可以被包含在氮化矽覆蓋層上。 Thus, the process scheme may include using a solid source doping layer (eg, boron-doped oxide) deposited on the fins after the fin etch. Later, after trench filling and grinding, the doped layer is recessed along with the trench fill material to define the fin height (HSi) of the device. This operation removes the doped layer from the sidewalls of the fin above the HSi. Thus, the doped layer occurs only along the fin sidewalls in the sub-fin region, which ensures precise control of doping placement. After a drive-in anneal, the high doping is confined to the sub-fin region, with a rapid transition to low doping in the adjacent region of the fin above the HSi, which constitutes the channel region of the transistor. miscellaneous. Typically, borosilicate glass (BSG) is applied to the NMOS fin doping, while a phosphosilicate glass (PSG) or arsenosilicate glass (AsSG) layer is applied to the PMOS fin doping. In one example, such a P-type solid dopant source layer is a BSG layer having a boron concentration in the range of approximately 0.1 to 10 weight percent (weight%). In another example, the N-type solid dopant source layer is a PSG layer or an AsSG layer having a phosphorus or arsenic concentration in the range of approximately 0.1 to 10 weight percent, respectively. A silicon nitride capping layer can be included on the doped layer, and a silicon dioxide or silicon oxide fill material can then be included on the silicon nitride capping layer.

依據本發明的另一實施例，對於相對較薄的鰭部(例如，具有小於約20奈米之寬度的鰭部)來說，子鰭部漏洩係足夠低的，而在相對較薄的鰭部中，未摻雜或輕度摻雜的氧化矽或二氧化矽膜係形成直接鄰接鰭部，氮化矽層係形成在未摻雜或輕度摻雜的氧化矽或二氧化矽膜上，而且二氧化矽或氧化矽填充材料被包含在氮化矽覆蓋層上。可領會到子鰭部區域的摻雜(諸如，環形摻雜)也可以用此種結構來予以佈植。 According to another embodiment of the present invention, sub-fin leakage is sufficiently low for relatively thin fins (e.g., fins having a width of less than about 20 nanometers), while in relatively thin fins In the portion, an undoped or lightly doped silicon oxide or silicon dioxide film is formed directly adjacent to the fin, and a silicon nitride layer is formed on the undoped or lightly doped silicon oxide or silicon dioxide film , and a silicon dioxide or silicon oxide fill material is contained on the silicon nitride capping layer. It can be appreciated that doping of sub-fin regions, such as halo doping, can also be implanted with this structure.

圖5A繪示依據本發明的一實施例，由三層的溝槽隔離結構所分隔之一對半導體鰭部的剖面視圖。 5A illustrates a cross-sectional view of a pair of semiconductor fins separated by a three-layer trench isolation structure according to an embodiment of the present invention.

參照圖5A，積體電路結構包含諸如矽鰭部的鰭部502。鰭部502具有下鰭部部位(子鰭部)502A和上鰭部部位502B(HSi)。第一絕緣層504係直接在鰭部502之下鰭部部位502A的側壁上。第二絕緣層506係直接在鰭部502之下鰭部部位502A的側壁上的第一絕緣層504上。電介質填充材料508係直接橫向鄰接於直接在直接在鰭部502之下鰭部部位502A的側壁上之第一絕緣層504上的第二絕緣層506。 Referring to FIG. 5A , the integrated circuit structure includes fins 502 such as silicon fins. Fin 502 has a lower fin location (sub-fin) 502A and an upper fin location 502B (H Si ). The first insulating layer 504 is directly under the fin 502 on the sidewall of the fin portion 502A. The second insulating layer 506 is directly on the first insulating layer 504 on the sidewalls of the fin portion 502A below the fin 502 . The dielectric fill material 508 is directly laterally adjacent to the second insulating layer 506 on the first insulating layer 504 directly on the sidewalls of the fin portion 502A directly below the fin 502 .

在一實施例中，第一絕緣層504為包含矽和氧的非摻雜(non-doped)絕緣層，諸如，氧化矽或二氧化矽絕緣層。在一實施例中，第一絕緣層504包含矽和氧並且沒有任何其他具有大於每立方公分1E15之原子濃度的原子物種。在一實施例中，第一絕緣層504具有在0.5到2奈米之範圍中的厚度。 In one embodiment, the first insulating layer 504 is a non-doped insulating layer including silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, the first insulating layer 504 includes silicon and oxygen and is free of any other atomic species having an atomic concentration greater than 1E15 per cubic centimeter. In one embodiment, the first insulating layer 504 has a thickness in the range of 0.5 to 2 nm.

在一實施例中，第二絕緣層506包含矽和氮，諸如化學當量的Si3N4氮化矽絕緣層、富含矽的氮化矽絕緣層、或貧含矽的氮化矽絕緣層。在一實施例中，第二絕緣層506具有在2到5奈米之範圍中的厚度。 In one embodiment, the second insulating layer 506 includes silicon and nitrogen, such as a chemically equivalent Si 3 N 4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. . In an embodiment, the second insulating layer 506 has a thickness in the range of 2 to 5 nanometers.

在一實施例中，電介質填充材料508包含矽和氧，諸如，氧化矽或二氧化矽絕緣層。在一實施例中，閘極電極最終被形成在鰭部502之上鰭部部位502B之側壁的頂部之上並且橫向鄰接於鰭部502之上鰭部部位502B的 側壁。 In one embodiment, the dielectric fill material 508 includes silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, the gate electrode is ultimately formed on top of the sidewalls of fin portion 502B above fin 502 and laterally adjacent to the top of fin portion 502B above fin 502 . side wall.

將領會到在處理期間，半導體鰭部的上鰭部部位可以被腐蝕(erode)或損耗(consume)。而且，鰭部之間的溝槽隔離結構也可以變成被腐蝕而具有非平面形貌(topography)，或者可以被形成有非平面形貌向上的製造。做為範例，圖5B繪示依據本發明的另一實施例，由另一個三層溝槽隔離結構所分隔之另一對半導體鰭部的剖面視圖。 It will be appreciated that during processing, upper fin portions of the semiconductor fins may be erode or consumed. Furthermore, the trench isolation structure between the fins may also become etched to have a non-planar topography, or may be formed with a topography-up fabrication. As an example, FIG. 5B shows a cross-sectional view of another pair of semiconductor fins separated by another three-layer trench isolation structure according to another embodiment of the present invention.

參照圖5B，積體電路結構包含諸如矽鰭部的第一鰭部552。第一鰭部552具有下鰭部部位552A和上鰭部部位552B以及在下鰭部部位552A與上鰭部部位552B間之區域處的肩部特徵554。諸如第二矽鰭部的第二鰭部562具有下鰭部部位562A和上鰭部部位562B以及在下鰭部部位562A與上鰭部部位562B間之區域處的肩部特徵564。第一絕緣層574係直接在第一鰭部552之下鰭部部位552A的側壁上並且直接在第二鰭部562之下鰭部部位562A的側壁上。第一絕緣層574具有實質上與第一鰭部552之肩部特徵554共平面的第一末端部位574A，而且第一絕緣層574另具有實質上與第二鰭部562之肩部特徵564共平面的第二末端部位574B。第二絕緣層576係直接在直接在第一鰭部552之下鰭部部位552A的側壁上的第一絕緣層574上，且直接在第二鰭部562的下鰭部部位562A的側壁上。 Referring to FIG. 5B , the integrated circuit structure includes a first fin 552 such as a silicon fin. The first fin 552 has a lower fin location 552A and an upper fin location 552B and a shoulder feature 554 at an area between the lower fin location 552A and the upper fin location 552B. A second fin 562 , such as a second silicon fin, has a lower fin location 562A and an upper fin location 562B and a shoulder feature 564 at an area between the lower fin location 562A and the upper fin location 562B. The first insulating layer 574 is directly on the sidewall of the fin portion 552A below the first fin 552 and directly on the sidewall of the fin portion 562A below the second fin 562 . The first insulating layer 574 has a first end portion 574A that is substantially coplanar with the shoulder feature 554 of the first fin 552, and the first insulating layer 574 further has a first end portion 574A that is substantially coplanar with the shoulder feature 564 of the second fin 562. Planar second end portion 574B. The second insulating layer 576 is directly on the first insulating layer 574 directly on the sidewall of the fin portion 552A directly below the first fin 552 and directly on the sidewall of the lower fin portion 562A of the second fin 562 .

電介質填充材料578係直接橫向鄰接於直接在直接在第一鰭部552之下鰭部部位552A的側壁上並且直 接在第二鰭部562之下鰭部部位562A的側壁上之第一絕緣層574上的第二絕緣層576。在一實施例中，電介質填充材料578具有上表面578A，其中，該電介質填充材料578之上表面578A的一部位係在第一鰭部552之該等肩部特徵554的至少其中一者之下以及在第二鰭部562之該等肩部特徵564的至少其中一者之下，如同圖5B中所描述的。 The dielectric fill material 578 is directly laterally adjacent to the sidewall of the fin portion 552A directly below the first fin 552 and directly The second insulating layer 576 is connected to the first insulating layer 574 on the sidewall of the fin portion 562A under the second fin 562 . In one embodiment, the dielectric fill material 578 has an upper surface 578A, wherein a portion of the upper surface 578A of the dielectric fill material 578 underlies at least one of the shoulder features 554 of the first fin 552 And under at least one of the shoulder features 564 of the second fin 562, as depicted in FIG. 5B.

在一實施例中，第一絕緣層574為包含矽和氧的非摻雜絕緣層，諸如，氧化矽或二氧化矽絕緣層。在一實施例中，第一絕緣層574包含矽和氧並且沒有任何其他具有大於每立方公分1E15之原子濃度的原子物種。在一實施例中，第一絕緣層574具有在0.5到2奈米之範圍中的厚度。 In one embodiment, the first insulating layer 574 is a non-doped insulating layer including silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, the first insulating layer 574 includes silicon and oxygen and is free of any other atomic species having an atomic concentration greater than 1E15 per cubic centimeter. In one embodiment, the first insulating layer 574 has a thickness in the range of 0.5 to 2 nm.

在一實施例中，第二絕緣層576包含矽和氮，諸如化學當量的Si3N4氮化矽絕緣層、富含矽的氮化矽絕緣層、或貧含矽的氮化矽絕緣層。在一實施例中，第二絕緣層576具有在2到5奈米之範圍中的厚度。 In one embodiment, the second insulating layer 576 includes silicon and nitrogen, such as a chemically equivalent Si 3 N 4 silicon nitride insulating layer, a silicon-rich silicon nitride insulating layer, or a silicon-poor silicon nitride insulating layer. . In an embodiment, the second insulating layer 576 has a thickness in the range of 2 to 5 nanometers.

在一實施例中，電介質填充材料578包含矽和氧，諸如，氧化矽或二氧化矽絕緣層。在一實施例中，閘極電極最終被形成在第一鰭部552之上鰭部部位552B之側壁的頂部之上並且橫向鄰接於第一鰭部552之上鰭部部位552B的側壁，而且在第二鰭部562之上鰭部部位562B之側壁的頂部之上並且橫向鄰接於第二鰭部562之上鰭部部位562B的側壁。閘極電極係進一步在第一鰭部552與第二鰭部562之間的電介質填充材料578之上。 In one embodiment, the dielectric fill material 578 includes silicon and oxygen, such as a silicon oxide or silicon dioxide insulating layer. In one embodiment, the gate electrode is ultimately formed on top of the sidewall of fin portion 552B above first fin 552 and laterally adjacent to the sidewall of fin portion 552B above first fin 552 , and at The top of the sidewall of the upper fin portion 562B of the second fin 562 is above and laterally adjacent to the sidewall of the upper fin portion 562B of the second fin 562 . The gate electrode is further over the dielectric fill material 578 between the first fin 552 and the second fin 562 .

圖6A到6D繪示依據本發明的一實施例，製造三層溝槽隔離結構之各種操作的剖面視圖。 6A to 6D illustrate cross-sectional views of various operations for fabricating a three-layer trench isolation structure in accordance with an embodiment of the present invention.

參照圖6A，製造積體電路結構的方法包含形成諸如矽鰭部的鰭部602。第一絕緣層604係直接形成在鰭部602上並且與鰭部602共形(conformal)，如同圖6B中所描述的。在一實施例中，第一絕緣層604包含矽和氧並且沒有任何其他具有大於每立方公分1E15之原子濃度的原子物種。 Referring to FIG. 6A, a method of fabricating an integrated circuit structure includes forming fins 602, such as silicon fins. The first insulating layer 604 is formed directly on and conformal to the fin 602 as described in FIG. 6B . In one embodiment, the first insulating layer 604 includes silicon and oxygen and is free of any other atomic species having an atomic concentration greater than 1E15 per cubic centimeter.

參照圖6C，第二絕緣層606係直接形成在第一絕緣層604上並且與第一絕緣層604共形。在一實施例中，第二絕緣層606包含矽和氮。電介質填充材料608係直接形成在第二絕緣層606上，如同圖6D中所描述的。 Referring to FIG. 6C , the second insulating layer 606 is formed directly on and conformal to the first insulating layer 604 . In one embodiment, the second insulating layer 606 includes silicon and nitrogen. A dielectric fill material 608 is formed directly on the second insulating layer 606, as depicted in FIG. 6D.

在一實施例中，該方法進一步涉及使電介質填充材料608、第一絕緣層604和第二絕緣層606凹入以提供具有露出之上鰭部部位602A的鰭部602(例如，諸如圖5A和5B的上鰭部部位502B,552B或562B)。該所得結構可以如同參照圖5A或5B所述者。在一實施例中，使電介質填充材料608、第一絕緣層604和第二絕緣層606凹入涉及使用濕式蝕刻製程。在另一實施例中，使電介質填充材料608、第一絕緣層604和第二絕緣層606凹入涉及使用電漿蝕刻或乾式蝕刻製程。 In one embodiment, the method further involves recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 to provide the fin 602 with exposed upper fin portion 602A (eg, such as in FIGS. 5A and 602A ). 5B upper fin portion 502B, 552B or 562B). The resulting structure may be as described with reference to Figures 5A or 5B. In one embodiment, recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 involves using a wet etch process. In another embodiment, recessing the dielectric fill material 608, the first insulating layer 604, and the second insulating layer 606 involves using a plasma etch or dry etch process.

在一實施例中，使用化學氣相沉積製程來形成第一絕緣層604。在一實施例中，使用化學氣相沉積製程來形成第二絕緣層606。在一實施例中，使用旋轉塗佈 (spin-on)製程來形成電介質填充材料608。在一個這樣的實施例中，電介質填充材料608為旋轉塗佈材料並且係暴露於蒸氣處理，例如在凹入蝕刻製程之前或之後，以提供包含矽和氧的固化材料(cured material)。在一實施例中，閘極電極最終被形成在鰭部602之上鰭部部位之側壁的頂部之上並且橫向鄰接於鰭部602之上鰭部部位的側壁。 In one embodiment, the first insulating layer 604 is formed using a chemical vapor deposition process. In one embodiment, the second insulating layer 606 is formed using a chemical vapor deposition process. In one embodiment, using spin coating (spin-on) process to form the dielectric filling material 608 . In one such embodiment, the dielectric fill material 608 is a spin-on material and is exposed to a vapor process, eg, before or after a recess etch process, to provide a cured material comprising silicon and oxygen. In one embodiment, the gate electrode is ultimately formed on top of the sidewall of the fin portion above the fin 602 and laterally adjacent to the sidewall of the fin portion above the fin 602 .

在另一態樣中，閘極側壁間隔層材料可以被保留在某些溝槽隔離區域之上作為在後續的處理操作期間對抗溝槽隔離區域之腐蝕的保護。例如，圖7A到7E繪示依據本發明的一實施例，在製造積體電路結構之方法中各種操作之有角度的三維剖面視圖。 In another aspect, gate sidewall spacer material may be retained over certain trench isolation regions as protection against corrosion of the trench isolation regions during subsequent processing operations. For example, FIGS. 7A-7E illustrate angled three-dimensional cross-sectional views of various operations in a method of fabricating an integrated circuit structure in accordance with one embodiment of the present invention.

參照圖7A，製造積體電路結構之方法包含形成諸如矽鰭部的鰭部702。鰭部702具有下鰭部部位702A和上鰭部部位702B。絕緣結構704被形成直接鄰接鰭部702之下鰭部部位702A的側壁。閘極結構706係形成在上鰭部部位702B之上和在絕緣結構704之上。在一實施例中，閘極結構為佔位件(placeholder)或假性(dummy)閘極結構，其包含犧牲閘極電介質層706A、犧牲閘極706B、和硬遮罩706C。電介質材料708係形成與鰭部702之上鰭部部位702B共形，與閘極結構706共形，以及與絕緣結構704共形。 Referring to FIG. 7A, a method of fabricating an integrated circuit structure includes forming fins 702, such as silicon fins. Fin 702 has a lower fin location 702A and an upper fin location 702B. Isolation structure 704 is formed directly adjacent to the sidewall of fin region 702A beneath fin 702 . Gate structure 706 is formed over upper fin portion 702B and over insulating structure 704 . In one embodiment, the gate structure is a placeholder or dummy gate structure, which includes a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C. Dielectric material 708 is formed conformal to fin region 702B above fin 702 , conformal to gate structure 706 , and conformal to isolation structure 704 .

參照圖7B，硬遮罩材料710係形成於電介質材料708之上。在一實施例中，硬遮罩材料710為使用旋轉塗佈製程所形成之以碳為基礎的硬遮罩材料。 Referring to FIG. 7B , hard mask material 710 is formed over dielectric material 708 . In one embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin coating process.

參照圖7C，硬遮罩材料710被凹入而形成凹入的硬遮罩材料712並且使電介質材料708之與鰭部702之上鰭部部位702B共形和與閘極結構706共形的部位暴露出。凹入的硬遮罩材料712覆蓋電介質材料708之與絕緣結構704共形的部位。在一實施例中，使用濕式蝕刻製程來使硬遮罩材料710被凹入。在另一實施例中，使用灰化、乾式蝕刻或電漿蝕刻製程來使硬遮罩材料710被凹入。 Referring to FIG. 7C , the hard mask material 710 is recessed to form a recessed hard mask material 712 and to conform the portion of the dielectric material 708 with the fin portion 702B above the fin 702 and with the gate structure 706 exposed. The recessed hard mask material 712 covers the portions of the dielectric material 708 that conform to the insulating structure 704 . In one embodiment, the hard mask material 710 is recessed using a wet etch process. In another embodiment, the hard mask material 710 is recessed using an ashing, dry etching, or plasma etching process.

參照圖7D，電介質材料708被各向異性蝕刻而沿著閘極結構706的側壁(作為電介質間隔層714A)、沿著鰭部702之上鰭部部位702B之側壁的部位、以及在絕緣結構704之上形成圖案化後的電介質材料714。 7D, the dielectric material 708 is anisotropically etched along the sidewalls of the gate structure 706 (as the dielectric spacer 714A), along the sidewalls of the fin portion 702B above the fin 702, and at the location of the insulating structure 704. A patterned dielectric material 714 is formed thereon.

參照圖7E，凹入的硬遮罩材料712從圖7D的結構中被去除。在一實施例中，閘極結構706為假性閘極結構，並且後續的處理包含用永久性閘極電介質和閘極電極堆疊來取代閘極結構706。在一實施例中，進一步的處理包含形成嵌入的源極或汲極結構於閘極結構706的相反側上，如同下面所更加詳細說明的。 Referring to FIG. 7E, the recessed hard mask material 712 is removed from the structure of FIG. 7D. In one embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and gate electrode stack. In one embodiment, further processing includes forming embedded source or drain structures on opposite sides of the gate structure 706, as described in more detail below.

再次參照圖7E，在一實施例中，積體電路結構700包含諸如第一矽鰭部的第一鰭部(左702)，該第一鰭部具有下鰭部部位702A和上鰭部部位702B。積體電路結構700包含進一步包含諸如第二矽鰭部的第二鰭部(右702)，該第二鰭部具有下鰭部部位702A和上鰭部部位702B。絕緣結構704被形成直接鄰接第一鰭部之下鰭部部位702A的側壁和直接鄰接第二鰭部之下鰭部部位702A的 側壁。閘極電極706係在第一鰭部(左702)的上鰭部部位702B之上、第二鰭部(右702)的上鰭部部位702B之上、以及在絕緣結構704的第一部位704A之上。第一電介質間隔層714A係沿著第一鰭部(左702)之上鰭部部位702B的側壁，且第二電介質間隔層702C係沿著第二鰭部(右702)之上鰭部部位702B的側壁。第二電介質間隔層714C在第一鰭部(左702)與第二鰭部(右702)之間與絕緣結構704的第二部位704B之上的第一電介質間隔層714B係連續的。 Referring again to FIG. 7E , in one embodiment, the integrated circuit structure 700 includes a first fin (left 702 ), such as a first silicon fin, having a lower fin portion 702A and an upper fin portion 702B. . The integrated circuit structure 700 further includes a second fin (right 702 ), such as a second silicon fin, having a lower fin location 702A and an upper fin location 702B. The insulating structure 704 is formed directly adjacent to the sidewall of the fin portion 702A directly below the first fin and directly adjacent to the sidewall of the fin portion 702A directly below the second fin. side wall. Gate electrode 706 is tied over upper fin portion 702B of the first fin (left 702 ), over upper fin portion 702B of the second fin (right 702 ), and at first portion 704A of insulating structure 704 above. The first dielectric spacer 714A is along the sidewall of the fin portion 702B above the first fin (left 702 ), and the second dielectric spacer 702C is along the fin portion 702B above the second fin (right 702 ). side wall. The second dielectric spacer layer 714C is continuous with the first dielectric spacer layer 714B over the second portion 704B of the insulating structure 704 between the first fin (left 702 ) and the second fin (right 702 ).

在一實施例中，第一和第二電介質間隔層714B和714C包含矽和氮，諸如化學當量的Si3N4氮化矽材料、富含矽的氮化矽材料、或貧含矽的氮化矽材料。 In one embodiment, the first and second dielectric spacers 714B and 714C comprise silicon and nitrogen, such as a stoichiometric Si 3 N 4 silicon nitride material, a silicon-rich silicon nitride material, or a silicon-poor nitrogen material. Silicon material.

在一實施例中，積體電路結構700進一步包含在閘極電極706之相反側上嵌入的源極或汲極結構、沿著第一和第二鰭部702之上鰭部部位702B的側壁具有在第一和第二電介質間隔層714B和714C的頂部表面之下的底部表面之嵌入的源極或汲極結構、以及沿著第一和第二鰭部702之上鰭部部位702B的側壁具有在第一和第二電介質間隔層714B和714C的頂部表面之上的頂部表面的源極或汲極結構，如同下面參照圖9B所述者。在一實施例中，絕緣結構704包含第一絕緣層、直接在第一絕緣層上的第二絕緣層、以及直接橫向地在第二絕緣層上的電介質填充材料，也如同下面參照圖9B所述者。 In one embodiment, the integrated circuit structure 700 further includes embedded source or drain structures on opposite sides of the gate electrode 706 , along the sidewalls of the fin portion 702B above the first and second fins 702 . Embedded source or drain structures between the bottom surfaces below the top surfaces of the first and second dielectric spacers 714B and 714C, and along the sidewalls of the fin portion 702B above the first and second fins 702 have The source or drain structures of the top surfaces over the top surfaces of the first and second dielectric spacers 714B and 714C are as described below with reference to FIG. 9B . In one embodiment, the insulating structure 704 includes a first insulating layer, a second insulating layer directly on the first insulating layer, and a dielectric fill material directly and laterally on the second insulating layer, also as described below with reference to FIG. 9B . Narrator.

圖8A到8F繪示依據本發明的一實施例，針對製造積體電路結構之方法中的各種操作，沿著圖7E的a 到a’軸線所取出之略微突出(projected)的剖面視圖。 8A to 8F illustrate various operations in a method of fabricating an integrated circuit structure, along line a of FIG. 7E , according to an embodiment of the present invention. Slightly projected sectional view taken to the a' axis.

參照圖8A，製造積體電路結構之方法包含形成諸如矽鰭部的鰭部702。鰭部702具有下鰭部部位(未見於圖8A中)和上鰭部部位702B。絕緣結構704被形成直接鄰接鰭部702之下鰭部部位702A的側壁。一對閘極結構706係形成在上鰭部部位702B之上和在絕緣結構704之上。可領會到圖8A到8F中所顯示的透視圖係稍微突出來顯示閘極結構706和絕緣結構在上鰭部部位702B之前(在頁面之外)的部位具有稍微進入該頁面中的上鰭部部位。在一實施例中，閘極結構706為佔位件(placeholder)或假性閘極結構，其包含犧牲閘極電介質層706A、犧牲閘極706B、和硬遮罩706C。 Referring to FIG. 8A, a method of fabricating an integrated circuit structure includes forming fins 702, such as silicon fins. Fin 702 has a lower fin location (not seen in FIG. 8A ) and an upper fin location 702B. Isolation structure 704 is formed directly adjacent to the sidewall of fin region 702A beneath fin 702 . A pair of gate structures 706 is formed over the upper fin portion 702B and over the isolation structure 704 . It can be appreciated that the perspective views shown in FIGS. 8A-8F are slightly extruded to show that the portion of the gate structure 706 and insulating structure before (outside of the page) the upper fin location 702B has the upper fin slightly into the page. parts. In one embodiment, the gate structure 706 is a placeholder or dummy gate structure, which includes a sacrificial gate dielectric layer 706A, a sacrificial gate 706B, and a hard mask 706C.

參照圖8B，其對應於相關於圖7A所說明的製程操作，電介質材料708係形成與鰭部702之上鰭部部位702B共形，與閘極結構706共形，以及與絕緣結構704之露出的部位共形。 Referring to FIG. 8B , which corresponds to the process operations described with respect to FIG. 7A , dielectric material 708 is formed conformal to fin portion 702B above fin 702 , conformal to gate structure 706 , and exposed to insulating structure 704 . The parts are conformal.

參照圖8C，其對應於相關於圖7B所說明的製程操作，硬遮罩材料710係形成於電介質材料708之上。在一實施例中，硬遮罩材料710為使用旋轉塗佈製程所形成之以碳為基礎的硬遮罩材料。 Referring to FIG. 8C , which corresponds to the process operations described with respect to FIG. 7B , hard mask material 710 is formed over dielectric material 708 . In one embodiment, the hard mask material 710 is a carbon-based hard mask material formed using a spin coating process.

參照圖8D，其對應於相關於圖7C所說明的製程操作，硬遮罩材料710被凹入而形成凹入的硬遮罩材料712並且使電介質材料708之與鰭部702之上鰭部部位702B共形和與閘極結構706共形的部位暴露出。凹入的硬 遮罩材料712覆蓋電介質材料708之與絕緣結構704共形的部位。在一實施例中，使用濕式蝕刻製程來使硬遮罩材料710被凹入。在另一實施例中，使用灰化、乾式蝕刻或電漿蝕刻製程來使硬遮罩材料710被凹入。 Referring to FIG. 8D , which corresponds to the process operation described with respect to FIG. 7C , the hard mask material 710 is recessed to form a recessed hard mask material 712 and to align the dielectric material 708 with the fin portion above the fin 702 . 702B is conformal and conformal with gate structure 706 is exposed. concave hard Masking material 712 covers portions of dielectric material 708 that conform to insulating structure 704 . In one embodiment, the hard mask material 710 is recessed using a wet etch process. In another embodiment, the hard mask material 710 is recessed using an ashing, dry etching, or plasma etching process.

參照圖8E，其對應於相關於圖7D所說明的製程操作，電介質材料708被各向異性蝕刻而沿著閘極結構706的側壁(作為部位714A)、沿著鰭部702之上鰭部部位702B之側壁的部位、以及在絕緣結構704之上形成圖案化後的電介質材料714。 Referring to FIG. 8E , which corresponds to the process operation described with respect to FIG. 7D , the dielectric material 708 is anisotropically etched along the sidewall of the gate structure 706 (as location 714A), along the fin portion above the fin 702 . The portion of the sidewall of 702B and the patterned dielectric material 714 are formed on the insulating structure 704 .

參照圖8F，其對應於相關於圖7E所說明的製程操作，凹入的硬遮罩材料712從圖8E的結構中被去除。在一實施例中，閘極結構706為假性閘極結構，並且後續的處理包含用永久性閘極電介質和閘極電極堆疊來取代閘極結構706。在一實施例中，進一步的處理包含形成嵌入的源極或汲極結構於閘極結構706的相反側上，如同下面所更加詳細說明的。 Referring to FIG. 8F , which corresponds to the process operation described with respect to FIG. 7E , the recessed hard mask material 712 is removed from the structure of FIG. 8E . In one embodiment, the gate structure 706 is a dummy gate structure, and subsequent processing includes replacing the gate structure 706 with a permanent gate dielectric and gate electrode stack. In one embodiment, further processing includes forming embedded source or drain structures on opposite sides of the gate structure 706, as described in more detail below.

再次參照圖8F，在一實施例中，積體電路結構700包含諸如矽鰭部的鰭部702，該鰭部702具有下鰭部部位(未見於圖8F中)和上鰭部部位702B。絕緣結構704被形成直接鄰接鰭部702之下鰭部部位的側壁。第一閘極電極(左706)係在上鰭部部位702B之上和在絕緣結構704的第一部位704A之上。第二閘極電極(右706)係在上鰭部部位702B之上和在絕緣結構704的第二部位704A’之上。第一電介質間隔層(左706的右714A)係沿著第一閘極電極(左706) 的側壁，且第二電介質間隔層(右706的左714A)係沿著第二閘極電極(右706)的側壁，第二電介質間隔層在第一閘極電極(左706)與第二閘極電極(右706)之間與絕緣結構704的第三部位704A”之上的第一電介質間隔層係連續的。 Referring again to FIG. 8F , in one embodiment, integrated circuit structure 700 includes a fin 702 , such as a silicon fin, having a lower fin portion (not shown in FIG. 8F ) and an upper fin portion 702B. The isolation structure 704 is formed directly adjacent to the sidewall of the fin portion below the fin 702 . A first gate electrode (left 706 ) is tied over the upper fin portion 702B and over the first portion 704A of the insulating structure 704 . The second gate electrode (right 706) is tied over the upper fin portion 702B and over the second portion 704A' The first dielectric spacer (right 714A of left 706) is along the first gate electrode (left 706) , and the second dielectric spacer (left 714A of right 706) is along the sidewall of the second gate electrode (right 706), and the second dielectric spacer is between the first gate electrode (left 706) and the second gate The first dielectric spacer layer is continuous between the polar electrodes (right 706 ) and above the third portion 704A″ of the insulating structure 704 .

圖9A繪示依據本發明的一實施例，針對包含永久性閘極堆疊和磊晶的源極或汲極區域之積體電路結構，沿著圖7E的a到a’軸線所取出之略微突出的剖面視圖。圖9B繪示依據本發明的一實施例，針對包含磊晶的源極或汲極區域和多層的溝槽隔離結構之積體電路結構，沿著圖7E的b到b-b’軸線所取出的剖面視圖。 9A shows a slight protrusion taken along the a to a' axis of FIG. 7E for an integrated circuit structure including a permanent gate stack and an epitaxial source or drain region according to an embodiment of the present invention. section view. FIG. 9B shows an integrated circuit structure including an epitaxial source or drain region and a multilayer trench isolation structure, taken along the axis b to bb' of FIG. 7E , according to an embodiment of the present invention. section view.

參照圖9A和9B，在一實施例中，積體電路結構包含在閘極電極706之相反側上的嵌入的源極或汲極結構910。嵌入的源極或汲極結構910具有沿著第一和第二鰭部702之上鰭部部位702B的側壁，在第一和第二電介質間隔層714B和714C的頂部表面990之下的底部表面910A。嵌入的源極或汲極結構910具有沿著第一和第二鰭部702之上鰭部部位702B的側壁，在第一和第二電介質間隔層714B和714C的頂部表面之上的頂部表面910B。 Referring to FIGS. 9A and 9B , in one embodiment, the integrated circuit structure includes an embedded source or drain structure 910 on the opposite side of the gate electrode 706 . The embedded source or drain structure 910 has a bottom surface below the top surface 990 of the first and second dielectric spacers 714B and 714C along the sidewalls of the fin portion 702B above the first and second fins 702 910A. The embedded source or drain structure 910 has a top surface 910B above the top surfaces of the first and second dielectric spacers 714B and 714C along the sidewalls of the fin portion 702B above the first and second fins 702 . .

在一實施例中，閘極堆疊706為永久性閘極堆疊920。在一個這樣的實施例中，永久性閘極堆疊920包含閘極電介質層922、諸如功函數閘極層的第一閘極層924、以及閘極填充材料926，如圖9A中所示。在一個實施例中，其中，永久性閘極結構920係在絕緣結構704之上，永久性閘極結構920係形成在殘餘的多晶矽部位930上，其 可以是涉及犧牲多晶矽閘極電極之置換(replacement)閘極製程的殘留物(remnant)。 In one embodiment, the gate stack 706 is a permanent gate stack 920 . In one such embodiment, a permanent gate stack 920 includes a gate dielectric layer 922, a first gate layer 924 such as a work function gate layer, and a gate fill material 926, as shown in FIG. 9A. In one embodiment, wherein the permanent gate structure 920 is formed on the insulating structure 704, the permanent gate structure 920 is formed on the residual polysilicon portion 930, which It may be a remnant of a replacement gate process involving a sacrificial polysilicon gate electrode.

在一實施例中，絕緣結構704包含第一絕緣層902、直接在第一絕緣層902上的第二絕緣層904、以及直接橫向地在第二絕緣層904上的電介質填充材料906。在一個實施例中，第一絕緣層902為包含矽和氧的非摻雜絕緣層。在一個實施例中，第二絕緣層904包含矽和氮。在一個實施例中，電介質填充材料906包含矽和氧。 In one embodiment, the insulating structure 704 includes a first insulating layer 902 , a second insulating layer 904 directly on the first insulating layer 902 , and a dielectric fill material 906 directly and laterally on the second insulating layer 904 . In one embodiment, the first insulating layer 902 is a non-doped insulating layer including silicon and oxygen. In one embodiment, the second insulating layer 904 includes silicon and nitrogen. In one embodiment, the dielectric fill material 906 includes silicon and oxygen.

在另一態樣中，磊晶嵌入的源極或汲極區域被施行作為用於半導體鰭部的源極或汲極結構。做為範例，圖10繪示依據本發明的一實施例，在源極或汲極位置所取出之積體電路結構的剖面視圖。 In another aspect, epitaxially embedded source or drain regions are implemented as source or drain structures for the semiconductor fins. As an example, FIG. 10 shows a cross-sectional view of an integrated circuit structure taken out at the source or drain position according to an embodiment of the present invention.

參照圖10，積體電路結構1000包含諸如P型金屬氧化物半導體(PMOS)裝置的P型裝置。積體電路結構1000也包含諸如N型金屬氧化物半導體(NMOS)裝置的N型裝置。 Referring to FIG. 10, an integrated circuit structure 1000 includes a P-type device such as a P-type metal oxide semiconductor (PMOS) device. The integrated circuit structure 1000 also includes N-type devices such as N-type metal oxide semiconductor (NMOS) devices.

圖10的PMOS裝置包含第一複數個半導體鰭部1002，諸如由塊狀矽基板1001所形成的矽鰭部。在源極或汲極位置處，鰭部1002的上部部位已經被去除，並且相同或不同的半導體材料被生長而形成源極或汲極結構1004。將可領會到源極或汲極結構1004在閘極電極的任一側所取出的剖面視圖處看起來將會是相同的，例如，基本上它們在源極側和在汲極側看起來將會是相同的。在一實施例中，如同所描述的，源極或汲極結構1004具有在絕緣 結構1006的上表面之下的部位和在絕緣結構1006的上表面之上的部位。在一實施例中，如同所描述的，源極或汲極結構1004被強烈地琢面(facet)。在一實施例中，導電性接觸1008係形成在源極或汲極結構1004之上。然而，在一個這樣的實施例中，強烈的琢面以及源極或汲極結構1004之相對寬的生長至少某種程度地抑止了由導電性接觸1008的良好覆蓋(coverage)。 The PMOS device of FIG. 10 includes a first plurality of semiconductor fins 1002 , such as silicon fins formed from a bulk silicon substrate 1001 . At the source or drain location, the upper portion of the fin 1002 has been removed and the same or a different semiconductor material is grown to form the source or drain structure 1004 . It will be appreciated that the source or drain structures 1004 will look the same at the cross-sectional view taken on either side of the gate electrode, e.g. basically they will look on the source side and on the drain side will be the same. In one embodiment, as described, the source or drain structure 1004 has an insulating A portion below the upper surface of the structure 1006 and a portion above the upper surface of the insulating structure 1006 . In one embodiment, the source or drain structure 1004 is strongly faceted as described. In one embodiment, a conductive contact 1008 is formed over the source or drain structure 1004 . However, in one such embodiment, the strong faceting and relatively wide growth of the source or drain structure 1004 prevents good coverage by the conductive contact 1008 at least to some extent.

圖10的NMOS裝置包含第二複數個半導體鰭部1052，諸如由塊狀矽基板1001所形成的矽鰭部。在源極或汲極位置處，鰭部1052的上部部位已經被去除，並且相同或不同的半導體材料被生長而形成源極或汲極結構1054。將可領會到源極或汲極結構1054在閘極電極的任一側所取出的剖面視圖處看起來將會是相同的，例如，基本上它們在源極側和在汲極側看起來將會是相同的。在一實施例中，如同所描述的，源極或汲極結構1054具有在絕緣結構1006的上表面之下的部位和在絕緣結構1006的上表面之上的部位。在一實施例中，如同所描述的，源極或汲極結構1054相對於源極或汲極結構1004被軟弱地琢面(facet)。在一實施例中，導電性接觸1058係形成在源極或汲極結構1054之上。在一個這樣的實施例中，相對軟弱的琢面以及源極或汲極結構1054之相對較窄的生長(相較於源極或汲極結構1004)提升了由導電性接觸1058的良好覆蓋。 The NMOS device of FIG. 10 includes a second plurality of semiconductor fins 1052 , such as silicon fins formed from bulk silicon substrate 1001 . At the source or drain location, the upper portion of the fin 1052 has been removed and the same or a different semiconductor material is grown to form the source or drain structure 1054 . It will be appreciated that the source or drain structures 1054 will look the same at the cross-sectional view taken on either side of the gate electrode, e.g. basically they will look the same on the source side and on the drain side will be the same. In one embodiment, the source or drain structure 1054 has a portion below the upper surface of the insulating structure 1006 and a portion above the upper surface of the insulating structure 1006 as depicted. In one embodiment, source or drain structure 1054 is weakly faceted relative to source or drain structure 1004 as described. In one embodiment, a conductive contact 1058 is formed over the source or drain structure 1054 . In one such embodiment, the relatively weak facets and relatively narrow growth of source or drain structure 1054 (compared to source or drain structure 1004 ) promote good coverage by conductive contact 1058 .

PMOS裝置之源極或汲極結構的形狀可以被 改變以改善和上覆(overlying)接觸的接觸面積。例如，圖11繪示依據本發明的一實施例，在源極或汲極位置所取出之另一積體電路結構的剖面視圖。 The shape of the source or drain structure of a PMOS device can be determined by Changed to improve contact area with overlying contact. For example, FIG. 11 shows a cross-sectional view of another integrated circuit structure taken at the source or drain position according to an embodiment of the present invention.

參照圖11，積體電路結構1100包含P型半導體(例如，PMOS)裝置。PMOS裝置包含諸如矽鰭部的第一鰭部1102。第一磊晶源極或汲極結構1104被嵌入第一鰭部1102中。在一個實施例中，雖然未被描述，第一磊晶源極或汲極結構1104係在第一閘極電極(其可以被形成在諸如鰭部1102之通道部位的上鰭部部位之上)的第一側，而且第二磊晶源極或汲極結構被嵌入第一鰭部1102中，在此一第一閘極電極之與第一側相反的第二側。在一實施例中，第一1104和第二磊晶源極或汲極結構包含矽和鍺並且具有外形(profile)1105。在一個實施例中，外形為火柴棒的外形，如圖11中所描述者。第一導電電極1108係在第一磊晶源極或汲極結構1104之上。 Referring to FIG. 11 , an integrated circuit structure 1100 includes a P-type semiconductor (eg, PMOS) device. The PMOS device includes a first fin 1102 such as a silicon fin. A first epitaxial source or drain structure 1104 is embedded in the first fin 1102 . In one embodiment, although not depicted, a first epitaxial source or drain structure 1104 is tied to a first gate electrode (which may be formed over an upper fin portion such as a channel portion of fin 1102 ) On the first side of the first gate electrode, and the second epitaxial source or drain structure is embedded in the first fin 1102, on the second side of the first gate electrode opposite to the first side. In one embodiment, the first 1104 and second epitaxial source or drain structures comprise silicon and germanium and have a profile 1105 . In one embodiment, the shape is that of a matchstick, as depicted in FIG. 11 . A first conductive electrode 1108 is attached to the first epitaxial source or drain structure 1104 .

再次參照圖11，在一實施例中，積體電路結構1100也包含N型半導體(例如，NMOS)裝置。NMOS裝置包含諸如矽鰭部的第二鰭部1152。第三磊晶源極或汲極結構1154被嵌入第二鰭部1152中。在一個實施例中，雖然未被描述，第三磊晶源極或汲極結構1154係在第二閘極電極(其可以被形成在諸如鰭部1152之通道部位的上鰭部部位之上)的第一側，而且第四磊晶源極或汲極結構被嵌入第二鰭部1152中，在此一第二閘極電極之與第一側相反的第二側。在一實施例中，第三1154和第四磊晶源極或汲極結 構包含矽並且具有實質上和第一和第二磊晶源極或汲極結構1004之外形1105相同的外形。第二導電電極1158係在第三磊晶源極或汲極結構1154之上。 Referring again to FIG. 11 , in one embodiment, the integrated circuit structure 1100 also includes N-type semiconductor (eg, NMOS) devices. The NMOS device includes a second fin 1152 such as a silicon fin. A third epitaxial source or drain structure 1154 is embedded in the second fin 1152 . In one embodiment, although not depicted, a third epitaxial source or drain structure 1154 is tied to the second gate electrode (which may be formed over an upper fin portion of the channel portion such as fin 1152 ) and the fourth epitaxial source or drain structure is embedded in the second fin 1152 on the second side of the second gate electrode opposite to the first side. In one embodiment, the third 1154 and fourth epitaxial source or drain junction The structure comprises silicon and has substantially the same shape as the shape 1105 of the first and second epitaxial source or drain structures 1004 . A second conductive electrode 1158 is attached to the third epitaxial source or drain structure 1154 .

在一實施例中，第一磊晶源極或汲極結構1104被軟弱地琢面。在一實施例中，第一磊晶源極或汲極結構1104具有約50奈米的高度而且具有在30到35奈米之範圍中的寬度。在一個這樣的實施例中，第三磊晶源極或汲極結構1154具有約50奈米的高度而且具有在30到35奈米之範圍中的寬度。 In one embodiment, the first epitaxial source or drain structure 1104 is weakly faceted. In one embodiment, the first epitaxial source or drain structure 1104 has a height of about 50 nm and a width in the range of 30 to 35 nm. In one such embodiment, the third epitaxial source or drain structure 1154 has a height of about 50 nanometers and a width in the range of 30 to 35 nanometers.

在一實施例中，第一磊晶源極或汲極結構1104以在第一磊晶源極或汲極結構1104的底部1104A約20%鍺濃度到第一磊晶源極或汲極結構1104的頂部1104B約45%鍺濃度來分等級。在一實施例中，第一磊晶源極或汲極結構1104係摻雜有硼原子。在一個實施例中，第三磊晶源極或汲極結構1154係摻雜有磷原子或砷原子。 In one embodiment, the first epitaxial source or drain structure 1104 is exposed to the first epitaxial source or drain structure 1104 with about 20% germanium concentration at the bottom 1104A of the first epitaxial source or drain structure 1104 The top 1104B is graded with a germanium concentration of approximately 45%. In one embodiment, the first epitaxial source or drain structure 1104 is doped with boron atoms. In one embodiment, the third epitaxial source or drain structure 1154 is doped with phosphorus atoms or arsenic atoms.

圖12A到12D繪示依據本發明的一實施例，在源極或汲極位置所取出且代表製造積體電路結構之製造中各種操作的剖面視圖。 12A-12D illustrate cross-sectional views taken at the source or drain location and representing various operations in the fabrication of an integrated circuit structure in accordance with an embodiment of the present invention.

參照圖12A，製造積體電路結構之方法包含形成諸如由矽基板1201所構成之矽鰭部的鰭部。鰭部1202具有下鰭部部位1202A和上鰭部部位1202B。在一實施例中，雖然未被描述，閘極電極係形成在鰭部1202之上鰭部部位1202B的部位之上，在進入頁面的位置處。此一閘極電極具有和第二側相反的第一側，並且界定在第一和第二 側上的源極或汲極位置。例如，為了例舉目的，圖12A到12D之視圖的剖面位置係取自閘極電極的其中一個側邊處的其中一個源極或汲極位置。 Referring to FIG. 12A , a method of fabricating an integrated circuit structure includes forming fins, such as silicon fins, formed from a silicon substrate 1201 . Fin 1202 has a lower fin location 1202A and an upper fin location 1202B. In one embodiment, although not depicted, a gate electrode is formed over fin 1202 at the location of fin location 1202B, at a location into the page. The gate electrode has a first side opposite to the second side and is defined between the first and second source or drain location on the side. For example, for illustrative purposes, the cross-sectional locations of the views of FIGS. 12A to 12D are taken from one of the source or drain locations at one of the sides of the gate electrode.

參照圖12B，鰭部1202的源極或汲極位置被凹入而形成凹入的鰭部部位1206。鰭部1202之凹入的源極或汲極位置可以是在閘極電極的側邊和在閘極電極的第二側。參照圖12A和12B兩者，在一實施例中，電介質間隔層1204係沿著鰭部1202之部位的側壁而形成，例如在閘極結構的側邊。在一個這樣的實施例中，使鰭部1202凹入包含使鰭部1202凹入電介質間隔層1204的頂部表面1204A以下。 Referring to FIG. 12B , the source or drain locations of fins 1202 are recessed to form recessed fin locations 1206 . The recessed source or drain location of the fin 1202 can be on the side of the gate electrode and on the second side of the gate electrode. Referring to both Figures 12A and 12B, in one embodiment, a dielectric spacer layer 1204 is formed along sidewalls at locations of the fins 1202, such as at the sides of the gate structures. In one such embodiment, recessing the fin 1202 includes recessing the fin 1202 below the top surface 1204A of the dielectric spacer layer 1204 .

參照圖12C，磊晶源極或汲極結構1208係形成在例如凹入的鰭部1206上，因而可以被形成在閘極電極的側邊。在一個這樣的實施例中，第二磊晶源極或汲極結構被形成在凹入的鰭部1206的第二部位上，在此一閘極電極的第二側邊處。在一實施例中，磊晶源極或汲極結構1208包含矽和鍺並且具有火柴棒的外形，如圖12C中所描述者。在一實施例中，電介質間隔層1204被包含並且沿著磊晶源極或汲極結構1208之側壁的下部部位1208A，如所描述者。 Referring to FIG. 12C , epitaxial source or drain structures 1208 are formed on, for example, recessed fins 1206 and thus can be formed on the side of the gate electrode. In one such embodiment, a second epitaxial source or drain structure is formed on a second portion of the recessed fin 1206 at a second side of the one gate electrode. In one embodiment, the epitaxial source or drain structure 1208 includes silicon and germanium and has a matchstick shape, as depicted in FIG. 12C . In one embodiment, a dielectric spacer layer 1204 is included along the lower portion 1208A of the sidewall of the epitaxial source or drain structure 1208, as depicted.

參照圖12D，導電電極1210被形成在磊晶源極或汲極結構1208上。在一實施例中，導電電極1210包含導電性阻障層1210A和導電性填充材料1201B。在一個實施例中，導電電極1210跟隨著磊晶源極或汲極結構1208的 外形輪廓走，如所描述者。在其他實施例中，磊晶源極或汲極結構1208的上部部位在導電電極1210的製作期間被腐蝕。 Referring to FIG. 12D , a conductive electrode 1210 is formed on the epitaxial source or drain structure 1208 . In one embodiment, the conductive electrode 1210 includes a conductive barrier layer 1210A and a conductive filling material 1201B. In one embodiment, the conductive electrode 1210 follows the epitaxial source or drain structure 1208 Outer profile goes as described. In other embodiments, the upper portion of the epitaxial source or drain structure 1208 is etched during the fabrication of the conductive electrode 1210 .

在另一態樣中，針對隔離的鰭部的鰭部修整隔離(FTI)和單閘極間隙被說明。利用半導體材料之從基板表面突出的鰭部之非平面型電晶體使用環繞該鰭部之二、三、或者甚至所有側邊的閘極電極(亦即，雙閘極、三閘極、奈米線電晶體)。源極和汲極區域然後典型地被形成在該鰭部中，或者被形成為該鰭部的再生長(re-grown)部位，在閘極電極的任一側上。為了隔開第一非平面型電晶體的源極或汲極區域與相鄰之第二非平面型電晶體的源極或汲極區域，間隙(gap)或空間(space)可以被形成在兩個相鄰的鰭部之間。這樣的隔離間隙通常需要某種的遮蔽式蝕刻(masked etch)。一旦被隔開，閘極堆疊然後被圖案化於個別的鰭部之上，典型上再次使用某種的遮蔽式蝕刻(例如，線蝕刻或開口蝕刻，視特定的施行而定)。 In another aspect, fin trimmed isolation (FTI) and single gate gaps for isolated fins are illustrated. Non-planar transistors utilizing fins of semiconductor material protruding from the substrate surface use gate electrodes surrounding two, three, or even all sides of the fin (i.e., double-gate, triple-gate, nanometer wire crystal). Source and drain regions are then typically formed in the fin, or as re-grown sites of the fin, on either side of the gate electrode. In order to separate the source or drain region of the first non-planar transistor from the source or drain region of the adjacent second non-planar transistor, a gap or space can be formed between the two. between adjacent fins. Such isolation gaps typically require some kind of masked etch. Once spaced, the gate stacks are then patterned over the individual fins, typically again using some kind of masked etch (eg, line etch or opening etch, depending on the particular implementation).

上面所述之鰭部隔離技術的其中一個潛在問題在於閘極不與鰭部的末端自我對準，而且閘極堆疊圖案與半導體鰭部圖案的對準有賴於這兩種圖案的覆蓋(overlay)。因此，光刻覆蓋誤差被加進半導體鰭部的尺寸標定(dimensioning)，與需要具有更大長度之鰭部的隔離間隙及比它們更大的隔離間隙將是用於給定等級的電晶體功能性。減少這種尺寸過大的裝置架構和製造技術因此提供在電晶體密度上之高度有利的改進。 One of the potential problems with the fin isolation technique described above is that the gate is not self-aligned with the end of the fin, and the alignment of the gate stack pattern with the semiconductor fin pattern is dependent on the overlay of the two patterns . Thus, lithographic overlay errors are added to the dimensioning of semiconductor fins, and isolation gaps requiring fins with greater lengths and isolation gaps larger than they will be for a given class of transistor function sex. Device architectures and fabrication techniques that reduce such overdimensions thus provide highly favorable improvements in transistor density.

上面所述之鰭部隔離技術的另一個潛在問題在於在半導體鰭部中用以改善載子移動率(carrier mobility)所想要的應力(stress)可能會從電晶體的通道區域中喪失掉，其中，太多鰭部表面在製造期間留著沒用，而讓鰭部應變(strain)能夠鬆弛。維持較高等級之想要的鰭部應力之裝置架構和製造技術因此提供在非平面型電晶體性能之有利的改進。 Another potential problem with the fin isolation techniques described above is that the desired stress in semiconductor fins to improve carrier mobility may be lost from the channel region of the transistor, Of these, too much of the fin surface is left unused during fabrication to allow the fin strain to relax. Device architectures and fabrication techniques that maintain higher levels of desired fin stress thus provide beneficial improvements in non-planar transistor performance.

依據本發明的實施例，穿通閘極(through-gate)鰭部隔離架構和技術被說明於本文中。在所繪示的代表性實施例中，微電子裝置中的非平面型電晶體(諸如，積體電路(IC))以自我對準於電晶體之閘極電極的方式而彼此隔開。雖然本發明的實施例係可應用於差不多是使用非平面型電晶體的任何IC，但是代表性的IC包含(但不限於)微處理器核心，其包含邏輯及記憶體(SRAM)部件、RFIC(例如，包含數位基帶和類比前端模組的無線IC)、以及功率IC。 Through-gate fin isolation architectures and techniques are described herein in accordance with embodiments of the present invention. In the depicted representative embodiment, non-planar transistors in a microelectronic device, such as an integrated circuit (IC), are spaced from each other in a manner that is self-aligned to the gate electrodes of the transistors. Although embodiments of the invention are applicable to virtually any IC that uses non-planar transistors, representative ICs include, but are not limited to, microprocessor cores that include logic and memory (SRAM) components, RFIC (for example, wireless ICs including digital baseband and analog front-end modules), and power ICs.

在實施例中，相鄰之半導體鰭部的兩個末端係以隔離區域而互相電隔離，該隔離區域僅使用一個圖案化遮罩等級而相對於閘極電極被定位。在一實施例中，單一遮罩被用來形成具有固定間距的複數個犧牲佔位件條紋(stripe)，該等佔位件條紋的第一子集合界定隔離區域的位置或尺寸，而該等佔位件條紋的第二子集合界定閘極電極的位置或尺寸。在某些實施例中，第一子集合的佔位件條紋被去除並且被隔離切割製作成該等開口中起因於第一子 集合去除的半導體鰭部，而該等佔位件條紋的第二子集合最終被非犧牲閘極電極堆疊所取代。因為利用於閘極電極置換之一子集合的佔位件被用來形成隔離區域，所以該方法和結果架構在本文中被稱為”穿通閘極”隔離。在本文中所述的一或更多個穿通閘極隔離實施例可以，例如，致能更高的電晶體密度和更高等級之有利的電晶體通道應力。 In an embodiment, two ends of adjacent semiconductor fins are electrically isolated from each other by an isolation region positioned relative to the gate electrode using only one patterned mask level. In one embodiment, a single mask is used to form a plurality of sacrificial placeholder stripes with a fixed pitch, a first subset of the placeholder stripes define the location or size of the isolation region, and the A second subset of placeholder stripes define the location or size of the gate electrodes. In some embodiments, the first subset of placeholder stripes are removed and isolation cuts are made into the openings resulting from the first subset The removed semiconductor fins are assembled, and a second subset of the placeholder stripes are eventually replaced by non-sacrificial gate electrode stacks. Because placeholders utilizing a subset of gate electrode replacements are used to form isolation regions, the method and resulting architecture are referred to herein as "punch-gate" isolation. One or more punch gate isolation embodiments described herein may, for example, enable higher transistor densities and higher levels of favorable transistor channel stress.

隨著在閘極電極的置換或界定之後所界定的隔離，更大的電晶體密度可以被達成，這是因為鰭部隔離尺寸標定和置換可以和閘極電極完美地做成於間距上(on-pitch)，而使得閘極電極和隔離區域兩者皆為單一遮蔽等級之最小特徵間距的整數倍。在半導體鰭部和鰭部被放置於其上之基板間具有晶格不匹配(lattice mismatch)的其他實施例中，藉由界定在閘極電極的置換或界定後之隔離來維持較大的應變程度。對於此等實施例，在界定鰭部的末端之前所形成之半導體的其他特徵(諸如，閘極電極和添加的源極或汲極材料)有助於機械性地維持在隔離切割被製作成鰭部之後的鰭部應變。 With the isolation defined after the replacement or definition of the gate electrode, greater transistor density can be achieved because the fin isolation dimensioning and replacement can be made perfectly on pitch with the gate electrode (on -pitch) so that both the gate electrode and the isolation region are integer multiples of the minimum feature pitch for a single shade level. In other embodiments where there is a lattice mismatch between the semiconductor fin and the substrate on which the fin is placed, a larger strain is maintained by defining isolation after replacement or definition of the gate electrode degree. For these embodiments, other features of the semiconductor formed prior to defining the ends of the fins, such as gate electrodes and added source or drain material, help to mechanically maintain the fins as the isolation cuts are made. The fins strain after the portion.

為了提供進一步的上下文，電晶體縮放可以獲利自晶片內之晶胞(cell)更緊密的封裝。目前，大部分的晶胞與它們的鄰居被兩個或更多個假性閘極所分開，其具有嵌入的鰭部。該等晶胞藉由蝕刻在這兩個或更多個假性閘極所分開，其使其中一個晶胞連接到另一個晶胞。如果使相鄰的晶胞分開之假性閘極的數量可以從兩個或兩個以上減少到一個，則縮放可以顯著地獲利。如上所解說 的，其中一個解決方法需要兩個或更多個假性閘極。在兩個或更多個假性閘極之下的鰭部被蝕刻於鰭部圖案化期間。此種方法之潛在的問題在於假性閘極消耗晶片上可以為晶胞所用的空間。在一實施例中，本文中所述的方法致使能夠僅使用單一個假性閘極來使相鄰的晶胞分開。 To provide further context, transistor scaling can benefit from tighter packing of cells within a wafer. Currently, most unit cells are separated from their neighbors by two or more pseudo-gates with embedded fins. The cells are separated by etching at the two or more dummy gates, which connect one of the cells to the other. Scaling can benefit significantly if the number of dummy gates separating adjacent cells can be reduced from two or more to one. as explained above , one of the solutions requires two or more dummy gates. The fins under the two or more dummy gates are etched during fin patterning. A potential problem with this approach is that the dummy gates consume space on the wafer that could be used by the unit cells. In one embodiment, the methods described herein enable the use of only a single dummy gate to separate adjacent unit cells.

在一實施例中，鰭部修整隔離方法被施行作為自我對準圖案化方案。在此，單一個閘極之下的鰭部被蝕刻掉。因此，相鄰的晶胞可以被單一個假性閘極所分開。此方法的優點可以包含節省晶片上的空間以及允許給定的面積有更多的計算能力。該方法也可以允許鰭部修整能夠被實施於子鰭部間距距離。 In one embodiment, the fin trim isolation method is implemented as a self-aligned patterning scheme. Here, the fins under a single gate are etched away. Therefore, adjacent cells can be separated by a single dummy gate. Advantages of this approach may include saving space on the die and allowing more computing power for a given area. This approach may also allow fin trimming to be performed at sub-fin pitch distances.

圖13A及13B繪示依據本發明的一實施例，代表使具有多個閘極間隙之鰭部圖案化用以形成局部隔離結構之方法中各種操作的平面視圖。 13A and 13B illustrate plan views representing various operations in a method of patterning a fin with multiple gate gaps to form local isolation structures in accordance with an embodiment of the present invention.

參照圖13A，複數個鰭部1302被顯示具有沿著第一方向1304的長度。具有間隙1307介於其間界定最終形成之複數條閘極線的位置之柵格(grid)1306被顯示沿著與第一方向1304正交的第二方向1308。 Referring to FIG. 13A , a plurality of fins 1302 is shown having a length along a first direction 1304 . A grid 1306 is shown along a second direction 1308 that is orthogonal to the first direction 1304 with gaps 1307 therebetween defining the locations of the resulting plurality of gate lines.

參照圖13B，複數個鰭部1302的一部分被切割(例如，藉由蝕刻製程來去除)而留下具有切割部1312於其中的鰭部1310。最終形成於切割部1312中之隔離結構因此具有多於單一條閘極線的尺寸，例如，三條閘極線1306的尺寸。因此，最終沿著閘極線1306之位置所形成的閘極結構將至少被局部形成在形成於切割部1312中的隔離結構 之上。因而，切割部1312為相對寬的鰭部切割部。 Referring to FIG. 13B , a portion of the plurality of fins 1302 is cut (eg, removed by an etching process) to leave a fin 1310 having cut portions 1312 therein. The isolation structures finally formed in the cutouts 1312 thus have the size of more than a single gate line, for example, the size of three gate lines 1306 . Thus, the gate structure finally formed along the position of the gate line 1306 will be at least partially formed in the isolation structure formed in the cutout 1312 above. Thus, cutout 1312 is a relatively wide fin cutout.

圖14A到14D繪示依據本發明的另一實施例，代表使具有單一閘極間隙之鰭部圖案化用以形成局部隔離結構之方法中多種操作的平面視圖。 14A-14D illustrate plan views representing various operations in a method of patterning a fin with a single gate gap to form a local isolation structure, according to another embodiment of the present invention.

參照圖14A，製造積體電路結構的方法包含形成複數個鰭部1402，該複數個鰭部1402之個別的一些沿著第一方向1404具有最長的尺寸。複數個閘極結構1406係在該複數個鰭部1402之上，閘極結構1406之個別的一些沿著與第一方向1404正交的第二方向1408具有最長的尺寸。在一實施例中，閘極結構1406為例如由多晶矽所製作的犧牲或假性閘極線。在一個實施例中，該複數個鰭部1402為矽鰭部而且和下面之矽基板的一部分係連續的。 Referring to FIG. 14A , the method of fabricating an integrated circuit structure includes forming a plurality of fins 1402 , individual ones of the plurality of fins 1402 have a longest dimension along a first direction 1404 . A plurality of gate structures 1406 are over the plurality of fins 1402 , individual ones of the gate structures 1406 have the longest dimension along a second direction 1408 orthogonal to the first direction 1404 . In one embodiment, the gate structure 1406 is a sacrificial or dummy gate line fabricated, for example, from polysilicon. In one embodiment, the plurality of fins 1402 are silicon fins and are continuous with a portion of the underlying silicon substrate.

參照圖14B，電介質材料結構1410被形成在複數個閘極結構1406之相鄰的一些閘極結構之間。 Referring to FIG. 14B , a dielectric material structure 1410 is formed between adjacent ones of the plurality of gate structures 1406 .

參照圖14C，複數個閘極結構1406之其中一個閘極結構的一部位1412被去除以使複數個鰭部1402之每一個鰭部的一部位1414暴露出。在一實施例中，去除複數個閘極結構1406之其中一個閘極結構的一部位1412涉及使用比複數個閘極結構1406之其中一個閘極結構的一部位1412之寬度1418更寬的光刻窗口1416。 Referring to FIG. 14C , a portion 1412 of one of the plurality of gate structures 1406 is removed to expose a portion 1414 of each of the plurality of fins 1402 . In one embodiment, removing a portion 1412 of one of the plurality of gate structures 1406 involves using a photolithographic process that is wider than the width 1418 of the portion 1412 of one of the plurality of gate structures 1406 Windows 1416.

參照圖14D，複數個鰭部1402之每一個鰭部的露出部位1414被去除以形成切割區域1420。在一實施例中，使用乾式或電漿蝕刻製程來去除複數個鰭部1402之每一個鰭部的露出部位1414。在一實施例中，去除複數個鰭 部1402之每一個鰭部的露出部位1414涉及蝕刻到小於複數個鰭部1402之高度的深度。在一個這樣的實施例中，該深度大於複數個鰭部1402中之源極或汲極區域的深度。在一實施例中，該深度深於複數個鰭部1402之作用部位的深度以提供隔離邊限制(margin)。在一實施例中，複數個鰭部1402之每一個鰭部的露出部位1414被去除，但沒有蝕刻或者沒有實質地蝕刻複數個鰭部1402的源極或汲極區域(諸如，磊晶的源極或汲極區域)。在一個這樣的實施例中，複數個鰭部1402之每一個鰭部的露出部位1414被去除，但沒有橫向地蝕刻或者沒有實質橫向地蝕刻複數個鰭部1402的源極或汲極區域(諸如，磊晶的源極或汲極區域)。 Referring to FIG. 14D , the exposed portion 1414 of each of the plurality of fins 1402 is removed to form a cutting region 1420 . In one embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed using a dry or plasma etching process. In one embodiment, multiple fins are removed Exposed portion 1414 of each fin of portion 1402 involves etching to a depth less than the height of fins 1402 . In one such embodiment, the depth is greater than the depth of the source or drain regions in the plurality of fins 1402 . In one embodiment, the depth is deeper than the depth where the plurality of fins 1402 are active to provide a margin. In one embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without etching or substantially etching the source or drain regions of the plurality of fins 1402 (such as an epitaxial source region). pole or drain region). In one such embodiment, the exposed portion 1414 of each of the plurality of fins 1402 is removed without laterally etching or substantially laterally etching the source or drain regions of the plurality of fins 1402, such as , epitaxy source or drain region).

在一實施例中，最終以絕緣層來填充切割區域1420，例如，在複數個鰭部1402之每一個鰭部之去除部位1414的位置中。代表性絕緣層或"多晶切割部(poly cut)”或”插塞(plug)”結構被說明於下。然而，在其他實施例中，切割區域1420僅部分地用絕緣層來填充，而導電結構然後被形成於絕緣層中。該導電結構可以被用作為局部互連(local interconnect)。在一實施例中，在用絕緣層或者用容納(housing)局部互連結構的絕緣層來填充切割區域1420之前，摻雜劑可以藉由固態源極摻雜劑層，經過切割區域1420而被佈植或輸送進該鰭部或該等鰭部的局部切割部位中。 In one embodiment, the cutting region 1420 is eventually filled with an insulating layer, eg, in the location of the removal site 1414 of each of the plurality of fins 1402 . Representative insulating layers or "poly cut" or "plug" structures are described below. However, in other embodiments, the cutting region 1420 is only partially filled with an insulating layer, and conductive structures are then formed in the insulating layer. The conductive structure can be used as a local interconnect. In one embodiment, dopants may be injected through the cut region 1420 by a solid source dopant layer before filling the cut region 1420 with an insulating layer or with an insulating layer housing the local interconnect structure. Implanted or delivered into the fin or localized cuts of the fins.

圖15繪示依據本發明的一實施例，具有帶有多個閘極間隙之鰭部用於局部隔離之積體電路結構的剖面 視圖。 15 shows a cross-section of an integrated circuit structure with fins with multiple gate gaps for local isolation, according to an embodiment of the present invention. view.

參照圖15，矽鰭部1502具有橫向鄰接第二鰭部部位1506的第一鰭部部位1504。第一鰭部部位1504藉由相對寬的切割部1508而與第二鰭部部位1506分開，諸如相關於圖13A及13B所述者，該相對寬的切割部1508具有寬度X。電介質填充材料1510被形成在相對寬的切割部1508中並且使第一鰭部部位1504與第二鰭部部位1506電隔離。複數條閘極線1512係在矽鰭部1502之上，其中，該等閘極線之各者可包含閘極電介質及閘極電極堆疊1514、電介質蓋層1516、和側壁間隔層1518。兩條閘極線(左邊的兩條閘極線1512)佔據相對寬的切割部1508，且因此，第一鰭部部位1504藉由實際上兩條假性或者不作用(inactive)閘極而與第二鰭部部位1506分開。 Referring to FIG. 15 , a silicon fin 1502 has a first fin portion 1504 laterally adjacent to a second fin portion 1506 . The first fin portion 1504 is separated from the second fin portion 1506 by a relatively wide cutout 1508 having a width X, such as described with respect to FIGS. 13A and 13B . A dielectric fill material 1510 is formed in the relatively wide cutout 1508 and electrically isolates the first fin location 1504 from the second fin location 1506 . A plurality of gate lines 1512 are over the silicon fins 1502 , wherein each of the gate lines may include a gate dielectric and gate electrode stack 1514 , a dielectric cap 1516 , and a sidewall spacer 1518 . Two gate lines (the two gate lines 1512 on the left) occupy a relatively wide cutout 1508, and thus, the first fin portion 1504 is separated from the gate by effectively two dummy or inactive gates. The second fin locations 1506 are separated.

相較之下，鰭部部位可以被單一個閘極距離所分開。作為範例，圖16A繪示依據本發明的另一實施例，具有帶有單一閘極間隙之鰭部用於局部隔離之積體電路結構的剖面視圖。 In contrast, fin regions can be separated by a single gate distance. As an example, FIG. 16A shows a cross-sectional view of an integrated circuit structure having fins with a single gate gap for partial isolation according to another embodiment of the present invention.

參照圖16A，矽鰭部1602具有橫向鄰接第二鰭部部位1606的第一鰭部部位1604。第一鰭部部位1604藉由相對窄的切割部1608而與第二鰭部部位1606分開，諸如相關於圖14A到14D所述者，該相對窄的切割部1608具有寬度Y，其中，Y小於圖15中的X。電介質填充材料1610被形成在相對窄的切割部1608中並且使第一鰭部部位1604與第二鰭部部位1606電隔離。複數條閘極線1612係在矽鰭部 1602之上，其中，該等閘極線之各者可包含閘極電介質及閘極電極堆疊1614、電介質蓋層1616、和側壁間隔層1618。電介質填充材料1610占據先前單一條閘極線的位置，且因此，第一鰭部部位1604藉由單一條”插入的(plugged)”閘極線而與第二鰭部部位1606分開。在一個實施例中，殘餘的間隔層材料1620仍然在去除之閘極線部位之位置的側壁上，如所描述的。將可領會到鰭部1602的其他區域可以藉由由先前之更寬廣的鰭部切割製程所製造的兩個或甚至更多個不作用閘極線(具有三條不作用閘極線的區域1622)而互相隔開，如下所述。 Referring to FIG. 16A , silicon fin portion 1602 has a first fin portion 1604 laterally adjacent to a second fin portion 1606 . The first fin portion 1604 is separated from the second fin portion 1606 by a relatively narrow cut 1608, such as described with respect to FIGS. 14A-14D , having a width Y, where Y is less than X in Figure 15. A dielectric fill material 1610 is formed in the relatively narrow cutout 1608 and electrically isolates the first fin location 1604 from the second fin location 1606 . A plurality of gate lines 1612 are tied to the silicon fins 1602 , wherein each of the gate lines may include a gate dielectric and gate electrode stack 1614 , a dielectric cap 1616 , and a sidewall spacer 1618 . The dielectric fill material 1610 occupies the place of the former single gate line, and thus, the first fin site 1604 is separated from the second fin site 1606 by a single "plugged" gate line. In one embodiment, residual spacer material 1620 remains on the sidewalls at the location of the removed gate line locations, as described. It will be appreciated that other areas of the fin 1602 may have two or even more inactive gate lines (area 1622 with three inactive gate lines) produced by the previous wider fin cutting process. are separated from each other, as described below.

再次參照圖16A，積體電路結構1600具有諸如矽鰭部的鰭部1602。鰭部1602沿著第一方向1650具有最長的尺寸。隔離結構1610沿著第一方向1650使鰭部1602的第一上部部位1604與鰭部1602的第二上部部位1606分開。隔離結構1610沿著第一方向1650具有中心1611。 Referring again to FIG. 16A , integrated circuit structure 1600 has fins 1602 such as silicon fins. Fin 1602 has a longest dimension along first direction 1650 . Isolation structure 1610 separates first upper portion 1604 of fin 1602 from second upper portion 1606 of fin 1602 along first direction 1650 . The isolation structure 1610 has a center 1611 along the first direction 1650 .

第一閘極結構1612A係在鰭部1602的第一上部部位1604之上，第一閘極結構1612A沿著與第一方向1650正交的第二方向1652(例如，進入頁面中)具有最長的尺寸。第一閘極結構1612A的中心1613A沿著第一方向1650而與隔離結構1610的中心1611間隔開一間距。第二閘極結構1612B係在鰭部的第一上部部位1604之上，第二閘極結構1612B沿著第二方向1652具有最長的尺寸。第二閘極結構1612B的中心1613B沿著第一方向1650而與第一閘極結構1612A的中心1613A間隔開一間距。第三閘極結構 1612C係在鰭部1602的第二上部部位1606之上，第三閘極結構1612C沿著第二方向1652具有最長的尺寸。第三閘極結構1612C的中心1613C沿著第一方向1650而與隔離結構1610的中心1611間隔開一間距。在一實施例中，隔離結構1610具有實質上與第一閘極結構1612A的頂部、與第二閘極結構1612B的頂部、以及與第三閘極結構1612C的頂部共平面的頂部，如所描述的。 Attached to the first upper portion 1604 of the fin 1602 is a first gate structure 1612A, the first gate structure 1612A has a longest size. The center 1613A of the first gate structure 1612A is spaced apart from the center 1611 of the isolation structure 1610 along the first direction 1650 by a distance. A second gate structure 1612B is tied over the first upper portion 1604 of the fin, the second gate structure 1612B having its longest dimension along the second direction 1652 . The center 1613B of the second gate structure 1612B is spaced apart from the center 1613A of the first gate structure 1612A along the first direction 1650 by a distance. third gate structure 1612C is tied over the second upper portion 1606 of the fin 1602 , the third gate structure 1612C having the longest dimension along the second direction 1652 . The center 1613C of the third gate structure 1612C is spaced apart from the center 1611 of the isolation structure 1610 along the first direction 1650 by a distance. In one embodiment, the isolation structure 1610 has a top that is substantially coplanar with the top of the first gate structure 1612A, with the top of the second gate structure 1612B, and with the top of the third gate structure 1612C, as depicted. of.

在一實施例中，第一閘極結構1612A、第二閘極結構1612B和第三閘極結構1612C之各者包含閘極電極1660在高k閘極電介質層1662的側壁上並且在高k閘極電介質層1662的側壁之間，如同針對代表性第三閘極結構1612C所繪示的。在一個這樣的實施例中，第一閘極結構1612A、第二閘極結構1612B和第三閘極結構1612C之各者另包含絕緣蓋部1616在閘極電極1660上以及在高k閘極電介質層1662的側壁上。 In one embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C includes a gate electrode 1660 on the sidewalls of the high-k gate dielectric layer 1662 and on the high-k gate between the sidewalls of the dielectric layer 1662, as depicted for the representative third gate structure 1612C. In one such embodiment, each of the first gate structure 1612A, the second gate structure 1612B, and the third gate structure 1612C further includes an insulating cap 1616 over the gate electrode 1660 and over the high-k gate dielectric layer 1662 on the sidewall.

在一實施例中，積體電路結構1600另包含在鰭部1602的第一上部部位1604上，在第一閘極結構1612A與隔離結構1610之間的第一磊晶半導體區域1664A。第二磊晶半導體區域1664B係在鰭部1602的第一上部部位1604上，在第一閘極結構1612A與第二閘極結構1612B之間。第三磊晶半導體區域1664C係在鰭部1602的第二上部部位1606上，在第三閘極結構1612C與隔離結構1610之間。在一個實施例中，第一1664A、第二1664B及第三1664C磊晶半導體區域包含矽和鍺。在另一實施例中，第一1664A、 第二1664B及第三1664C磊晶半導體區域包含矽。 In one embodiment, the integrated circuit structure 1600 further includes a first epitaxial semiconductor region 1664A on the first upper portion 1604 of the fin portion 1602 between the first gate structure 1612A and the isolation structure 1610 . The second epitaxial semiconductor region 1664B is located on the first upper portion 1604 of the fin 1602 between the first gate structure 1612A and the second gate structure 1612B. The third epitaxial semiconductor region 1664C is located on the second upper portion 1606 of the fin 1602 between the third gate structure 1612C and the isolation structure 1610 . In one embodiment, the first 1664A, second 1664B, and third 1664C epitaxial semiconductor regions include silicon and germanium. In another embodiment, the first 1664A, The second 1664B and third 1664C epitaxial semiconductor regions include silicon.

在一實施例中，隔離結構1610包含在鰭部1602的第一上部部位1604上和在鰭部1602的第二上部部位1606上的應力。在一個實施例中，應力為壓縮應力。在另一實施例中，應力為伸張應力。在其他實施例中，隔離結構1610為局部填充絕緣層，而導電結構然後被形成於局部填充絕緣層中。導電結構可被用作為局部互連。在一實施例中，在用絕緣層或者用容納局部互連結構的絕緣層來形成隔離結構1610之前，摻雜劑可以藉由固態源極摻雜劑層而被佈植或輸送進該鰭部或該等鰭部的局部切割部位中。 In one embodiment, the isolation structure 1610 includes stresses on the first upper portion 1604 of the fin 1602 and on the second upper portion 1606 of the fin 1602 . In one embodiment, the stress is compressive stress. In another embodiment, the stress is tensile stress. In other embodiments, the isolation structure 1610 is a partially filled insulating layer, and the conductive structure is then formed in the partially filled insulating layer. Conductive structures may be used as local interconnects. In one embodiment, dopants may be implanted or delivered into the fins by a solid source dopant layer prior to forming the isolation structure 1610 with an insulating layer or with an insulating layer accommodating a local interconnect structure. or in partial cuts of such fins.

在另一態樣中，可以領會到諸如上面所述之隔離結構1610的隔離結構可以被形成來取代在鰭部切割部的局部位置處或者在鰭部切割部的較寬廣位置處的作用閘極電極。此外，鰭部切割部之此一局部位置處或者較寬廣位置的深度可以被形成來改變鰭部內相對於彼此的深度。在第一範例中，圖16B繪示依據本發明的一實施例，顯示其中鰭部隔離結構可以被形成來取代閘極電極之位置的剖面視圖。 In another aspect, it is appreciated that an isolation structure such as isolation structure 1610 described above may be formed to replace the active gate at a localized location of the fin cut or at a broader location of the fin cut. electrode. Furthermore, the depth of the fin cuts at this localized location or at a broader location may be formed to vary the depth within the fin relative to each other. In a first example, FIG. 16B illustrates a cross-sectional view showing locations where fin isolation structures may be formed instead of gate electrodes, according to an embodiment of the present invention.

參照圖16B，諸如矽鰭部的鰭部1680被形成在基板1682之上並且可以和基板1682係連續的。鰭部1680具有鰭部末端或寬廣的鰭部切割部1684，例如，其可以被形成在鰭部圖案化之時，諸如在上面所述的鰭部修整最終法中。鰭部1680也具有局部切割部1686，在該處，鰭部1680的一部分被去除，例如，使用鰭部修整隔離法，在該 鰭部修整隔離法中，假性閘極如上所述地用電介質插塞來取代。作用閘極電極1688被形成在鰭部之上，並且為了例舉目的，如所示地稍微在鰭部1680的前面，而鰭部1680係在背景中，在該處，虛線表示從前視圖所覆蓋的區域(area)。電介質插塞1690可以被形成在鰭部末端或寬廣的鰭部切割部1684處來代替在此等位置處使用作用閘極(active gate)。除此之外，或者替代地，電介質插塞1692可以被形成在局部切割部1686處來代替在此一位置處使用作用閘極(active gate)。可以領會到磊晶的源極或汲極區域1694也被顯示於鰭部1680在作用閘極電極1688與插塞1690或1692之間的位置。此外，在一實施例中，在局部切割部1686處之鰭部末端的表面粗糙度比在較寬廣的切割部位置處之鰭部末端的表面粗糙度更粗糙，如圖16B中所描述者。 Referring to FIG. 16B , fins 1680 , such as silicon fins, are formed over substrate 1682 and may be continuous with substrate 1682 . Fins 1680 have fin ends or broad fin cuts 1684 , which may be formed, for example, when the fins are patterned, such as in the fin trimming process described above. Fin 1680 also has a partial cut 1686 where a portion of fin 1680 is removed, for example, using fin trim isolation where In the fin trim isolation approach, the dummy gates are replaced with dielectric plugs as described above. The active gate electrode 1688 is formed over the fins and, for illustrative purposes, is shown slightly in front of the fins 1680, while the fins 1680 are tied in the background, where the dotted lines indicate the overlay from the front view. The area (area). Dielectric plugs 1690 may be formed at the fin ends or broad fin cuts 1684 instead of using active gates at these locations. Additionally, or alternatively, a dielectric plug 1692 may be formed at the partial cut 1686 instead of using an active gate at this location. It can be appreciated that an epitaxial source or drain region 1694 is also shown at the location of the fin 1680 between the active gate electrode 1688 and the plug 1690 or 1692 . Furthermore, in one embodiment, the surface roughness of the fin tip at the partial cut 1686 is rougher than the surface roughness of the fin tip at the location of the wider cut, as depicted in FIG. 16B .

圖17A到17C繪示依據本發明的一實施例，使用鰭部修整隔離法所製造之鰭部切割部的各種深度可能性。 17A to 17C illustrate various depth possibilities for fin cutouts fabricated using the fin trim isolation method in accordance with one embodiment of the present invention.

參照圖17A，諸如矽鰭部的半導體鰭部1700被形成在下面的基板1702之上並且可以和下面的基板1702係連續的。鰭部1700具有下鰭部部位1700A和上鰭部部位1700B，如同由絕緣結構1704相對於鰭部1700的高度所界定的。局部鰭部隔離切割部1706A使鰭部1700分開成為第一鰭部部位1710與第二鰭部部位1712。在圖17A的範例中，如所示地沿著a到a’軸線，局部鰭部隔離切割部1706A 的深度為鰭部1700到基板1702的整個深度。 Referring to FIG. 17A , semiconductor fins 1700 , such as silicon fins, are formed over and may be continuous with an underlying substrate 1702 . Fin 1700 has a lower fin location 1700A and an upper fin location 1700B, as defined by the height of insulating structure 1704 relative to fin 1700 . Partial fin isolation cut 1706A separates fin 1700 into first fin location 1710 and second fin location 1712 . In the example of Figure 17A, along the a to a' axis as shown, the partial fin isolation cut 1706A The depth of is the entire depth from the fin 1700 to the base plate 1702 .

參照圖17B，在第二範例中，如所示地沿著a到a’軸線，局部鰭部隔離切割部1706B的深度比鰭部1700到基板1702的整個深度更深。也就是說，切割部1706B延伸進入下面的基板1702中。 Referring to Figure 17B, in a second example, the depth of the partial fin isolation cut 1706B is deeper than the entire depth of the fin 1700 to the base plate 1702 along the a to a' axis as shown. That is, the cutout 1706B extends into the underlying substrate 1702 .

參照圖17C，在第三範例中，如所示地沿著a到a’軸線，局部鰭部隔離切割部1706C的深度比鰭部1700的整個深度更淺，但是比絕緣結構1704的上表面更深。再次參照圖17C，在第四範例中，如所示地沿著a到a’軸線，局部鰭部隔離切割部1706D的深度比鰭部1700的整個深度更淺，而且是在約與絕緣結構1704的上表面共平面的水平面處。 17C, in a third example, along the a to a' axis as shown, the depth of the partial fin isolation cut 1706C is shallower than the entire depth of the fin 1700, but deeper than the upper surface of the insulating structure 1704 . Referring again to FIG. 17C , in a fourth example, along the a to a' axis as shown, the partial fin isolation cut 1706D is shallower in depth than the entire depth of the fin 1700 and is at about the same distance as the insulating structure 1704 at the level of the coplanar upper surface.

圖18繪示依據本發明的一實施例，沿著a到a’軸線所取出，顯示鰭部內之鰭部切割部的深度對鰭部切割部之較寬廣位置之可能選項的平面視圖和對應的剖面視圖。 Figure 18 shows a plan view taken along the a to a' axis showing possible options for the depth of the fin cuts within the fin versus the wider location of the fin cuts and the corresponding Section view.

參照圖18，諸如矽鰭部的第一及第二半導體鰭部1800及1802具有延伸在絕緣結構1804之上的上鰭部部位1800B及1802B。鰭部1800及1802兩者具有鰭部末端或寬廣的鰭部切割部1806，例如，其可以被形成在鰭部圖案化之時，諸如在上面所述的鰭部修整最終法中。鰭部1800及1802兩者也具有局部切割部1808，在該局部切割部1808處，鰭部1800或1802的一部分被去除，例如，使用鰭部修整隔離法，在該鰭部修整隔離法中，假性閘極如上所述地 用電介質插塞來取代。在一實施例中，在局部切割部1808處之鰭部1800及1802末端的表面粗糙度比在較寬廣的鰭部切割部1806位置處之鰭部末端的表面粗糙度更粗糙，如圖18中所描述者。 Referring to FIG. 18 , first and second semiconductor fins 1800 and 1802 , such as silicon fins, have upper fin portions 1800B and 1802B extending over insulating structure 1804 . Both fins 1800 and 1802 have fin ends or broad fin cuts 1806 , which may be formed, for example, when the fins are patterned, such as in the fin trimming process described above. Both fins 1800 and 1802 also have a partial cut 1808 where a portion of fin 1800 or 1802 is removed, for example, using a fin trim isolation method in which, Pseudo-gate as described above Use a dielectric plug instead. In one embodiment, the surface roughness of the ends of the fins 1800 and 1802 at the partial cut 1808 is rougher than the surface roughness of the ends of the fins at the location of the wider fin cut 1806, as shown in FIG. described.

參照圖18的剖面視圖，可以看到下鰭部部位1800A及1802A在絕緣結構1804的高度之下。而且，在該剖面視圖所看到的是在絕緣結構1804的形成之前，鰭部之被去除於鰭部修整最終製程時的殘餘部位1810，如上所述。雖然被顯示突出於基板之上，殘餘部位1810也可以在基板的水平面處或者進入基板中，如同由額外的代表性寬廣切割深度1820所描述的。可以領會到用於鰭部1800及1802的寬廣切割部1806也可以在針對切割深度1820所述的水平面處，其範例被描述。局部切割部1808可以具有對應於針對圖17A到17C所述之深度的代表性深度。 Referring to the cross-sectional view of FIG. 18 , it can be seen that the lower fin locations 1800A and 1802A are below the height of the isolation structure 1804 . Also, seen in this cross-sectional view is the remnant portion 1810 of the fin that was removed in the final fin trim process prior to the formation of the isolation structure 1804, as described above. Although shown protruding above the substrate, the remnant 1810 may also be at the level of the substrate or into the substrate, as depicted by the additional representative wide cut depth 1820 . It can be appreciated that broad cuts 1806 for fins 1800 and 1802 may also be at the level noted for cut depth 1820, an example of which is described. Partial cuts 1808 may have representative depths corresponding to those described for FIGS. 17A-17C .

共同地參照圖16A,16B,17A到17C和18，依據本發明的一實施例，包含鰭部(其包含矽)的積體電路結構，該鰭部具有頂部和側壁，其中，頂部沿著第一方向具有最長的尺寸。第一隔離結構沿著第一方向使鰭部之第一部位的第一末端與鰭部之第二部位的第一末端分開。第一隔離結構沿著第一方向具有寬度。鰭部之第一部位的第一末端具有表面粗糙度。閘極結構包含在鰭部之第一部位之區域的側壁的頂部之上並且橫向鄰接於鰭部之第一部位之區域的側壁的閘極電極。閘極結構沿著第一方向具有寬度，而且閘極結構的中心與第一隔離結構的中心沿著第一 方向而被間隔開一間距。第二隔離結構係在鰭部之第一部位的第二末端之上，第二末端和第一末端相對立。第二隔離結構沿著第一方向具有寬度，而且鰭部之第一部位的第二末端具有比鰭部之第一部位之第一末端的表面粗糙度更小的表面粗糙度。第二隔離結構的中心與閘極結構的中心沿著第一方向而被間隔開一間距。 16A, 16B, 17A to 17C and 18 collectively, in accordance with an embodiment of the present invention, an integrated circuit structure comprising a fin comprising silicon having a top and sidewalls, wherein the top is along the One direction has the longest dimension. The first isolation structure separates the first end of the first portion of the fin from the first end of the second portion of the fin along the first direction. The first isolation structure has a width along a first direction. The first end of the first portion of the fin has surface roughness. The gate structure includes a gate electrode on top of the sidewall of the region of the first portion of the fin and laterally adjacent to the sidewall of the region of the first portion of the fin. The gate structure has a width along the first direction, and the center of the gate structure and the center of the first isolation structure are along the first direction. directions are spaced apart by a gap. The second isolation structure is attached to the second end of the first portion of the fin, and the second end is opposite to the first end. The second isolation structure has a width along the first direction, and the second end of the first portion of the fin has a surface roughness smaller than that of the first end of the first portion of the fin. The center of the second isolation structure and the center of the gate structure are separated by a distance along the first direction.

在一實施例中，鰭部之第一部位的第一末端具有扇形形貌(scalloped topography)，如圖16B中所描述者。在一個實施例中，第一磊晶半導體區域係在鰭部之第一部位上，在閘極結構與第一隔離結構之間。第二磊晶半導體區域係在鰭部之第一部位上，在閘極結構與第二隔離結構之間。在一個實施例中，第一及第二磊晶半導體區域沿著與第一方向正交的第二方向具有寬度，沿著第二方向的寬度比鰭部之第一部位在閘極結構之下沿著第二方向的寬度更寬，例如，如同相關於圖11及12D所述的磊晶特徵，其具有比鰭部部位更寬的寬度，而它們在該等鰭部部位上被生長於圖11及12D中所顯示的透視圖中。在一個實施例中，閘極結構另包含高k閘極電介質層在閘極電極與鰭部的第一部位之間，並且沿著閘極電極的側壁。 In one embodiment, the first end of the first portion of the fin has a scalloped topography, as depicted in FIG. 16B . In one embodiment, the first epitaxial semiconductor region is on a first portion of the fin between the gate structure and the first isolation structure. The second epitaxial semiconductor region is on the first portion of the fin between the gate structure and the second isolation structure. In one embodiment, the first and second epitaxial semiconductor regions have a width along a second direction perpendicular to the first direction, the width along the second direction being greater than that of the first portion of the fin portion below the gate structure The width along the second direction is wider, for example, the epitaxial features as described in relation to FIGS. Perspective views shown in 11 and 12D. In one embodiment, the gate structure further includes a high-k gate dielectric layer between the gate electrode and the first portion of the fin, and along sidewalls of the gate electrode.

共同地參照圖16A,16B,17A到17C和18，依據本發明的另一實施例，積體電路結構包含鰭部(其包含矽)，該鰭部具有頂部和側壁，其中，頂部沿著一方向具有最長的尺寸。第一隔離結構沿著該方向使鰭部之第一部位的第一末端與鰭部之第二部位的第一末端分開。鰭部之 第一部位的第一末端具有深度。閘極結構包含在鰭部之第一部位之區域的頂部之上並且橫向鄰接於鰭部之第一部位之區域的側壁的閘極電極。第二隔離結構係在鰭部之第一部位的第二末端之上，第二末端和第一末端相對立。鰭部之第一部位的第二末端具有與鰭部之第一部位之第一末端的深度不同的深度。 16A, 16B, 17A to 17C, and 18 collectively, according to another embodiment of the present invention, an integrated circuit structure includes a fin (which includes silicon) having a top and sidewalls, wherein the top is along a The direction has the longest dimension. The first isolation structure separates the first end of the first portion of the fin from the first end of the second portion of the fin along the direction. of the fins The first end of the first location has a depth. The gate structure includes a gate electrode on top of the region of the first portion of the fin and laterally adjacent sidewalls of the region of the first portion of the fin. The second isolation structure is attached to the second end of the first portion of the fin, and the second end is opposite to the first end. The second end of the first portion of the fin has a different depth than the depth of the first end of the first portion of the fin.

在一個實施例中，鰭部之第一部位之第二末端的深度小於鰭部之第一部位之第一末端的深度。在一個實施例中，鰭部之第一部位之第二末端的深度大於鰭部之第一部位之第一末端的深度。在一個實施例中，第一隔離結構沿著該方向具有寬度，而且閘極結構沿著該方向具有寬度。第二隔離結構沿著該方向具有寬度。在一個實施例中，閘極結構的中心與第一隔離結構的中心沿著該方向而被間隔開一間距，而且第二隔離結構的中心與閘極結構的中心沿著該方向而被間隔開一間距。 In one embodiment, the depth of the second end of the first portion of the fin is less than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the second end of the first portion of the fin is greater than the depth of the first end of the first portion of the fin. In one embodiment, the first isolation structure has a width along the direction, and the gate structure has a width along the direction. The second isolation structure has a width along the direction. In one embodiment, the center of the gate structure is spaced apart from the center of the first isolation structure by a distance along the direction, and the center of the second isolation structure is spaced apart from the center of the gate structure along the direction. one pitch.

共同地參照圖16A,16B,17A到17C和18，依據本發明的另一實施例，積體電路結構包含第一鰭部(其包含矽)，該第一鰭部具有頂部和側壁，其中，頂部沿著一方向具有最長的尺寸，而且中斷(discontinuity)沿著該方向使第一鰭部之第一部位的第一末端與鰭部之第二部位的第一末端分開。第一鰭部的第一部位具有與第一末端對立的第二末端，而且該鰭部之第一部位的第一末端具有深度。該積體電路結構也包含第二鰭部(其包含矽)，該第二鰭部具有頂部和側壁，其中，頂部沿著該方向具有最長的 尺寸。該積體電路結構也包含在第一鰭部與第二鰭部之間的殘餘或殘留的鰭部部位。殘留的鰭部部位具有頂部和側壁，其中，頂部沿著該方向具有最長的尺寸，而且該頂部係與該鰭部之第一部位之第一末端的深度非共平面的。 Referring collectively to FIGS. 16A, 16B, 17A to 17C and 18, in accordance with another embodiment of the present invention, an integrated circuit structure includes a first fin (comprising silicon) having a top and sidewalls, wherein, The top has a longest dimension along a direction, and a discontinuity along the direction separates the first end of the first portion of the first fin from the first end of the second portion of the fin. The first portion of the first fin has a second end opposite to the first end, and the first end of the first portion of the fin has a depth. The integrated circuit structure also includes a second fin (which includes silicon) having a top and sidewalls, wherein the top has a longest size. The integrated circuit structure also includes a remnant or residual fin portion between the first fin and the second fin. The remaining fin portion has a top and sidewalls, wherein the top has a longest dimension along the direction, and the top is non-coplanar with the depth of the first end of the first portion of the fin.

在一個實施例中，鰭部之第一部位之第一末端的深度係在該殘餘或殘留之鰭部部位的頂部之下。在一個實施例中，該鰭部之第一部位的第二末端具有與該鰭部之第一部位之第一末端的深度共平面的深度。在一個實施例中，該鰭部之第一部位之第二末端具有在該鰭部之第一部位之第一末端的深度之下的深度。在一個實施例中，該鰭部之第一部位之第二末端具有在該鰭部之第一部位之第一末端的深度之上的深度。在一個實施例中，該鰭部之第一部位之第一末端的深度係在該殘餘或殘留之鰭部部位的頂部之上。在一個實施例中，該鰭部之第一部位的第二末端具有與該鰭部之第一部位之第一末端的深度共平面的深度。在一個實施例中，該鰭部之第一部位之第二末端具有在該鰭部之第一部位之第一末端的深度之下的深度。在一個實施例中，該鰭部之第一部位之第二末端具有在該鰭部之第一部位之第一末端的深度之上的深度。在一個實施例中，該鰭部之第一部位之第二末端具有與該殘留之鰭部部位的頂部共平面的深度。在一個實施例中，該鰭部之第一部位之第二末端具有在該殘留之鰭部部位的頂部之下的深度。在一個實施例中，該鰭部之第一部位之第二末端具有在該殘留之鰭部部位的頂部之上的深度。 In one embodiment, the depth of the first end of the first portion of the fin is below the top of the residual or residual fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth below the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth greater than the depth of the first end of the first portion of the fin. In one embodiment, the depth of the first end of the first portion of the fin is above the top of the residual or remaining fin portion. In one embodiment, the second end of the first portion of the fin has a depth that is coplanar with the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth below the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth greater than the depth of the first end of the first portion of the fin. In one embodiment, the second end of the first portion of the fin has a depth that is coplanar with the top of the remaining fin portion. In one embodiment, the second end of the first portion of the fin has a depth below the top of the remaining fin portion. In one embodiment, the second end of the first portion of the fin has a depth above the top of the remaining fin portion.

在另一態樣中，形成在局部或寬廣鰭部切割部的位置中之電介質插塞可以被修改(tailored)以將特別的應力提供給鰭部或鰭部部位。該電介質插塞在此等施行中可以被稱為鰭部末端應力源(stressor)。 In another aspect, dielectric plugs formed in the locations of localized or broad fin cuts may be tailored to provide specific stress to the fin or fin regions. The dielectric plug may be referred to as a fin tip stressor in these implementations.

一或更多個實施例係有關以鰭部為基礎的半導體裝置的製造。此等裝置的性能改善可以經由由多晶插塞填充製程所誘發(induced)的通道應力來達成。實施例可包含多晶插塞填充製程中之材料特性的開發(exploitation)而誘發機械應力於金屬氧化物半導體場效電晶體(MOSFET)通道中。結果，誘發應力可以促進(boost)電晶體的遷移率和驅動電流。除此之外，本文中所述的插塞填充方法可以允許能夠去除沉積期間之任何的接縫(seam)或空洞(void)形成。 One or more embodiments relate to the fabrication of fin-based semiconductor devices. Improved performance of these devices can be achieved through channel stress induced by the poly plug fill process. Embodiments may include the exploitation of material properties in poly plug fill processes to induce mechanical stress in MOSFET channels. As a result, induced stress can boost the mobility and drive current of the transistor. In addition, the plug-fill method described herein may allow any seam or void formation during deposition to be eliminated.

為了提供上下文，操縱使鰭部毗連(abut)之插塞填充的獨特材料特性可以誘發通道內的應力。依據一或更多個實施例，藉由調諧插塞填充材料的組成、沉積、和後處理條件，通道中的應力被調變而有利於NMOS電晶體和PMOS電晶體兩者。除此之外，相較於其他一般的應力源技術，此等插塞於鰭部基板中可以位在更深的位置，諸如磊晶的源極或汲極。插塞填充來達成此種功效的本性也消除沉積期間的接縫或空洞，而且減緩該製程期間的某些缺陷模式。 To provide context, manipulation of unique material properties of the plug fill that abuts the fin can induce stress within the channel. According to one or more embodiments, by tuning the composition of the plug fill material, deposition, and post-processing conditions, the stress in the channel is tuned to benefit both the NMOS transistor and the PMOS transistor. In addition, the plugs can be located deeper in the fin substrate than other common stressor techniques, such as epitaxial source or drain. The nature of plug fill to achieve this effect also eliminates seams or voids during deposition and mitigates certain defect modes during the process.

為了提供進一步上下文，目前對於閘極(多晶)插塞沒有有意的應力工程(stress engineering)。來自傳 統應力源(諸如，磊晶的源極或汲極、假性多晶閘極去除、應力襯墊(stress liner)、等等)的應力提升不幸地傾向隨著裝置間距縮小而減小。對付上述問題的一或多者，依據本發明的一或更多個實施例，額外的應力源被併入電晶體結構中。此一製程的另一可能好處可能是該插塞內之接縫或空洞的消除，其可能是其他化學氣相沉積方法常見的。 To provide further context, there is currently no intentional stress engineering on gate (poly) plugs. Biography The stress rise of conventional stressors (such as epitaxial source or drain, pseudo poly gate removal, stress liner, etc.) unfortunately tends to decrease as device pitch shrinks. To address one or more of the above problems, in accordance with one or more embodiments of the present invention, additional stressors are incorporated into the transistor structure. Another possible benefit of this process may be the elimination of seams or voids within the plug, which may be common to other chemical vapor deposition methods.

圖19A及19B繪示依據本發明的一實施例，在選擇鰭部的末端(其具有寬廣的切割部)處之鰭部末端應力源位置的方法(例如，作為如上所述之鰭部修整最終製程的部分)中之各種操作的剖面視圖。 19A and 19B illustrate a method of selecting the location of a fin tip stressor at the tip of a fin (which has a broad cut) in accordance with an embodiment of the present invention (eg, as a final result of fin trimming as described above). A cross-sectional view of various operations in part of the process).

參照圖19A，諸如矽鰭部的鰭部1900被形成在基板1902之上並且可以和基板1902係連續的。鰭部1900具有鰭部末端或寬廣的鰭部切割部1904，例如，其可以被形成在鰭部圖案化之時，諸如在上面所述的鰭部修整最終法中。作用閘極電極位置1906和假性閘極電極位置1908被形成在鰭部1900之上，並且為了例舉目的，如所示地稍微在鰭部1900的前面，而鰭部1900係在背景中，在該處，虛線表示從前視圖所覆蓋的區域。可以領會到磊晶的源極或汲極區域1910也被顯示於鰭部1900在閘極位置1906與1908之間的位置處。除此之外，層間電介質材料1912被包含在鰭部1900在閘極位置1906與1908之間的位置處。 Referring to FIG. 19A , fins 1900 , such as silicon fins, are formed over a substrate 1902 and may be continuous with the substrate 1902 . Fin 1900 has a fin tip or broad fin cut 1904 , which may be formed, for example, when the fin is patterned, such as in the fin trimming process described above. An active gate electrode location 1906 and a dummy gate electrode location 1908 are formed over the fin 1900 and, for illustrative purposes, are shown slightly in front of the fin 1900 with the fin 1900 tied in the background, Here, dashed lines indicate the area covered from the front view. It can be appreciated that an epitaxial source or drain region 1910 is also shown at the location of the fin 1900 between the gate locations 1906 and 1908 . In addition, interlayer dielectric material 1912 is included at the location of fin 1900 between gate locations 1906 and 1908 .

參照圖19B，閘極佔位件結構或假性閘極位置1908被去除，使鰭部末端或寬廣的鰭部切割部1904暴露 出。該去除產生開口1920，而在開口1920處，例如鰭部末端應力源電介質插塞的電介質插塞最終可以被形成。 Referring to FIG. 19B, the gate placer structures or dummy gate locations 1908 are removed, exposing the fin ends or broad fin cuts 1904. out. This removal creates an opening 1920 where a dielectric plug, such as a fin end stressor dielectric plug, may eventually be formed.

圖20A及20B繪示依據本發明的一實施例，在選擇鰭部的末端(其具有局部的切割部)處之鰭部末端應力源位置的方法(例如，作為如上所述之鰭部修整最終製程的部分)中之各種操作的剖面視圖。 20A and 20B illustrate a method of selecting the location of a fin tip stressor at the tip of a fin (which has a localized cutout), in accordance with an embodiment of the present invention (eg, as a final result of fin trimming as described above). A cross-sectional view of various operations in part of the process).

參照圖20A，諸如矽鰭部的鰭部2000被形成在基板2002之上並且可以和基板2002係連續的。鰭部2000具有局部的切割部2004，在該局部的切割部2004處，鰭部2000的一部分被去除，例如，使用鰭部修整隔離法，在該鰭部修整隔離法中，假性閘極如上所述地被去除而且該鰭部被蝕刻於局部位置中。作用閘極電極位置2006和假性閘極電極位置2008被形成在鰭部2000之上，並且為了例舉目的，如所示地稍微在鰭部2000的前面，而鰭部2000係在背景中，在該處，虛線表示從前視圖所覆蓋的區域。可以領會到磊晶的源極或汲極區域2010也被顯示於鰭部2000在閘極位置2006與2008之間的位置處。除此之外，層間電介質材料2012被包含在鰭部2000在閘極位置2006與2008之間的位置處。 Referring to FIG. 20A , fins 2000 , such as silicon fins, are formed over a substrate 2002 and may be continuous with the substrate 2002 . The fin 2000 has a partial cut 2004 where a portion of the fin 2000 is removed, for example, using a fin trim isolation method in which the dummy gate is as above The ground is removed and the fin is etched in localized locations. An active gate electrode location 2006 and a dummy gate electrode location 2008 are formed over the fin 2000 and, for illustrative purposes, are shown slightly in front of the fin 2000 with the fin 2000 tied in the background, Here, dashed lines indicate the area covered from the front view. It can be appreciated that an epitaxial source or drain region 2010 is also shown on the fin 2000 at a location between the gate locations 2006 and 2008 . In addition, an interlayer dielectric material 2012 is included at the location of the fin 2000 between the gate locations 2006 and 2008 .

參照圖20B，閘極佔位件結構或假性閘極位置2008被去除，使鰭部末端或寬廣的鰭部切割部2004暴露出。該去除產生開口2020，而在開口2020處，例如鰭部末端應力源電介質插塞的電介質插塞最終可以被形成。 Referring to FIG. 20B , the gate placer structures or dummy gate locations 2008 are removed, exposing the fin ends or broad fin cuts 2004 . This removal creates an opening 2020 where a dielectric plug, such as a fin end stressor dielectric plug, may eventually be formed.

圖21A到21M繪示依據本發明的一實施例， 製造具有差異化(differentiated)鰭部末端電介質插塞之積體電路結構的方法中之各種操作的剖面視圖。 21A to 21M illustrate an embodiment according to the present invention, Cross-sectional views of various operations in a method of fabricating an integrated circuit structure with differentiated fin-tip dielectric plugs.

參照圖21A，起始結構2100包含NMOS區域和PMOS區域。起始結構2100的NMOS區域包含諸如第一矽鰭部的第一鰭部2102，第一鰭部2102被形成在基板2104之上並且可以和基板2104係連續的。第一鰭部2102具有可以由局部或寬廣的鰭部切割部所形成的鰭部末端2106。第一作用閘極電極位置2108和第一假性閘極電極位置2110被形成在第一鰭部2102之上，並且為了例舉目的，如所示地稍微在第一鰭部2102的前面，而第一鰭部2102係在背景中，在該處，虛線表示從前視圖所覆蓋的區域。諸如磊晶的矽源極或汲極結構之磊晶的N型源極或汲極區域2112也被顯示於第一鰭部2102在閘極位置2108與2110之間的位置處。除此之外，層間電介質材料2114被包含在第一鰭部2102在閘極位置2108與2110之間的位置處。 Referring to FIG. 21A, a starting structure 2100 includes an NMOS region and a PMOS region. The NMOS region of the starting structure 2100 includes a first fin 2102 , such as a first silicon fin, that is formed over and may be continuous with the substrate 2104 . The first fin 2102 has a fin tip 2106 which may be formed by a partial or broad fin cut. A first active gate electrode location 2108 and a first dummy gate electrode location 2110 are formed over the first fin 2102 and, for illustrative purposes, slightly in front of the first fin 2102 as shown, while The first fin 2102 is in the background, where the dashed lines indicate the area covered from the front view. An epitaxial N-type source or drain region 2112 such as an epitaxial silicon source or drain structure is also shown at the location of the first fin 2102 between gate locations 2108 and 2110 . Additionally, an interlayer dielectric material 2114 is included at the location of the first fin 2102 between gate locations 2108 and 2110 .

起始結構2100的PMOS區域包含諸如第二矽鰭部的第二鰭部2122，第二鰭部2122被形成在基板2104之上並且可以和基板2104係連續的。第二鰭部2122具有可以由局部或寬廣的鰭部切割部所形成的鰭部末端2126。第二作用閘極電極位置2128和第二假性閘極電極位置2130被形成在第二鰭部2122之上，並且為了例舉目的，如所示地稍微在第二鰭部2122的前面，而第二鰭部2122係在背景中，在該處，虛線表示從前視圖所覆蓋的區域。諸如磊晶的矽鍺源極或汲極結構之磊晶的P型源極或汲極區域2132也被 顯示於第二鰭部2122在閘極位置2128與2130之間的位置處。除此之外，層間電介質材料2134被包含在第二鰭部2122在閘極位置2128與2130之間的位置處。 The PMOS region of the starting structure 2100 includes a second fin 2122 , such as a second silicon fin, formed over the substrate 2104 and may be continuous with the substrate 2104 . The second fin 2122 has a fin tip 2126 which may be formed by a partial or broad fin cut. A second active gate electrode location 2128 and a second dummy gate electrode location 2130 are formed over the second fin 2122 and, for example purposes, slightly in front of the second fin 2122 as shown, while The second fin 2122 is tied in the background, where the dashed line indicates the area covered from the front view. Epitaxial P-type source or drain regions 2132 such as epitaxial silicon germanium source or drain structures are also It is shown at the location of the second fin 2122 between the gate locations 2128 and 2130 . Additionally, an interlayer dielectric material 2134 is included at the location of the second fin 2122 between gate locations 2128 and 2130 .

參照圖21B，分別在位置2110和2130的第一和第二假性閘極電極被去除。在去除後，第一鰭部2102的鰭部末端2106和第二鰭部2122的鰭部末端2126就被暴露出。該去除也分別產生開口2116和2136，在該處，例如鰭部末端電介質插塞的電介質插塞最終可以被形成。 Referring to FIG. 21B, the first and second dummy gate electrodes at locations 2110 and 2130, respectively, are removed. After removal, the fin end 2106 of the first fin 2102 and the fin end 2126 of the second fin 2122 are exposed. This removal also creates openings 2116 and 2136, respectively, where dielectric plugs, such as fin-tip dielectric plugs, may eventually be formed.

參照圖21C，材料襯墊2140被形成與圖21B的結構共形。在一實施例中，該材料襯墊包含矽和氮，諸如氮化矽材料襯墊。 Referring to Figure 21C, a liner of material 2140 is formed conformal to the structure of Figure 21B. In one embodiment, the material liner includes silicon and nitrogen, such as a silicon nitride material liner.

參照圖21D，諸如金屬氮化物層的保護冠層2142被形成在圖21C的結構上。 Referring to Figure 21D, a protective canopy 2142, such as a metal nitride layer, is formed over the structure of Figure 21C.

參照圖21E，諸如基於碳之(carbon-based)硬遮罩材料的硬遮罩材料2144被形成在圖21D的結構之上。光刻遮罩或遮罩堆疊2146被形成在硬遮罩材料2144之上。 Referring to FIG. 21E, a hard mask material 2144, such as a carbon-based hard mask material, is formed over the structure of FIG. 21D. A photolithographic mask or mask stack 2146 is formed over hard mask material 2144 .

參照圖21F，硬遮罩材料2144和保護冠層2142之在PMOS區域的部分從圖21E的結構中被去除。光刻遮罩或遮罩堆疊2146也被去除。 Referring to FIG. 21F, hard mask material 2144 and portions of protective canopy 2142 in the PMOS region are removed from the structure of FIG. 21E. The photolithographic mask or mask stack 2146 is also removed.

參照圖21G，第二材料襯墊2148被形成與圖21F的結構共形。在一實施例中，該第二材料襯墊包含矽和氮，諸如第二氮化矽材料襯墊。在一實施例中，該第二材料襯墊2148具有不同的應力以調整在露出之插塞中的應力。 Referring to Figure 21G, a second liner of material 2148 is formed conformal to the structure of Figure 21F. In one embodiment, the second liner of material includes silicon and nitrogen, such as a second liner of silicon nitride material. In one embodiment, the second material liner 2148 has a different stress to adjust the stress in the exposed plug.

參照圖21H，諸如基於碳之第二硬遮罩材料的第二硬遮罩材料2150被形成在圖21G的結構之上，而後被凹入於該結構之PMOS區域的開口2136內。 Referring to FIG. 21H, a second hard mask material 2150, such as a carbon-based second hard mask material, is formed over the structure of FIG. 21G and then recessed within the opening 2136 of the PMOS region of the structure.

參照圖21I，第二材料襯墊2148從圖21H的結構中被蝕刻而從NMOS區域中去除該第二材料襯墊2148，並且使該結構之PMOS區域中的該第二材料襯墊2148凹入。 Referring to FIG. 21I, the second liner of material 2148 is etched from the structure of FIG. 21H to remove the second liner of material 2148 from the NMOS region and to recess the second liner of material 2148 in the PMOS region of the structure. .

參照圖21J，從圖21I的結構中去除硬遮罩材料2144、保護冠層2142、和第二硬遮罩材料2150。相較於開口2136，該去除為開口2116分別留下了兩個不同的填充結構。 Referring to Figure 21J, hard mask material 2144, protective canopy 2142, and second hard mask material 2150 are removed from the structure of Figure 21I. This removal leaves two different filling structures for opening 2116, respectively, compared to opening 2136.

參照圖21K，絕緣填充材料2152被形成在圖21J之結構的開口2116和2136中，並且被平坦化。在一實施例中，絕緣填充材料2152為流動性(flowable)氧化物材料，諸如流動性氧化矽或二氧化矽材料。 Referring to FIG. 21K, insulating fill material 2152 is formed in openings 2116 and 2136 of the structure of FIG. 21J and planarized. In one embodiment, the insulating filling material 2152 is a flowable oxide material, such as a flowable silicon oxide or silicon dioxide material.

參照圖21L，絕緣填充材料2152被凹入於圖21K之結構的開口2116和2136內以形成凹入的絕緣填充材料2154。在一實施例中，蒸汽氧化製程被實施作為該凹入製程的部分或者在該凹入製程之後，以使凹入的絕緣填充材料2154固化。在一實施例中，凹入的絕緣填充材料2154縮減，誘發鰭部2102和2122上的伸張應力。但是，在PMOS區域中比在NMOS區域有相對較小的伸張應力誘發(stress-inducing)材料。 Referring to FIG. 21L , insulating fill material 2152 is recessed within openings 2116 and 2136 of the structure of FIG. 21K to form recessed insulating fill material 2154 . In one embodiment, a vapor oxidation process is performed as part of or after the recess process to cure the recessed insulating fill material 2154 . In one embodiment, the recessed insulating fill material 2154 shrinks, inducing tensile stress on the fins 2102 and 2122 . However, there is relatively less tensile stress-inducing material in the PMOS region than in the NMOS region.

參照圖21M，第三材料襯墊2156係在圖21L 的結構之上。在一實施例中，第三材料襯墊2156包含矽和氮，諸如第三氮化矽材料襯墊。在一實施例中，第三材料襯墊2156防止凹入的絕緣填充材料2154在後續的源極或汲極接觸蝕刻期間被蝕刻掉。 Referring to FIG. 21M, a third material liner 2156 is attached to FIG. 21L on the structure. In one embodiment, the third material liner 2156 includes silicon and nitrogen, such as a third silicon nitride material liner. In one embodiment, the third material liner 2156 prevents the recessed insulating fill material 2154 from being etched away during a subsequent source or drain contact etch.

圖22A到22D繪示依據本發明的一實施例，PMOS鰭部末端應力源電介質插塞之代表性結構的剖面視圖。 22A-22D illustrate cross-sectional views of representative structures of PMOS fin end stressor dielectric plugs in accordance with one embodiment of the present invention.

參照圖22A，結構2100之PMOS區域的開口2136包含沿著開口2136之側壁的材料襯墊2140。第二材料襯墊2148係與材料襯墊2140的下部部位共形，但是相對於材料襯墊2140的上部部位而被凹入。凹入的絕緣填充材料2154係在第二材料襯墊2148之內，而且具有與第二材料襯墊2148之上部表面共平面的上部表面。第三材料襯墊2156係在材料襯墊2140的上部部位之內，並且在絕緣填充材料2154的上部表面而且在第二材料襯墊2148的上部表面上。第三材料襯墊2156具有接縫2157，例如，作為沉積製程被用來形成第三材料襯墊2156的加工品(artifact)。 Referring to FIG. 22A , the opening 2136 of the PMOS region of the structure 2100 includes a liner of material 2140 along the sidewalls of the opening 2136 . Second pad of material 2148 is conformal to a lower portion of pad of material 2140 , but is recessed relative to an upper portion of pad of material 2140 . The recessed insulating fill material 2154 is tied within the second liner of material 2148 and has an upper surface that is coplanar with the upper surface of the second liner of material 2148 . The third liner of material 2156 is tied within the upper portion of the liner of material 2140 and is on the upper surface of the insulating filler material 2154 and on the upper surface of the second liner of material 2148 . The third liner of material 2156 has a seam 2157 , eg, as an artifact of the deposition process used to form the third liner of material 2156 .

參照圖22B，結構2100之PMOS區域的開口2136包含沿著開口2136之側壁的材料襯墊2140。第二材料襯墊2148係與材料襯墊2140的下部部位共形，但是相對於材料襯墊2140的上部部位而被凹入。凹入的絕緣填充材料2154係在第二材料襯墊2148之內，而且具有與第二材料襯墊2148之上部表面共平面的上部表面。第三材料襯墊2156係在材料襯墊2140的上部部位之內，並且在絕緣填充材料 2154的上部表面而且在第二材料襯墊2148的上部表面上。第三材料襯墊2156沒有接縫。 Referring to FIG. 22B , the opening 2136 of the PMOS region of the structure 2100 includes a liner of material 2140 along the sidewalls of the opening 2136 . Second pad of material 2148 is conformal to a lower portion of pad of material 2140 , but is recessed relative to an upper portion of pad of material 2140 . The recessed insulating fill material 2154 is tied within the second liner of material 2148 and has an upper surface that is coplanar with the upper surface of the second liner of material 2148 . The third liner of material 2156 is tied within the upper portion of the liner of material 2140, and in the insulating filler material The upper surface of the liner 2154 is also on the upper surface of the second liner of material 2148 . The third pad of material 2156 has no seams.

參照圖22C，結構2100之PMOS區域的開口2136包含沿著開口2136之側壁的材料襯墊2140。第二材料襯墊2148係與材料襯墊2140的下部部位共形，但是相對於材料襯墊2140的上部部位而被凹入。凹入的絕緣填充材料2154係在第二材料襯墊2148之內並且在第二材料襯墊2148之上，而且具有在第二材料襯墊2148之上部表面之上的上部表面。第三材料襯墊2156係在材料襯墊2140的上部部位之內，並且在絕緣填充材料2154的上部表面上。第三材料襯墊2156被顯示沒有接縫，但是在其他實施例中，第三材料襯墊2156具有接縫。 Referring to FIG. 22C , the opening 2136 of the PMOS region of the structure 2100 includes a liner of material 2140 along the sidewalls of the opening 2136 . Second pad of material 2148 is conformal to a lower portion of pad of material 2140 , but is recessed relative to an upper portion of pad of material 2140 . The recessed insulating fill material 2154 is tied within and over the second liner of material 2148 and has an upper surface over the upper surface of the second liner of material 2148 . A third liner of material 2156 is tied within an upper portion of liner of material 2140 and on an upper surface of insulating fill material 2154 . The third pad of material 2156 is shown without a seam, but in other embodiments, the third pad of material 2156 has a seam.

參照圖22D，結構2100之PMOS區域的開口2136包含沿著開口2136之側壁的材料襯墊2140。第二材料襯墊2148係與材料襯墊2140的下部部位共形，但是相對於材料襯墊2140的上部部位而被凹入。凹入的絕緣填充材料2154係在第二材料襯墊2148之內，而且具有凹入於第二材料襯墊2148之上部表面之下的上部表面。第三材料襯墊2156係在材料襯墊2140的上部部位之內，並且在絕緣填充材料2154的上部表面而且在第二材料襯墊2148的上部表面上。第三材料襯墊2156被顯示沒有接縫，但是在其他實施例中，第三材料襯墊2156具有接縫。 Referring to FIG. 22D , the opening 2136 of the PMOS region of the structure 2100 includes a liner of material 2140 along the sidewalls of the opening 2136 . Second pad of material 2148 is conformal to a lower portion of pad of material 2140 , but is recessed relative to an upper portion of pad of material 2140 . The recessed insulating fill material 2154 is tied within the second liner of material 2148 and has an upper surface recessed below the upper surface of the second liner of material 2148 . The third liner of material 2156 is tied within the upper portion of the liner of material 2140 and is on the upper surface of the insulating filler material 2154 and on the upper surface of the second liner of material 2148 . The third pad of material 2156 is shown without a seam, but in other embodiments, the third pad of material 2156 has a seam.

共同地參照圖19A,19B,20A,20B,21A到21M和22A到22D，依據本發明的一實施例，積體電路結構 包含諸如矽的鰭部，該鰭部具有頂部和側壁。該頂部沿著一方向具有最長的尺寸。第一隔離結構係在該鰭部的第一末端之上。閘極結構包含在該鰭部之區域的側壁的頂部之上並且橫向鄰接於該鰭部之區域的側壁的閘極電極。該閘極結構沿著該方向而與第一隔離結構間隔開。第二隔離結構係在該鰭部的第二末端之上，第二末端和第一末端相對立。該第二隔離結構沿著該方向而與該閘極結構間隔開。第一隔離結構和第二隔離結構兩者皆包含第一電介質材料(例如，材料襯墊2140)，第一電介質材料係橫向環繞與第一電介質材料不同之凹入的第二電介質材料(例如，第二材料襯墊2148)。凹入的第二電介質材料係橫向環繞與第一及第二電介質材料不同之第三電介質材料(例如，凹入的絕緣填充材料2154)的至少一部分。 19A, 19B, 20A, 20B, 21A to 21M and 22A to 22D collectively, according to an embodiment of the present invention, the integrated circuit structure A fin, such as silicon, is included having a top and sidewalls. The top has the longest dimension along a direction. A first isolation structure is tied over the first end of the fin. The gate structure includes a gate electrode on top of and laterally adjacent to sidewalls of the region of the fin. The gate structure is spaced apart from the first isolation structure along the direction. A second isolation structure is attached to a second end of the fin, the second end being opposite to the first end. The second isolation structure is spaced apart from the gate structure along the direction. Both the first isolation structure and the second isolation structure comprise a first dielectric material (eg, liner of material 2140) laterally surrounding a recessed second dielectric material (eg, liner 2140) different from the first dielectric material. second material liner 2148). The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material (eg, recessed insulating fill material 2154 ) that is different from the first and second dielectric materials.

在一個實施例中，第一隔離結構和第二隔離結構兩者皆另包含由第一電介質材料之上部部位所橫向環繞的第四電介質材料(例如，第三材料襯墊2156)，該第四電介質材料係在第三電介質材料的上部表面上。在一個這樣的實施例中，該第四電介質材料進一步在第二電介質材料的上部表面上。在另一個這樣的實施例中，該第四電介質材料具有大約垂直的中央接縫。在另一個這樣的實施例中，該第四電介質材料沒有接縫。 In one embodiment, both the first isolation structure and the second isolation structure further include a fourth dielectric material (eg, third material liner 2156 ) laterally surrounded by an upper portion of the first dielectric material, the fourth dielectric material A dielectric material is tied on the upper surface of the third dielectric material. In one such embodiment, the fourth dielectric material is further on the upper surface of the second dielectric material. In another of these embodiments, the fourth dielectric material has an approximately vertical central seam. In another of these embodiments, the fourth dielectric material has no seams.

在一個實施例中，第三電介質材料具有與第二電介質材料之上部表面共平面的上部表面。在一個實施例中，第三電介質材料具有在第二電介質材料的上部表面 之下的上部表面。在一個實施例中，第三電介質材料具有在第二電介質材料的上部表面之上的上部表面，而且第三電介質材料係進一步在第二電介質材料的上部表面之上。在一個實施例中，第一及第二隔離結構誘發鰭部上的壓縮應力。在一個這樣的實施例中，閘極電極為P型閘極電極。 In one embodiment, the third dielectric material has an upper surface that is coplanar with the upper surface of the second dielectric material. In one embodiment, the third dielectric material has an upper surface of the second dielectric material below the upper surface. In one embodiment, the third dielectric material has an upper surface above the upper surface of the second dielectric material, and the third dielectric material is further above the upper surface of the second dielectric material. In one embodiment, the first and second isolation structures induce compressive stress on the fin. In one such embodiment, the gate electrode is a P-type gate electrode.

在一個實施例中，第一隔離結構沿著該方向具有寬度，閘極結構沿著該方向具有寬度，並且第二隔離結構沿著該方向具有寬度。在一個這樣的實施例中，閘極結構的中心沿著該方向與第一隔離結構的中心間隔開一間隙，並且第二隔離結構的中心沿著該方向與閘極結構的中心間隔開一間隙。在一個實施例中，第一和第二隔離結構兩者皆在層間電介質層的對應溝槽中。 In one embodiment, the first isolation structure has a width along the direction, the gate structure has a width along the direction, and the second isolation structure has a width along the direction. In one such embodiment, the center of the gate structure is spaced along the direction by a gap from the center of the first isolation structure, and the center of the second isolation structure is spaced along the direction by a gap from the center of the gate structure . In one embodiment, both the first and second isolation structures are in corresponding trenches of the interlayer dielectric layer.

在一個這樣的實施例中，第一源極或汲極區域係在閘極結構與第一隔離結構之間。第二源極或汲極區域係在閘極結構與第二隔離結構之間。在一個這樣的實施例中，第一及第二源極或汲極區域為包含矽和鍺之嵌入的源極或汲極區域。在一個這樣的實施例中，閘極結構另包含在閘極電極與鰭部之間而且沿著閘極電極之側壁的高k電介質層。 In one such embodiment, the first source or drain region is between the gate structure and the first isolation structure. The second source or drain region is between the gate structure and the second isolation structure. In one such embodiment, the first and second source or drain regions are embedded source or drain regions comprising silicon and germanium. In one such embodiment, the gate structure further includes a high-k dielectric layer between the gate electrode and the fin and along sidewalls of the gate electrode.

在另一態樣中，個別電介質插塞的深度在半導體結構之內或者在形成於共同基板上的架構之內可以改變。作為一範例，圖23A繪示依據本發明的另一實施例，具有鰭部末端應力誘發特徵之另一半導體結構的剖面視 圖。參照圖23A，包含有淺的電介質插塞2308A連同一對深的電介質插塞2308B和2308C。在一個這樣的實施例中，如同所描述的，淺的電介質插塞2308A係在約等於基板2304內之半導體鰭部2302之深度的深度處，而一對深的電介質插塞2308B和2308C係在約在基板2304內之半導體鰭部2302的深度之下的深度處。 In another aspect, the depth of individual dielectric plugs may vary within a semiconductor structure or within a framework formed on a common substrate. As an example, FIG. 23A shows a cross-sectional view of another semiconductor structure having fin-end stress-inducing features according to another embodiment of the present invention. picture. Referring to FIG. 23A, a shallow dielectric plug 2308A is included along with a pair of deep dielectric plugs 2308B and 2308C. In one such embodiment, shallow dielectric plug 2308A is at a depth approximately equal to the depth of semiconductor fin 2302 within substrate 2304, while a pair of deep dielectric plugs 2308B and 2308C are at a depth as depicted. At a depth approximately below the depth of the semiconductor fin 2302 within the substrate 2304 .

再次參照圖23A，此一配置可以致能在蝕刻更深入基板2304內之溝槽中之鰭部修整隔離(FTI)裝置的應力放大，以便提供相鄰鰭部2302之間的隔離。此一方法可以被施行來增加晶片上之電晶體的密度。在一實施例中，因為應力轉移發生在鰭部和電晶體下面的基板或井兩者中，所以在電晶體上由插塞填充所誘發的應力效應被放大於FTI電晶體中。 Referring again to FIG. 23A , such a configuration may enable stress amplification of fin trim isolation (FTI) devices etched deeper into the trenches into the substrate 2304 to provide isolation between adjacent fins 2302 . This approach can be implemented to increase the density of transistors on a wafer. In one embodiment, the stress effects induced by plug fill on the transistor are amplified in the FTI transistor because stress transfer occurs both in the fin and in the substrate or well below the transistor.

在另一態樣中，包含在電介質插塞中之伸張應力誘發氧化物層的寬度或量可以改變於半導體結構之內或者在形成於共同基板上的架構之內，例如，視該裝置為PMOS裝置或NMOS裝置而定。作為一範例，圖23B繪示依據本發明的另一實施例，具有鰭部末端應力誘發特徵之另一半導體結構的剖面視圖。參照圖23B，在一特別的實施例中，NMOS裝置比相對應的PMOS裝置包含相對更多的伸張應力誘發氧化物層2350。 In another aspect, the width or amount of the tensile stress-inducing oxide layer included in the dielectric plug can be varied within the semiconductor structure or within the framework formed on a common substrate, e.g., considering the device as a PMOS device or NMOS device. As an example, FIG. 23B shows a cross-sectional view of another semiconductor structure with fin end stress inducing features according to another embodiment of the present invention. Referring to FIG. 23B, in a particular embodiment, an NMOS device includes relatively more tensile stress inducing oxide layer 2350 than a corresponding PMOS device.

再次參照圖23B，在一實施例中，差異化的插塞填充被施行來誘發適當的應力於NMOS和PMOS中。例如，NMOS插塞2308D和2308E比PMOS插塞2308F和 2308G具有伸張應力誘發氧化物層2350之更大的體積和更大的寬度。插塞填充可以被圖案化來誘發不同的應力於NMOS和PMOS裝置中。例如，光刻圖案化可以被用來打開PMOS裝置(例如，加寬PMOS裝置的電介質插塞溝槽)，在該點，不同的填充選項可以被實施來使NMOS對PMOS裝置中的插塞填充差異化。在一代表性實施例中，減少PMOS裝置上插塞中之流動性氧化物的體積可以減少誘發出的伸張應力。在一個這樣的實施例中，壓縮應力可能主導，例如，從壓縮性應力源極和汲極區域。在其他的實施例中，不同的插塞襯墊或不同的填充材料的使用提供可調諧的應力控制。 Referring again to FIG. 23B , in one embodiment, differentiated plug fill is performed to induce proper stress in NMOS and PMOS. For example, NMOS plugs 2308D and 2308E are more efficient than PMOS plugs 2308F and 2308G has a larger volume and a larger width of the tensile stress inducing oxide layer 2350 . The plug fill can be patterned to induce different stresses in NMOS and PMOS devices. For example, photolithographic patterning can be used to open the PMOS device (e.g., widen the dielectric plug trenches of the PMOS device), at which point different fill options can be implemented to make the plug fill difference in NMOS vs. PMOS devices change. In a representative embodiment, reducing the volume of fluid oxide in a plug on a PMOS device reduces induced tensile stress. In one such embodiment, compressive stress may dominate, for example, from compressive stress source and drain regions. In other embodiments, the use of different plug liners or different fill materials provides tunable stress control.

如上所述，可以領會到多晶插塞應力效應可以有利於NMOS電晶體(例如，伸張通道應力)和PMOS電晶體(例如，壓縮通道應力)兩者。依據本發明的一實施例，半導體鰭部為單軸應力的半導體鰭部。該單軸應力的半導體鰭部可以用伸張應力或者用壓縮應力來施以單軸應力。例如，圖24A繪示依據本發明的一或更多個實施例，具有伸張單軸應力之鰭部的有角度視圖，而圖24B繪示依據本發明的一或更多個實施例，具有壓縮單軸應力之鰭部之有角度的視圖。 As noted above, it can be appreciated that polyplug stress effects can benefit both NMOS transistors (eg, tensile channel stress) and PMOS transistors (eg, compressive channel stress). According to an embodiment of the present invention, the semiconductor fins are uniaxially stressed semiconductor fins. The uniaxially stressed semiconductor fin may be uniaxially stressed with tensile stress or with compressive stress. For example, Figure 24A shows an angled view of a fin with tensile uniaxial stress in accordance with one or more embodiments of the present invention, while Figure 24B shows a fin with compressive stress in accordance with one or more embodiments of the present invention. Angled view of the fin under uniaxial stress.

參照圖24A，半導體鰭部2400具有分離的通道區域(C)設置於其中。源極區域(S)和汲極區域(D)係設置在半導體鰭部2400中，於通道區域(C)的任一側上。半導體鰭部2400之分離的通道區域沿著單軸壓縮應力的方向 (箭頭指向彼此遠離而且朝向末端2402和2404)具有電流流動方向，從源極區域(S)到汲極區域(D)。 Referring to FIG. 24A , a semiconductor fin 2400 has a separate channel region (C) disposed therein. A source region (S) and a drain region (D) are disposed in the semiconductor fin 2400 on either side of the channel region (C). The isolated channel regions of semiconductor fin 2400 are along the direction of uniaxial compressive stress (arrows pointing away from each other and towards ends 2402 and 2404 ) has a current flow direction, from source region (S) to drain region (D).

參照圖24B，半導體鰭部2450具有分離的通道區域(C)設置於其中。源極區域(S)和汲極區域(D)係設置在半導體鰭部2450中，於通道區域(C)的任一側上。半導體鰭部2450之分離的通道區域沿著單軸壓縮應力的方向(箭頭指向彼此而且從末端2452和2454開始)具有電流流動方向，從源極區域(S)到汲極區域(D)。因此，本文中所述的實施例可以被施行來改善電晶體遷移率和驅動電流，允許更快速實施的電路和晶片。 Referring to FIG. 24B , the semiconductor fin 2450 has a separate channel region (C) disposed therein. A source region (S) and a drain region (D) are disposed in the semiconductor fin 2450 on either side of the channel region (C). The separated channel regions of semiconductor fin 2450 have a current flow direction, from source region (S) to drain region (D), along the direction of uniaxial compressive stress (arrows pointing toward each other and from ends 2452 and 2454 ). Accordingly, the embodiments described herein can be implemented to improve transistor mobility and drive current, allowing for more rapidly implemented circuits and chips.

在另一態樣中，在做成閘極線切割部(多晶切割部)與做成鰭部修整隔離(FTI)局部鰭部切割部的位置之間可能有一種關係。在一實施例中，FTI局部鰭部切割部被做成於僅僅在做成多晶切割部的位置處。但是，在一個這樣的實施例中，FTI切割部不需要被做成於做成多晶切割部的每一個位置處。 In another aspect, there may be a relationship between where the gate line cuts (poly cuts) are made and where the fin trim isolation (FTI) local fin cuts are made. In one embodiment, FTI local fin cuts are made only where poly cuts are made. However, in one such embodiment, an FTI cutout need not be made at every location where a polycrystalline cutout is made.

圖25A及25B繪示依據本發明的一實施例，代表使具有單閘極間隙之鰭部圖案化用以形成局部隔離結構於選擇閘極線切割位置中的方法中之各種操作的平面視圖。 25A and 25B illustrate plan views representing various operations in a method of patterning a fin with a single gate gap for forming local isolation structures in select gate line cut locations in accordance with an embodiment of the present invention.

參照圖25A，製造積體電路結構的方法包含形成複數個鰭部2502，該複數個鰭部2502之個別的一些沿著第一方向2504具有最長的尺寸。複數個閘極結構2506係在該複數個鰭部2502之上，該等閘極結構2506之個別的一 些沿著與第一方向2504正交的第二方向2508具有最長的尺寸。在一實施例中，該等閘極結構2506為犧牲或假性閘極線，例如，由多晶矽所製成。在一個實施例中，該複數個鰭部2502為矽鰭部並且與下面的矽基板的一部分係連續的。 Referring to FIG. 25A , a method of fabricating an integrated circuit structure includes forming a plurality of fins 2502 , individual ones of the plurality of fins 2502 have a longest dimension along a first direction 2504 . A plurality of gate structures 2506 are over the plurality of fins 2502, an individual one of the gate structures 2506 Some have the longest dimension along a second direction 2508 that is orthogonal to the first direction 2504. In one embodiment, the gate structures 2506 are sacrificial or dummy gate lines, eg, made of polysilicon. In one embodiment, the plurality of fins 2502 are silicon fins and are continuous with a portion of the underlying silicon substrate.

再次參照圖25A，電介質材料結構2510被形成在複數個閘極結構2506之相鄰的一些閘極結構之間。該複數個閘極結構2506之兩個的部位2512和2513被去除以使該複數個鰭部2502之各者的部位暴露出。在一實施例中，去除該複數個閘極結構2506之兩個的部位2512和2513涉及使用比該等閘極結構2506之兩個部位2510和2513的寬度更寬的光刻窗口。該複數個鰭部2502之各者在位置2512的露出部位被去除而形成切割區域2520。在一實施例中，使用乾式或電漿蝕刻製程來去除該複數個鰭部2502之各者的露出部位。但是，該複數個鰭部2502之各者在位置2513的露出部位被遮蔽而未被去除。在一實施例中，區域2512/2520代表多晶切割部和FTI局部鰭部切割部兩者。但是，位置2513僅代表多晶切割部。 Referring again to FIG. 25A , a dielectric material structure 2510 is formed between adjacent ones of the plurality of gate structures 2506 . Portions 2512 and 2513 of two of the plurality of gate structures 2506 are removed to expose portions of each of the plurality of fins 2502 . In one embodiment, removing the portions 2512 and 2513 of the plurality of gate structures 2506 involves using a lithographic window wider than the width of the two portions 2510 and 2513 of the gate structures 2506 . The exposed portion of each of the plurality of fins 2502 at location 2512 is removed to form a cut region 2520 . In one embodiment, a dry or plasma etch process is used to remove exposed portions of each of the plurality of fins 2502 . However, the exposed portion of each of the plurality of fins 2502 at location 2513 is masked and not removed. In one embodiment, regions 2512/2520 represent both poly cuts and FTI local fin cuts. However, location 2513 represents only the polycrystalline cut.

參照圖25B，多晶切割部和FTI局部鰭部切割部的位置2512/2520以及多晶切割部的位置2513係用諸如電介質插塞的絕緣結構2530來予以填充。”多晶切割部”和”插塞”結構的代表性絕緣結構被說明於下。 Referring to FIG. 25B , poly cut and FTI local fin cut locations 2512 / 2520 and poly cut location 2513 are filled with insulating structures 2530 such as dielectric plugs. Representative insulating structures of "poly cut" and "plug" structures are described below.

圖26A到26C繪示依據本發明的一實施例，針對圖25B之結構的各種區域，關於用於多晶切割部和FTI 局部鰭部切割部以及僅用於多晶切割部之位置的電介質插塞的各種可能性的剖面視圖。 26A to 26C illustrate various regions for the structure of FIG. 25B , with respect to polycrystalline cutouts and FTIs, in accordance with an embodiment of the present invention. Cross-sectional views of various possibilities for partial fin cuts and dielectric plugs only at the location of the poly cuts.

參照圖26A，電介質插塞2530在位置2513之部位2600A的剖面視圖係顯示沿著圖25B之結構的a到a’軸線。電介質插塞2530的部位2600A被顯示係在未被切割的鰭部2502上且在電介質材料結構2510之間。 Referring to FIG. 26A, a cross-sectional view of a portion 2600A of a dielectric plug 2530 at location 2513 is shown along the a to a' axis of the structure of FIG. 25B. Portion 2600A of dielectric plug 2530 is shown tied over uncut fin 2502 and between dielectric material structures 2510 .

參照圖26B，電介質插塞2530在位置2512之部位2600B的剖面視圖係顯示沿著圖25B之結構的b到b’軸線。電介質插塞2530的部位2600B被顯示係在被切割的鰭部位置2520上且在電介質材料結構2510之間。 Referring to FIG. 26B, a cross-sectional view of a portion 2600B of a dielectric plug 2530 at location 2512 is shown along the b to b' axis of the structure of FIG. 25B. Portion 2600B of dielectric plug 2530 is shown tied over cut fin location 2520 and between dielectric material structures 2510 .

參照圖26C，電介質插塞2530在位置2512之部位2600C的剖面視圖係顯示沿著圖25B之結構的c到c’軸線。電介質插塞2530的部位2600C被顯示係在鰭部2502之間的溝槽隔離結構2602上且在電介質材料結構2510之間。在一實施例中，其範例被說明於上，溝槽隔離結構2602包含第一絕緣層2602A、第二絕緣層2602B、以及第二絕緣層2602B上的絕緣填充材料2602C。 Referring to FIG. 26C, a cross-sectional view of a portion 2600C of a dielectric plug 2530 at location 2512 is shown along the c to c' axis of the structure of FIG. 25B. Portion 2600C of dielectric plug 2530 is shown tied over trench isolation structure 2602 between fins 2502 and between dielectric material structures 2510 . In one embodiment, an example of which is described above, the trench isolation structure 2602 includes a first insulating layer 2602A, a second insulating layer 2602B, and an insulating fill material 2602C on the second insulating layer 2602B.

共同地參照圖25A,25B和26A到26C，依據本發明的一實施例，製造積體電路結構的方法包含形成複數個鰭部，該複數個鰭部之個別的一些沿著第一方向具有最長的尺寸。複數個閘極結構係形成在該複數個鰭部之上，該等閘極結構之個別的一些係沿著與第一方向正交的第二方向。電介質材料結構被形成在複數個閘極結構之相鄰的一些閘極結構之間。該複數個閘極結構之第一個的部位被 去除以使該複數個鰭部之各者的第一部位暴露出。該複數個閘極結構之第二個的部位被去除以使該複數個鰭部之各者的第二部位暴露出。該複數個鰭部之各者之露出的第一部位被去除，但是該複數個鰭部之各者之露出的第二部位未被去除。第一絕緣結構被形成在該複數個鰭部之被去除的第一部位的位置中。第二絕緣結構被形成在該複數個閘極結構之第二個的去除部位的位置中。 Referring collectively to FIGS. 25A, 25B and 26A to 26C, according to an embodiment of the present invention, a method of fabricating an integrated circuit structure includes forming a plurality of fins, individual ones of the plurality of fins having a longest length along a first direction. size of. A plurality of gate structures are formed over the plurality of fins, individual ones of the gate structures are along a second direction orthogonal to the first direction. The dielectric material structure is formed between adjacent gate structures of the plurality of gate structures. The portion of the first of the plurality of gate structures is Removing to expose a first portion of each of the plurality of fins. A portion of a second one of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed. A first insulating structure is formed in the location of the removed first portion of the plurality of fins. A second insulating structure is formed in the location of the removed portion of a second one of the plurality of gate structures.

在一實施例中，去除該複數個閘極結構之第一個和第二個的部位涉及使用比該複數個閘極結構之第一個和第二個部位之各者的寬度更寬的光刻窗口。在一實施例中，去除該複數個鰭部各者之露出的第一部位涉及蝕刻至比該複數個鰭部之高度更少的深度。在一這樣的實施例中，該深度大於複數個鰭部中之源極或汲極區域的深度。在一個這樣的實施例中，該深度大於複數個鰭部中之源極或汲極區域的深度。在一個實施例中，該複數個鰭部包含矽並且與矽基板的一部分係連續的。 In one embodiment, removing the first and second portions of the plurality of gate structures involves using a light beam wider than the width of each of the first and second portions of the plurality of gate structures. engraved window. In one embodiment, removing the exposed first portion of each of the plurality of fins involves etching to a depth that is less than a height of the plurality of fins. In one such embodiment, the depth is greater than the depth of the source or drain regions in the plurality of fins. In one such embodiment, the depth is greater than the depth of the source or drain regions in the plurality of fins. In one embodiment, the plurality of fins comprise silicon and are continuous with a portion of the silicon substrate.

共同地參照圖16A,25A,25B和26A到26C，依據本發明的另一實施例，積體電路結構包含鰭部(包含矽)，該鰭部沿著第一方向具有最長的尺寸。隔離結構係在該鰭部的上部部位之上，該隔離結構沿著第一方向具有中心。第一閘極結構係在鰭部的上部部位之上，該第一閘極結構沿著與第一方向正交的第二方向具有最長的尺寸。第一閘極結構的中心沿著第一方向而與隔離結構的中心間隔開一間距。第二閘極結構係在鰭部的上部部位之上，第 二閘極結構沿著第二方向具有最長的尺寸。第二閘極結構的中心沿著第一方向而與第一閘極結構的中心間隔開一間距。第三閘極結構係在鰭部之與隔離結構從第一和第二閘極結構開始的一側相對立的上部部位之上，第三閘極結構沿著第二方向具有最長的尺寸。第三閘極結構的中心沿著第一方向而與隔離結構的中心間隔開一間距。 Referring collectively to FIGS. 16A, 25A, 25B, and 26A-26C, in accordance with another embodiment of the present invention, an integrated circuit structure includes a fin (including silicon) having a longest dimension along a first direction. An isolation structure is tied over the upper portion of the fin, the isolation structure having a center along a first direction. A first gate structure is tied over the upper portion of the fin, the first gate structure having a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is spaced apart from the center of the isolation structure by a distance along the first direction. The second gate structure is tied over the upper portion of the fin, the first The two-gate structure has the longest dimension along the second direction. The center of the second gate structure is spaced apart from the center of the first gate structure by a distance along the first direction. A third gate structure is attached to an upper portion of the fin opposite a side of the isolation structure from the first and second gate structures, the third gate structure having a longest dimension along the second direction. The center of the third gate structure is spaced apart from the center of the isolation structure by a distance along the first direction.

在一個實施例中，第一閘極結構、第二閘極結構與第三閘極結構之各者包含在高k閘極電介質層的側壁上並且在高k閘極電介質層的側壁之間的閘極結構。在一個這樣的實施例中，第一閘極結構、第二閘極結構與第三閘極結構之各者另包含在閘極電極上以及在高k閘極電介質層的側壁上的絕緣蓋部。 In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure are included on the sidewalls of the high-k gate dielectric layer and between the sidewalls of the high-k gate dielectric layer gate structure. In one such embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating cap on the gate electrode and on sidewalls of the high-k gate dielectric layer .

在一個實施例中，第一磊晶半導體區域係在鰭部之介於第一閘極結構與隔離結構之間的上部部位上。第二磊晶半導體區域係在鰭部之介於第一閘極結構與第二閘極結構之間的上部部位上。第三磊晶半導體區域係在鰭部之介於第三閘極結構與隔離結構之間的上部部位上。在一個這樣的實施例中，第一、第二及第三磊晶半導體區域包含矽和鍺。在另一個這樣的實施例中，第一、第二及第三磊晶半導體區域包含矽。 In one embodiment, the first epitaxial semiconductor region is on an upper portion of the fin between the first gate structure and the isolation structure. The second epitaxial semiconductor region is on an upper portion of the fin between the first gate structure and the second gate structure. The third epitaxial semiconductor region is on an upper portion of the fin between the third gate structure and the isolation structure. In one such embodiment, the first, second and third epitaxial semiconductor regions comprise silicon and germanium. In another of these embodiments, the first, second and third epitaxial semiconductor regions comprise silicon.

共同地參照圖16A,25A,25B和26A到26C，依據本發明的另一實施例，積體電路結構包含淺溝槽隔離(STI)結構在一對半導體鰭部之間，該STI結構沿著第一方向具有最長的尺寸。隔離結構係在該STI結構上，該隔離 結構沿著第一方向具有中心。第一閘極結構係在該STI結構上，該第一閘極結構沿著與第一方向正交的第二方向具有最長的尺寸。第一閘極結構的中心沿著第一方向而與隔離結構的中心間隔開一間距。第二閘極結構係在該STI結構上，第二閘極結構沿著第二方向具有最長的尺寸。第二閘極結構的中心沿著第一方向而與第一閘極結構的中心間隔開一間距。第三閘極結構係在該STI結構上，與隔離結構從第一和第二閘極結構開始的一側相對立，第三閘極結構沿著第二方向具有最長的尺寸。第三閘極結構的中心沿著第一方向而與隔離結構的中心間隔開一間距。 16A, 25A, 25B and 26A to 26C collectively, according to another embodiment of the present invention, the integrated circuit structure includes a shallow trench isolation (STI) structure between a pair of semiconductor fins, the STI structure along The first direction has the longest dimension. The isolation structure is tied to the STI structure, the isolation The structure has a center along the first direction. A first gate structure is attached to the STI structure, the first gate structure having a longest dimension along a second direction orthogonal to the first direction. The center of the first gate structure is spaced apart from the center of the isolation structure by a distance along the first direction. A second gate structure is attached to the STI structure, the second gate structure having a longest dimension along a second direction. The center of the second gate structure is spaced apart from the center of the first gate structure by a distance along the first direction. A third gate structure is attached to the STI structure opposite the side of the isolation structure from the first and second gate structures, the third gate structure having a longest dimension along the second direction. The center of the third gate structure is spaced apart from the center of the isolation structure by a distance along the first direction.

在一個實施例中，第一閘極結構、第二閘極結構和第三閘極結構之各者包含在高k閘極電介質層的側壁上並且在高k閘極電介質層的側壁之間的閘極結構。在一個這樣的實施例中，第一閘極結構、第二閘極結構與第三閘極結構之各者另包含在閘極電極上以及在高k閘極電介質層的側壁上的絕緣蓋部。在一個實施例中，該一對半導體鰭部為一對矽鰭部。 In one embodiment, each of the first gate structure, the second gate structure, and the third gate structure are included on the sidewalls of the high-k gate dielectric layer and between the sidewalls of the high-k gate dielectric layer gate structure. In one such embodiment, each of the first gate structure, the second gate structure, and the third gate structure further includes an insulating cap on the gate electrode and on sidewalls of the high-k gate dielectric layer . In one embodiment, the pair of semiconductor fins is a pair of silicon fins.

在另一態樣中，多晶切割部和FTI局部鰭部切割部一起或者是僅多晶切割部，用來填充切割部位置的絕緣結構或電介質插塞可以橫向地延伸進對應之切割的閘極線的電介質間隔層中，或者甚至延伸超出對應之切割的閘極線的電介質間隔層外。 In another aspect, poly cuts and FTI local fin cuts together or only poly cuts, the insulating structures or dielectric plugs used to fill the cut locations may extend laterally into the corresponding cut gates. In the dielectric spacer layer of the gate line, or even extending beyond the dielectric spacer layer of the corresponding cut gate line.

在溝槽接觸(trench contact)形狀不受多晶切割部電介質插塞所影響的第一範例中，圖27A繪示依據本 發明的一實施例，具有帶有延伸進閘極線之電介質間隔層中的電介質插塞之閘極線切割部的積體電路結構的平面視圖和對應的剖面視圖。 In a first example where the shape of the trench contact is not affected by the poly cut dielectric plug, FIG. 27A shows A plan view and corresponding cross-sectional view of an integrated circuit structure having a gate line cutout with a dielectric plug extending into a dielectric spacer layer of the gate line, in accordance with an embodiment of the invention.

參照圖27A，積體電路結構2700A包含沿著第一方向2703具有最長尺寸的第一矽鰭部2702。第二矽鰭部2704沿著第一方向2703具有最長的尺寸。絕緣器材料2706係在第一矽鰭部2702與第二矽鰭部2704之間。閘極線2708沿著第二方向2709係在第一矽鰭部2702之上並且在第二矽鰭部2704之上，第二方向2709與第一方向2703正交。該閘極線2708具有第一側邊2708A和第二側邊2708B，並且具有第一末端2708C和第二末端2708D。該閘極線2708在絕緣器材料2706之上，在閘極線2708的第一末端2708C與第二末端2708D之間具有中斷2710。該中斷2710被電介質插塞2712所填充。 Referring to FIG. 27A , an integrated circuit structure 2700A includes a first silicon fin 2702 having a longest dimension along a first direction 2703 . The second silicon fin 2704 has the longest dimension along the first direction 2703 . An insulator material 2706 is interposed between the first silicon fin 2702 and the second silicon fin 2704 . The gate line 2708 is tied over the first silicon fin portion 2702 and over the second silicon fin portion 2704 along a second direction 2709 that is orthogonal to the first direction 2703 . The gate line 2708 has a first side 2708A and a second side 2708B, and has a first end 2708C and a second end 2708D. The gate line 2708 is above the insulator material 2706 with a break 2710 between a first end 2708C and a second end 2708D of the gate line 2708 . The discontinuity 2710 is filled with a dielectric plug 2712 .

溝槽接觸2714沿著第二方向2709於閘極線2708的第一側邊2708A係在第一矽鰭部2702之上並且在第二矽鰭部2704之上。溝槽接觸2714在絕緣器材料2706之上於橫向鄰接於電介質插塞2712的位置2715處係連續的。電介質間隔層2716係橫向地在溝槽接觸2714與閘極線2708的第一側邊2708A之間。電介質間隔層2716沿著閘極線2708的第一側邊2708A和電介質插塞2712係連續的。電介質間隔層2716在橫向鄰接於電介質插塞2712的寬度(W2)比在橫向鄰接於閘極線2708之第一側邊2708A的寬度(W1)更薄。 The trench contact 2714 is over the first silicon fin 2702 and over the second silicon fin 2704 along the second direction 2709 at the first side 2708A of the gate line 2708 . Trench contact 2714 is continuous above insulator material 2706 at location 2715 laterally adjacent to dielectric plug 2712 . Dielectric spacer 2716 is laterally between trench contact 2714 and first side 2708A of gate line 2708 . The dielectric spacer 2716 is continuous along the first side 2708A of the gate line 2708 and the dielectric plug 2712 . The width ( W2 ) of the dielectric spacer layer 2716 laterally adjacent to the dielectric plug 2712 is thinner than the width ( W1 ) laterally adjacent to the first side 2708A of the gate line 2708 .

在一個實施例中，第二溝槽接觸2718沿著第 二方向2709於閘極線2708的第二側邊2708B係在第一矽鰭部2702之上並且在第二矽鰭部2704之上。第二溝槽接觸2718在絕緣器材料2706之上於橫向鄰接於電介質插塞2712的位置2719處係連續的。在一個這樣的實施例中，第二電介質間隔層2720係橫向地在第二溝槽接觸2718與閘極線2708的第二側邊2708B之間。第二電介質間隔層2720沿著閘極線2708的第二側邊2708B和電介質插塞2712係連續的。第二電介質間隔層在橫向鄰接於電介質插塞2712的寬度比在橫向鄰接於閘極線2708之第二側邊2708B的寬度更薄。 In one embodiment, the second trench contact 2718 is along the Two directions 2709 are on the second side 2708B of the gate line 2708 over the first silicon fin 2702 and over the second silicon fin 2704 . The second trench contact 2718 is continuous above the insulator material 2706 at a location 2719 laterally adjacent to the dielectric plug 2712 . In one such embodiment, the second dielectric spacer 2720 is laterally between the second trench contact 2718 and the second side 2708B of the gate line 2708 . The second dielectric spacer 2720 is continuous along the second side 2708B of the gate line 2708 and the dielectric plug 2712 . The width of the second dielectric spacer laterally adjacent to the dielectric plug 2712 is thinner than the width of the second side 2708B laterally adjacent to the gate line 2708 .

在一個實施例中，閘極線2708包含高k閘極電介質層2722、閘極電極2724、和電介質蓋層2726。在一個實施例中，電介質插塞2712包含與電介質間隔層2714相同但是與電介質間隔層2714分離的材料。在一個實施例中，電介質插塞2712包含與電介質間隔層2714不同的材料。 In one embodiment, gate line 2708 includes high-k gate dielectric layer 2722 , gate electrode 2724 , and dielectric capping layer 2726 . In one embodiment, dielectric plug 2712 comprises the same material as, but separate from, dielectric spacer layer 2714 . In one embodiment, the dielectric plug 2712 comprises a different material than the dielectric spacer layer 2714 .

在溝槽接觸形狀不受多晶切割部電介質插塞所影響的第二範例中，圖27B繪示依據本發明的另一實施例，具有帶有延伸出閘極線之電介質間隔層外的電介質插塞之閘極線切割部的積體電路結構的平面視圖和對應的剖面視圖。 In a second example where the trench contact shape is not affected by the poly cut dielectric plug, FIG. 27B shows another embodiment according to the present invention having a dielectric with a dielectric spacer extending beyond the gate line. Plan view and corresponding cross-sectional view of the integrated circuit structure of the gate line cut portion of the plug.

參照圖27B，積體電路結構2700B包含沿著第一方向2753具有最長尺寸的第一矽鰭部2752。第二矽鰭部2754沿著第一方向2753具有最長的尺寸。絕緣材料2756 係在第一矽鰭部2752與第二矽鰭部2754之間。閘極線2758沿著第二方向2759係在第一矽鰭部2752之上並且在第二矽鰭部2754之上，第二方向2759與第一方向2753正交。該閘極線2758具有第一側邊2758A和第二側邊2758B，並且具有第一末端2758C和第二末端2758D。該閘極線2758在絕緣器材料2756之上，在閘極線2758的第一末端2758C與第二末端2758D之間具有中斷2760。該中斷2760被電介質插塞2762所填充。 Referring to FIG. 27B , the integrated circuit structure 2700B includes a first silicon fin 2752 having a longest dimension along a first direction 2753 . The second silicon fin 2754 has the longest dimension along the first direction 2753 . Insulating material 2756 It is tied between the first silicon fin 2752 and the second silicon fin 2754 . The gate line 2758 is tied over the first silicon fin portion 2752 and over the second silicon fin portion 2754 along a second direction 2759 that is orthogonal to the first direction 2753 . The gate line 2758 has a first side 2758A and a second side 2758B, and has a first end 2758C and a second end 2758D. The gate line 2758 is above the insulator material 2756 with a discontinuity 2760 between a first end 2758C and a second end 2758D of the gate line 2758 . The interruption 2760 is filled with a dielectric plug 2762 .

溝槽接觸2764沿著第二方向2759於閘極線2758的第一側邊2758A係在第一矽鰭部2752之上並且在第二矽鰭部2754之上。溝槽接觸2764在絕緣器材料2756之上於橫向鄰接於電介質插塞2762的位置2765處係連續的。電介質間隔層2766係橫向地在溝槽接觸2764與閘極線2758的第一側邊2758A之間。電介質間隔層2766係沿著閘極線2758的第一側邊2758A但是不沿著電介質插塞2762，其導致不連續的電介質間隔層2766。溝槽接觸2764在橫向鄰接於電介質插塞2762的寬度(W1)比在橫向鄰接於電介質間隔層2766的寬度(W2)更薄。 Trench contact 2764 is over first silicon fin 2752 and over second silicon fin 2754 along second direction 2759 at first side 2758A of gate line 2758 . Trench contact 2764 is continuous above insulator material 2756 at a location 2765 laterally adjacent to dielectric plug 2762 . Dielectric spacer 2766 is laterally between trench contact 2764 and first side 2758A of gate line 2758 . Dielectric spacer 2766 is along first side 2758A of gate line 2758 but not along dielectric plug 2762 , which results in a discontinuous dielectric spacer 2766 . The width ( W1 ) of trench contact 2764 laterally adjacent to dielectric plug 2762 is thinner than the width ( W2 ) laterally adjacent to dielectric spacer 2766 .

在一個實施例中，第二溝槽接觸2768沿著第二方向2759於閘極線2758的第二側邊2758B係在第一矽鰭部2752之上並且在第二矽鰭部2754之上。第二溝槽接觸2768在絕緣器材料2756之上於橫向鄰接於電介質插塞2762的位置2769處係連續的。在一個這樣的實施例中，第二電介質間隔層2770係橫向地在第二溝槽接觸2768與閘極線 2758的第二側邊2758B之間。第二電介質間隔層2770沿著閘極線2758的第二側邊2508B但是不沿著電介質插塞2762，其導致不連續的電介質間隔層2770。第二溝槽接觸2768在橫向鄰接於電介質插塞2762的寬度比在橫向鄰接於電介質間隔層2770的寬度更薄。 In one embodiment, the second trench contact 2768 is over the first silicon fin 2752 and over the second silicon fin 2754 along the second direction 2759 at the second side 2758B of the gate line 2758 . The second trench contact 2768 is continuous above the insulator material 2756 at a location 2769 laterally adjacent to the dielectric plug 2762 . In one such embodiment, the second dielectric spacer 2770 is laterally between the second trench contact 2768 and the gate line between second sides 2758B of 2758 . The second dielectric spacer 2770 is along the second side 2508B of the gate line 2758 but not along the dielectric plug 2762 , which results in a discontinuous dielectric spacer 2770 . The width of second trench contact 2768 laterally adjacent to dielectric plug 2762 is thinner than the width laterally adjacent to dielectric spacer layer 2770 .

在一個實施例中，閘極線2758包含高k閘極電介質層2772、閘極電極2774、和電介質蓋層2776。在一個實施例中，電介質插塞2762包含與電介質間隔層2764相同但是與電介質間隔層2764分離的材料。在一個實施例中，電介質插塞2762包含與電介質間隔層2764不同的材料。 In one embodiment, gate line 2758 includes a high-k gate dielectric layer 2772 , a gate electrode 2774 , and a dielectric capping layer 2776 . In one embodiment, dielectric plug 2762 comprises the same material as, but separate from, dielectric spacer layer 2764 . In one embodiment, dielectric plug 2762 comprises a different material than dielectric spacer layer 2764 .

在用於多晶切割部位置的電介質插塞從插塞的頂部到插塞的底部逐漸變細的第三範例中，圖28A到28F繪示依據本發明的另一實施例，在製造積體電路結構之方法中各種操作的剖面視圖，該積體電路結構具有帶有電介質插塞之閘極線切割部，該電介質插塞具有延伸出閘極線之電介質間隔層外的上部部位和延伸進閘極線之電介質間隔層中的下部部位。 In a third example where the dielectric plug tapers from the top of the plug to the bottom of the plug for the location of the poly cut, FIGS. Cross-sectional views of various operations in a method of circuit structure having a gate line cutout with a dielectric plug having an upper portion extending beyond a dielectric spacer layer of a gate line and extending into The lower part of the dielectric spacer layer of the gate line.

參照圖28A，複數條閘極線2802被形成在結構2804之上，諸如在半導體鰭部之間的溝槽隔離結構之上。在一個實施例中，該等閘極線2802之各者為犧牲或假性閘極線，例如，具有假性閘極電極2806和電介質蓋部2808。此種犧牲或假性閘極線的部位稍後在置換閘極製程中可以被取代，例如，在下面所述的電介質插塞形成之 後。電介質間隔層2810係沿著該等閘極線2802的側壁。諸如電介質間層的電介質材料2812係在該等閘極線2802之間。遮罩2814被形成而且被光刻圖案化以使該等閘極線2802之其中一個的部位暴露出。 Referring to FIG. 28A, a plurality of gate lines 2802 are formed over a structure 2804, such as over a trench isolation structure between semiconductor fins. In one embodiment, each of the gate lines 2802 is a sacrificial or dummy gate line, eg, with a dummy gate electrode 2806 and a dielectric cap 2808 . Such sacrificial or dummy gate line locations can be replaced later in the replacement gate process, for example, after dielectric plug formation as described below. back. Dielectric spacers 2810 are along the sidewalls of the gate lines 2802 . A dielectric material 2812 such as a dielectric interlayer is tied between the gate lines 2802 . A mask 2814 is formed and photolithographically patterned to expose a portion of one of the gate lines 2802 .

參照圖28B，隨著遮罩2814在適當的位置上，中央的閘極線2802係以蝕刻製程來予以去除。遮罩2814然後被去除。在一實施例中，蝕刻製程腐蝕被去除之閘極線2802之電介質間隔層2810的部位，形成縮減後的電介質間隔層2816。除此之外，電介質材料2812被遮罩2814所暴露出的上部部位在蝕刻製程中被腐蝕，形成腐蝕後的電介質材料部位2818。在一特別的實施例中，剩餘之假性閘極材料2820，諸如剩餘的多晶矽，仍然保留在結構中，作為未完成之蝕刻製程的加工品。 Referring to Figure 28B, with the mask 2814 in place, the central gate line 2802 is removed by an etch process. Mask 2814 is then removed. In one embodiment, the etching process etches the removed portion of the dielectric spacer 2810 of the gate line 2802 to form a reduced dielectric spacer 2816 . In addition, the upper portion of the dielectric material 2812 exposed by the mask 2814 is etched during the etching process to form an etched dielectric material portion 2818 . In a particular embodiment, remaining dummy gate material 2820, such as remaining polysilicon, remains in the structure as a artifact of an incomplete etch process.

參照圖28C，硬遮罩2822被形成在圖28B的結構之上。硬遮罩2822可以與圖28B之結構的上部部位係共形的，特別是與腐蝕後的電介質材料部位2818。 Referring to Figure 28C, a hard mask 2822 is formed over the structure of Figure 28B. The hard mask 2822 may be conformal with the upper portion of the structure of FIG. 28B , particularly with the etched dielectric material portion 2818 .

參照圖28D，剩餘之假性閘極材料2820例如以蝕刻製程來予以去除，其可以在化學上類似於用來去除該等閘極線2802之中央閘極線的蝕刻製程。在一實施例中，硬遮罩2822保護該腐蝕後的電介質材料部位2818，以免於在去除剩餘之假性閘極材料2820期間被進一步腐蝕。 Referring to FIG. 28D , the remaining dummy gate material 2820 is removed, for example, with an etch process that may be chemically similar to the etch process used to remove the central gate line of the gate lines 2802 . In one embodiment, the hard mask 2822 protects the etched dielectric material portion 2818 from further etching during removal of the remaining dummy gate material 2820 .

參照圖28E，硬遮罩2822被去除。在一個實施例中，硬遮罩2822去除，但是沒有或基本上沒有腐蝕後之電介質材料部位2818的進一步腐蝕。 Referring to Figure 28E, the hard mask 2822 is removed. In one embodiment, the hard mask 2822 is removed, but there is no or substantially no further etching of the etched dielectric material site 2818 .

參照圖28F，電介質插塞2830被形成在圖28E之結構的開口中。電介質插塞2830的上部部位係在該腐蝕後的電介質材料部位2818之上，例如，實際上超過原始的間隔層2810。電介質插塞2830的下部部位係鄰接於縮減後的電介質間隔層2816，例如，實際上深入但並未超過原始的間隔層2810。結果是，電介質插塞2830具有和圖28F中所描述之一樣的漸細外形。可以領會到，電介質插塞2830可以是由上面針對多晶切割部或FTI插塞或局部末端應力源所述之材料及製程所製造的。 Referring to Figure 28F, a dielectric plug 2830 is formed in the opening of the structure of Figure 28E. An upper portion of the dielectric plug 2830 rests above the etched dielectric material portion 2818 , eg, substantially beyond the original spacer layer 2810 . The lower portion of the dielectric plug 2830 is adjacent to the reduced dielectric spacer layer 2816 , eg, actually deep into but not beyond the original spacer layer 2810 . As a result, the dielectric plug 2830 has the same tapered profile as that depicted in FIG. 28F. It can be appreciated that the dielectric plug 2830 may be fabricated from the materials and processes described above for the polysaw or FTI plug or localized terminal stressor.

在另一態樣中，佔位件閘極結構或假性閘極結構的部位可以被保持在永久性閘極結構之下的溝槽隔離區域之上，作為在置換閘極製程期間防止溝槽隔離區域之腐蝕的保護。例如，圖29A到29C繪示依據本發明的一實施例，在永久閘極堆疊之底部部位具有剩餘之假性閘極材料之積體電路結構的平面視圖和對應的剖面視圖。 In another aspect, the site of the placeholder gate structure or the dummy gate structure may be maintained above the trench isolation region below the permanent gate structure as a means of preventing trench isolation during the replacement gate process. Corrosion protection for isolated areas. For example, FIGS. 29A-29C illustrate a plan view and corresponding cross-sectional views of an integrated circuit structure with dummy gate material remaining at the bottom portion of the permanent gate stack in accordance with one embodiment of the present invention.

參照圖29A到29C，積體電路結構包含從半導體基板2904中突出之諸如矽鰭部的鰭部2902。鰭部2902具有下鰭部部位2902B和上鰭部部位2902A。上鰭部部位2902A具有頂部2902C和側壁2902D。隔離結構2906包圍下鰭部部位2902B。隔離結構2906包含具有頂部表面2907的絕緣材料2906C。半導體材料2908係在絕緣材料2906C之頂部表面2907的部位上。半導體材料2908和鰭部2902分離。 Referring to FIGS. 29A to 29C , the integrated circuit structure includes fins 2902 , such as silicon fins, protruding from a semiconductor substrate 2904 . Fin 2902 has a lower fin location 2902B and an upper fin location 2902A. Upper fin portion 2902A has a top 2902C and sidewalls 2902D. Isolation structure 2906 surrounds lower fin portion 2902B. Isolation structure 2906 includes insulating material 2906C having top surface 2907 . Semiconductor material 2908 is located on top surface 2907 of insulating material 2906C. The semiconductor material 2908 is separated from the fin 2902 .

閘極電介質層2910係在上鰭部部位2902A的 頂部2902C之上並且橫向鄰接上鰭部部位2902A的側壁2902D。閘極電介質層2910係進一步在絕緣材料2906C之頂部表面2907部位上的半導體材料2908上。中介(intervening)之額外的閘極電介質層2911，諸如鰭部2902的氧化部位，可以在上鰭部部位2902A的頂部2902C之上的閘極電介質層2910之間並且橫向鄰接上鰭部部位2902A的側壁2902D。閘極電極2912係在上鰭部部位2902A的頂部2902C之上的閘極電介質層2910之上並且橫向鄰接上鰭部部位2902A的側壁2902D。該閘極電極2912係進一步在絕緣材料2906C之頂部表面2907部位上之半導體材料2908上的閘極電介質層2910之上。第一源極或汲極區域2916係鄰接該閘極電極2912的第一側，且第二源極或汲極區域2918係鄰接該閘極電極2912的第二側，該第二側和該第一側相對立。在一實施例中，其範例被說明於上，隔離結構2906包含第一絕緣層2906A、第二絕緣層2906B、和絕緣材料2906C。 Gate dielectric layer 2910 is attached to upper fin portion 2902A Top 2902C is above and laterally adjoins sidewall 2902D of upper fin portion 2902A. Gate dielectric layer 2910 is further on semiconductor material 2908 at the location of top surface 2907 of insulating material 2906C. An additional gate dielectric layer 2911 of intervening, such as an oxidized portion of the fin portion 2902, may be between the gate dielectric layer 2910 over the top 2902C of the upper fin portion 2902A and laterally adjacent to the top of the upper fin portion 2902A. Sidewall 2902D. Gate electrode 2912 is tied over gate dielectric layer 2910 over top 2902C of upper fin portion 2902A and laterally adjoins sidewall 2902D of upper fin portion 2902A. The gate electrode 2912 is further over the gate dielectric layer 2910 on the semiconductor material 2908 at the location of the top surface 2907 of the insulating material 2906C. A first source or drain region 2916 is adjacent to a first side of the gate electrode 2912, and a second source or drain region 2918 is adjacent to a second side of the gate electrode 2912, the second side and the first side One side is opposite. In one embodiment, examples of which are described above, the isolation structure 2906 includes a first insulating layer 2906A, a second insulating layer 2906B, and an insulating material 2906C.

在一個實施例中，在絕緣材料2906C之頂部表面2907部位上的半導體材料2908為或包含多晶矽。在一個實施例中，絕緣材料2906C的頂部表面2907具有凹陷部(concave depression)，如同所描述的，而且半導體材料2908係在該凹陷部中。在一個實施例中，隔離結構2906包含沿著絕緣材料2906C之底部和側壁的第二絕緣材料(2906A或2906B或者2906A/2906B兩者)。在一個這樣的實施例中，第二絕緣材料(2906A或2906B或者2906A/2906B 兩者)沿著絕緣材料2906C之側壁的部位具有在絕緣材料2906C之最上面的表面之上的頂部表面，如同所描述的。在一個實施例中，第二絕緣材料(2906A或2906B或者2906A/2906B兩者)的頂部表面係在半導體材料2908之最上面的表面之上或者與半導體材料2908之最上面的表面共平面。 In one embodiment, the semiconductor material 2908 on top surface 2907 of the insulating material 2906C is or includes polysilicon. In one embodiment, the top surface 2907 of the insulating material 2906C has a concave depression, as described, and the semiconductor material 2908 is tied within the depression. In one embodiment, the isolation structure 2906 includes a second insulating material (2906A or 2906B or both 2906A/2906B) along the bottom and sidewalls of the insulating material 2906C. In one such embodiment, the second insulating material (2906A or 2906B or 2906A/2906B Both) the locations along the sidewalls of the insulating material 2906C have a top surface above the uppermost surface of the insulating material 2906C, as depicted. In one embodiment, the top surface of the second insulating material (2906A or 2906B or both 2906A/2906B) is above or coplanar with the uppermost surface of the semiconductor material 2908.

在一個實施例中，在絕緣材料2906C之頂部表面2907部位上的半導體材料2908並不延伸超過該閘極電介質層2910。也就是說，從平面透視圖來看，半導體材料2908的位置被限定於由閘極堆疊2912/2910所覆蓋的區域。在一個實施例中，第一電介質間隔層2920係沿著該閘極電極2912的第一側。第二電介質間隔層2922係沿著該閘極電極2912的第二側。在一個這樣的實施例中，該閘極電介質層2910進一步沿著第一電介質間隔層2920和第二電介質間隔層2922的側壁延伸，如同圖29B中所描述的。 In one embodiment, the semiconductor material 2908 on top of the top surface 2907 of the insulating material 2906C does not extend beyond the gate dielectric layer 2910 . That is, from a plan perspective, the location of semiconductor material 2908 is limited to the area covered by gate stacks 2912/2910. In one embodiment, a first dielectric spacer layer 2920 is along the first side of the gate electrode 2912 . A second dielectric spacer layer 2922 is along the second side of the gate electrode 2912 . In one such embodiment, the gate dielectric layer 2910 further extends along the sidewalls of the first dielectric spacer layer 2920 and the second dielectric spacer layer 2922, as depicted in FIG. 29B.

在一個實施例中，閘極電極2912包含共形的導電層2912A(例如，功函數層)。在一個這樣的實施例中，功函數層2912A包含鈦和氮。在另一實施例中，功函數層2912A包含鈦、鋁、碳和氮。在一個實施例中，閘極電極2912另包含功函數層2912A之上的導電性填充金屬層2912B。在一個這樣的實施例中，導電性填充金屬層2912B包含鎢。在一特別的實施例中，導電性填充金屬層2912B包含95或更大原子百分率的鎢以及0.1到2原子百分率的氟。在一個實施例中，絕緣蓋部2924係在該閘極電極 2912上並且可以延伸於該閘極電介質層2910之上，如同圖29B中所描述的。 In one embodiment, the gate electrode 2912 includes a conformal conductive layer 2912A (eg, a work function layer). In one such embodiment, work function layer 2912A includes titanium and nitrogen. In another embodiment, work function layer 2912A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the gate electrode 2912 further includes a conductive fill metal layer 2912B on the work function layer 2912A. In one such embodiment, conductive fill metal layer 2912B includes tungsten. In a particular embodiment, conductive fill metal layer 2912B includes 95 atomic percent or greater of tungsten and 0.1 to 2 atomic percent of fluorine. In one embodiment, an insulating cap 2924 is tied to the gate electrode 2912 and may extend over the gate dielectric layer 2910, as depicted in FIG. 29B.

圖30A到30D繪示依據本發明的另一實施例，在製造積體電路結構之方法中各種操作的剖面視圖，該積體電路結構在永久閘極堆疊之底部部位具有剩餘之假性閘極材料。該透視圖顯示係沿著圖29C之結構的a到a’軸線的部位。 30A through 30D illustrate cross-sectional views of various operations in a method of fabricating an integrated circuit structure having a dummy gate remaining at the bottom portion of the permanent gate stack in accordance with another embodiment of the present invention. Material. The perspective view shows the location along the a to a' axis of the structure of Fig. 29C.

參照圖30A，製造積體電路結構之方法包含從半導體基板3002形成鰭部3000。鰭部3000具有下鰭部部位3000A和上鰭部部位3000B。上鰭部部位3000B具有頂部3000C和側壁3000D。隔離結構3004包圍下鰭部部位3000A。隔離結構3004包含具有頂部表面3005的絕緣材料3004C。佔位件閘極電極3006係在上鰭部部位3000B的頂部3000C之上並且橫向鄰接上鰭部部位3000B的側壁3000D。佔位件閘極電極3006包含半導體材料。 Referring to FIG. 30A , a method of fabricating an integrated circuit structure includes forming a fin 3000 from a semiconductor substrate 3002 . Fin 3000 has a lower fin location 3000A and an upper fin location 3000B. The upper fin portion 3000B has a top 3000C and sidewalls 3000D. Isolation structure 3004 surrounds lower fin region 3000A. The isolation structure 3004 includes an insulating material 3004C having a top surface 3005 . The placeholder gate electrode 3006 is tied over the top 3000C of the upper fin portion 3000B and laterally adjoins the sidewall 3000D of the upper fin portion 3000B. The placeholder gate electrode 3006 comprises a semiconductor material.

雖然從圖30A的透視圖中未顯示出(但是其位置係顯示在圖29C中)，第一源極或汲極區域可以被形成鄰接佔位件閘極電極3006的第一側，而且第二源極或汲極區域可以被形成鄰接佔位件閘極電極3006的第二側，該第二側和該第一側相對立。除此之外，閘極電介質間隔層可以被形成沿著佔位件閘極電極3006的側壁，而且層間電介質(ILD)層可以被形成橫向鄰接該佔位件閘極電極3006。 Although not shown from the perspective view of FIG. 30A (but its location is shown in FIG. 29C ), a first source or drain region may be formed adjacent to a first side of the placeholder gate electrode 3006, and a second A source or drain region may be formed adjacent to a second side of the placeholder gate electrode 3006, which is opposite the first side. In addition, a gate dielectric spacer layer may be formed along sidewalls of the placeholder gate electrode 3006 and an interlayer dielectric (ILD) layer may be formed laterally adjacent to the placeholder gate electrode 3006 .

在一個實施例中，佔位件閘極電極3006為或包含多晶矽。在一個實施例中，隔離結構3004之絕緣材料 3004C的頂部表面3005具有凹陷部，如同所描述的。佔位件閘極電極3006的一部位係在該凹陷部中。在一個實施例中，隔離結構3004包含沿著絕緣材料3004C之底部和側壁的第二絕緣材料(3004A或3004B或者3004A及3004B兩者)。在一個這樣的實施例中，第二絕緣材料(3004A或3004B或者3004A及3004B兩者)沿著絕緣材料3004C之側壁的部位具有在絕緣材料3004C之頂部表面3005的至少一部位之上的頂部表面。在一個實施例中，第二絕緣材料(3004A或3004B或者3004A及3004B兩者)的頂部表面係在佔位件閘極電極3006的一部位之最下面的表面之上。 In one embodiment, the placeholder gate electrode 3006 is or includes polysilicon. In one embodiment, the insulating material of the isolation structure 3004 The top surface 3005 of 3004C has a recess, as described. A portion of the placeholder gate electrode 3006 is seated in the recess. In one embodiment, isolation structure 3004 includes a second insulating material (3004A or 3004B or both 3004A and 3004B) along the bottom and sidewalls of insulating material 3004C. In one such embodiment, the second insulating material (3004A or 3004B or both 3004A and 3004B) has a top surface over at least a portion of the top surface 3005 of the insulating material 3004C along a portion of the sidewall of the insulating material 3004C . In one embodiment, the top surface of the second insulating material (3004A or 3004B or both 3004A and 3004B) is above the lowermost surface of a portion of the placeholder gate electrode 3006 .

參照圖30B，佔位件閘極電極3006從上鰭部部位3000B的頂部3000C和側壁3000D之上被蝕刻，例如，沿著圖30A的方向3008。該蝕刻製程可以被稱為置換閘極製程。在一實施例中，該蝕刻或置換閘極製程係未完成而且在隔離結構3004之絕緣材料3004C的頂部表面3005的至少一部位上留下佔位件閘極電極3006的一部位3012。 Referring to FIG. 30B , the placeholder gate electrode 3006 is etched from above the top 3000C and sidewalls 3000D of the upper fin region 3000B, eg, along direction 3008 of FIG. 30A . This etch process may be referred to as a replacement gate process. In one embodiment, the etch or replacement gate process is not completed and leaves a portion 3012 of the placeholder gate electrode 3006 on at least a portion of the top surface 3005 of the insulating material 3004C of the isolation structure 3004 .

參照圖30A和30B兩者，在一實施例中，在形成佔位件閘極電極3006之前所形成之上鰭部部位3000B的氧化部位3010被保留於該蝕刻製程期間，如同所描述的。但是，在另一實施例中，佔位件閘極電介質層被形成在形成佔位件閘極電極3006之前，而且佔位件閘極電介質層被去除於蝕刻佔位件閘極電極之後。 Referring to both FIGS. 30A and 30B , in one embodiment, the oxidized portion 3010 of the upper fin portion 3000B formed prior to the formation of the placeholder gate electrode 3006 is retained during the etch process, as described. However, in another embodiment, the placeholder gate dielectric layer is formed before the placeholder gate electrode 3006 is formed, and the placeholder gate dielectric layer is removed after the placeholder gate electrode is etched.

參照圖30C，閘極電介質層3014被形成在上鰭部部位3000B的頂部3000C之上並且橫向鄰接上鰭部部 位3000B的側壁3000D。在一個實施例中，閘極電介質層3014被形成在上鰭部部位3000B的頂部3000C之上的上鰭部部位3000B之氧化部位3010上，並且橫向鄰接上鰭部部位3000B的側壁3000D，如同所描述的。在另一實施例中，在上鰭部部位3000B的氧化部位3010被去除於蝕刻佔位件閘極電極之後的情況下，閘極電介質層3014被形成直接在上鰭部部位3000B的頂部3000C之上的上鰭部部位3000B上，並且橫向鄰接上鰭部部位3000B的側壁3000D。在任一情況下，在一實施例中，閘極電介質層3014被進一步形成在隔離結構3004之絕緣材料3004C的頂部表面3005部位上之佔位件閘極電極3006的該部位3012上。 Referring to FIG. 30C , a gate dielectric layer 3014 is formed over the top 3000C of the upper fin portion 3000B and laterally adjacent to the upper fin portion Sidewall 3000D of bit 3000B. In one embodiment, a gate dielectric layer 3014 is formed on the oxidized portion 3010 of the upper fin portion 3000B above the top portion 3000C of the upper fin portion 3000B and laterally adjacent to the sidewalls 3000D of the upper fin portion 3000B, as shown. describe. In another embodiment, where the oxidized portion 3010 of the upper fin portion 3000B is removed after etching the placeholder gate electrode, a gate dielectric layer 3014 is formed directly on top 3000C of the upper fin portion 3000B On the upper fin portion 3000B on the top, and laterally adjacent to the sidewall 3000D of the upper fin portion 3000B. In either case, in one embodiment, a gate dielectric layer 3014 is further formed on the portion 3012 of the placeholder gate electrode 3006 on the portion of the top surface 3005 of the insulating material 3004C of the isolation structure 3004 .

參照圖30D，永久性閘極電極3016被形成在上鰭部部位3000B的頂部3000C之上的閘極電介質層3014之上並且橫向鄰接上鰭部部位3000B的側壁3000D。該永久性閘極電極3016係進一步在絕緣材料3004C的頂部表面3005部位上之佔位件閘極電極3006的該部位3012的閘極電介質層3014之上。 Referring to FIG. 30D , a permanent gate electrode 3016 is formed over gate dielectric layer 3014 over top 3000C of upper fin portion 3000B and laterally adjacent sidewalls 3000D of upper fin portion 3000B. The permanent gate electrode 3016 is further over the gate dielectric layer 3014 at the portion 3012 of the placeholder gate electrode 3006 at the portion of the top surface 3005 of the insulating material 3004C.

在一個實施例中，形成永久性閘極電極3016包含形成功函數層3016A。在一個這樣的實施例中，功函數層3016A包含鈦和氮。在另一個這樣的實施例中，功函數層3016A包含鈦、鋁、碳和氮。在一個實施例中，形成永久性閘極電極3016另包含形成形成在功函數層3016A之上的導電性填充金屬層3016B。在一個這樣的實施例中，形成導電性填充金屬層3016B包含使用原子層沉積法 (ALD)以六氟化鎢(WF6)先驅物(precursor)來形成含鎢膜。在一實施例中，絕緣閘極蓋層3018被形成在該永久性閘極電極3016上。 In one embodiment, forming the permanent gate electrode 3016 includes forming the work function layer 3016A. In one such embodiment, the work function layer 3016A includes titanium and nitrogen. In another of these embodiments, the work function layer 3016A includes titanium, aluminum, carbon, and nitrogen. In one embodiment, forming the permanent gate electrode 3016 further includes forming a conductive fill metal layer 3016B formed on the work function layer 3016A. In one such embodiment, forming the conductive fill metal layer 3016B includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF 6 ) precursor. In one embodiment, an insulating gate capping layer 3018 is formed on the permanent gate electrode 3016 .

在另一態樣中，本發明的一些實施例包含在用於閘極電極之閘極電介質結構中的非晶高k層。在其他的實施例中，部分或全部結晶高k層被包含在用於閘極電極之閘極電介質結構中。在包含有部分或全部結晶高k層的一個實施例中，閘極電介質結構為鐵電(FE)閘極電介質結構。在不包含有部分或全部結晶高k層的另一實施例中，閘極電介質結構為反鐵電(AFE)閘極電介質結構。 In another aspect, some embodiments of the invention include an amorphous high-k layer in the gate dielectric structure for the gate electrode. In other embodiments, part or all of the crystalline high-k layer is included in the gate dielectric structure for the gate electrode. In one embodiment comprising a partially or fully crystalline high-k layer, the gate dielectric structure is a ferroelectric (FE) gate dielectric structure. In another embodiment that does not include a partially or fully crystalline high-k layer, the gate dielectric structure is an antiferroelectric (AFE) gate dielectric structure.

在一實施例中，在本文中說明藉由採用鐵電或反鐵電閘極氧化物來增加裝置通道中的電荷並且改善次臨界行為的方法。鐵電或反鐵電閘極氧化物可以為更高電流而增加通道電荷並且也可以做成更陡峭的導通(turn-on)行為。 In one embodiment, a method for increasing charge in a device channel and improving subthreshold behavior by employing ferroelectric or antiferroelectric gate oxides is described herein. Ferroelectric or antiferroelectric gate oxides can increase channel charge for higher currents and can also be made for steeper turn-on behavior.

為了提供上下文，以鉿或鋯(Hf或Zr)為基礎的鐵電或反鐵電(FE或AFE)材料典型上遠比諸如鋯鈦酸鉛(PZT)的鐵電材料更薄，因而可以和高度縮放的邏輯技術相容。FE或AFE材料有兩個特性可以改善邏輯電晶體的性能：(1)由FE或AFE偏極化(polarization)所達成之通道中更高的電荷和(2)由於尖銳的FE或AFE轉變(transition)導致之更陡峭的導通行為。此等性質可以藉由增加電流或減小次臨界擺幅(subthreshold swing,SS)來改善電晶體性能。 To provide context, ferroelectric or antiferroelectric (FE or AFE) materials based on hafnium or zirconium (Hf or Zr) are typically much thinner than ferroelectric materials such as lead zirconate titanate (PZT), and thus can be compared with Highly scalable logic technology compatible. FE or AFE materials have two properties that can improve the performance of logic transistors: (1) higher charge in the channel achieved by FE or AFE polarization and (2) due to sharp FE or AFE transition ( transition) resulting in a steeper turn-on behavior. These properties can improve transistor performance by increasing current or reducing subthreshold swing (SS).

圖31A繪示依據本發明的一實施例，具有鐵 電或反鐵電閘極電介質結構之半導體裝置的剖面視圖。 Figure 31A shows an embodiment according to the present invention, with iron Cross-sectional view of a semiconductor device with an electric or antiferroelectric gate dielectric structure.

參照圖31A，積體電路結構3100包含在基板3104之上的閘極結構3102。在一個實施例中，閘極結構3102係在包含諸如單晶矽之單晶材料的半導體通道結構3106的上方或之上。閘極結構3102包含在半導體通道結構3106之上的閘極電介質和在閘極電介質結構之上的閘極電極。閘極電介質包含鐵電或反鐵電多晶材料層3102A。閘極電極具有在鐵電或反鐵電多晶材料層3102A之上的導電層3102B。導電層3102B包含金屬並且可以是阻障層、功函數層、或模板層(templating layer)，其提高FE或AFE層的結晶化。閘極填充層3102C係在導電層3102B上或之上。源極區域3108和汲極區域3110係在閘極結構3102的相反側上。源極或汲極接觸3112在位置3149處係電連接至源極區域3108和汲極區域3110，並且藉由層間電介質層3114或閘極電介質間隔層3116的其中一者或兩者而與閘極結構3102間隔分開。在圖31A的範例中，源極區域3108和汲極區域3110為基板3104的區域。在一實施例中，源極或汲極接觸3112包含阻障層3112A和導電性溝槽填充材料3112B。在一個實施例中，鐵電或反鐵電多晶材料層3102A沿著電介質間隔層3116延伸，如同圖31A中所描述的。 Referring to FIG. 31A , an integrated circuit structure 3100 includes a gate structure 3102 over a substrate 3104 . In one embodiment, the gate structure 3102 is on or over a semiconductor channel structure 3106 comprising a single crystal material, such as single crystal silicon. Gate structure 3102 includes a gate dielectric over semiconductor channel structure 3106 and a gate electrode over the gate dielectric structure. The gate dielectric comprises a layer 3102A of ferroelectric or antiferroelectric polycrystalline material. The gate electrode has a conductive layer 3102B over a layer 3102A of ferroelectric or antiferroelectric polycrystalline material. Conductive layer 3102B includes metal and may be a barrier layer, work function layer, or templating layer, which enhances the crystallization of the FE or AFE layer. Gate-fill layer 3102C is on or over conductive layer 3102B. The source region 3108 and the drain region 3110 are on opposite sides of the gate structure 3102 . Source or drain contact 3112 is electrically connected to source region 3108 and drain region 3110 at location 3149 and is connected to the gate by either or both of interlayer dielectric layer 3114 or gate dielectric spacer layer 3116. Structures 3102 are spaced apart. In the example of FIG. 31A , source region 3108 and drain region 3110 are regions of substrate 3104 . In one embodiment, the source or drain contact 3112 includes a barrier layer 3112A and a conductive trench fill material 3112B. In one embodiment, the layer of ferroelectric or antiferroelectric polycrystalline material 3102A extends along the dielectric spacer layer 3116, as depicted in FIG. 31A.

在一實施例中，而且如同可適用於本發明各處，鐵電或反鐵電多晶材料層3102A為鐵電多晶材料層。在一個實施例中，鐵電多晶材料層為包含Zr和Hf，具有50：50或者Zr更大之Zr：Hf比值的氧化物。鐵電效應可以隨 著正交結晶度(orthorhombic crystallinity)的增加而增加。在一個實施例中，鐵電多晶材料層具有至少80%的正交結晶度。 In one embodiment, and as applicable throughout the present invention, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is a ferroelectric polycrystalline material layer. In one embodiment, the ferroelectric polycrystalline material layer is an oxide comprising Zr and Hf, with a Zr:Hf ratio of 50:50 or Zr greater. The ferroelectric effect can be It increases with the increase of orthorhombic crystallinity. In one embodiment, the layer of ferroelectric polycrystalline material has an orthorhombic crystallinity of at least 80%.

在一實施例中，而且如同可適用於本發明各處，鐵電或反鐵電多晶材料層3102A為反鐵電多晶材料層。在一個實施例中，反鐵電多晶材料層為包含Zr和Hf，具有80：20或者Zr更大而且Zr甚至高到100%(ZrO2)之Zr：Hf比值的氧化物。在一個實施例中，反鐵電多晶材料層具有至少80%的四方結晶度(tetragonal crystallinity)。 In one embodiment, and as applicable throughout the present invention, the ferroelectric or antiferroelectric polycrystalline material layer 3102A is an antiferroelectric polycrystalline material layer. In one embodiment, the antiferroelectric polycrystalline material layer is an oxide comprising Zr and Hf, with a Zr:Hf ratio of 80:20 or greater for Zr and even Zr as high as 100% (ZrO 2 ). In one embodiment, the layer of antiferroelectric polycrystalline material has a tetragonal crystallinity of at least 80%.

在一實施例中，而且如同可適用於本發明各處，閘極堆疊3102的閘極電介質進一步在鐵電或反鐵電多晶材料層3102A與半導體通道結構3106之間包含非晶電介質層3103，諸如天然的氧化矽層、高K電介質(HfOx,Al2O3等等)、或氧化物和高K的組合。在一實施例中，而且如同可適用於本發明各處，鐵電或反鐵電多晶材料層3102A具有在1奈米到8奈米的範圍中的厚度。在一實施例中，而且如同可適用於本發明各處，鐵電或反鐵電多晶材料層3102A具有約在20奈米以上的範圍中的晶粒大小。 In one embodiment, and as applicable throughout the present invention, the gate dielectric of the gate stack 3102 further comprises an amorphous dielectric layer 3103 between the ferroelectric or antiferroelectric polycrystalline material layer 3102A and the semiconductor channel structure 3106 , such as natural silicon oxide layers, high-K dielectrics (HfOx, Al 2 O 3, etc.), or a combination of oxides and high-K. In one embodiment, and as applicable throughout the present invention, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a thickness in the range of 1 nm to 8 nm. In one embodiment, and as applicable throughout the present invention, the ferroelectric or antiferroelectric polycrystalline material layer 3102A has a grain size approximately in the range above 20 nm.

在一實施例中，在鐵電或反鐵電多晶材料層3102A的沉積之後，例如藉由原子層沉積法(ALD)，包含金屬的層(例如，層3102B，諸如5到10奈米的氮化鈦或者氮化組或鎢)被形成在鐵電或反鐵電多晶材料層3102A上。然後實施退火。在一個實施例中，退火被實施持續1毫秒到30分鐘的範圍中的時間期間。在一個實施例中，退火被 實施於攝氏500到1100度的溫度範圍中。 In one embodiment, after deposition of the ferroelectric or antiferroelectric polycrystalline material layer 3102A, for example, by atomic layer deposition (ALD), a metal-containing layer (eg, layer 3102B, such as 5 to 10 nm Titanium nitride or nitride group or tungsten) is formed on the ferroelectric or antiferroelectric polycrystalline material layer 3102A. Annealing is then performed. In one embodiment, annealing is performed for a period of time in the range of 1 millisecond to 30 minutes. In one embodiment, the annealing is Implemented in a temperature range of 500 to 1100 degrees Celsius.

圖31B繪示依據本發明的另一實施例，具有鐵電或反鐵電閘極電介質結構之另一半導體裝置的剖面視圖。 31B shows a cross-sectional view of another semiconductor device with a ferroelectric or antiferroelectric gate dielectric structure according to another embodiment of the present invention.

參照圖31B，積體電路結構3150包含在基板3154之上的閘極結構3152。在一個實施例中，閘極結構3152係在包含諸如單晶矽之單晶材料的半導體通道結構3156的上方或之上。閘極結構3152包含在半導體通道結構3156之上的閘極電介質和在閘極電介質結構之上的閘極電極。閘極電介質包含鐵電或反鐵電多晶材料層3152A，並且可另包含非晶氧化物層3153。閘極電極具有在鐵電或反鐵電多晶材料層3152A之上的導電層3152B。導電層3152B包含金屬並且可以是阻障層或功函數層。閘極填充層3152C係在導電層3152B上或之上。突起的(raised)源極區域3158和突起的汲極區域3160(諸如，和半導體通道結構3156不同之半導體材料的區域)係在閘極結構3152的相反側上。源極或汲極接觸3162在位置3199處係電連接至源極區域3158和汲極區域3160，並且藉由層間電介質層3164或閘極電介質間隔層3166的其中一者或兩者而與閘極結構3152間隔分開。在一實施例中，源極或汲極接觸3162包含阻障層3162A和導電性溝槽填充材料3162B。在一個實施例中，鐵電或反鐵電多晶材料層3152A沿著電介質間隔層3166延伸，如同圖31B中所描述的。 Referring to FIG. 31B , an integrated circuit structure 3150 includes a gate structure 3152 over a substrate 3154 . In one embodiment, the gate structure 3152 is on or over a semiconductor channel structure 3156 comprising a single crystal material, such as single crystal silicon. Gate structure 3152 includes a gate dielectric over semiconductor channel structure 3156 and a gate electrode over the gate dielectric structure. The gate dielectric includes a layer of ferroelectric or antiferroelectric polycrystalline material 3152A and may additionally include an amorphous oxide layer 3153 . The gate electrode has a conductive layer 3152B over a layer 3152A of ferroelectric or antiferroelectric polycrystalline material. The conductive layer 3152B contains metal and may be a barrier layer or a work function layer. Gate-fill layer 3152C is on or over conductive layer 3152B. Raised source regions 3158 and raised drain regions 3160 , such as regions of a different semiconductor material than semiconductor channel structure 3156 , are on opposite sides of gate structure 3152 . Source or drain contact 3162 is electrically connected to source region 3158 and drain region 3160 at location 3199 and is connected to the gate by either or both of interlayer dielectric layer 3164 or gate dielectric spacer layer 3166. Structures 3152 are spaced apart. In one embodiment, the source or drain contact 3162 includes a barrier layer 3162A and a conductive trench fill material 3162B. In one embodiment, the layer of ferroelectric or antiferroelectric polycrystalline material 3152A extends along the dielectric spacer layer 3166, as depicted in FIG. 31B.

圖32A繪示依據本發明的另一實施例，在一 對半導體鰭部之上的複數條閘極線的平面視圖。 Fig. 32A shows another embodiment according to the present invention, in a A plan view of a plurality of gate lines over a semiconductor fin.

參照圖32A，複數條作用閘極線3204被形成在複數個半導體鰭部3200之上。假性閘極線3206係在該複數個半導體鰭部3200的末端。閘極線3204/3206之間的間隙3208為溝槽接觸可以被定位來提供導電接觸給源極或汲極區域(諸如，源極或汲極區域3251,3252,3253，和3254)的位置。在一實施例中，該複數條閘極線3204/3206的圖案或該複數個半導體鰭部3200的圖案被敘述為光柵結構。在一個實施例中，該光柵狀圖案包含以固定間距間隔開並且具有固定寬度之該複數條閘極線3204/3206的圖案或該複數個半導體鰭部3200，或者該複數條閘極線3204/3206的圖案和該複數個半導體鰭部3200兩者。 Referring to FIG. 32A , a plurality of active gate lines 3204 are formed over a plurality of semiconductor fins 3200 . Dummy gate lines 3206 are tied at the ends of the plurality of semiconductor fins 3200 . The gap 3208 between the gate lines 3204/3206 is where trench contacts can be positioned to provide conductive contact to source or drain regions such as source or drain regions 3251, 3252, 3253, and 3254. In one embodiment, the pattern of the plurality of gate lines 3204/3206 or the plurality of semiconductor fins 3200 is described as a grating structure. In one embodiment, the grating-like pattern comprises the pattern of the plurality of gate lines 3204/3206 or the plurality of semiconductor fins 3200 spaced apart at a fixed pitch and having a fixed width, or the plurality of gate lines 3204/3206 Both the pattern of 3206 and the plurality of semiconductor fins 3200.

圖32B繪示依據本發明的一實施例，沿著圖32A之a到a’軸線所取下的剖面視圖。 Figure 32B shows a cross-sectional view taken along the a to a' axis of Figure 32A according to an embodiment of the present invention.

參照圖32B，複數條作用閘極線3264被形成在形成於基板3260之上方的半導體鰭部3262之上。假性閘極線3266係在該半導體鰭部3262的末端。電介質層3270係在假性閘極線3266之外。溝槽接觸材料3297係在作用閘極線3264之間，以及在假性閘極線3266與作用閘極線3264之間。嵌入的源極或汲極結構3268係在作用閘極線3264之間以及在假性閘極線3266與作用閘極線3264之間的半導體鰭部3262中。 Referring to FIG. 32B , a plurality of active gate lines 3264 are formed over semiconductor fins 3262 formed over substrate 3260 . A dummy gate line 3266 is tied at the end of the semiconductor fin 3262 . Dielectric layer 3270 is tied over dummy gate line 3266 . Trench contact material 3297 is placed between active gate lines 3264 , and between dummy gate lines 3266 and active gate lines 3264 . Embedded source or drain structures 3268 are in semiconductor fin 3262 between active gate lines 3264 and between dummy gate lines 3266 and active gate lines 3264 .

作用閘極線3264包含閘極電介質結構3272、功函數閘極電極部3274和填充閘極電極部3276、以及電介 質覆蓋層3278。電介質間隔層3280使作用閘極線3264和假性閘極線3266的側壁列隊(line)。在一實施例中，閘極電介質結構3272包含鐵電或反鐵電多晶材料層3298。在一個實施例中，閘極電介質結構3272另包含非晶氧化物層3299。 Active gate line 3264 includes gate dielectric structure 3272, work function gate electrode portion 3274 and filled gate electrode portion 3276, and dielectric Quality overlay 3278. Dielectric spacer 3280 lines the sidewalls of active gate line 3264 and dummy gate line 3266 . In one embodiment, the gate dielectric structure 3272 includes a layer 3298 of ferroelectric or antiferroelectric polycrystalline material. In one embodiment, the gate dielectric structure 3272 further includes an amorphous oxide layer 3299 .

在另一態樣中，同一導電類型，例如N型或P型的裝置針對相同的導電類型可以具有不同的閘極電極堆疊。但是，為了比較目的，具有相同導電類型的裝置基於調變的摻雜可以具有差異化的電壓臨界值(VT)。 In another aspect, devices of the same conductivity type, such as N-type or P-type, may have different gate electrode stacks for the same conductivity type. However, for comparison purposes, modulation-based doping of devices with the same conductivity type may have a differentiated voltage threshold (VT).

圖33A繪示依據本發明的一實施例，基於調變的摻雜而具有差異化的電壓臨界值的一對NMOS裝置和基於調變的摻雜而具有差異化的電壓臨界值的一對PMOS裝置的剖面視圖。 33A illustrates a pair of NMOS devices with differentiated voltage thresholds based on modulated doping and a pair of PMOS devices with differentiated voltage thresholds based on modulated doping, according to an embodiment of the present invention. Sectional view of the device.

參照圖33A，第一NMOS裝置3302在半導體作用區域3300之上(諸如，在矽鰭部或基板之上)係鄰接第二NMOS裝置3304。第一NMOS裝置3302和第二NMOS裝置3304兩者皆包含閘極電介質層3306、諸如功函數層的第一閘極電極導電層3308、和閘極電極導電填充3310。在一實施例中，第一NMOS裝置3302的第一閘極電極導電層3308和第二NMOS裝置3304的第一閘極電極導電層3308具有相同的材料和相同的厚度，因而具有相同的功函數。但是，第一NMOS裝置3302具有比第二NMOS裝置3304低的VT。在一個這樣的實施例中，第一NMOS裝置3302被稱為”標準的VT”裝置，而第二NMOS裝置3304被稱為”高的VT”裝 置。在一實施例中，在第一NMOS裝置3302和第二NMOS裝置3304的區域3312處藉由使用調變或差異化的佈植摻雜來達成差異化的VT。 Referring to FIG. 33A , a first NMOS device 3302 is adjacent to a second NMOS device 3304 over a semiconductor active region 3300 , such as over a silicon fin or substrate. Both the first NMOS device 3302 and the second NMOS device 3304 include a gate dielectric layer 3306 , a first gate electrode conductive layer 3308 such as a work function layer, and a gate electrode conductive fill 3310 . In one embodiment, the first gate electrode conductive layer 3308 of the first NMOS device 3302 and the first gate electrode conductive layer 3308 of the second NMOS device 3304 have the same material and the same thickness, thus have the same work function . However, the first NMOS device 3302 has a lower VT than the second NMOS device 3304 . In one such embodiment, the first NMOS device 3302 is referred to as a "standard VT" device and the second NMOS device 3304 is referred to as a "high VT" device. place. In one embodiment, differential VT is achieved at regions 3312 of the first NMOS device 3302 and the second NMOS device 3304 by using modulation or differential implant doping.

再次參照圖33A，第一PMOS裝置3322在半導體作用區域3320之上(諸如，在矽鰭部或基板之上)係鄰接第二PMOS裝置3324。第一PMOS裝置3322和第二PMOS裝置3324兩者皆包含閘極電介質層3326、諸如功函數層的第一閘極電極導電層3328、和閘極電極導電填充3330。在一實施例中，第一PMOS裝置3322的第一閘極電極導電層3328和第二PMOS裝置3324的第一閘極電極導電層3328具有相同的材料和相同的厚度，因而具有相同的功函數。但是，第一PMOS裝置3322具有比第二PMOS裝置3324高的VT。在一個這樣的實施例中，第一PMOS裝置3322被稱為”標準的VT”裝置，而第二PMOS裝置3324被稱為”低的VT”裝置。在一實施例中，在第一PMOS裝置3322和第二PMOS裝置3324的區域3332處藉由使用調變或差異化的佈植摻雜來達成差異化的VT。 Referring again to FIG. 33A , the first PMOS device 3322 is adjacent to the second PMOS device 3324 over the semiconductor active region 3320 , such as over a silicon fin or substrate. Both the first PMOS device 3322 and the second PMOS device 3324 include a gate dielectric layer 3326 , a first gate electrode conductive layer 3328 such as a work function layer, and a gate electrode conductive fill 3330 . In one embodiment, the first gate electrode conductive layer 3328 of the first PMOS device 3322 and the first gate electrode conductive layer 3328 of the second PMOS device 3324 have the same material and the same thickness, thus have the same work function . However, the first PMOS device 3322 has a higher VT than the second PMOS device 3324 . In one such embodiment, the first PMOS device 3322 is referred to as a "standard VT" device and the second PMOS device 3324 is referred to as a "low VT" device. In one embodiment, differentiated VT is achieved at region 3332 of first PMOS device 3322 and second PMOS device 3324 by using modulation or differentiated implant doping.

相反於圖33A，圖33B繪示依據本發明的另一實施例，基於調變的閘極電極結構而具有差異化的電壓臨界值的一對NMOS裝置和基於調變的閘極電極結構而具有差異化的電壓臨界值的一對PMOS裝置的剖面視圖。 Contrary to FIG. 33A , FIG. 33B shows a pair of NMOS devices having differentiated voltage thresholds based on a modulated gate electrode structure and a pair of NMOS devices based on a modulated gate electrode structure in accordance with another embodiment of the present invention. Cross-sectional view of a pair of PMOS devices with differentiated voltage thresholds.

參照圖33B，第一NMOS裝置3352在半導體作用區域3350之上(諸如，在矽鰭部或基板之上)係鄰接第二NMOS裝置3354。第一NMOS裝置3352和第二NMOS裝置 3354兩者皆包含閘極電介質層3356。但是，第一NMOS裝置3352和第二NMOS裝置3354具有在結構上不同的閘極電極堆疊。特別是，第一NMOS裝置3352包含諸如第一功函數層的第一閘極電極導電層3358、和閘極電極導電填充3360。第二NMOS裝置3354包含諸如第二功函數層的第二閘極電極導電層3359、第一閘極電極導電層3358和閘極電極導電填充3360。第一NMOS裝置3352具有比第二NMOS裝置3354低的VT。在一個這樣的實施例中，第一NMOS裝置3352被稱為”標準的VT”裝置，而第二NMOS裝置3354被稱為”高的VT”裝置。在一實施例中，藉由對相同導電類型裝置使用差異化的閘極堆疊來達成差異化的VT。 Referring to FIG. 33B , a first NMOS device 3352 adjoins a second NMOS device 3354 over a semiconductor active region 3350 , such as over a silicon fin or substrate. The first NMOS device 3352 and the second NMOS device Both 3354 include a gate dielectric layer 3356 . However, the first NMOS device 3352 and the second NMOS device 3354 have structurally different gate electrode stacks. In particular, the first NMOS device 3352 includes a first gate electrode conductive layer 3358 , such as a first work function layer, and a gate electrode conductive fill 3360 . The second NMOS device 3354 includes a second gate electrode conductive layer 3359 such as a second work function layer, a first gate electrode conductive layer 3358 and a gate electrode conductive fill 3360 . The first NMOS device 3352 has a lower VT than the second NMOS device 3354 . In one such embodiment, the first NMOS device 3352 is referred to as a "standard VT" device and the second NMOS device 3354 is referred to as a "high VT" device. In one embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.

再次參照圖33B，第一PMOS裝置3372在半導體作用區域3370之上(諸如，在矽鰭部或基板之上)係鄰接第二PMOS裝置3374。第一PMOS裝置3372和第二PMOS裝置3374兩者皆包含閘極電介質層3376。但是，第一PMOS裝置3372和第二PMOS裝置3374具有在結構上不同的閘極電極堆疊。特別是，第一PMOS裝置3372包含諸如第一功函數層之具有第一厚度的閘極電極導電層3378A、和閘極電極導電填充3380。第二PMOS裝置3374包含具有第二厚度的閘極電極導電層3378B和閘極電極導電填充3380。在一個實施例中，閘極電極導電層3378A和閘極電極導電層3378B具有相同的組成，但是閘極電極導電層3378B的厚度(第二厚度)大於閘極電極導電層3378A的厚度(第一厚度)。第一PMOS裝置3372具有比第二PMOS裝置3374高的 VT。在一個這樣的實施例中，第一PMOS裝置3372被稱為”標準的VT”裝置，而第二PMOS裝置3374被稱為”低的VT”裝置。在一實施例中，藉由對相同導電類型裝置使用差異化的閘極堆疊來達成差異化的VT。 Referring again to FIG. 33B , the first PMOS device 3372 is adjacent to the second PMOS device 3374 over the semiconductor active region 3370 , such as over a silicon fin or substrate. Both the first PMOS device 3372 and the second PMOS device 3374 include a gate dielectric layer 3376 . However, the first PMOS device 3372 and the second PMOS device 3374 have structurally different gate electrode stacks. In particular, the first PMOS device 3372 includes a gate electrode conductive layer 3378A having a first thickness, such as a first work function layer, and a gate electrode conductive fill 3380 . The second PMOS device 3374 includes a gate electrode conductive layer 3378B having a second thickness and a gate electrode conductive fill 3380 . In one embodiment, gate electrode conductive layer 3378A and gate electrode conductive layer 3378B have the same composition, but gate electrode conductive layer 3378B has a thickness (second thickness) greater than the thickness of gate electrode conductive layer 3378A (first thickness). thickness). The first PMOS device 3372 has a higher VT. In one such embodiment, the first PMOS device 3372 is referred to as a "standard VT" device and the second PMOS device 3374 is referred to as a "low VT" device. In one embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type.

再次參照圖33B，依據本發明的一實施例，積體電路結構包含鰭部(例如，諸如3350的矽鰭部)。可以領會到鰭部具有頂部(如所示者)和側壁(進入和離開頁面)。閘極電介質層3356係在鰭部的頂部之上並且橫向鄰接鰭部的側壁。裝置3354的N型閘極電極係在鰭部的頂部之上的閘極電介質層3356之上並且橫向鄰接鰭部的側壁。N型閘極電極包含閘極電介質層3356上的P型金屬層3359，以及P型金屬層3359上的N型金屬層3358。如同將領會到的，第一N型源極或汲極區域可以鄰接閘極電極的第一側(例如，進入頁面)，以及第二N型源極或汲極區域可以鄰接閘極電極的第二側(例如，離開頁面)，該第二側和該第一側相對立。 Referring again to FIG. 33B , according to one embodiment of the invention, the integrated circuit structure includes fins (eg, silicon fins such as 3350 ). It can be appreciated that the fin has a top (as shown) and sidewalls (entering and exiting the page). A gate dielectric layer 3356 is over the top of the fin and laterally adjoins the sidewalls of the fin. The N-type gate electrode of device 3354 is tied over gate dielectric layer 3356 over the top of the fin and laterally adjoins the sidewalls of the fin. The N-type gate electrode includes a P-type metal layer 3359 on the gate dielectric layer 3356 , and an N-type metal layer 3358 on the P-type metal layer 3359 . As will be appreciated, a first N-type source or drain region may adjoin a first side of the gate electrode (eg, into the page), and a second N-type source or drain region may adjoin a second side of the gate electrode. Two sides (eg, off the page), the second side is opposite the first side.

在一個實施例中，P型金屬層3359包含鈦和氮，而且N型金屬層3358包含鈦、鋁、碳和氮。在一個實施例中，P型金屬層3359具有在2到12埃(Angstrom)之範圍中的厚度，並且在一特定實施例中，P型金屬層3359具有在2到4埃之範圍中的厚度。在一個實施例中，N型閘極電極另包含N型金屬層3358上的導電填充金屬層3360。在一個這樣的實施例中，導電填充金屬層3360包含鎢。在一個特別的實施例中，導電填充金屬層3360包含95或更大原子 百分率的鎢以及0.1到2原子百分率的氟。 In one embodiment, P-type metal layer 3359 includes titanium and nitrogen, and N-type metal layer 3358 includes titanium, aluminum, carbon, and nitrogen. In one embodiment, the P-type metal layer 3359 has a thickness in the range of 2 to 12 Angstroms (Angstrom), and in a particular embodiment, the P-type metal layer 3359 has a thickness in the range of 2 to 4 Angstroms . In one embodiment, the N-type gate electrode further includes a conductive fill metal layer 3360 on the N-type metal layer 3358 . In one such embodiment, conductive fill metal layer 3360 includes tungsten. In a particular embodiment, the conductive fill metal layer 3360 contains 95 or more atomic percent tungsten and 0.1 to 2 atomic percent fluorine.

再次參照圖33B，依據本發明的另一實施例，積體電路結構包含具有電壓臨界值(VT)的第一N型裝置3352、具有第一閘極電介質層3356的第一N型裝置3352、和第一閘極電介質層3356上的第一N型金屬層3358。而且，所包含的是具有電壓臨界值(VT)的第二N型裝置3354、具有第二閘極電介質層3356的第二N型裝置3354、第二閘極電介質層3356上的P型金屬層3359、和P型金屬層3359上的第二N型金屬層3358。 Referring again to FIG. 33B, according to another embodiment of the present invention, the integrated circuit structure includes a first N-type device 3352 having a voltage threshold (VT), a first N-type device 3352 having a first gate dielectric layer 3356, and the first N-type metal layer 3358 on the first gate dielectric layer 3356 . Also included is a second N-type device 3354 with a voltage threshold (VT), a second N-type device 3354 with a second gate dielectric layer 3356, a P-type metal layer on the second gate dielectric layer 3356 3359, and the second N-type metal layer 3358 on the P-type metal layer 3359.

在一個實施例中，其中，第二N型裝置3354的VT比第一N型裝置3352的VT高。在一個實施例中，第一N型金屬層3358和第二N型金屬層3358具有相同的組成。在一個實施例中，第一N型金屬層3358和第二N型金屬層3358具有相同的厚度。在一個實施例中，其中，N型金屬層3358包含鈦、鋁、碳和氮，而且P型金屬層3359包含鈦和氮。 In one embodiment, the VT of the second N-type device 3354 is higher than the VT of the first N-type device 3352 . In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same composition. In one embodiment, the first N-type metal layer 3358 and the second N-type metal layer 3358 have the same thickness. In one embodiment, the N-type metal layer 3358 includes titanium, aluminum, carbon and nitrogen, and the P-type metal layer 3359 includes titanium and nitrogen.

再次參照圖33B，依據本發明的另一實施例，積體電路結構包含具有電壓臨界值(VT)的第一P型裝置3372、具有第一閘極電介質層3376的第一P型裝置3372、和第一閘極電介質層3376上的第一P型金屬層3378A。第一P型金屬層3378A具有厚度。第二P型裝置3374也被包含而且具有電壓臨界值(VT)。第二P型裝置3374具有第二閘極電介質層3376和第二閘極電介質層3376上的第二P型金屬層3378B。第二P型金屬層3378B具有大 於第一P型金屬層3378A之厚度的厚度。 Referring again to FIG. 33B, according to another embodiment of the present invention, the integrated circuit structure includes a first P-type device 3372 having a voltage threshold (VT), a first P-type device 3372 having a first gate dielectric layer 3376, and the first P-type metal layer 3378A on the first gate dielectric layer 3376 . The first P-type metal layer 3378A has a thickness. A second P-type device 3374 is also included and has a voltage threshold (VT). The second P-type device 3374 has a second gate dielectric layer 3376 and a second P-type metal layer 3378B on the second gate dielectric layer 3376 . The second P-type metal layer 3378B has a large The thickness of the first P-type metal layer 3378A.

在一個實施例中，第二P型裝置3374的VT係低於第一P型裝置3372的VT。在一個實施例中，第一P型金屬層3378A和第二P型金屬層3378B具有相同的組成。在一個實施例中，第一P型金屬層3378A和第二P型金屬層3378B兩者皆包含鈦和氮。在一個實施例中，第一P型金屬層3378A的厚度係低於第一P型金屬層3378A之材料的功函數飽和厚度。在一個實施例中，雖然未被描述出，第二P型金屬層3378B包含第二金屬膜(例如，來自第一沉積)上的第一金屬膜(例如，來自第二沉積)，而且接縫係在第一金屬膜與第二金屬膜之間。 In one embodiment, the VT of the second P-type device 3374 is lower than the VT of the first P-type device 3372 . In one embodiment, the first P-type metal layer 3378A and the second P-type metal layer 3378B have the same composition. In one embodiment, both the first P-type metal layer 3378A and the second P-type metal layer 3378B include titanium and nitrogen. In one embodiment, the thickness of the first P-type metal layer 3378A is lower than the work function saturation thickness of the material of the first P-type metal layer 3378A. In one embodiment, although not depicted, the second P-type metal layer 3378B includes a first metal film (eg, from a second deposition) on a second metal film (eg, from a first deposition), and the seam It is tied between the first metal film and the second metal film.

再次參照圖33B，依據本發明的另一實施例，積體電路結構包含具有第一閘極電介質層3356的第一N型裝置3352、和第一閘極電介質層3356上的第一N型金屬層3358。第二N型裝置3354具有第二閘極電介質層3356、第二閘極電介質層3356上的第一P型金屬層3359、和第一P型金屬層3359上的第二N型金屬層3358。第一P型裝置3372具有第三閘極電介質層3376、和第三閘極電介質層3376上的第二P型金屬層3378A。第二P型金屬層3378A具有厚度。第二P型裝置3374具有第四閘極電介質層3376、和第四閘極電介質層3376上的第三P型金屬層3378B。第三P型金屬層3378B具有比第二P型金屬層3378A之厚度更大的厚度。 Referring again to FIG. 33B, according to another embodiment of the present invention, the integrated circuit structure includes a first N-type device 3352 having a first gate dielectric layer 3356, and a first N-type metal on the first gate dielectric layer 3356. Layer 3358. The second N-type device 3354 has a second gate dielectric layer 3356 , a first P-type metal layer 3359 on the second gate dielectric layer 3356 , and a second N-type metal layer 3358 on the first P-type metal layer 3359 . The first P-type device 3372 has a third gate dielectric layer 3376 , and a second P-type metal layer 3378A on the third gate dielectric layer 3376 . The second P-type metal layer 3378A has a thickness. The second P-type device 3374 has a fourth gate dielectric layer 3376 , and a third P-type metal layer 3378B on the fourth gate dielectric layer 3376 . The third P-type metal layer 3378B has a greater thickness than the second P-type metal layer 3378A.

在一個實施例中，第一N型裝置3352具有電 壓臨界值(VT)，第二N型裝置3354具有電壓臨界值(VT)，而且第二N型裝置3354的VT比第一N型裝置3352的VT低。在一個實施例中，第一P型裝置3372具有電壓臨界值(VT)，第二P型裝置3374具有電壓臨界值(VT)，而且第二P型裝置3374的VT係低於第一P型裝置3372的VT。在一個實施例中，第三P型金屬層3378B包含第二金屬膜上的第一金屬膜，以及在第一金屬膜與第二金屬膜之間的接縫。 In one embodiment, the first N-type device 3352 has an electrical Voltage threshold (VT), the second N-type device 3354 has a voltage threshold (VT), and the VT of the second N-type device 3354 is lower than the VT of the first N-type device 3352 . In one embodiment, the first P-type device 3372 has a voltage threshold (VT), the second P-type device 3374 has a voltage threshold (VT), and the VT of the second P-type device 3374 is lower than that of the first P-type device. VT of device 3372. In one embodiment, the third P-type metal layer 3378B includes a first metal film on a second metal film, and a seam between the first metal film and the second metal film.

可以領會到對於相同導電類型之大於兩種類型的VT裝置可以被包含在同一個結構中，諸如在同一個晶粒中。在第一範例中，圖34A繪示依據本發明的一實施例，基於差異化之閘極電極結構和調變的摻雜而具有差異化的電壓臨界值之三個一組(triplet)的NMOS裝置和基於差異化之閘極電極結構和調變的摻雜而具有差異化的電壓臨界值之三個一組的PMOS裝置的剖面視圖。 It can be appreciated that more than two types of VT devices for the same conductivity type may be contained in the same structure, such as in the same die. In a first example, FIG. 34A shows NMOS triplets with differentiated voltage thresholds based on differentiated gate electrode structures and modulated doping, according to an embodiment of the present invention. Cross-sectional views of devices and PMOS devices with differentiated voltage threshold triplets based on differentiated gate electrode structures and modulated doping.

參照圖34A，第一NMOS裝置3402在半導體作用區域3400之上(諸如，在矽鰭部或基板之上)係鄰接第二NMOS裝置3404和第三NMOS裝置3403。第一NMOS裝置3402、第二NMOS裝置3404和第三NMOS裝置3403包含閘極電介質層3406。第一NMOS裝置3402和第三NMOS裝置3403在結構上具有相同或相似的閘極電極堆疊。但是，第二NMOS裝置3404在結構上具有與第一NMOS裝置3402和第三NMOS裝置3403不同的閘極電極堆疊。特別是，第一NMOS裝置3402和第三NMOS裝置3403包含諸如第一功函數層的第一閘極電極導電層3408、和閘極電極導電填充 3410。第二NMOS裝置3404包含諸如第二功函數層的第二閘極電極導電層3409、第一閘極電極導電層3408和閘極電極導電填充3410。第一NMOS裝置3402具有比第二NMOS裝置3404低的VT。在一個這樣的實施例中，第一NMOS裝置3402被稱為”標準的VT”裝置，而第二NMOS裝置3404被稱為”高的VT”裝置。在一實施例中，針對相同導電類型裝置藉由使用差異化的閘極堆疊來達成差異化的VT。在一實施例中，第三NMOS裝置3403具有與第一NMOS裝置3402和第二NMOS裝置3404之VT不同的VT，即使是第三NMOS裝置3403的閘極電極結構和第一NMOS裝置3402的閘極電極結構相同。在一個實施例中，第三NMOS裝置3403的VT係在第一NMOS裝置3402與第二NMOS裝置3404的VT之間。在一實施例中，在第三NMOS裝置3403的區域3412處藉由使用調變或差異化的佈植摻雜來達成第三NMOS裝置3403與第一NMOS裝置3402間之差異化的VT。在一個這樣的實施例中，第三NMOS裝置3403具有一通道區域，該通道區域具有與第一NMOS裝置3402之通道區域的摻雜濃度不同的摻雜濃度。 Referring to FIG. 34A , a first NMOS device 3402 is adjacent to a second NMOS device 3404 and a third NMOS device 3403 over a semiconductor active region 3400 , such as over a silicon fin or substrate. The first NMOS device 3402 , the second NMOS device 3404 and the third NMOS device 3403 include a gate dielectric layer 3406 . The first NMOS device 3402 and the third NMOS device 3403 have the same or similar gate electrode stack in structure. However, the second NMOS device 3404 has a different gate electrode stack than the first NMOS device 3402 and the third NMOS device 3403 in structure. In particular, the first NMOS device 3402 and the third NMOS device 3403 include a first gate electrode conductive layer 3408 such as a first work function layer, and a gate electrode conductive fill 3410. The second NMOS device 3404 includes a second gate electrode conductive layer 3409 such as a second work function layer, a first gate electrode conductive layer 3408 and a gate electrode conductive fill 3410 . The first NMOS device 3402 has a lower VT than the second NMOS device 3404 . In one such embodiment, the first NMOS device 3402 is referred to as a "standard VT" device and the second NMOS device 3404 is referred to as a "high VT" device. In one embodiment, differentiated VT is achieved for devices of the same conductivity type by using differentiated gate stacks. In one embodiment, the third NMOS device 3403 has a different VT than the VT of the first NMOS device 3402 and the second NMOS device 3404, even though the gate electrode structure of the third NMOS device 3403 is different from the gate electrode structure of the first NMOS device 3402. The electrodes have the same structure. In one embodiment, the VT of the third NMOS device 3403 is tied between the VTs of the first NMOS device 3402 and the second NMOS device 3404 . In one embodiment, the differential VT between the third NMOS device 3403 and the first NMOS device 3402 is achieved at the region 3412 of the third NMOS device 3403 by using modulation or differential implant doping. In one such embodiment, the third NMOS device 3403 has a channel region having a different doping concentration than the doping concentration of the channel region of the first NMOS device 3402 .

再次參照圖34A，第一PMOS裝置3422在半導體作用區域3420之上(諸如，在矽鰭部或基板之上)係鄰接第二PMOS裝置3424和第三PMOS裝置3423。第一PMOS裝置3422、第二PMOS裝置3424和第三PMOS裝置3423包含閘極電介質層3426。第一PMOS裝置3422和第三PMOS裝置3423在結構上具有相同或相似的閘極電極堆疊。但是，第 二PMOS裝置3424在結構上具有與第一PMOS裝置3422和第三PMOS裝置3423不同的閘極電極堆疊。特別是，第一PMOS裝置3422和第三PMOS裝置3423包含諸如功函數層之具有第一厚度的閘極電極導電層3428A、和閘極電極導電填充3430。第二PMOS裝置3424包含具有第二厚度的閘極電極導電層3428B、和閘極電極導電填充3430。在一個實施例中，閘極電極導電層3428A和閘極電極導電層3428B具有相同的組成，但是閘極電極導電層3428B的厚度(第二厚度)係大於閘極電極導電層3428A的厚度(第一厚度)。在一實施例中，第一PMOS裝置3422具有比第二PMOS裝置3424高的VT。在一個這樣的實施例中，第一PMOS裝置3422被稱為”標準的VT”裝置，而第二PMOS裝置3424被稱為”低的VT”裝置。在一實施例中，針對相同導電類型裝置藉由使用差異化的閘極堆疊來達成差異化的VT。在一實施例中，第三PMOS裝置3423具有與第一PMOS裝置3422和第二PMOS裝置3424之VT不同的VT，即使是第三PMOS裝置3423的閘極電極結構和第一PMOS裝置3422的閘極電極結構相同。在一個實施例中，第三PMOS裝置3423的VT係在第一PMOS裝置3422與第二PMOS裝置3424的VT之間。在一實施例中，在第三PMOS裝置3423的區域3432處藉由使用調變或差異化的佈植摻雜來達成第三PMOS裝置3423與第一PMOS裝置3422間之差異化的VT。在一個這樣的實施例中，第三PMOS裝置3423具有一通道區域，該通道區域具有與第一PMOS裝置3422之通道區域的摻雜濃 度不同的摻雜濃度。 Referring again to FIG. 34A , a first PMOS device 3422 is adjacent to a second PMOS device 3424 and a third PMOS device 3423 over a semiconductor active region 3420 , such as over a silicon fin or substrate. The first PMOS device 3422 , the second PMOS device 3424 and the third PMOS device 3423 include a gate dielectric layer 3426 . The first PMOS device 3422 and the third PMOS device 3423 have the same or similar gate electrode stacks in structure. However, the The second PMOS device 3424 has a different gate electrode stack than the first PMOS device 3422 and the third PMOS device 3423 in structure. In particular, the first PMOS device 3422 and the third PMOS device 3423 include a gate electrode conductive layer 3428A having a first thickness, such as a work function layer, and a gate electrode conductive fill 3430 . The second PMOS device 3424 includes a gate electrode conductive layer 3428B having a second thickness, and a gate electrode conductive fill 3430 . In one embodiment, the gate electrode conductive layer 3428A and the gate electrode conductive layer 3428B have the same composition, but the thickness of the gate electrode conductive layer 3428B (the second thickness) is greater than the thickness of the gate electrode conductive layer 3428A (the second thickness). a thickness). In one embodiment, the first PMOS device 3422 has a higher VT than the second PMOS device 3424 . In one such embodiment, the first PMOS device 3422 is referred to as a "standard VT" device and the second PMOS device 3424 is referred to as a "low VT" device. In one embodiment, differentiated VT is achieved for devices of the same conductivity type by using differentiated gate stacks. In one embodiment, the third PMOS device 3423 has a different VT than the VT of the first PMOS device 3422 and the second PMOS device 3424, even though the gate electrode structure of the third PMOS device 3423 is different from the gate electrode structure of the first PMOS device 3422. The electrodes have the same structure. In one embodiment, the VT of the third PMOS device 3423 is tied between the VTs of the first PMOS device 3422 and the second PMOS device 3424 . In one embodiment, the differential VT between the third PMOS device 3423 and the first PMOS device 3422 is achieved at the region 3432 of the third PMOS device 3423 by using modulation or differential implant doping. In one such embodiment, the third PMOS device 3423 has a channel region having a dopant concentration equal to that of the channel region of the first PMOS device 3422. different doping concentrations.

在第二範例中，圖34B繪示依據本發明的另一實施例，基於差異化之閘極電極結構和調變的摻雜而具有差異化的電壓臨界值之三個一組的NMOS裝置和基於差異化之閘極電極結構和調變的摻雜而具有差異化的電壓臨界值之三個一組的PMOS裝置的剖面視圖。 In a second example, FIG. 34B illustrates NMOS devices with differentiated triplets of voltage thresholds based on differentiated gate electrode structures and modulated doping, according to another embodiment of the present invention and Cross-sectional views of PMOS devices with differentiated voltage threshold triplets based on differentiated gate electrode structures and modulated doping.

參照圖34B，第一NMOS裝置3452在半導體作用區域3450之上(諸如，在矽鰭部或基板之上)係鄰接第二NMOS裝置3454和第三NMOS裝置3453。第一NMOS裝置3452、第二NMOS裝置3454和第三NMOS裝置3453包含閘極電介質層3456。第二NMOS裝置3454和第三NMOS裝置3453在結構上具有相同或相似的閘極電極堆疊。但是，第一NMOS裝置3452在結構上具有與第二NMOS裝置3454和第三NMOS裝置3453不同的閘極電極堆疊。特別是，第一NMOS裝置3452包含諸如第一功函數層的第一閘極電極導電層3458、和閘極電極導電填充3460。第二NMOS裝置3454和第三NMOS裝置3453包含諸如第二功函數層的第二閘極電極導電層3459、第一閘極電極導電層3458和閘極電極導電填充3460。第一NMOS裝置3452具有比第二NMOS裝置3454低的VT。在一個這樣的實施例中，第一NMOS裝置3452被稱為”標準的VT”裝置，而第二NMOS裝置3454被稱為”高的VT”裝置。在一實施例中，藉由對相同導電類型裝置使用差異化的閘極堆疊來達成差異化的VT。在一實施例中，第三NMOS裝置3453具有與第一NMOS裝 置3452和第二NMOS裝置3454之VT不同的VT，即使是第三NMOS裝置3453的閘極電極結構和第二NMOS裝置3454的閘極電極結構相同。在一個實施例中，第三NMOS裝置3453的VT係在第一NMOS裝置3452與第二NMOS裝置3454的VT之間。在一實施例中，在第三NMOS裝置3453的區域3462處藉由使用調變或差異化的佈植摻雜來達成第三NMOS裝置3453與第二NMOS裝置3454間之差異化的VT。在一個這樣的實施例中，第三NMOS裝置3453具有一通道區域，該通道區域具有與第二NMOS裝置3454之通道區域的摻雜濃度不同的摻雜濃度。 Referring to FIG. 34B , a first NMOS device 3452 is adjacent to a second NMOS device 3454 and a third NMOS device 3453 over a semiconductor active region 3450 , such as over a silicon fin or substrate. The first NMOS device 3452 , the second NMOS device 3454 and the third NMOS device 3453 include a gate dielectric layer 3456 . The second NMOS device 3454 and the third NMOS device 3453 have the same or similar gate electrode stack in structure. However, the first NMOS device 3452 has a structurally different gate electrode stack than the second NMOS device 3454 and the third NMOS device 3453 . In particular, the first NMOS device 3452 includes a first gate electrode conductive layer 3458 , such as a first work function layer, and a gate electrode conductive fill 3460 . The second NMOS device 3454 and the third NMOS device 3453 include a second gate electrode conductive layer 3459 such as a second work function layer, a first gate electrode conductive layer 3458 and a gate electrode conductive fill 3460 . The first NMOS device 3452 has a lower VT than the second NMOS device 3454 . In one such embodiment, the first NMOS device 3452 is referred to as a "standard VT" device and the second NMOS device 3454 is referred to as a "high VT" device. In one embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, the third NMOS device 3453 has the same The VT of the second NMOS device 3452 and the VT of the second NMOS device 3454 are different, even though the gate electrode structure of the third NMOS device 3453 and the gate electrode structure of the second NMOS device 3454 are the same. In one embodiment, the VT of the third NMOS device 3453 is tied between the VTs of the first NMOS device 3452 and the second NMOS device 3454 . In one embodiment, the differential VT between the third NMOS device 3453 and the second NMOS device 3454 is achieved at the region 3462 of the third NMOS device 3453 by using modulation or differential implant doping. In one such embodiment, the third NMOS device 3453 has a channel region having a different doping concentration than the doping concentration of the channel region of the second NMOS device 3454 .

再次參照圖34B，第一PMOS裝置3472在半導體作用區域3470之上(諸如，在矽鰭部或基板之上)係鄰接第二PMOS裝置3474和第三PMOS裝置3473。第一PMOS裝置3472、第二PMOS裝置3474和第三PMOS裝置3473包含閘極電介質層3476。第二PMOS裝置3474和第三PMOS裝置3473在結構上具有相同或相似的閘極電極堆疊。但是，第一PMOS裝置3472在結構上具有與第二PMOS裝置3474和第三PMOS裝置3473不同的閘極電極堆疊。特別是，第一PMOS裝置3472包含諸如第一功函數層之具有第一厚度的閘極電極導電層3478A、和閘極電極導電填充3480。第二PMOS裝置3474和第三PMOS裝置3473包含具有第二厚度的閘極電極導電層3478B和閘極電極導電填充3480。在一個實施例中，閘極電極導電層3478A和閘極電極導電層3478B具有相同的組成，但是閘極電極導電層3478B的厚 度(第二厚度)大於閘極電極導電層3478A的厚度(第一厚度)。在一實施例中，第一PMOS裝置3472具有比第二PMOS裝置3474高的VT。在一個這樣的實施例中，第一PMOS裝置3472被稱為”標準的VT”裝置，而第二PMOS裝置3474被稱為”低的VT”裝置。在一實施例中，藉由對相同導電類型裝置使用差異化的閘極堆疊來達成差異化的VT。在一實施例中，第三PMOS裝置3473具有與第一PMOS裝置3472和第二PMOS裝置3474之VT不同的VT，即使是第三PMOS裝置3473的閘極電極結構和第二PMOS裝置3474的閘極電極結構相同。在一個實施例中，第三PMOS裝置3473的VT係在第一PMOS裝置3472與第二PMOS裝置3474的VT之間。在一實施例中，在第三PMOS裝置3473的區域3482處藉由使用調變或差異化的佈植摻雜來達成第三PMOS裝置3473與第一PMOS裝置3472間之差異化的VT。在一個這樣的實施例中，第三PMOS裝置3473具有一通道區域，該通道區域具有與第二PMOS裝置3474之通道區域的摻雜濃度不同的摻雜濃度。 Referring again to FIG. 34B , a first PMOS device 3472 is adjacent to a second PMOS device 3474 and a third PMOS device 3473 over a semiconductor active region 3470 , such as over a silicon fin or substrate. The first PMOS device 3472 , the second PMOS device 3474 and the third PMOS device 3473 include a gate dielectric layer 3476 . The second PMOS device 3474 and the third PMOS device 3473 have the same or similar gate electrode stack in structure. However, the first PMOS device 3472 has a structurally different gate electrode stack than the second PMOS device 3474 and the third PMOS device 3473 . In particular, the first PMOS device 3472 includes a gate electrode conductive layer 3478A having a first thickness, such as a first work function layer, and a gate electrode conductive fill 3480 . The second PMOS device 3474 and the third PMOS device 3473 include a gate electrode conductive layer 3478B having a second thickness and a gate electrode conductive fill 3480 . In one embodiment, the gate electrode conductive layer 3478A and the gate electrode conductive layer 3478B have the same composition, but the thickness of the gate electrode conductive layer 3478B is The thickness (second thickness) is greater than the thickness (first thickness) of the gate electrode conductive layer 3478A. In one embodiment, the first PMOS device 3472 has a higher VT than the second PMOS device 3474 . In one such embodiment, the first PMOS device 3472 is referred to as a "standard VT" device and the second PMOS device 3474 is referred to as a "low VT" device. In one embodiment, differentiated VT is achieved by using differentiated gate stacks for devices of the same conductivity type. In one embodiment, the third PMOS device 3473 has a different VT than the VT of the first PMOS device 3472 and the second PMOS device 3474, even though the gate electrode structure of the third PMOS device 3473 and the gate electrode structure of the second PMOS device 3474 The electrodes have the same structure. In one embodiment, the VT of the third PMOS device 3473 is tied between the VTs of the first PMOS device 3472 and the second PMOS device 3474 . In one embodiment, the differential VT between the third PMOS device 3473 and the first PMOS device 3472 is achieved at the region 3482 of the third PMOS device 3473 by using modulation or differential implant doping. In one such embodiment, the third PMOS device 3473 has a channel region having a different doping concentration than the doping concentration of the channel region of the second PMOS device 3474 .

圖35A到35D繪示依據本發明的另一實施例，在製造NMOS裝置之方法中各種操作的剖面視圖，該NMOS裝置基於差異化之閘極電極結構而具有差異化的電壓臨界值。 35A to 35D illustrate cross-sectional views of various operations in a method of fabricating an NMOS device having differentiated voltage thresholds based on differentiated gate electrode structures according to another embodiment of the present invention.

參照圖35A，其中，”標準的VT NMOS”區域(STD VT NMOS)和”高的VT NMOS”區域(HIGH VT NMOS)被顯示如同被分叉(bifurcated)於共同的基板上，製 造積體電路結構的方法包含形成閘極電介質層3506在第一半導體鰭部3502之上和在第二半導體鰭部3504之上，諸如，在第一及第二矽鰭部之上。P型金屬層3508被形成在第一半導體鰭部3502之上和第二半導體鰭部3504之上的閘極電介質層3506上。 Referring to FIG. 35A, in which, the "standard VT NMOS" region (STD VT NMOS) and the "high VT NMOS" region (HIGH VT NMOS) are shown as being bifurcated on a common substrate, fabricated The method of fabricating an integrated circuit structure includes forming a gate dielectric layer 3506 over the first semiconductor fin 3502 and over the second semiconductor fin 3504, such as over the first and second silicon fins. A P-type metal layer 3508 is formed on the gate dielectric layer 3506 over the first semiconductor fin 3502 and over the second semiconductor fin 3504 .

參照圖35B，P型金屬層3508的一部位從第一半導體鰭部3502之上的閘極電介質層3506中被去除，但是P型金屬層3508的一部位3509被保留在第二半導體鰭部3504之上的閘極電介質層3506上。 Referring to FIG. 35B, a portion of the P-type metal layer 3508 is removed from the gate dielectric layer 3506 over the first semiconductor fin 3502, but a portion 3509 of the P-type metal layer 3508 is retained on the second semiconductor fin 3504. on the gate dielectric layer 3506 above.

參照圖35C，N型金屬層3510被形成在第一半導體鰭部3502之上的閘極電介質層3506上，以及在第二半導體鰭部3504之上的閘極電介質層3506上之P型金屬層3508的該部位3509上。在一實施例中，後續的處理包含形成具有電壓臨界值(VT)的第一N型裝置在第一半導體鰭部3502之上，以及形成具有電壓臨界值(VT)的第二N型裝置在第二半導體鰭部3504之上，其中，第二N型裝置的VT係高於第一N型裝置的VT。 Referring to FIG. 35C, an N-type metal layer 3510 is formed on the gate dielectric layer 3506 above the first semiconductor fin 3502, and a P-type metal layer on the gate dielectric layer 3506 above the second semiconductor fin 3504. 3509 on the part of 3508. In one embodiment, subsequent processing includes forming a first N-type device with a voltage threshold (VT) on the first semiconductor fin 3502, and forming a second N-type device with a voltage threshold (VT) on the On the second semiconductor fin 3504, wherein the VT of the second N-type device is higher than the VT of the first N-type device.

參照圖35D，在一實施例中，導電填充金屬層3512被形成在第一N型金屬層3510上。在一個這樣的實施例中，形成導電填充金屬層3512包含使用原子層沉積法(ALD)以六氟化鎢(WF6)先驅物(precursor)來形成含鎢膜。 Referring to FIG. 35D , in one embodiment, a conductive fill metal layer 3512 is formed on the first N-type metal layer 3510 . In one such embodiment, forming the conductive fill metal layer 3512 includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF 6 ) precursor.

圖36A到36D繪示依據本發明的另一實施例，在製造PMOS裝置之方法中各種操作的剖面視圖，該PMOS裝置基於差異化之閘極電極結構而具有差異化的電 壓臨界值。 36A to 36D illustrate cross-sectional views of various operations in a method of fabricating a PMOS device having differentiated electrical conductivity based on differentiated gate electrode structures according to another embodiment of the present invention. Pressure critical value.

參照圖36A，其中，”標準的VT PMOS”區域(STD VT PMOS)和”低的VT PMOS”區域(LOW VT PMOS)被顯示如同被分叉(bifurcated)於共同的基板上，製造積體電路結構的方法包含形成閘極電介質層3606在第一半導體鰭部3602之上和在第二半導體鰭部3604之上，諸如，在第一及第二矽鰭部之上。第一P型金屬層3608被形成在第一半導體鰭部3602之上和第二半導體鰭部3604之上的閘極電介質層3606上。 Referring to FIG. 36A, in which the "Standard VT PMOS" region (STD VT PMOS) and the "Low VT PMOS" region (LOW VT PMOS) are shown as being bifurcated on a common substrate for fabrication of integrated circuits The method of structure includes forming a gate dielectric layer 3606 over the first semiconductor fin 3602 and over the second semiconductor fin 3604, such as over the first and second silicon fins. A first P-type metal layer 3608 is formed on the gate dielectric layer 3606 over the first semiconductor fin 3602 and over the second semiconductor fin 3604 .

參照圖36B，第一P型金屬層3608的一部位從第一半導體鰭部3602之上的閘極電介質層3606中被去除，但是第一P型金屬層3608的一部位3609被保留在第二半導體鰭部3604之上的閘極電介質層3606上。 Referring to FIG. 36B, a portion of the first P-type metal layer 3608 is removed from the gate dielectric layer 3606 over the first semiconductor fin 3602, but a portion 3609 of the first P-type metal layer 3608 remains on the second On the gate dielectric layer 3606 above the semiconductor fin 3604 .

參照圖36C，第二P型金屬層3610被形成在第一半導體鰭部3602之上的閘極電介質層3606上，以及在第二半導體鰭部3604之上的閘極電介質層3606上之第一P型金屬層3608的該部位3609上。在一實施例中，後續的處理包含形成具有電壓臨界值(VT)的第一P型裝置在第一半導體鰭部3602之上，以及形成具有電壓臨界值(VT)的第二P型裝置在第二半導體鰭部3604之上，其中，第二P型裝置的VT係低於第一P型裝置的VT。 Referring to FIG. 36C , a second P-type metal layer 3610 is formed on the gate dielectric layer 3606 over the first semiconductor fin 3602 , and the first P-type metal layer 3606 over the second semiconductor fin 3604 on the part 3609 of the P-type metal layer 3608 . In one embodiment, subsequent processing includes forming a first P-type device with a voltage threshold (VT) on the first semiconductor fin 3602, and forming a second P-type device with a voltage threshold (VT) on the On the second semiconductor fin 3604, wherein the VT of the second P-type device is lower than the VT of the first P-type device.

在一個實施例中，第一P型金屬層3608和第二P型金屬層3610具有相同的組成。在一個實施例中，第一P型金屬層3608和第二P型金屬層3610具有相同的厚度。 在一個實施例中，第一P型金屬層3608和第二P型金屬層3610具有相同的厚度和相同的組成。在一個實施例中，接縫3611係在第一P型金屬層3608與第二P型金屬層3610之間，如同所描述的。 In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same composition. In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same thickness. In one embodiment, the first P-type metal layer 3608 and the second P-type metal layer 3610 have the same thickness and the same composition. In one embodiment, seam 3611 is tied between first P-type metal layer 3608 and second P-type metal layer 3610, as described.

參照圖36D，在一實施例中，導電填充金屬層3612被形成在P型金屬層3610上。在一個這樣的實施例中，形成導電填充金屬層3612包含使用原子層沉積法(ALD)以六氟化鎢(WF6)先驅物(precursor)來形成含鎢膜。在一個實施例中，在形成導電填充金屬層3612之前，N型金屬層3614被形成在P型金屬層3610上，如同所描述的。在一個這樣的實施例中，N型金屬層3614為雙金屬閘極置換處理方案的加工品。 Referring to FIG. 36D , in one embodiment, a conductive fill metal layer 3612 is formed on the P-type metal layer 3610 . In one such embodiment, forming the conductive fill metal layer 3612 includes forming a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF 6 ) precursor. In one embodiment, an N-type metal layer 3614 is formed on the P-type metal layer 3610 prior to forming the conductive fill metal layer 3612, as described. In one such embodiment, the N-type metal layer 3614 is the artifact of a dual metal gate replacement processing scheme.

在另一態樣中，說明用於互補式金屬氧化物半導體(CMOS)半導體裝置的金屬閘極結構。在範例中，圖37繪示依據本發明的一實施例，具有P/N接面之積體電路結構的剖面視圖。 In another aspect, a metal gate structure for a complementary metal oxide semiconductor (CMOS) semiconductor device is described. In an example, FIG. 37 shows a cross-sectional view of an integrated circuit structure with a P/N junction according to an embodiment of the present invention.

參照圖37，積體電路結構3700包含半導體基板3702，該半導體基板3702具有從那裏突出之第一半導體鰭部3706的N井區域3704和具有從那裏突出之第二半導體鰭部3710的P井區域3708。第一半導體鰭部3706與第二半導體鰭部3710被間隔開。在半導體基板3702中，N井區域3704係直接鄰接於P井區域3708。溝槽隔離結構3712係在第一3706與第二3710半導體鰭部之外和之間的半導體基板3702上。第一3706與第二3710半導體鰭部在溝槽隔離結構 3712之上延伸。 37, an integrated circuit structure 3700 includes a semiconductor substrate 3702 having an N-well region 3704 having a first semiconductor fin 3706 protruding therefrom and a P-well region having a second semiconductor fin 3710 protruding therefrom 3708. The first semiconductor fin 3706 is spaced apart from the second semiconductor fin 3710 . In semiconductor substrate 3702 , N-well region 3704 is directly adjacent to P-well region 3708 . Trench isolation structures 3712 are attached to the semiconductor substrate 3702 outside and between the first 3706 and second 3710 semiconductor fins. First 3706 and second 3710 semiconductor fins in trench isolation structure 3712 above the extension.

閘極電介質層3714係在第一3706與第二3710半導體鰭部上以及在溝槽隔離結構3712上。閘極電介質層3714在第一3706與第二3710半導體鰭部之間係連續的。導電層3716係在第一半導體鰭部3706之上的閘極電介質層3714之上，但是不在第二半導體鰭部3710之上。在一個實施例中，導電層3716包含鈦、氮和氧。p型金屬閘極層3718係在第一半導體鰭部3706之上的導電層3716之上，但是不在第二半導體鰭部3710之上。p型金屬閘極層3718係進一步在第一半導體鰭部3706與第二半導體鰭部3710間之溝槽隔離結構3712的一部位上而不是全部。n型金屬閘極層3720係在第二半導體鰭部3710之上、在第一半導體鰭部3706與第二半導體鰭部3710之間的溝槽隔離結構3712之上、以及在p型金屬閘極層3718之上。 A gate dielectric layer 3714 is placed on the first 3706 and second 3710 semiconductor fins and on the trench isolation structure 3712 . The gate dielectric layer 3714 is continuous between the first 3706 and second 3710 semiconductor fins. A conductive layer 3716 is tied over the gate dielectric layer 3714 over the first semiconductor fin 3706 , but not over the second semiconductor fin 3710 . In one embodiment, conductive layer 3716 includes titanium, nitrogen, and oxygen. The p-type metal gate layer 3718 is over the conductive layer 3716 over the first semiconductor fin 3706 , but not over the second semiconductor fin 3710 . The p-type metal gate layer 3718 is further on a part but not all of the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710 . The n-type metal gate layer 3720 is over the second semiconductor fin 3710, over the trench isolation structure 3712 between the first semiconductor fin 3706 and the second semiconductor fin 3710, and over the p-type metal gate Above layer 3718.

在一個實施例中，層間電介質(ILD)層3722係在第一半導體鰭部3706和第二半導體鰭部3710之外部上的溝槽隔離結構3712之上。ILD層3722具有開口3724，開口3724使第一3706與第二3710半導體鰭部暴露出。在一個這樣的實施例中，導電層3716、p型金屬閘極層3718、及n型金屬閘極層3720係進一步沿著開口3724的側壁3726形成，如同所描述的。在一特別的實施例中，導電層3716具有沿著p型金屬閘極層3718的頂部表面3719之下的開口3724之側壁3726的頂部表面3717和沿著開口3724的側壁3726之n型金屬閘極層3720的頂部表面3721，如同所描述 的。 In one embodiment, an interlayer dielectric (ILD) layer 3722 is over the trench isolation structure 3712 on the exterior of the first semiconductor fin 3706 and the second semiconductor fin 3710 . The ILD layer 3722 has an opening 3724 exposing the first 3706 and second 3710 semiconductor fins. In one such embodiment, conductive layer 3716, p-type metal gate layer 3718, and n-type metal gate layer 3720 are further formed along sidewalls 3726 of opening 3724, as described. In a particular embodiment, the conductive layer 3716 has a top surface 3717 along the sidewalls 3726 of the opening 3724 below the top surface 3719 of the p-type metal gate layer 3718 and an n-type metal gate along the sidewalls 3726 of the opening 3724. Top surface 3721 of polar layer 3720, as described of.

在一個實施例中，P型金屬閘極層3718包含鈦和氮。在一個實施例中，n型金屬閘極層3720包含鈦和鋁。在一個實施例中，導電填充金屬層3730係在n型金屬閘極層3720之上，如同所描述的。在一個這樣的實施例中，導電填充金屬層3730包含鎢。在一特別的實施例中，導電填充金屬層3730包含95或更大原子百分率的鎢以及0.1到2原子百分率的氟。在一個實施例中，閘極電介質層3714具有包含鉿及氧的一層。在一個實施例中，熱或化學氧化物層3732係在第一3706與第二3710半導體鰭部的上部部位之間，如同所描述的。在一個實施例中，半導體基板3702為塊狀矽半導體基板。 In one embodiment, P-type metal gate layer 3718 includes titanium and nitrogen. In one embodiment, n-type metal gate layer 3720 includes titanium and aluminum. In one embodiment, conductive fill metal layer 3730 is tied over n-type metal gate layer 3720, as described. In one such embodiment, conductive fill metal layer 3730 includes tungsten. In a particular embodiment, conductive fill metal layer 3730 includes 95 atomic percent or greater of tungsten and 0.1 to 2 atomic percent of fluorine. In one embodiment, the gate dielectric layer 3714 has a layer comprising hafnium and oxygen. In one embodiment, a thermal or chemical oxide layer 3732 is interposed between the upper portions of the first 3706 and second 3710 semiconductor fins, as described. In one embodiment, the semiconductor substrate 3702 is a bulk silicon semiconductor substrate.

現在僅參照圖37的右手側，依據本發明的一實施例，積體電路結構包含半導體基板3702，該半導體基板3702具有從那裏突出之半導體鰭部3706的N井區域3704。溝槽隔離結構3712係在半導體鰭部3706之周圍的半導體基板3702上。半導體鰭部3706在溝槽隔離結構3712之上延伸。閘極電介質層3714係在半導體鰭部3706之上。導電層3716係在半導體鰭部3706之上的閘極電介質層3714之上。在一個實施例中，導電層3716包含鈦、氮和氧。P型金屬閘極層3718係在半導體鰭部3706之上的導電層3716之上。 Referring now only to the right hand side of FIG. 37 , in accordance with one embodiment of the present invention, an integrated circuit structure includes a semiconductor substrate 3702 having an N-well region 3704 with semiconductor fins 3706 protruding therefrom. Trench isolation structures 3712 are formed on the semiconductor substrate 3702 around the semiconductor fins 3706 . Semiconductor fins 3706 extend over trench isolation structures 3712 . A gate dielectric layer 3714 is tied over the semiconductor fin 3706 . Conductive layer 3716 is tied over gate dielectric layer 3714 over semiconductor fin 3706 . In one embodiment, conductive layer 3716 includes titanium, nitrogen, and oxygen. P-type metal gate layer 3718 is overlying conductive layer 3716 over semiconductor fin 3706 .

在一個實施例中，層間電介質(ILD)層3722係在溝槽隔離結構3712之上。ILD層具有開口，而開口使 半導體鰭部3706暴露出。導電層3716和P型金屬閘極層3718係進一步沿著開口的側壁形成。在一個這樣的實施例中，導電層3716具有沿著p型金屬閘極層3718的頂部表面之下的開口之側壁的頂部表面。在一個實施例中，p型金屬閘極層3718係在導電層3716上。在一個實施例中，p型金屬閘極層3718包含鈦和氮。在一個實施例中，導電填充金屬層3730係在p型金屬閘極層3718之上。在一個這樣的實施例中，導電填充金屬層3730包含鎢。在一特別的這樣的實施例中，導電填充金屬層3730係由95或更大原子百分率的鎢以及0.1到2原子百分率的氟組成。在一個實施例中，閘極電介質層3714包含具有鉿及氧的一層。 In one embodiment, an interlayer dielectric (ILD) layer 3722 is tied over the trench isolation structure 3712 . The ILD layer has openings, and the openings enable Semiconductor fins 3706 are exposed. The conductive layer 3716 and the P-type metal gate layer 3718 are further formed along the sidewalls of the opening. In one such embodiment, the conductive layer 3716 has a top surface along the sidewalls of the opening below the top surface of the p-type metal gate layer 3718 . In one embodiment, p-type metal gate layer 3718 is tied to conductive layer 3716 . In one embodiment, p-type metal gate layer 3718 includes titanium and nitrogen. In one embodiment, a conductive fill metal layer 3730 is tied over the p-type metal gate layer 3718 . In one such embodiment, conductive fill metal layer 3730 includes tungsten. In a particular such embodiment, the conductive fill metal layer 3730 is composed of 95 atomic percent or greater of tungsten and 0.1 to 2 atomic percent of fluorine. In one embodiment, the gate dielectric layer 3714 includes a layer comprising hafnium and oxygen.

圖38A到38H繪示依據本發明的一實施例，在使用雙金屬閘極置換閘極處理流程來製造積體電路結構之方法中各種操作的剖面視圖。 38A through 38H illustrate cross-sectional views of various operations in a method of fabricating an integrated circuit structure using a dual metal gate replacement gate process flow, in accordance with an embodiment of the present invention.

參照圖38A，其顯示NMOS(N型)區域和PMOS(P型)區域，製造積體電路結構的方法包含形成在基板3800之上的第一3804與第二3806半導體鰭部之上的層間電介質(ILD)層3802。開口3808被形成在ILD層3802中，該開口3808使第一3804與第二3806半導體鰭部暴露出。在一個實施例中，藉由去除閘極佔位件或假性閘極結構來形成開口3808，而閘極佔位件或假性閘極結構係初始在第一3804與第二3806半導體鰭部之上的適當位置處。 Referring to FIG. 38A , which shows NMOS (N-type) regions and PMOS (P-type) regions, a method of fabricating an integrated circuit structure includes forming an interlayer dielectric over first 3804 and second 3806 semiconductor fins over a substrate 3800 (ILD) layer 3802. An opening 3808 is formed in the ILD layer 3802 that exposes the first 3804 and second 3806 semiconductor fins. In one embodiment, the opening 3808 is formed by removing the gate placeholders or dummy gate structures that were initially formed on the first 3804 and second 3806 semiconductor fins. appropriate position above.

閘極電介質層3810係形成在開口3808中以及在第一3804與第二3806半導體鰭部之上和在溝槽隔離結構 3812之在第一3804與第二3806半導體鰭部之間的部位上。在一個實施例中，閘極電介質層3810係形成在熱或化學氧化物層3811(諸如，氧化矽或二氧化矽層)上，而熱或化學氧化物層3811係形成在第一3804與第二3806半導體鰭部之上，如同所描述的。在另一實施例中，閘極電介質層3810係直接形成在第一3804與第二3806半導體鰭部之上。 A gate dielectric layer 3810 is formed in the opening 3808 and over the first 3804 and second 3806 semiconductor fins and in the trench isolation structure 3812 at the location between the first 3804 and second 3806 semiconductor fins. In one embodiment, the gate dielectric layer 3810 is formed on a thermal or chemical oxide layer 3811, such as a silicon oxide or silicon dioxide layer, and the thermal or chemical oxide layer 3811 is formed on the first 3804 and the second Two 3806 semiconductor fins, as described. In another embodiment, the gate dielectric layer 3810 is formed directly over the first 3804 and second 3806 semiconductor fins.

導電層3814係形成在形成於第一3804與第二3806半導體鰭部之上的閘極電介質層3810之上。在一個實施例中，導電層3814包含鈦、氮和氧。p型金屬閘極層3816係形成在形成於第一半導體鰭部3804之上與第二半導體鰭部3806之上的導電層3814之上。 A conductive layer 3814 is formed over the gate dielectric layer 3810 formed over the first 3804 and second 3806 semiconductor fins. In one embodiment, conductive layer 3814 includes titanium, nitrogen, and oxygen. The p-type metal gate layer 3816 is formed over the conductive layer 3814 formed over the first semiconductor fin 3804 and over the second semiconductor fin 3806 .

參照圖38B，電介質蝕刻停止層3818係形成在p型金屬閘極層3816上。在一個實施例中，電介質蝕刻停止層3818包含第一矽氧化物層(例如，SiO2)、該第一矽氧化物層上的鋁氧化物層(例如，Al2O3)、以及該鋁氧化物層上的第二矽氧化物層(例如，SiO2)。 Referring to FIG. 38B , a dielectric etch stop layer 3818 is formed on the p-type metal gate layer 3816 . In one embodiment, dielectric etch stop layer 3818 includes a first silicon oxide layer (eg, SiO 2 ), an aluminum oxide layer (eg, Al 2 O 3 ) on the first silicon oxide layer, and the aluminum A second silicon oxide layer (eg, SiO 2 ) on the oxide layer.

參照圖38C，遮罩3820係形成在圖38B的結構之上。該遮罩3820覆蓋PMOS區域而且使NMOS區域暴露出。 Referring to Figure 38C, a mask 3820 is formed over the structure of Figure 38B. The mask 3820 covers the PMOS region and leaves the NMOS region exposed.

參照圖38D，電介質蝕刻停止層3818、p型金屬閘極層3816和導電層3814被圖案化以提供圖案化後的電介質蝕刻停止層3819、在第一半導體鰭部3804之上但是不在第二半導體鰭部3806之上的圖案化後導電層3815之上的圖案化後P型金屬閘極層3817。在一實施例中，導電層 3814在該圖案化期間保護第二半導體鰭部3806。 38D, the dielectric etch stop layer 3818, the p-type metal gate layer 3816 and the conductive layer 3814 are patterned to provide a patterned dielectric etch stop layer 3819 over the first semiconductor fin 3804 but not over the second semiconductor fin 3819. Patterned P-type metal gate layer 3817 over patterned conductive layer 3815 over fins 3806 . In one embodiment, the conductive layer 3814 protects the second semiconductor fin 3806 during this patterning.

參照圖38E，遮罩3820從圖38D的結構中被去除。參照圖38F，圖案化後的電介質蝕刻停止層3819從圖38E的結構中被去除。 Referring to Figure 38E, mask 3820 is removed from the structure of Figure 38D. Referring to Figure 38F, the patterned dielectric etch stop layer 3819 is removed from the structure of Figure 38E.

參照圖38G，n型金屬閘極層3822係形成在第二半導體鰭部3806之上、在溝槽隔離結構3812介於第一3804與第二3806半導體鰭部之間的部位之上、以及在圖案化後的p型金屬閘極層3817之上。在一實施例中，圖案化後的導電層3815、圖案化後的p型金屬閘極層3817、以及n型金屬閘極層3822被進一步沿著開口3808的側壁3824形成。在一個這樣的實施例中，圖案化後的導電層3815具有沿著圖案化後p型金屬閘極層3817的頂部表面之下的開口3808之側壁3824的頂部表面以及n型金屬閘極層3822沿著開口3808之側壁3824的頂部表面。 Referring to FIG. 38G, the n-type metal gate layer 3822 is formed on the second semiconductor fin 3806, on the trench isolation structure 3812 between the first semiconductor fin 3804 and the second semiconductor fin 3806, and on the on the patterned p-type metal gate layer 3817 . In one embodiment, the patterned conductive layer 3815 , the patterned p-type metal gate layer 3817 , and the n-type metal gate layer 3822 are further formed along the sidewall 3824 of the opening 3808 . In one such embodiment, the patterned conductive layer 3815 has a top surface along the sidewall 3824 of the opening 3808 below the top surface of the patterned p-type metal gate layer 3817 and the n-type metal gate layer 3822 along the top surface of the sidewall 3824 of the opening 3808 .

參照圖38H，導電填充金屬層3826係形成在n型金屬閘極層3822之上。在一個實施例中，藉由使用原子層沉積法(ALD)以六氟化鎢(WF6)先驅物來沉積含鎢膜而形成導電填充金屬層3826。 Referring to FIG. 38H , a conductive fill metal layer 3826 is formed over the n-type metal gate layer 3822 . In one embodiment, conductive fill metal layer 3826 is formed by depositing a tungsten-containing film using atomic layer deposition (ALD) with a tungsten hexafluoride (WF 6 ) precursor.

在另一態樣中，說明用於互補式金屬氧化物半導體(CMOS)半導體裝置的雙矽化物(dual silicide)結構。做為代表性處理流程，圖39A到39H繪示依據本發明的一實施例，代表在製造以雙矽化物為基礎的積體電路之方法中各種操作的剖面視圖。 In another aspect, a dual silicide structure for a complementary metal oxide semiconductor (CMOS) semiconductor device is described. As a representative process flow, FIGS. 39A through 39H illustrate cross-sectional views representing various operations in a method of fabricating a dual-silicide-based integrated circuit, in accordance with one embodiment of the present invention.

參照圖39A，其中，NMOS區域和PMOS區域 被顯示為分叉於共同基板上，製造積體電路結構的方法包含形成第一閘極結構3902(其可以包含電介質側壁間隔層3903)在諸如第一矽鰭部的第一鰭部3904之上。第二閘極結構3952(其可以包含電介質側壁間隔層3953)係形成在諸如第二矽鰭部的第二鰭部3954之上。絕緣材料3906係形成鄰接於第一鰭部3904之上的第一閘極結構3902以及鄰接於第二鰭部3954之上的第二閘極結構3952。在一個實施例中，在雙矽化物製程中，絕緣材料3906為犧牲材料並且被使用作為遮罩。 Referring to Figure 39A, where the NMOS region and the PMOS region Shown as bifurcating on a common substrate, the method of fabricating the integrated circuit structure includes forming a first gate structure 3902 (which may include a dielectric sidewall spacer 3903) over a first fin 3904, such as a first silicon fin . A second gate structure 3952 (which may include dielectric sidewall spacers 3953) is formed over a second fin 3954, such as a second silicon fin. The insulating material 3906 forms the first gate structure 3902 adjacent to the first fin 3904 and the second gate structure 3952 adjacent to the second fin 3954 . In one embodiment, the insulating material 3906 is a sacrificial material and is used as a mask in a dual silicide process.

參照圖39B，絕緣材料3906的第一部位從第一鰭部3904之上但是未從第二鰭部3954之上被去除，以使第一鰭部3904鄰接於第一閘極結構3902的第一3908和第二3910源極或汲極區域暴露出。在一實施例中，第一3908和第二3910源極或汲極區域為形成在第一鰭部3904的凹入部位之內的磊晶區域，如同所描述的。在一個這樣的實施例中，第一3908和第二3910源極或汲極區域包含矽和鍺。 Referring to FIG. 39B , a first portion of insulating material 3906 is removed from over first fin 3904 but not over second fin 3954 such that first fin 3904 is adjacent to the first portion of first gate structure 3902 . 3908 and a second 3910 source or drain region are exposed. In one embodiment, the first 3908 and second 3910 source or drain regions are epitaxial regions formed within the recesses of the first fin 3904, as described. In one such embodiment, the first 3908 and second 3910 source or drain regions comprise silicon and germanium.

參照圖39C，第一金屬矽化物層3912係形成在第一鰭部3904的第一3908和第二3910源極或汲極區域上。在一個實施例中，藉由在圖39B的結構上沉積包含鎳和鉑的一層、使包含鎳和鉑的該一層退火、以及去除包含鎳和鉑的該一層之未起反應的部位(unreacted portion)來形成該第一金屬矽化物層3912。 Referring to FIG. 39C , a first metal silicide layer 3912 is formed on the first 3908 and second 3910 source or drain regions of the first fin 3904 . In one embodiment, by depositing a layer comprising nickel and platinum on the structure of FIG. 39B , annealing the layer comprising nickel and platinum, and removing unreacted portions of the layer comprising nickel and platinum ) to form the first metal silicide layer 3912.

參照圖39D，在形成該第一金屬矽化物層3912之後，絕緣材料3906的第二部位從第二鰭部3954之上 被去除，以使第二鰭部3954鄰接於第二閘極結構3952的第三3958和第四3960源極或汲極區域暴露出。在一實施例中，第三3958和第四3960源極或汲極區域係形成在第二鰭部3954之內，諸如在第二矽鰭部之內，如同所描述的。然而，在另一實施例中，第三3958和第四3960源極或汲極區域為形成在第二鰭部3954的凹入部位之內的磊晶區域。在一個這樣的實施例中，第三3958和第四3960源極或汲極區域包含矽。 Referring to FIG. 39D , after forming the first metal silicide layer 3912 , the second portion of insulating material 3906 is removed from above the second fin 3954 are removed such that the third 3958 and fourth 3960 source or drain regions of the second fin 3954 adjacent to the second gate structure 3952 are exposed. In one embodiment, the third 3958 and fourth 3960 source or drain regions are formed within the second fin 3954, such as within the second silicon fin, as described. However, in another embodiment, the third 3958 and fourth 3960 source or drain regions are epitaxial regions formed within the recesses of the second fin 3954 . In one such embodiment, the third 3958 and fourth 3960 source or drain regions comprise silicon.

參照圖39E，第一金屬層3914係形成在圖39D的結構上，亦即，在第一3908、第二3910、第三3958和第四3960源極或汲極區域上。第二金屬矽化物層3962然後被形成在第二鰭部3954的第三3958和第四3960源極或汲極區域上。第二金屬矽化物層3962係從第一金屬層3914，例如使用退火製程所形成的。在一實施例中，第二金屬矽化物層3962的組成與第一金屬矽化物層3912的組成不同。在一個實施例中，第一金屬層3914為或包含鈦層。在一實施例中，第一金屬層3914係形成為共形金屬層，例如，與圖39D的開口溝槽共形，如同所描述的。 Referring to FIG. 39E , a first metal layer 3914 is formed on the structure of FIG. 39D , ie, on the first 3908 , second 3910 , third 3958 and fourth 3960 source or drain regions. A second metal suicide layer 3962 is then formed on the third 3958 and fourth 3960 source or drain regions of the second fin 3954 . The second metal silicide layer 3962 is formed from the first metal layer 3914, eg, using an annealing process. In one embodiment, the composition of the second metal silicide layer 3962 is different from that of the first metal silicide layer 3912 . In one embodiment, the first metal layer 3914 is or includes a titanium layer. In one embodiment, the first metal layer 3914 is formed as a conformal metal layer, eg, conformal to the open trench of FIG. 39D, as described.

參照圖39F，在一實施例中，第一金屬層3914被凹入而在第一3908、第二3910、第三3958和第四3960源極或汲極區域的各者之上形成U型金屬層3916。 39F, in one embodiment, the first metal layer 3914 is recessed to form a U-shaped metal layer over each of the first 3908, second 3910, third 3958, and fourth 3960 source or drain regions. Layer 3916.

參照圖39G，在一實施例中，第二金屬層3918被形成在圖39F之結構的U型金屬層3916上。在一實施例中，第二金屬層3918的組成與U型金屬層3916的組成 不同。 Referring to FIG. 39G, in one embodiment, a second metal layer 3918 is formed on the U-shaped metal layer 3916 of the structure of FIG. 39F. In one embodiment, the composition of the second metal layer 3918 is the same as that of the U-shaped metal layer 3916 different.

參照圖39H，在一實施例中，第三金屬層3920被形成在圖39G之結構的第二金屬層3918上。在一實施例中，第三金屬層3920具有和U型金屬層3916之組成相同的組成。 Referring to FIG. 39H, in one embodiment, a third metal layer 3920 is formed on the second metal layer 3918 of the structure of FIG. 39G. In one embodiment, the third metal layer 3920 has the same composition as that of the U-shaped metal layer 3916 .

再次參照圖39H，依據本發明的一實施例，積體電路結構3900包含基板之上的P型半導體裝置(PMOS)。P型半導體裝置包含諸如第一矽鰭部的第一鰭部3904。可以領會到第一鰭部具有頂部(顯示為3904A)和側壁(例如，進入和離開頁面)。第一閘極電極3902包含在第一鰭部3904的頂部3904A之上並且橫向鄰接第一鰭部3904的側壁之第一閘極電介質層，而且包含在第一鰭部3904的頂部3904A之上的第一閘極電介質層之上並且橫向鄰接第一鰭部3904的側壁之第一閘極電極。第一閘極電極3902具有第一側3902A和與第一側3902A對立的第二側3902B。 Referring again to FIG. 39H , according to an embodiment of the present invention, an integrated circuit structure 3900 includes a P-type semiconductor device (PMOS) on a substrate. The P-type semiconductor device includes a first fin 3904 such as a first silicon fin. It can be appreciated that the first fin has a top (shown as 3904A) and sidewalls (eg, entering and exiting the page). The first gate electrode 3902 includes a first gate dielectric layer over the top 3904A of the first fin 3904 and laterally adjoining the sidewalls of the first fin 3904, and includes a layer over the top 3904A of the first fin 3904. The first gate electrode overlies the first gate dielectric layer and laterally adjoins the sidewall of the first fin 3904 . The first gate electrode 3902 has a first side 3902A and a second side 3902B opposite the first side 3902A.

第一3908和第二3910半導體源極或汲極區域係分別鄰接第一閘極電極3902的第一側3902A和第二側3902B。第一3930和第二3932溝槽接觸結構係分別在鄰接第一閘極電極3902之第一側3902A和第二側3902B的第一3908和第二3910半導體源極或汲極區域之上。第一金屬矽化物層3912係分別直接在第一3930和第二3932溝槽接觸結構與第一3908和第二3910半導體源極或汲極區域之間。 The first 3908 and second 3910 semiconductor source or drain regions adjoin the first side 3902A and the second side 3902B of the first gate electrode 3902, respectively. The first 3930 and second 3932 trench contact structures are respectively above the first 3908 and second 3910 semiconductor source or drain regions adjacent to the first side 3902A and the second side 3902B of the first gate electrode 3902 . The first metal silicide layer 3912 is directly between the first 3930 and second 3932 trench contact structures and the first 3908 and second 3910 semiconductor source or drain regions, respectively.

積體電路結構3900包含基板之上的N型半導體裝置(NMOS)。N型半導體裝置包含諸如第二矽鰭部的第 二鰭部3954。可以領會到第二鰭部具有頂部(顯示為3954A)和側壁(例如，進入和離開頁面)。第二閘極電極3952包含在第二鰭部3954的頂部3954A之上並且橫向鄰接第二鰭部3954的側壁之第二閘極電介質層，而且包含在第二鰭部3954的頂部3954A之上的第二閘極電介質層之上並且橫向鄰接第二鰭部3954的側壁之第二閘極電極。第二閘極電極3952具有第一側3952A和與第一側3952A對立的第二側3952B。 The integrated circuit structure 3900 includes an N-type semiconductor device (NMOS) on a substrate. The N-type semiconductor device includes a first silicon fin such as a second Two fins 3954. It can be appreciated that the second fin has a top (shown as 3954A) and sidewalls (eg, entering and exiting the page). The second gate electrode 3952 includes a second gate dielectric layer over the top 3954A of the second fin 3954 and laterally adjoining the sidewalls of the second fin 3954 , and includes a layer over the top 3954A of the second fin 3954 . The second gate electrode overlies the second gate dielectric layer and laterally adjoins the sidewall of the second fin 3954 . The second gate electrode 3952 has a first side 3952A and a second side 3952B opposite the first side 3952A.

第三3958和第四3960半導體源極或汲極區域係分別鄰接第二閘極電極3952的第一側3952A和第二側3952B。第三3970和第四3972溝槽接觸結構係分別在鄰接第二閘極電極3952之第一側3952A和第二側3952B的第三3958和第四3960半導體源極或汲極區域之上。第二金屬矽化物層3962係分別直接在第三3970和第四3972溝槽接觸結構與第三3958和第四3960半導體源極或汲極區域之間。在一實施例中，第一金屬矽化物層3912包含不包含在第二金屬矽化物層3962中的至少一金屬物種(species)。 The third 3958 and fourth 3960 semiconductor source or drain regions adjoin the first side 3952A and the second side 3952B of the second gate electrode 3952, respectively. The third 3970 and fourth 3972 trench contact structures are respectively over the third 3958 and fourth 3960 semiconductor source or drain regions adjacent to the first side 3952A and the second side 3952B of the second gate electrode 3952 . The second metal silicide layer 3962 is directly between the third 3970 and fourth 3972 trench contact structures and the third 3958 and fourth 3960 semiconductor source or drain regions, respectively. In one embodiment, the first metal silicide layer 3912 includes at least one metal species not included in the second metal silicide layer 3962 .

在一個實施例中，第二金屬矽化物層3962包含鈦和矽。第一金屬矽化物層3912包含鎳、鉑和矽。在一個實施例中，第一金屬矽化物層3912另包含鍺。在一個實施例中，第一金屬矽化物層3912另包含鈦，例如，如同在第二金屬矽化物層3962與第一金屬層3914的後續形成期間被結合入第一金屬矽化物層3912中。在一個這樣的實施例中，已被形成在PMOS源極或汲極區域上的矽化物層係藉 由用來形成矽化物區域於NMOS源極或汲極區域上的退火製程而被進一步修改。這可能會導致在PMOS源極或汲極區域上的矽化物層具有所有矽化金屬的分數百分率(fractional percentage)。然而，在其他實施例中，已被形成在PMOS源極或汲極區域上之這樣的矽化物層並不被或者並不實質被用來形成矽化物區域於NMOS源極或汲極區域上的退火製程改變。 In one embodiment, the second metal suicide layer 3962 includes titanium and silicon. The first metal silicide layer 3912 includes nickel, platinum and silicon. In one embodiment, the first metal silicide layer 3912 further includes germanium. In one embodiment, first metal silicide layer 3912 further comprises titanium, eg, as incorporated into first metal silicide layer 3912 during subsequent formation of second metal silicide layer 3962 and first metal layer 3914 . In one such embodiment, the silicide layer that has been formed over the PMOS source or drain regions is It is further modified by the annealing process used to form silicide regions on the NMOS source or drain regions. This may result in the silicide layer having a fractional percentage of all silicide metal on the PMOS source or drain regions. However, in other embodiments, such silicide layers that have been formed on the PMOS source or drain regions are not, or are not substantially, used to form silicide regions on the NMOS source or drain regions. Annealing process changes.

在一個實施例中，第一3908和第二3910半導體源極或汲極區域為包含矽和鍺之第一和第二嵌入的半導體源極或汲極區域。在一個這樣的實施例中，第三3958和第四3960半導體源極或汲極區域為包含矽之第三和第四嵌入的半導體源極或汲極區域。在另一實施例中，第三3958和第四3960半導體源極或汲極區域被形成在鰭部3954中而且不是嵌入的磊晶區域。 In one embodiment, the first 3908 and second 3910 semiconductor source or drain regions are first and second embedded semiconductor source or drain regions comprising silicon and germanium. In one such embodiment, the third 3958 and fourth 3960 semiconductor source or drain regions are third and fourth embedded semiconductor source or drain regions comprising silicon. In another embodiment, the third 3958 and fourth 3960 semiconductor source or drain regions are formed in the fin 3954 and are not embedded epitaxial regions.

在一實施例中，第一3930、第二3932、第三3970和第四3972溝槽接觸結構皆包含U型金屬層3916以及在整個U型金屬層3916上和在整個U型金屬層3916之上的T型金屬層3918。在一個實施例中，U型金屬層3916包含鈦，而且T型金屬層3918包含鈷。在一個實施例中，第一3930、第二3932、第三3970和第四3972溝槽接觸結構皆進一步包含T型金屬層3918上的第三金屬層3920。在一個實施例中，第三金屬層3920和U型金屬層3916具有相同的組成。在一特別的實施例中，第三金屬層3920和U型金屬層3916包含鈦，而且T型金屬層3918包含鈷。 In one embodiment, the first 3930, the second 3932, the third 3970 and the fourth 3972 trench contact structures all include the U-shaped metal layer 3916 and on and between the entire U-shaped metal layer 3916. T-shaped metal layer 3918 on. In one embodiment, U-shaped metal layer 3916 includes titanium and T-shaped metal layer 3918 includes cobalt. In one embodiment, each of the first 3930 , second 3932 , third 3970 and fourth 3972 trench contact structures further includes a third metal layer 3920 on the T-shaped metal layer 3918 . In one embodiment, the third metal layer 3920 and the U-shaped metal layer 3916 have the same composition. In a particular embodiment, the third metal layer 3920 and the U-shaped metal layer 3916 include titanium, and the T-shaped metal layer 3918 includes cobalt.

在另一態樣中，例如源極或汲極區域的溝槽接觸結構被說明。在一範例中，圖40A繪示依據本發明的一實施例，具有用於NMOS裝置之溝槽接觸的積體電路結構的剖面視圖。圖40B繪示依據本發明的另一實施例，具有用於PMOS裝置之溝槽接觸的積體電路結構的剖面視圖。 In another aspect, trench contact structures such as source or drain regions are illustrated. In one example, FIG. 40A shows a cross-sectional view of an integrated circuit structure with trench contacts for NMOS devices according to an embodiment of the present invention. 40B shows a cross-sectional view of an integrated circuit structure with trench contacts for a PMOS device according to another embodiment of the present invention.

參照圖40A，積體電路結構4000包含諸如矽鰭部的鰭部4002。閘極電介質層4004係在鰭部4002之上。閘極電極4006係在閘極電介質層4004之上。在一實施例中，閘極電極4006包含共形導電層4008和導電填充4010。在一實施例中，電介質蓋部4012係在閘極電極4006之上以及在閘極電介質層4004之上。閘極電極具有第一側4006A和與第一側4006A對立的第二側4006B。電介質間隔層4013係沿著閘極電極4006的側壁。在一個實施例中，閘極電介質層4004係進一步在電介質間隔層4013中的第一個與閘極電極4006的第一側4006A之間以及在電介質間隔層4013中的第二個與閘極電極4006的第二側4006B之間，如同所描述的。在一實施例中，雖然未被描述出，薄的氧化物層，諸如熱或化學氧化矽或二氧化矽層，係在鰭部4002與閘極電介質層4004之間。 Referring to FIG. 40A, an integrated circuit structure 4000 includes fins 4002, such as silicon fins. A gate dielectric layer 4004 is tied over the fins 4002 . Gate electrode 4006 is tied over gate dielectric layer 4004 . In one embodiment, the gate electrode 4006 includes a conformal conductive layer 4008 and a conductive fill 4010 . In one embodiment, a dielectric cap 4012 is placed over the gate electrode 4006 and over the gate dielectric layer 4004 . The gate electrode has a first side 4006A and a second side 4006B opposite the first side 4006A. A dielectric spacer 4013 is along the sidewalls of the gate electrode 4006 . In one embodiment, the gate dielectric layer 4004 is further between a first one of the dielectric spacers 4013 and the first side 4006A of the gate electrode 4006 and a second one of the dielectric spacers 4013 and the gate electrode 4006 between the second side 4006B, as described. In one embodiment, although not depicted, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is tied between the fin 4002 and the gate dielectric layer 4004 .

第一4014和第二4016半導體源極或汲極區域係分別鄰接閘極電極4006的第一側4006A和第二側4006B之間。在一個實施例中，第一4014和第二4016半導體源極或汲極區域係在鰭部4002中，如同所描述的。然而，在另 一實施例中，第一4014和第二4016半導體源極或汲極區域為形成在鰭部4002的凹部中之嵌入的磊晶區域。 The first 4014 and second 4016 semiconductor source or drain regions adjoin the gate electrode 4006 between the first side 4006A and the second side 4006B, respectively. In one embodiment, the first 4014 and second 4016 semiconductor source or drain regions are tied in the fin 4002 as described. However, in another In one embodiment, the first 4014 and second 4016 semiconductor source or drain regions are embedded epitaxial regions formed in recesses of the fin 4002 .

第一4018和第二4020溝槽接觸結構係分別在鄰接閘極電極4006之第一側4006A和第二側4006B的第一4014和第二4016半導體源極或汲極區域之上。第一4018和第二4020溝槽接觸結構兩者皆包含U型金屬層4022以及在整個U型金屬層4022上和在整個U型金屬層4022之上的T型金屬層4024。在一個實施例中，U型金屬層4022和T型金屬層4024的組成不同。在一個實施例中，U型金屬層4022包含鈦，而且T型金屬層4024包含鈷。在一個實施例中，第一4018和第二4020溝槽接觸結構兩者皆進一步包含T型金屬層4024上的第三金屬層4026。在一個這樣的實施例中，第三金屬層4026和U型金屬層4022具有相同的組成。在一特別的實施例中，第三金屬層4026和U型金屬層4022包含鈦，而且T型金屬層4024包含鈷。 The first 4018 and second 4020 trench contact structures are respectively over the first 4014 and second 4016 semiconductor source or drain regions adjoining the first side 4006A and the second side 4006B of the gate electrode 4006 . Both the first 4018 and second 4020 trench contact structures include a U-shaped metal layer 4022 and a T-shaped metal layer 4024 on and above the entire U-shaped metal layer 4022 . In one embodiment, the compositions of the U-shaped metal layer 4022 and the T-shaped metal layer 4024 are different. In one embodiment, the U-shaped metal layer 4022 includes titanium and the T-shaped metal layer 4024 includes cobalt. In one embodiment, both the first 4018 and the second 4020 trench contact structures further include a third metal layer 4026 on the T-shaped metal layer 4024 . In one such embodiment, third metal layer 4026 and U-shaped metal layer 4022 have the same composition. In a particular embodiment, the third metal layer 4026 and the U-shaped metal layer 4022 include titanium, and the T-shaped metal layer 4024 includes cobalt.

第一溝槽接觸介層(contact via)4028係電連接至第一溝槽接觸4018。在一特別的實施例中，第一溝槽接觸介層4028係在第一溝槽接觸4018的第三金屬層4026上並且被耦接至第一溝槽接觸4018的第三金屬層4026。第一溝槽接觸介層4028係進一步在電介質間隔層4013中的其中一個的一個部位之上並且與其相接觸，而且在電介質蓋部4012的一個部位之上並且與其相接觸。第二溝槽接觸介層4030係電連接至第二溝槽接觸4020。在一特別的實施例中，第二溝槽接觸介層4030係在第二溝槽接觸4020的第三 金屬層4026上並且被耦接至第二溝槽接觸4020的第三金屬層4026。第二溝槽接觸介層4030係進一步在電介質間隔層4013中的另一個的一個部位之上並且與其相接觸，而且在電介質蓋部4012的另一個部位之上並且與其相接觸。 A first trench contact via 4028 is electrically connected to the first trench contact 4018 . In a particular embodiment, the first trench contact via 4028 is on the third metal layer 4026 of the first trench contact 4018 and is coupled to the third metal layer 4026 of the first trench contact 4018 . The first trench contact via 4028 is further over and in contact with a portion of one of the dielectric spacers 4013 , and over and in contact with a portion of the dielectric cap 4012 . The second trench contact via 4030 is electrically connected to the second trench contact 4020 . In a particular embodiment, the second trench contact via 4030 is on the third third of the second trench contact 4020 A third metal layer 4026 is on the metal layer 4026 and is coupled to the second trench contact 4020 . The second trench contact via 4030 is further over and in contact with one portion of the other of the dielectric spacer layers 4013 , and over and in contact with another portion of the dielectric cap 4012 .

在一實施例中，金屬矽化物層4032係分別直接在第一4018和第二4020溝槽接觸結構之間以及第一4014和第二4016半導體源極或汲極區域之間。在一個實施例中，金屬矽化物層4032包含鈦和矽。在一特別這樣的實施例中，第一4014和第二4016半導體源極或汲極區域為第一和第二N型半導體源極或汲極區域。 In one embodiment, the metal silicide layer 4032 is directly between the first 4018 and second 4020 trench contact structures and between the first 4014 and second 4016 semiconductor source or drain regions, respectively. In one embodiment, the metal silicide layer 4032 includes titanium and silicon. In a particularly such embodiment, the first 4014 and second 4016 semiconductor source or drain regions are first and second N-type semiconductor source or drain regions.

參照圖40B，積體電路裝置4050包含諸如矽鰭部的鰭部4052。閘極電介質層4054係在鰭部4052之上。閘極電極4056係在閘極電介質層4054之上。在一實施例中，閘極電極4056包含共形導電層4058和導電填充4060。在一實施例中，電介質蓋部4062係在閘極電極4056之上以及在閘極電介質層4054之上。閘極電極具有第一側4056A和與第一側4056A對立的第二側4056B。電介質間隔層4063係沿著閘極電極4056的側壁。在一個實施例中，閘極電介質層4054係進一步在電介質間隔層4063中的第一個與閘極電極4056的第一側4056A之間以及在電介質間隔層4063中的第二個與閘極電極4056的第二側4056B之間，如同所描述的。在一實施例中，雖然未被描述出，薄的氧化物層，諸如熱或化學氧化矽或二氧化矽層，係在鰭部4052與閘極電介質層4054之間。 Referring to FIG. 40B , an integrated circuit device 4050 includes fins 4052 such as silicon fins. A gate dielectric layer 4054 is tied over the fins 4052 . Gate electrode 4056 is tied over gate dielectric layer 4054 . In one embodiment, the gate electrode 4056 includes a conformal conductive layer 4058 and a conductive fill 4060 . In one embodiment, a dielectric cap 4062 is placed over the gate electrode 4056 and over the gate dielectric layer 4054 . The gate electrode has a first side 4056A and a second side 4056B opposite the first side 4056A. A dielectric spacer 4063 is along the sidewalls of the gate electrode 4056 . In one embodiment, the gate dielectric layer 4054 is further between a first one of the dielectric spacers 4063 and the first side 4056A of the gate electrode 4056 and a second one of the dielectric spacers 4063 and the gate electrode. 4056 between the second side 4056B, as described. In one embodiment, although not depicted, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is tied between the fin 4052 and the gate dielectric layer 4054 .

第一4064和第二4066半導體源極或汲極區域係分別鄰接閘極電極4056的第一側4056A和第二側4056B之間。在一個實施例中，第一4064和第二4066半導體源極或汲極區域為分別形成在鰭部4052之凹部4065和4067中之嵌入的磊晶區域，如同所描述的。然而，在另一實施例中，第一4064和第二4066半導體源極或汲極區域係在鰭部4052中。 The first 4064 and second 4066 semiconductor source or drain regions adjoin the gate electrode 4056 between the first side 4056A and the second side 4056B, respectively. In one embodiment, the first 4064 and second 4066 semiconductor source or drain regions are embedded epitaxial regions formed in the recesses 4065 and 4067 of the fin 4052, respectively, as described. However, in another embodiment, the first 4064 and second 4066 semiconductor source or drain regions are tied in the fin 4052 .

第一4068和第二4070溝槽接觸結構係分別在鄰接閘極電極4056之第一側4056A和第二側4056B的第一4064和第二4066半導體源極或汲極區域之上。第一4068和第二4070溝槽接觸結構兩者皆包含U型金屬層4072以及在整個U型金屬層4072上和在整個U型金屬層4072之上的T型金屬層4074。在一個實施例中，U型金屬層4072和T型金屬層4074的組成不同。在一個實施例中，U型金屬層4072包含鈦，而且T型金屬層4074包含鈷。在一個實施例中，第一4068和第二4070溝槽接觸結構兩者皆進一步包含T型金屬層4074上的第三金屬層4076。在一個這樣的實施例中，第三金屬層4076和U型金屬層4072具有相同的組成。在一特別的實施例中，第三金屬層4076和U型金屬層4072包含鈦，而且T型金屬層4074包含鈷。 The first 4068 and second 4070 trench contact structures are respectively over the first 4064 and second 4066 semiconductor source or drain regions adjoining the first side 4056A and the second side 4056B of the gate electrode 4056 . Both the first 4068 and the second 4070 trench contact structures include a U-shaped metal layer 4072 and a T-shaped metal layer 4074 on and above the entire U-shaped metal layer 4072 . In one embodiment, the U-shaped metal layer 4072 and the T-shaped metal layer 4074 have different compositions. In one embodiment, the U-shaped metal layer 4072 includes titanium and the T-shaped metal layer 4074 includes cobalt. In one embodiment, both the first 4068 and the second 4070 trench contact structures further include a third metal layer 4076 on the T-shaped metal layer 4074 . In one such embodiment, third metal layer 4076 and U-shaped metal layer 4072 have the same composition. In a particular embodiment, the third metal layer 4076 and the U-shaped metal layer 4072 include titanium, and the T-shaped metal layer 4074 includes cobalt.

第一溝槽接觸介層4078係電連接至第一溝槽接觸4068。在一特別的實施例中，第一溝槽接觸介層4078係在第一溝槽接觸4068的第三金屬層4076上並且被耦接至第一溝槽接觸4068的第三金屬層4076。第一溝槽接觸介層 4078係進一步在電介質間隔層4063中的其中一個的一個部位之上並且與其相接觸，而且在電介質蓋部4062的一個部位之上並且與其相接觸。第二溝槽接觸介層4080係電連接至第二溝槽接觸4070。在一特別的實施例中，第二溝槽接觸介層4080係在第二溝槽接觸4070的第三金屬層4076上並且被耦接至第二溝槽接觸4070的第三金屬層4076。第二溝槽接觸介層4080係進一步在電介質間隔層4063中的另一個的一個部位之上並且與其相接觸，而且在電介質蓋部4062的另一個部位之上並且與其相接觸。 The first trench contact via 4078 is electrically connected to the first trench contact 4068 . In a particular embodiment, the first trench contact via 4078 is overlying and coupled to the third metal layer 4076 of the first trench contact 4068 . first trench contact via 4078 is further over and in contact with a portion of one of the dielectric spacers 4063 and over and in contact with a portion of the dielectric cap 4062 . The second trench contact via 4080 is electrically connected to the second trench contact 4070 . In a particular embodiment, the second trench contact via 4080 is overlaid on and coupled to the third metal layer 4076 of the second trench contact 4070 . The second trench contact via 4080 is further over and in contact with one portion of the other of the dielectric spacers 4063 , and over and in contact with another portion of the dielectric cap 4062 .

在一實施例中，金屬矽化物層4082係分別直接在第一4068和第二4070溝槽接觸結構之間以及第一4064和第二4066半導體源極或汲極區域之間。在一個實施例中，金屬矽化物層4082包含鎳、鉑和矽。在一特別這樣的實施例中，第一4064和第二4066半導體源極或汲極區域為第一和第二P型半導體源極或汲極區域。在一個實施例中，金屬矽化物層4082另包含鍺。在一個實施例中，金屬矽化物層4082另包含鈦。 In one embodiment, the metal silicide layer 4082 is directly between the first 4068 and second 4070 trench contact structures and between the first 4064 and second 4066 semiconductor source or drain regions, respectively. In one embodiment, metal suicide layer 4082 includes nickel, platinum, and silicon. In a particular such embodiment, the first 4064 and second 4066 semiconductor source or drain regions are first and second P-type semiconductor source or drain regions. In one embodiment, the metal silicide layer 4082 further includes germanium. In one embodiment, the metal silicide layer 4082 further includes titanium.

本文中所述的一或更多個實施例係有關針對環繞式(wrap-around)半導體接觸之金屬化學氣相沉積的使用。諸實施例可以應用於或者包含化學氣相沉積(CVD)、電漿輔助化學氣相沉積(PECVD)、原子層沉積(ALD)、導電接觸製造、或薄膜的其中一者或更多者。 One or more embodiments described herein relate to the use of metal chemical vapor deposition for wrap-around semiconductor contacts. Embodiments may be applied to or include one or more of chemical vapor deposition (CVD), plasma assisted chemical vapor deposition (PECVD), atomic layer deposition (ALD), conductive contact fabrication, or thin films.

特別的實施例可以包含使用接觸金屬之低溫(例如，少於攝氏500度，或者在攝氏400到500度的範圍 中)化學氣相沉積之鈦等金屬層的製造以提供共形的源極或汲極接觸。此種共形的源極或汲極接觸的施行可以改善三維(3D)電晶體互補式金屬氧化物半導體(CMOS)性能。 Particular embodiments may involve the use of low temperature contact metals (e.g., less than 500 degrees Celsius, or in the range of 400 to 500 degrees Celsius Middle) Fabrication of chemical vapor deposited metal layers such as titanium to provide conformal source or drain contacts. The implementation of such conformal source or drain contacts can improve three-dimensional (3D) transistor complementary metal-oxide-semiconductor (CMOS) performance.

為了提供上下文，金屬對半導體接觸層可以使用濺鍍來予以沉積。濺鍍是一種直視性(line of sight)製程而且可能相當不適合3D電晶體製造。已知的濺鍍解決方案在裝置接觸表面上因為沉積入射的角度而具有不良或不完整的金屬半導體接面。 To provide context, the metal-to-semiconductor contact layer can be deposited using sputtering. Sputtering is a line of sight process and may be quite unsuitable for 3D transistor fabrication. Known sputtering solutions have poor or incomplete metal-semiconductor junctions on the device contact surface due to the angle of incidence of the deposition.

依據本發明的一或更多個實施例，低溫化學氣相沉積製程被施行來製造接觸金屬以提供三維上的共形，並且使金屬半導體接面接觸面積達最大。結果之更大的接觸面積可以減小接面的電阻(resistance)。諸實施例可以包含具有非平坦的形貌(non-flat topography)之半導體表面上的沉積，在該處，區域的形貌指的是表面形狀和它們自己的特徵，而且非平坦的形貌包含非平坦的表面形狀及特徵或非平坦的表面形狀及特徵的部位，亦即，並非完全平坦的表面形狀及特徵。 According to one or more embodiments of the present invention, a low temperature chemical vapor deposition process is performed to fabricate the contact metal to provide three-dimensional conformality and maximize the metal-semiconductor junction contact area. The resulting larger contact area can reduce the resistance of the junction. Embodiments may involve deposition on semiconductor surfaces with non-flat topography, where the topography of regions refers to the surface shape and their own characteristics, and the non-flat topography includes Non-flat surface shapes and features or locations of non-flat surface shapes and features, ie, surface shapes and features that are not perfectly flat.

本文中所述的實施例可以包含環繞式接觸結構的製造。在一個這樣的實施例中，藉由化學氣相沉積、電漿輔助化學氣相沉積、原子層沉積、或電漿輔助原子層沉積而被共形地沉積於電晶體源極-汲極接觸上之純金屬的使用被說明。此種共形沉積可以被用來增加金屬半導體接觸的可用面積並且減小電阻，改善電晶體裝置的性能。在一實施例中，該沉積之相對低的溫度導致每單位面積之 接面的電阻最小化。 Embodiments described herein may include the fabrication of wrap-around contact structures. In one such embodiment, is conformally deposited on the transistor source-drain contact by chemical vapor deposition, plasma assisted chemical vapor deposition, atomic layer deposition, or plasma assisted atomic layer deposition The use of pure metals is illustrated. Such conformal deposition can be used to increase the available area of metal-semiconductor contacts and reduce resistance, improving the performance of transistor devices. In one embodiment, the relatively low temperature of the deposition results in a The resistance of the junction is minimized.

可以領會到，各種積體電路結構可以使用如同本文中所述之涉及金屬層沉積的整合方案來予以製造。依據本發明的一實施例，製造積體電路結構的方法包含在具有RF源的化學氣相沉積(CVD)室中設置一基板，該基板具有一特徵於其上。該方法也包含使四氯化鈦(TiCl4)和氫(H2)起反應而在基板的該特徵上形成鈦(Ti)層。 It can be appreciated that various integrated circuit structures can be fabricated using an integrated scheme involving metal layer deposition as described herein. According to one embodiment of the present invention, a method of fabricating an integrated circuit structure includes disposing a substrate having a feature thereon in a chemical vapor deposition (CVD) chamber having an RF source. The method also includes reacting titanium tetrachloride ( TiCl4 ) and hydrogen ( H2 ) to form a titanium (Ti) layer on the feature of the substrate.

在一實施例中，該鈦層具有包含98%或更大的鈦以及0.5到2%的氯的總原子組成。在替換實施例中，類似的製程被用來製造高純度之鋯(Zr)、鉿(Hf)、鉭(Ta)、鈮(Nb)或釩(V)的金屬層。在一實施例中，有相當小的膜厚度變化，例如，在一實施例中，所有的覆蓋率係大於50%而且標稱為70%或更大(亦即，30%或更少的厚度變化)。在一實施例中，當矽(Si)或矽鍺(SiGe)在沉積期間起反應而且加快Ti的速度時，Si或SiGe上的厚度比在其他表面上的厚度在測量上係更厚的。在一實施例中，膜組成包含約0.5%的Cl(或少於1%)作為雜質，基本上沒有觀察到有其他雜質。在一實施例中，該沉積製程致能非直視性(non-line of sight)表面上的金屬覆蓋率，諸如，受濺鍍沉積直視(line of sight)所隱藏的表面。本文中所述的實施例可以被施行來藉由減少正經由源極和汲極接觸來予以驅動之電流的外部阻力來改善電晶體裝置驅動。 In one embodiment, the titanium layer has a total atomic composition comprising 98% or greater titanium and 0.5 to 2% chlorine. In alternative embodiments, a similar process is used to fabricate high purity zirconium (Zr), hafnium (Hf), tantalum (Ta), niobium (Nb) or vanadium (V) metal layers. In one embodiment, there is relatively little variation in film thickness, e.g., in one embodiment, all coverage is greater than 50% and nominally 70% or greater (i.e., 30% or less in thickness Variety). In one embodiment, when silicon (Si) or silicon germanium (SiGe) reacts during deposition and speeds up Ti, the thickness on Si or SiGe is measured to be thicker than on other surfaces. In one embodiment, the film composition includes about 0.5% Cl (or less than 1%) as an impurity, and substantially no other impurities are observed. In one embodiment, the deposition process enables metal coverage on non-line of sight surfaces, such as surfaces hidden by the line of sight of sputter deposition. Embodiments described herein can be implemented to improve transistor device drive by reducing the external resistance to current being driven through source and drain contacts.

依據本發明的一實施例，基板的該特徵為使半導體源極或汲極結構暴露出的源極或汲極接觸溝槽。該 鈦層(或其他高純度金屬層)為用於該半導體源極或汲極結構的導電接觸層。此種施行的代表性實施例在下面參照圖41A,41B,42,43A到43C和44來做說明。 According to an embodiment of the invention, the feature of the substrate is a source or drain contact trench exposing the semiconductor source or drain structure. Should The titanium layer (or other high purity metal layer) is the conductive contact layer for the semiconductor source or drain structure. Representative examples of such implementations are described below with reference to FIGS.

圖41A繪示依據本發明的一實施例，具有源極或汲極區域上之導電接觸之半導體裝置的剖面視圖。 Figure 41A illustrates a cross-sectional view of a semiconductor device with conductive contacts on source or drain regions in accordance with one embodiment of the present invention.

參照圖41A，半導體結構4100包含在基板4104之上的閘極結構4102。該閘極結構4102包含閘極電介質層4102A、功函數層4102B、和閘極填充4102C。源極區域4108和汲極區域4110係在該閘極結構4102的相反側上。源極或汲極接觸4112係電連接至源極區域4108和汲極區域4110，而且藉由層間電介質層4114或閘極電介質間隔層4116的其中一者或兩者而與該閘極結構4102間隔分開。源極區域4108和汲極區域4110為基板4104的區域。 Referring to FIG. 41A , a semiconductor structure 4100 includes a gate structure 4102 over a substrate 4104 . The gate structure 4102 includes a gate dielectric layer 4102A, a work function layer 4102B, and a gate fill 4102C. A source region 4108 and a drain region 4110 are tied on opposite sides of the gate structure 4102 . A source or drain contact 4112 is electrically connected to the source region 4108 and the drain region 4110 and is spaced from the gate structure 4102 by either or both an interlayer dielectric layer 4114 or a gate dielectric spacer layer 4116. separate. The source region 4108 and the drain region 4110 are regions of the substrate 4104 .

在一實施例中，源極或汲極接觸4112包含高純度金屬層4112A，諸如如上所述者，和導電性溝槽填充材料4112B。在一個實施例中，該高純度金屬層4112A具有包含98%或更大之鈦的總原子組成。在一個這樣的實施例中，該高純度金屬層4112A的總原子組成另包含0.5到2%的氯。在一實施例中，該高純度金屬層4112A具有30%或更小的厚度變化。在一實施例中，該導電性溝槽填充材料4112B係由導電材料組成，諸如但不限於，Cu,Al,W、或其合金。 In one embodiment, the source or drain contact 4112 includes a high purity metal layer 4112A, such as described above, and a conductive trench fill material 4112B. In one embodiment, the high purity metal layer 4112A has a total atomic composition comprising 98% or greater titanium. In one such embodiment, the total atomic composition of the high purity metal layer 4112A additionally includes 0.5 to 2% chlorine. In one embodiment, the high purity metal layer 4112A has a thickness variation of 30% or less. In one embodiment, the conductive trench fill material 4112B is composed of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

圖41B繪示依據本發明的一實施例，具有突起的源極和汲極區域上之導電接觸之另一半導體裝置的剖 面視圖。 41B shows a cross-section of another semiconductor device with conductive contacts on raised source and drain regions in accordance with an embodiment of the present invention. face view.

參照圖41B，半導體結構4150包含在基板4154之上的閘極結構4152。該閘極結構4152包含閘極電介質層4152A、功函數層4152B、和閘極填充4152C。源極區域4158和汲極區域4160係在該閘極結構4152的相反側上。源極或汲極接觸4162係電連接至源極區域4158和汲極區域4160，而且藉由層間電介質層4164或閘極電介質間隔層4166的其中一者或兩者而與該閘極結構4152間隔分開。源極區域4158和汲極區域4160為形成在基板4154之被蝕刻掉的區域中之磊晶或嵌入的材料區域。如同所描述的，在一實施例中，源極區域4158和汲極區域4160為突起的源極和汲極區域。在一個特定之這樣的實施例中，該等突起的源極和汲極區域為突起的矽源極和汲極區域或突起的矽鍺源極和汲極區域。 Referring to FIG. 41B , a semiconductor structure 4150 includes a gate structure 4152 over a substrate 4154 . The gate structure 4152 includes a gate dielectric layer 4152A, a work function layer 4152B, and a gate fill 4152C. A source region 4158 and a drain region 4160 are tied on opposite sides of the gate structure 4152 . A source or drain contact 4162 is electrically connected to source region 4158 and drain region 4160 and is spaced from the gate structure 4152 by either or both an interlayer dielectric layer 4164 or a gate dielectric spacer layer 4166. separate. Source regions 4158 and drain regions 4160 are regions of epitaxial or embedded material formed in the etched away regions of substrate 4154 . As depicted, in one embodiment, source region 4158 and drain region 4160 are raised source and drain regions. In a specific such embodiment, the raised source and drain regions are raised silicon source and drain regions or raised silicon germanium source and drain regions.

在一實施例中，源極或汲極接觸4162包含高純度金屬層4162A，諸如如上所述者，和導電性溝槽填充材料4162B。在一個實施例中，該高純度金屬層4162A具有包含98%或更大之鈦的總原子組成。在一個這樣的實施例中，該高純度金屬層4162A的總原子組成另包含0.5到2%的氯。在一實施例中，該高純度金屬層4162A具有30%或更小的厚度變化。在一實施例中，該導電性溝槽填充材料4162B係由導電材料組成，諸如但不限於，Cu,Al,W、或其合金。 In one embodiment, the source or drain contact 4162 includes a high purity metal layer 4162A, such as described above, and a conductive trench fill material 4162B. In one embodiment, the high purity metal layer 4162A has a total atomic composition comprising 98% or greater titanium. In one such embodiment, the total atomic composition of the high purity metal layer 4162A additionally includes 0.5 to 2% chlorine. In one embodiment, the high purity metal layer 4162A has a thickness variation of 30% or less. In one embodiment, the conductive trench fill material 4162B is composed of a conductive material such as, but not limited to, Cu, Al, W, or alloys thereof.

因此，在一實施例中，共同參照圖41A和 41B，積體電路結構包含具有表面的特徵(使半導體源極或汲極結構暴露出的源極或汲極接觸溝槽)。高純度金屬層4112A或4162A係在該源極或汲極接觸溝槽的表面上。可以領會到，接觸形成製程會涉及源極或汲極區域露出之矽或鍺或矽鍺材料的耗損。這樣的耗損會使裝置性能劣化。相反地，依據本發明的一實施例，半導體源極(4108或4158)或汲極(4110或4160)結構在該源極或汲極接觸溝槽之下的表面(4149或4199)未被腐蝕或耗損，或者實質上未被腐蝕或耗損。在一個這樣的實施例中，缺乏耗損或腐蝕起因於高純度金屬接觸層的低溫沉積。 Therefore, in one embodiment, collective reference is made to FIGS. 41A and 41B, the integrated circuit structure includes features with surfaces (source or drain contact trenches exposing semiconductor source or drain structures). A high purity metal layer 4112A or 4162A is on the surface of the source or drain contact trench. It can be appreciated that the contact formation process involves depletion of exposed silicon or germanium or silicon germanium material in the source or drain regions. Such wear and tear can degrade device performance. Conversely, according to an embodiment of the present invention, the surface (4149 or 4199) of the semiconductor source (4108 or 4158) or drain (4110 or 4160) structure below the source or drain contact trench is not etched or worn, or substantially uncorroded or worn. In one such embodiment, the lack of wear or corrosion results from the low temperature deposition of the high purity metal contact layer.

圖42繪示依據本發明的一實施例，在一對半導體鰭部之上的複數條閘極線的平面視圖。 42 illustrates a plan view of a plurality of gate lines over a pair of semiconductor fins in accordance with one embodiment of the present invention.

參照圖42，複數條作用閘極線4204係形成在複數個半導體鰭部4200之上。假性閘極線4206係在複數個半導體鰭部4200的末端處。閘極線4204/4206之間的間隙4208為溝槽接觸可以被形成作為到源極或汲極區域(諸如，源極或汲極區域4251,4252,4253，和4254)之導電接觸的位置。 Referring to FIG. 42 , a plurality of active gate lines 4204 are formed over a plurality of semiconductor fins 4200 . Dummy gate lines 4206 are tied at the ends of the plurality of semiconductor fins 4200 . The gap 4208 between the gate lines 4204/4206 is where trench contacts can be formed as conductive contacts to source or drain regions such as source or drain regions 4251, 4252, 4253, and 4254.

圖43A到43C繪示依據本發明的一實施例，針對製造積體電路結構之方法中的各種操作，沿著圖42的a到a’軸線所取出的剖面視圖。 43A to 43C illustrate cross-sectional views taken along the a to a' axes of FIG. 42 for various operations in a method of fabricating an integrated circuit structure in accordance with an embodiment of the present invention.

參照圖43A，複數條作用閘極線4304係形成於形成在基板4300之上的半導體鰭部4302之上。假性閘極線4306係在該半導體鰭部4302的末端處。電介質層4310係 在該等作用閘極線4304之間，在假性閘極線4306與作用閘極線4304之間，以及在假性閘極線4306之外。嵌入的源極或汲極結構4308係在該等作用閘極線4304之間，以及在假性閘極線4306與作用閘極線4304之間的半導體鰭部4302中。該等作用閘極線4304包含閘極電介質層4312、功函數閘極電極部4314和填充閘極電極部4316、以及電介質覆蓋層4318。電介質間隔層4320使作用閘極線4304和假性閘極線4306的側壁列隊(line)。 Referring to FIG. 43A , a plurality of active gate lines 4304 are formed over semiconductor fins 4302 formed over a substrate 4300 . A dummy gate line 4306 is tied at the end of the semiconductor fin 4302 . Dielectric layer 4310 series Between the active gate lines 4304 , between the dummy gate lines 4306 and the active gate lines 4304 , and outside the dummy gate lines 4306 . Embedded source or drain structures 4308 are between the active gate lines 4304 and in the semiconductor fin 4302 between the dummy gate lines 4306 and the active gate lines 4304 . The active gate lines 4304 include a gate dielectric layer 4312 , a work function gate electrode portion 4314 and a filled gate electrode portion 4316 , and a dielectric capping layer 4318 . Dielectric spacer 4320 lines the sidewalls of active gate line 4304 and dummy gate line 4306 .

參照圖43B，電介質層4310之在該等作用閘極線4304之間以及在假性閘極線4306與作用閘極線4304之間的部位被去除，以提供開口4330於溝槽接觸要被形成的位置中。電介質層4310之在該等作用閘極線4304之間以及在假性閘極線4306與作用閘極線4304之間的部位的去除可以導致嵌入的源極或汲極結構4308的腐蝕，以提供腐蝕後之嵌入的源極或汲極結構4332，其可以具有上鞍形(saddle-shaped)形貌，如同圖43B中所描述的。 Referring to FIG. 43B, portions of the dielectric layer 4310 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304 are removed to provide openings 4330 where trench contacts are to be formed. in the location. Removal of the dielectric layer 4310 between the active gate lines 4304 and between the dummy gate lines 4306 and the active gate lines 4304 may result in erosion of the embedded source or drain structures 4308 to provide The etched embedded source or drain structure 4332 may have a saddle-shaped topography, as depicted in FIG. 43B.

參照圖43C，溝槽接觸4334係形成在該等作用閘極線4304之間以及在假性閘極線4306與作用閘極線4304之間的開口4330中。該等溝槽接觸4334之各者可以包含金屬接觸層4336和導電性填充材料4338。 Referring to FIG. 43C , trench contacts 4334 are formed in openings 4330 between the active gate lines 4304 and between dummy gate lines 4306 and active gate lines 4304 . Each of the trench contacts 4334 may include a metal contact layer 4336 and a conductive fill material 4338 .

圖44繪示依據本發明的一實施例，針對一積體電路結構，沿著圖42的b到b’軸線所取出的剖面視圖。 FIG. 44 shows a cross-sectional view taken along the axis b to b' of FIG. 42 for an integrated circuit structure according to an embodiment of the present invention.

參照圖44，鰭部4402係描述在基板4404之上。鰭部4402的下部部位被溝槽隔離材料4404所包圍。鰭 部4402的上部部位已經被去除以致能嵌入的源極或汲極結構4406的生長。溝槽接觸4408係形成在電介質層4410的開口中，該開口使嵌入的源極或汲極結構4406暴露出。該溝槽接觸包含金屬接觸層4412和導電性填充材料4414。可以領會到，依據本發明的一實施例，金屬接觸層4412延伸到溝槽接觸4408的頂部，如同圖44中所描述的。但是，在另一實施例中，金屬接觸層4412並未延伸到溝槽接觸4408的頂部，而且有點凹入進溝槽接觸4408內，例如，類似於圖43C中之金屬接觸層4336的描述。 Referring to FIG. 44 , a fin 4402 is depicted over a substrate 4404 . The lower portion of the fin 4402 is surrounded by trench isolation material 4404 . fin The upper portion of portion 4402 has been removed to enable the growth of embedded source or drain structures 4406 . Trench contacts 4408 are formed in openings in dielectric layer 4410 that expose embedded source or drain structures 4406 . The trench contact includes a metal contact layer 4412 and a conductive fill material 4414 . It can be appreciated that metal contact layer 4412 extends to the top of trench contact 4408, as depicted in FIG. 44, in accordance with an embodiment of the present invention. However, in another embodiment, the metal contact layer 4412 does not extend to the top of the trench contact 4408, but is somewhat recessed into the trench contact 4408, eg, similar to the description of the metal contact layer 4336 in FIG. 43C.

因此，共同參照圖42、43A到43C和44，依據本發明的一實施例，該積體電路結構包含在基板(4300,4400)之上的半導體鰭部(4200,4302,4402)。該半導體鰭部(4200,4302,4402)具有頂部和側壁。閘極電極(4204,4304)係在該半導體鰭部(4200,4302,4402)之一部位的頂部之上並且鄰接於該半導體鰭部(4200,4302,4402)之一部位的側壁。閘極電極(4204,4304)界定該半導體鰭部(4200,4302,4402)中的通道區域。第一半導體源極或汲極結構(4251,4332,4406)係在該閘極電極(4204,4304)第一側之通道區域的第一末端處，該第一半導體源極或汲極結構(4251,4332,4406)具有非平坦的形貌。第二半導體源極或汲極結構(4252,4332,4406)係在該閘極電極(4204,4304)第二側之通道區域的第二末端處，該第二末端和該第一末端相對立，且該第二側和該第一側相對立。該第二半導體源極或汲極結構(4252,4332,4406)具有非平坦的形貌。金屬接觸 材料(4336,4412)係直接在該第一半導體源極或汲極結構(4251,4332,4406)上以及直接在該第二半導體源極或汲極結構(4252,4332,4406)上。該金屬接觸材料(4336,4412)與該第一半導體源極或汲極結構(4251,4332,4406)之非平坦的形貌係共形的，並且與該第二半導體源極或汲極結構(4252,4332,4406)之非平坦的形貌係共形的。 Accordingly, referring collectively to FIGS. 42, 43A to 43C and 44, in accordance with an embodiment of the present invention, the integrated circuit structure includes semiconductor fins (4200, 4302, 4402) over a substrate (4300, 4400). The semiconductor fin (4200, 4302, 4402) has a top and sidewalls. A gate electrode (4204, 4304) is on top of a portion of the semiconductor fin (4200, 4302, 4402) and adjacent to a sidewall of a portion of the semiconductor fin (4200, 4302, 4402). Gate electrodes (4204, 4304) define channel regions in the semiconductor fins (4200, 4302, 4402). A first semiconductor source or drain structure (4251, 4332, 4406) is at a first end of the channel region on a first side of the gate electrode (4204, 4304), the first semiconductor source or drain structure ( 4251, 4332, 4406) have non-flat topography. A second semiconductor source or drain structure (4252, 4332, 4406) is at a second end of the channel region on a second side of the gate electrode (4204, 4304), the second end being opposite the first end , and the second side is opposite to the first side. The second semiconductor source or drain structure (4252, 4332, 4406) has a non-planar topography. metal contact Material (4336, 4412) is directly on the first semiconductor source or drain structure (4251, 4332, 4406) and directly on the second semiconductor source or drain structure (4252, 4332, 4406). The metal contact material (4336, 4412) is conformal with the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and with the second semiconductor source or drain structure The non-planar topography of (4252, 4332, 4406) is conformal.

在一實施例中，該金屬接觸材料(4336,4412)具有包含95%或更大之單一金屬物種的總原子組成。在一個這樣的實施例中，該金屬接觸材料(4336,4412)具有包含98%或更大之鈦的總原子組成。在一特定之這樣的實施例中，該金屬接觸材料(4336,4412)的總原子組成另包含0.5到2%的氯。在一實施例中，該金屬接觸材料(4336,4412)沿著該第一半導體源極或汲極結構(4251,4332,4406)之非平坦的形貌以及沿著該第二半導體源極或汲極結構(4252,4332,4406)之非平坦的形貌具有30%或更小的厚度變化。 In one embodiment, the metal contact material (4336, 4412) has a total atomic composition comprising 95% or greater of a single metal species. In one such embodiment, the metal contact material (4336, 4412) has a total atomic composition comprising 98% or greater titanium. In a specific such embodiment, the total atomic composition of the metal contact material (4336, 4412) additionally includes 0.5 to 2% chlorine. In one embodiment, the metal contact material (4336, 4412) is along the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and along the second semiconductor source or The non-planar topography of the drain structure (4252, 4332, 4406) has a thickness variation of 30% or less.

在一實施例中，該第一半導體源極或汲極結構(4251,4332,4406)之非平坦的形貌以及該第二半導體源極或汲極結構(4252,4332,4406)之非平坦的形貌兩者皆包含突起的中央部位和下側部位，例如，如同圖44中所描述的。在一實施例中，該第一半導體源極或汲極結構(4251,4332,4406)之非平坦的形貌以及該第二半導體源極或汲極結構(4252,4332,4406)之非平坦的形貌兩者皆包含鞍形的部位，例如，如同圖43C中所描述的。 In one embodiment, the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406) The topography of both includes a central portion and an underside portion of the protrusion, eg, as depicted in FIG. 44 . In one embodiment, the non-planar topography of the first semiconductor source or drain structure (4251, 4332, 4406) and the non-planar topography of the second semiconductor source or drain structure (4252, 4332, 4406) The topography of both includes saddle-shaped sites, eg, as depicted in FIG. 43C .

在一實施例中，該第一半導體源極或汲極結構(4251,4332,4406)和該第二半導體源極或汲極結構(4252,4332,4406)兩者皆包含矽。在一實施例中，該第一半導體源極或汲極結構(4251,4332,4406)和該第二半導體源極或汲極結構(4252,4332,4406)兩者皆包含鍺，例如，以矽鍺的形式。 In an embodiment, both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) comprise silicon. In one embodiment, both the first semiconductor source or drain structure (4251, 4332, 4406) and the second semiconductor source or drain structure (4252, 4332, 4406) comprise germanium, for example, in form of silicon germanium.

在一實施例中，直接在該第一半導體源極或汲極結構(4251,4332,4406)上的該金屬接觸材料(4336,4412)係進一步沿著該第一半導體源極或汲極結構(4251,4332,4406)之上的電介質層(4320,4410)中之溝槽的側壁，該溝槽使該第一半導體源極或汲極結構(4251,4332,4406)的一部位暴露出。在一個這樣的實施例中，該金屬接觸材料(4336)沿著該溝槽之側壁的厚度從該第一半導體源極或汲極結構(在4332處的4336A)到該第一半導體源極或汲極結構(4332)之上的位置(4336B)減薄，其依範例係繪示於圖43C中。在一實施例中，導電性填充材料(4338,4414)係在該溝槽之內的該金屬接觸材料(4336,4412)上，如同圖43C和44中所描述的。 In one embodiment, the metal contact material (4336, 4412) directly on the first semiconductor source or drain structure (4251, 4332, 4406) is further along the first semiconductor source or drain structure sidewalls of a trench in a dielectric layer (4320, 4410) above (4251, 4332, 4406), the trench exposing a portion of the first semiconductor source or drain structure (4251, 4332, 4406) . In one such embodiment, the metal contact material (4336) extends from the first semiconductor source or drain structure (4336A at 4332) to the first semiconductor source or drain along the thickness of the sidewall of the trench. The location (4336B) above the drain structure (4332) is thinned, which is shown by way of example in Figure 43C. In one embodiment, conductive fill material (4338, 4414) is tied on the metal contact material (4336, 4412) within the trench, as described in FIGS. 43C and 44 .

在一實施例中，該積體電路結構另包含具有頂部和側壁的第二半導體鰭部(例如，圖42的上鰭部4200,4302,4402)。該閘極電極(4204,4304)係在該第二半導體鰭部之一部位的頂部之上並且鄰接於該第二半導體鰭部之一部位的側壁，該閘極電極界定該第二半導體鰭部中的通道區域。第三半導體源極或汲極結構(4253,4332,4406)係在 該閘極電極(4204,4304)第一側之該第二半導體鰭部之通道區域的第一末端處，該第三半導體源極或汲極結構具有非平坦的形貌。第四半導體源極或汲極結構(4254,4332,4406)係在該閘極電極(4204,4304)第二側之該第二半導體鰭部之通道區域的第二末端處，該第二末端和該第一末端相對立，該第四半導體源極或汲極結構(4254,4332,4406)具有非平坦的形貌。該金屬接觸材料(4336,4412)係直接在該第三半導體源極或汲極結構(4253,4332,4406)上以及直接在該第四半導體源極或汲極結構(4254,4332,4406)上，該金屬接觸材料(4336,4412)與該第三半導體源極或汲極結構(4253,4332,4406)之非平坦的形貌係共形的，並且與該第四半導體源極或汲極結構(4254,4332,4406)之非平坦的形貌係共形的。在一實施例中，該金屬接觸材料(4336,4412)在該第一半導體源極或汲極結構(4251,4332,左側4406)與該第三半導體源極或汲極結構(4253,4332，右側4406)之間係連續的，以及在該第二半導體源極或汲極結構(4252)與該第四半導體源極或汲極結構(4254)之間係連續的。 In one embodiment, the integrated circuit structure further includes a second semiconductor fin having a top and sidewalls (eg, upper fins 4200 , 4302 , 4402 of FIG. 42 ). The gate electrode (4204, 4304) is over the top of a portion of the second semiconductor fin and is adjacent to a sidewall of a portion of the second semiconductor fin, the gate electrode defining the second semiconductor fin in the channel area. The third semiconductor source or drain structure (4253, 4332, 4406) is in At the first end of the channel region of the second semiconductor fin on the first side of the gate electrode (4204, 4304), the third semiconductor source or drain structure has a non-planar topography. A fourth semiconductor source or drain structure (4254, 4332, 4406) is at a second end of the channel region of the second semiconductor fin on a second side of the gate electrode (4204, 4304), the second end Opposite the first end, the fourth semiconductor source or drain structure (4254, 4332, 4406) has a non-planar topography. The metal contact material (4336, 4412) is directly on the third semiconductor source or drain structure (4253, 4332, 4406) and directly on the fourth semiconductor source or drain structure (4254, 4332, 4406) Above, the metal contact material (4336, 4412) is conformal to the non-planar topography of the third semiconductor source or drain structure (4253, 4332, 4406), and is conformal to the fourth semiconductor source or drain The non-planar topography of pole structures (4254, 4332, 4406) is conformal. In one embodiment, the metal contact material (4336, 4412) is between the first semiconductor source or drain structure (4251, 4332, left side 4406) and the third semiconductor source or drain structure (4253, 4332, There is continuity between the right side 4406 ), and between the second semiconductor source or drain structure ( 4252 ) and the fourth semiconductor source or drain structure ( 4254 ).

在另一態樣中，硬遮罩材料被用來保留(抑制腐蝕)溝槽線位置中的電介質材料，而且可以被保持在溝槽線位置中的電介質材料之上，在溝槽線位置處，導電性溝槽接觸被中斷，例如在接觸插塞位置中。舉例來說，圖45A和45B繪示依據本發明的一實施例，分別為包含具有硬遮罩材料於其上之溝槽接觸插塞的積體電路結構的平 面視圖和對應的剖面視圖。 In another aspect, a hard mask material is used to retain (inhibit etch) the dielectric material in the trench line locations, and may be held over the dielectric material in the trench line locations, at the trench line locations , the conductive trench contact is interrupted, for example in the position of a contact plug. For example, FIGS. 45A and 45B illustrate a planar view of an integrated circuit structure including trench contact plugs with hard mask material thereon, respectively, in accordance with an embodiment of the present invention. Surface views and corresponding section views.

參照圖45A和45B，在一實施例中，積體電路結構4500包含鰭部4502A，諸如矽鰭部。複數個閘極結構4506係在該鰭部4502A之上。該等閘極結構4506之個別的一些係沿著與該鰭部4502A正交的方向4508並且具有一對電介質側壁間隔層4510。溝槽接觸結構4512係在該鰭部4502A之上並且直接在該等閘極結構4506之第一對4506A/4506B的電介質側壁間隔層4510之間。接觸插塞4514B係在該鰭部4502A之上並且直接在該等閘極結構4506之第二對4506B/4506C的電介質側壁間隔層4510之間。接觸插塞4514B包含下電介質材料4516和上硬遮罩材料4518。 45A and 45B, in one embodiment, an integrated circuit structure 4500 includes a fin 4502A, such as a silicon fin. A plurality of gate structures 4506 are tied over the fin 4502A. Individual ones of the gate structures 4506 are along a direction 4508 normal to the fin 4502A and have a pair of dielectric sidewall spacers 4510 . A trench contact structure 4512 is over the fin 4502A and directly between the dielectric sidewall spacers 4510 of the first pair 4506A/4506B of the gate structures 4506 . A contact plug 4514B is over the fin 4502A and directly between the dielectric sidewall spacers 4510 of the second pair 4506B/4506C of the gate structures 4506 . Contact plug 4514B includes a lower dielectric material 4516 and an upper hard mask material 4518 .

在一實施例中，該接觸插塞4516B的下電介質材料4516包含矽和氧，例如，諸如氧化矽和二氧化矽材料。該接觸插塞4516B的上硬遮罩材料4518包含矽和氮，例如，矽氮化物、富含矽的氮化物、或貧含矽的氮化物材料。 In one embodiment, the lower dielectric material 4516 of the contact plug 4516B includes silicon and oxygen, eg, materials such as silicon oxide and silicon dioxide. The upper hard mask material 4518 of the contact plug 4516B includes silicon and nitrogen, eg, silicon nitride, silicon-rich nitride, or silicon-poor nitride material.

在一實施例中，該溝槽接觸結構4512包含下導電結構4520和在該下導電結構4520上的電介質蓋部4522。在一個實施例中，該溝槽接觸結構4512的電介質蓋部4522具有與該接觸插塞4514B之上硬遮罩材料4518的上表面共平面的上表面，如同所描述的。 In one embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520 . In one embodiment, the dielectric cap portion 4522 of the trench contact structure 4512 has an upper surface that is coplanar with the upper surface of the hard mask material 4518 over the contact plug 4514B, as described.

在一實施例中，該複數個閘極結構4506之個別的一些包含閘極電介質層4526上的閘極電極4524。電介 質蓋部4528係在該閘極電極4524上。在一個實施例中，該複數個閘極結構4506之個別的一些的電介質蓋部4528具有與該接觸插塞4514B之上硬遮罩材料4518的上表面共平面的上表面，如同所描述的。在一實施例中，雖然未被描述出，諸如熱或化學氧化矽或二氧化矽層之薄的氧化物層係在該鰭部4502A與該閘極電介質層4526之間。 In one embodiment, individual ones of the plurality of gate structures 4506 include a gate electrode 4524 on a gate dielectric layer 4526 . Dielectric A mass cap 4528 is attached to the gate electrode 4524 . In one embodiment, the dielectric caps 4528 of individual ones of the plurality of gate structures 4506 have upper surfaces that are coplanar with the upper surface of the hard mask material 4518 over the contact plugs 4514B, as described. In one embodiment, although not depicted, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between the fin 4502A and the gate dielectric layer 4526 .

再次參照圖45A和45B，在一實施例中，積體電路結構4500包含複數個鰭部4502，諸如複數個矽鰭部。複數個鰭部4502之個別的一些係沿著第一方向4504。複數個閘極結構4506係在該複數個鰭部4502之上。該複數個閘極結構4506之個別的一些係沿著與該第一方向4504正交的第二方向4508。該複數個閘極結構4506之個別的一些具有一對電介質側壁間隔層4510。溝槽接觸結構4512係在該複數個鰭部4502的第一個鰭部4502A之上並且直接在該等閘極結構4506之一對閘極結構的電介質側壁間隔層4510之間。接觸插塞4514A係在該複數個鰭部4502的第二個鰭部4502B之上並且直接在該等閘極結構4506之該對閘極結構的電介質側壁間隔層4510之間。類似於接觸插塞4514B的剖面視圖，該接觸插塞4514A包含下電介質材料4516和上硬遮罩材料4518。 Referring again to FIGS. 45A and 45B , in one embodiment, an integrated circuit structure 4500 includes a plurality of fins 4502 , such as a plurality of silicon fins. Individual ones of the plurality of fins 4502 are along the first direction 4504 . A plurality of gate structures 4506 are tied over the plurality of fins 4502 . Individual ones of the plurality of gate structures 4506 are along a second direction 4508 orthogonal to the first direction 4504 . Individual ones of the plurality of gate structures 4506 have a pair of dielectric sidewall spacers 4510 . A trench contact structure 4512 is positioned over a first fin 4502A of the plurality of fins 4502 and directly between the dielectric sidewall spacers 4510 of a pair of gate structures 4506 . A contact plug 4514A is over a second fin 4502B of the plurality of fins 4502 and directly between the dielectric sidewall spacers 4510 of the pair of gate structures 4506 . Similar to the cross-sectional view of contact plug 4514B, the contact plug 4514A includes a lower dielectric material 4516 and an upper hard mask material 4518 .

在一實施例中，該接觸插塞4516A的下電介質材料4516包含矽和氧，例如，諸如氧化矽和二氧化矽材料。該接觸插塞4516A的上硬遮罩材料4518包含矽和氮，例如，矽氮化物、富含矽的氮化物、或貧含矽的氮化物材 料。 In one embodiment, the lower dielectric material 4516 of the contact plug 4516A includes silicon and oxygen, eg, materials such as silicon oxide and silicon dioxide. The upper hard mask material 4518 of the contact plug 4516A includes silicon and nitrogen, for example, silicon nitride, a silicon-rich nitride, or a silicon-poor nitride material. material.

在一實施例中，該溝槽接觸結構4512包含下導電結構4520和在該下導電結構4520上的電介質蓋部4522。在一個實施例中，該溝槽接觸結構4512的電介質蓋部4522具有與該接觸插塞4514A或4514B之上硬遮罩材料4518的上表面共平面的上表面，如同所描述的。 In one embodiment, the trench contact structure 4512 includes a lower conductive structure 4520 and a dielectric cap 4522 on the lower conductive structure 4520 . In one embodiment, the dielectric cap portion 4522 of the trench contact structure 4512 has an upper surface that is coplanar with the upper surface of the hard mask material 4518 over the contact plug 4514A or 4514B, as described.

在一實施例中，該複數個閘極結構4506之個別的一些包含閘極電介質層4526上的閘極電極4524。電介質蓋部4528係在該閘極電極4524上。在一個實施例中，該複數個閘極結構4506之個別的一些的電介質蓋部4528具有與該接觸插塞4514A或4514B之上硬遮罩材料4518的上表面共平面的上表面，如同所描述的。在一實施例中，雖然未被描述出，諸如熱或化學氧化矽或二氧化矽層之薄的氧化物層係在該鰭部4502A與該閘極電介質層4526之間。 In one embodiment, individual ones of the plurality of gate structures 4506 include a gate electrode 4524 on a gate dielectric layer 4526 . A dielectric cap 4528 is tied over the gate electrode 4524 . In one embodiment, the dielectric caps 4528 of individual ones of the plurality of gate structures 4506 have upper surfaces that are coplanar with the upper surface of the hard mask material 4518 over the contact plugs 4514A or 4514B, as described. of. In one embodiment, although not depicted, a thin oxide layer, such as a thermal or chemical silicon oxide or silicon dioxide layer, is between the fin 4502A and the gate dielectric layer 4526 .

本發明的一或更多個實施例係有關閘極對齊接觸製程(gate aligned contact process)。此種製程可以被施行來形成用於半導體結構製造(例如，積體電路製造)的接觸結構。在一實施例中，接觸圖案被形成為對齊於現有的閘極圖案。相比之下，其他方法典型上涉及具有光刻接觸圖案對現有的閘極圖案的緊密對位(tight registration)結合選擇性接觸蝕刻之額外的光刻製程。例如，另一製程可以包含具有分開地圖案化接觸和接觸插塞之多晶(閘極)柵格的圖案化。 One or more embodiments of the invention relate to a gate aligned contact process. Such processes may be performed to form contact structures for semiconductor structure fabrication (eg, integrated circuit fabrication). In one embodiment, contact patterns are formed to align with existing gate patterns. In contrast, other approaches typically involve an additional photolithographic process with tight registration of the photolithographic contact pattern to the existing gate pattern combined with selective contact etching. For example, another process may include patterning of a poly (gate) grid with separately patterned contacts and contact plugs.

依據本文中所述的一或更多個實施例，接觸 形成的方法涉及接觸圖案的形成，其基本上完美地對準於現有的閘極圖案，且同時排除需要有極度緊密對位預算(budget)的光刻操作之使用。在一個實施例中，此方法致使能夠使用在本質上為高度選擇性的濕式蝕刻(對上乾式或電漿蝕刻)來產生接觸開口。在一實施例中，藉由利用現有的閘極圖案結合接觸插塞光刻操作來形成接觸圖案。在一個這樣的實施例中，該方法致使能夠排除需要使用其他臨界(critical)光刻操作來產生接觸圖案，如同在其他方法中所使用的。在一實施例中，溝槽接觸柵格不被分開地圖案化，而是被形成在多晶(閘極)線之間。例如，在一個這樣的實施例中，溝槽接觸柵格被形成在閘極光柵圖案化之後而不是在閘極光柵切割之前。 According to one or more embodiments described herein, contacting The method of formation involves the formation of a contact pattern that is substantially perfectly aligned to the existing gate pattern while at the same time precluding the use of photolithographic operations that require extremely tight alignment budgets. In one embodiment, this method enables the use of wet etching (over dry or plasma etching) which is highly selective in nature to create contact openings. In one embodiment, the contact pattern is formed by using the existing gate pattern combined with a contact plug photolithography operation. In one such embodiment, the method enables the elimination of the need to use other critical photolithographic operations to generate contact patterns, as used in other methods. In an embodiment, the trench contact grid is not patterned separately, but is formed between the poly (gate) lines. For example, in one such embodiment, the trench contact grid is formed after gate grating patterning rather than before gate grating cutting.

圖46A到46D繪示依據本發明的一實施例，代表製造包含具有硬遮罩材料形成於其上之溝槽接觸插塞之積體電路結構的方法中之各種操作的剖面視圖。 46A-46D illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure including trench contact plugs having hard mask material formed thereon in accordance with an embodiment of the present invention.

參照圖46A，製造積體電路結構的方法包含複數個鰭部，該複數個鰭部之個別的一些4602係沿著第一方向4604。該複數個鰭部之個別的一些4602可以包含擴散區域4606。複數個閘極結構4608係形成在該複數個鰭部之上。該複數個閘極結構4608之個別的一些係沿著與該第一方向4604正交的第二方向4610(例如，方向4610係進入或離開頁面)。犧牲材料結構4612係形成在該等閘極結構4608的第一對之間。接觸插塞4614係形成在該等閘極結構4608的第二對之間。該接觸插塞包含下電介質材料4616。 硬遮罩材料4618係在該下電介質材料4616上。 Referring to FIG. 46A , a method of fabricating an integrated circuit structure includes a plurality of fins, individual ones 4602 of the plurality of fins are along a first direction 4604 . Individual ones 4602 of the plurality of fins may include diffusion regions 4606 . A plurality of gate structures 4608 are formed over the plurality of fins. Individual ones of the plurality of gate structures 4608 are along a second direction 4610 that is orthogonal to the first direction 4604 (eg, direction 4610 is into or out of a page). A sacrificial material structure 4612 is formed between the first pair of gate structures 4608 . Contact plugs 4614 are formed between the second pair of gate structures 4608 . The contact plug includes a lower dielectric material 4616 . Hard mask material 4618 is tied to the lower dielectric material 4616 .

在一實施例中，該等閘極結構4608包含犧牲或假性閘極堆疊和電介質間隔層4609。該犧牲或假性閘極堆疊可以由多晶矽或氮化矽短柱(pillar)或者某樣其他的犧牲材料，其可以被稱為閘極假性材料。 In one embodiment, the gate structures 4608 include sacrificial or dummy gate stacks and dielectric spacers 4609 . The sacrificial or dummy gate stack may consist of polysilicon or silicon nitride pillars or some other sacrificial material, which may be referred to as a gate dummy material.

參照圖46B，犧牲材料結構4612從圖46A的結構中被去除以形成開口4620在該等閘極結構4608的第一對之間。 Referring to FIG. 46B , the sacrificial material structure 4612 is removed from the structure of FIG. 46A to form an opening 4620 between the first pair of gate structures 4608 .

參照圖46C，溝槽接觸結構4622係形成該等閘極結構4608的第一對之間的開口4620中。除此之外，在一實施例中，作為形成溝槽接觸結構4622的部件，圖46A和46B的硬遮罩4618被平坦化。最後最終的接觸插塞4614’包含下電介質材料4616和從硬遮罩材料4618所形成的上硬遮罩材料4624。 Referring to FIG. 46C , trench contact structures 4622 are formed in openings 4620 between the first pair of gate structures 4608 . Additionally, in one embodiment, the hard mask 4618 of FIGS. 46A and 46B is planarized as part of the formation of the trench contact structure 4622 . The final final contact plug 4614' comprises a lower dielectric material 4616 and an upper hard mask material 4624 formed from a hard mask material 4618.

在一實施例中，該等接觸插塞4614’之各者的下電介質材料4616包含矽和氧，而且該等接觸插塞4614’之各者的上硬遮罩材料4624包含矽和氮。在一實施例中，該等溝槽接觸結構4622之各者包含下導電結構4626和在該下導電結構4626上的電介質蓋部4628。在一個實施例中，該溝槽接觸結構4622的電介質蓋部4628具有與該接觸插塞4614’之上硬遮罩材料4624的上表面共平面的上表面。 In one embodiment, the lower dielectric material 4616 of each of the contact plugs 4614' includes silicon and oxygen, and the upper hard mask material 4624 of each of the contact plugs 4614' includes silicon and nitrogen. In one embodiment, each of the trench contact structures 4622 includes a lower conductive structure 4626 and a dielectric cap 4628 on the lower conductive structure 4626 . In one embodiment, the dielectric cap portion 4628 of the trench contact structure 4622 has an upper surface that is coplanar with the upper surface of the hard mask material 4624 over the contact plug 4614'.

參照圖46D，閘極結構4608之犧牲或假性閘極堆疊被置換於置換閘極製程方案中。在這樣的方案中， 諸如多晶矽或氮化矽短柱材料的假性閘極材料被去除並且以永久性閘極電極材料來取代。在一個這樣的實施例中，永久性閘極電介質層也被形成於此製程中，而不是被實施自先前的處理中。 Referring to FIG. 46D, the sacrificial or dummy gate stack of gate structure 4608 is replaced in a replacement gate process scheme. In such a scheme, The dummy gate material, such as polysilicon or silicon nitride stub material, is removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process rather than being implemented from a previous process.

因此，永久性閘極結構4630包含永久性閘極電介質層4632和永久性閘極電極層或堆疊4634。除此之外，在一實施例中，永久性閘極結構4630的頂部藉由蝕刻製程來予以去除，並且用電介質蓋部4634來取代。在一實施例中，永久性閘極結構4630之個別的一些的電介質蓋部4636具有與該接觸插塞4614’之上硬遮罩材料4624的上表面共平面的上表面。 Thus, permanent gate structure 4630 includes permanent gate dielectric layer 4632 and permanent gate electrode layer or stack 4634 . Additionally, in one embodiment, the top of the permanent gate structure 4630 is removed by an etch process and replaced with a dielectric cap 4634 . In one embodiment, the dielectric caps 4636 of individual ones of the permanent gate structures 4630 have upper surfaces that are coplanar with the upper surface of the hard mask material 4624 over the contact plugs 4614'.

再次參照圖46A到46D，在一實施例中，置換閘極製程被實施於形成溝槽接觸結構4622之後，如同所描述的。然而，依據其他實施例，置換閘極製程被實施於形成溝槽接觸結構4622之前。 Referring again to FIGS. 46A-46D , in one embodiment, a replacement gate process is performed after forming the trench contact structure 4622 , as described. However, according to other embodiments, the replacement gate process is performed before forming the trench contact structure 4622 .

在另一態樣中，接觸在作用閘極之上(COAG)結構以及製程被說明。本發明的一或更多個實施例係有關半導體結構或裝置，其具有一或更多個閘極接觸結構(例如，閘極接觸介層)被設置在半導體結構或裝置之閘極電極的作用部位之上。本發明的一或更多個實施例係有關製造半導體結構或裝置的方法，該半導體結構或裝置具有一或更多個閘極接觸結構被形成在半導體結構或裝置之閘極電極的作用部位之上。本文中所述的方法可以被用來藉由致使能夠形成閘極接觸於作用閘極區域之上來減小 標準的晶胞面積(cell area)。在一或更多個實施例中，被製造來接觸該等閘極電極的閘極接觸結構為自對準的介層結構。 In another aspect, a contact-on-active-gate (COAG) structure and process are described. One or more embodiments of the present invention relate to a semiconductor structure or device having one or more gate contact structures (eg, gate contact vias) disposed on the gate electrode of the semiconductor structure or device. on the part. One or more embodiments of the present invention relate to methods of fabricating a semiconductor structure or device having one or more gate contact structures formed between the active sites of a gate electrode of the semiconductor structure or device superior. The methods described herein can be used to reduce the Standard unit cell area (cell area). In one or more embodiments, the gate contact structures fabricated to contact the gate electrodes are self-aligned via structures.

在其空間和佈局限制相較於目前世代的空間和佈局限制有點放寬的技術中，可以藉由做出到該閘極電極設置在隔離區域之上的部位的接觸來製作到閘極結構的接觸。做為範例，圖47A繪示半導體裝置的平面視圖，該半導體裝置具有閘極接觸被設置在閘極電極的非作用部位之上。 In technologies whose space and layout constraints are somewhat relaxed compared to those of current generations, contact to the gate structure can be made by making contact to the portion of the gate electrode disposed over the isolation region . As an example, FIG. 47A shows a plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode.

參照圖47A，半導體結構或裝置4700A包含設置在基板4702中的擴散或作用區域4704，而且在隔離區域4706之內。諸如閘極線4708A,4708B及4708C的一或更多條閘極線(也稱為多晶線(poly line))被設置在該擴散或作用區域4704之上以及在隔離區域4706的一部位之上。諸如接觸4710A及4710B的源極或汲極接觸(也稱為溝槽接觸)被設置在半導體結構或裝置4700A的源極和汲極區域之上。溝槽接觸介層4712A及4712B分別提供到溝槽接觸4710A及4710B的接觸。分開的閘極接觸4714，以及上覆的閘極接觸介層4716，提供到閘極線4708B的接觸。與源極或汲極溝槽接觸4710A或4710B對比，從平面視圖透視圖來看，該閘極接觸4714被設置在隔離區域4706之上，但是不在該擴散或作用區域4704之上。此外，該閘極接觸4714和該閘極接觸介層4716兩者皆未被設置在源極或汲極溝槽接觸4710A和4710B之間。 Referring to FIG. 47A , a semiconductor structure or device 4700A includes a diffusion or active region 4704 disposed in a substrate 4702 and within an isolation region 4706 . One or more gate lines (also referred to as poly lines), such as gate lines 4708A, 4708B, and 4708C, are disposed over the diffusion or active region 4704 and between a portion of the isolation region 4706 superior. Source or drain contacts (also referred to as trench contacts), such as contacts 4710A and 4710B, are disposed over the source and drain regions of semiconductor structure or device 4700A. Trench contact vias 4712A and 4712B provide contacts to trench contacts 4710A and 4710B, respectively. Separate gate contacts 4714, and overlying gate contact vias 4716, provide contact to gate line 4708B. In contrast to source or drain trench contacts 4710A or 4710B, the gate contact 4714 is disposed over the isolation region 4706 but not over the diffusion or active region 4704 from a plan view perspective. Additionally, neither the gate contact 4714 nor the gate contact via 4716 is disposed between source or drain trench contacts 4710A and 4710B.

圖47B繪示非平面型半導體裝置的剖面視圖，該非平面型半導體裝置具有閘極接觸被設置在閘極電極的非作用部位之上。參照圖47B，半導體結構或裝置4700B，例如，圖47A之非平面版本的裝置4700A，包含從基板4702所形成的非平面擴散或作用區域4704C(例如，鰭部結構)，而且在隔離區域4706之內。閘極線4708B被設置在該非平面擴散或作用區域4704B之上以及在隔離區域4706的一部位之上。如同所示，閘極線4708B包含閘極電極4750和閘極電介質層4752以及電介質蓋層4754。閘極接觸4714和上覆的(overlying)閘極接觸介層4716連同上覆的金屬互連部4760一起也從此透視圖中被看到，這些都被設置在層間電介質堆疊或層4770中。也從圖47B的透視圖中看到，該閘極接觸4714被設置在隔離區域4706之上，但是不在該非平面擴散或作用區域4704B之上。 47B shows a cross-sectional view of a non-planar semiconductor device with a gate contact disposed over an inactive portion of the gate electrode. Referring to FIG. 47B, a semiconductor structure or device 4700B, such as the non-planar version of device 4700A of FIG. Inside. Gate line 4708B is disposed over the non-planar diffusion or active region 4704B and over a portion of isolation region 4706 . As shown, gate line 4708B includes gate electrode 4750 and gate dielectric layer 4752 and dielectric capping layer 4754 . Gate contact 4714 and overlying gate contact via 4716 are also seen from this perspective along with overlying metal interconnect 4760 , which are all disposed in interlayer dielectric stack or layer 4770 . Also seen from the perspective view of FIG. 47B, the gate contact 4714 is disposed over the isolation region 4706, but not over the non-planar diffusion or active region 4704B.

再次參照圖47A和47B，半導體結構或裝置4700A和4700B的配置分別將閘極接觸放置在隔離區域之上。此種配置浪費佈局空間。然而，將閘極接觸放置在作用區域之上將會需要極度緊密對位預算(budget)或閘極尺寸，此將必須增加來提供足夠的空間來置放閘極接觸。此外，在歷史上，為了防止鑽穿過其他閘極材料(例如，多晶矽)和接觸下面的作用區域的風險，已經避開了到擴散區域之上的閘極之接觸。本文中所述之一或更多個實施例藉由提供可行方法來對付上面的問題，而且結果的結構，要製造接觸閘極電極形成在擴散或作用區域之上的部位之 接觸結構。 Referring again to FIGS. 47A and 47B , the configurations of semiconductor structures or devices 4700A and 4700B respectively place gate contacts over isolation regions. This configuration wastes layout space. However, placing the gate contact above the active area would require an extremely tight alignment budget or gate size, which would have to be increased to provide enough space to place the gate contact. Furthermore, historically, contact to the gate above the diffusion region has been avoided in order to prevent the risk of drilling through other gate material (eg, polysilicon) and contacting the active area below. One or more embodiments described herein address the above problems by providing a viable method, and resulting structure, to fabricate contact gate electrodes formed at sites over diffusion or active regions. contact structure.

做為範例，圖48A繪示依據本發明的一實施例，半導體裝置的平面視圖，該半導體裝置具有閘極接觸介質被設置在閘極電極的作用部位之上。參照圖48A，半導體結構或裝置4800A包含設置在基板4802中的擴散或作用區域4804，而且在隔離區域4806之內。諸如閘極線4808A,4808B及4808C的一或更多條閘極線被設置在該擴散或作用區域4804之上以及在隔離區域4806的一部位之上。諸如溝槽接觸4810A及4810B的源極或汲極溝槽接觸被設置在半導體結構或裝置4800A的源極和汲極區域之上。溝槽接觸介層4812A及4812B分別提供到溝槽接觸4810A及4810B的接觸。沒有中介之分開的閘極接觸層的閘極接觸介層4816提供到閘極線4808B的接觸。與圖47A對比，從平面視圖透視圖來看，該閘極接觸4816被設置在該擴散或作用區域4804之上，而且在源極或汲極溝槽接觸4810A和4810B之間。 As an example, FIG. 48A shows a plan view of a semiconductor device having a gate contact dielectric disposed over the active portion of the gate electrode in accordance with an embodiment of the present invention. Referring to FIG. 48A , a semiconductor structure or device 4800A includes a diffusion or active region 4804 disposed in a substrate 4802 and within an isolation region 4806 . One or more gate lines, such as gate lines 4808A, 4808B, and 4808C, are disposed over the diffusion or active region 4804 and over a portion of the isolation region 4806 . Source or drain trench contacts, such as trench contacts 4810A and 4810B, are disposed over the source and drain regions of semiconductor structure or device 4800A. Trench contact vias 4812A and 4812B provide contacts to trench contacts 4810A and 4810B, respectively. Gate contact via 4816 without an intervening separate gate contact layer provides contact to gate line 4808B. In contrast to FIG. 47A , from a plan view perspective, the gate contact 4816 is disposed over the diffusion or active region 4804 and between source or drain trench contacts 4810A and 4810B.

圖48B繪示依據本發明的一實施例，非平面型半導體裝置的剖面視圖，該非平面型半導體裝置具有閘極接觸介層被設置在閘極電極的作用部位之上。參照圖48B，半導體結構或裝置4800B，例如，圖48A之非平面版本的裝置4800A，包含從基板4802所形成的非平面擴散或作用區域4804B(例如，鰭部結構)，而且在隔離區域4806之內。閘極線4808B被設置在該非平面擴散或作用區域4804B之上以及在隔離區域4806的一部位之上。如同所 示，閘極線4808B包含閘極電極4850和閘極電介質層4852連同電介質蓋層4854一起。閘極接觸介層4816連同上覆(overlying)的金屬互連部4860一起也從此透視圖中被看到，這兩者都被設置在層間電介質堆疊或層4870中。也從圖48B的透視圖中看到，該閘極接觸介層4816被設置在非平面擴散或作用區域4804B之上。 48B is a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over the active portion of the gate electrode, according to an embodiment of the present invention. Referring to FIG. 48B, a semiconductor structure or device 4800B, such as the non-planar version of device 4800A of FIG. Inside. Gate line 4808B is disposed over the non-planar diffusion or active region 4804B and over a portion of isolation region 4806 . as said As shown, gate line 4808B includes gate electrode 4850 and gate dielectric layer 4852 together with dielectric capping layer 4854 . Gate contact via 4816 is also seen from this perspective along with overlying metal interconnect 4860 , both of which are disposed in interlayer dielectric stack or layer 4870 . Also seen in the perspective view of FIG. 48B, the gate contact via 4816 is disposed over the non-planar diffusion or active region 4804B.

因此，再次參照圖48A和48B，在一實施例中，溝槽接觸介層4812A,4812B和閘極接觸介層4816被形成在同一個層中而且基本上係共平面的。相較於圖47A和47B，到閘極線的接觸將另外包含額外的閘極接觸層，例如，其可以運行垂直於對應的閘極線。然而，在相關圖48A和48B所說明的結構中，結構4800A和4800B的製造分別致使直接來自金屬互連層的接觸能夠置放在作用閘極部位，而不會使相鄰的源極汲極區域短路(shorting)。在一實施例中，此種配置藉由排除延伸隔離區域上的電晶體閘極以形成可靠的接觸的需求來提供電路佈局中大面積縮減。如同此說明書全文所使用的，在一實施例中，對閘極之作用部位的參考係指閘極線或結構設置在下面的基板之作用或擴散區域之上(從平面視圖透視圖)的部位。在一實施例中，對閘極之非作用部位的參考係指閘極線或結構設置在下面的基板之隔離區域之上(從平面視圖透視圖)的部位。 Thus, referring again to FIGS. 48A and 48B, in one embodiment, trench contact vias 4812A, 4812B and gate contact via 4816 are formed in the same layer and are substantially coplanar. Compared to Figures 47A and 47B, the contacts to the gate lines would additionally comprise an additional gate contact layer, eg, which could run perpendicular to the corresponding gate lines. However, in the structures described with respect to Figures 48A and 48B, structures 4800A and 4800B, respectively, are fabricated such that contacts directly from the metal interconnect layer can be placed at the active gate site without disabling the adjacent source-drain Area shorting. In one embodiment, this configuration provides a large area reduction in circuit layout by eliminating the need to extend the gate of the transistor over the isolation region to form a reliable contact. As used throughout this specification, in one embodiment, reference to the active site of the gate refers to the site where the gate line or structure is disposed (from a plan view perspective) over the active or diffusion area of the underlying substrate. . In one embodiment, references to inactive locations of the gate refer to locations where the gate lines or structures are disposed over (from a plan view perspective) isolated regions of the underlying substrate.

在一實施例中，半導體結構或裝置4800為非平面型裝置，諸如但不限於鰭部-FET(fin-FET)或三閘極裝置。在這樣的實施例中，對應的半導體通道區域係由三維 本體組成或者被形成於三維本體中。在一個這樣的實施例中，閘極電極堆疊的閘極線4808A到4808C包圍至少三維本體的頂部表面及一對側壁。在另一實施例中，至少該通道區域被做成為分離的三維本體，諸如在閘極全繞式(gate-all-around)裝置中。在一個這樣的實施例中，該等閘極電極堆疊的閘極線4808A到4808C各自完全地包圍該通道區域。 In one embodiment, the semiconductor structure or device 4800 is a non-planar device such as, but not limited to, a fin-FET (fin-FET) or a tri-gate device. In such an embodiment, the corresponding semiconductor channel region is composed of three-dimensional A body is composed or formed in a three-dimensional body. In one such embodiment, the gate lines 4808A-4808C of the gate electrode stack surround at least a top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, at least the channel region is made as a separate three-dimensional body, such as in a gate-all-around device. In one such embodiment, the gate lines 4808A-4808C of the gate electrode stacks each completely surround the channel region.

更一般地說，一或更多個實施例係有關使閘極接觸介層直接置放在作用電晶體閘極上的方法，以及從使閘極接觸介層直接置放在作用電晶體閘極上所形成的結構。此等方法可以排除為了接觸目的而延伸隔離區域上的閘極線之需求。此等方法也可以排除分開的閘極接觸(GCN)層以傳導來自閘極線或結構的信號之需求。在一實施例中，藉由使溝槽接觸(TCN)中的接觸金屬凹入並且在該製程流程(例如，TILA)中導入額外的電介質材料來達成消除上面的特徵。該額外的電介質材料被包含作為溝槽接觸電介質蓋部層，其具有與閘極對準接觸製程(GAP)處理方案(例如，GILA)中已經被使用於溝槽接觸對準之閘極電介質材料蓋層不同的蝕刻特性。 More generally, one or more embodiments relate to a method for placing a gate contact via directly on the gate of an active transistor, and methods for placing a gate contact via directly on the gate of an active transistor. formed structure. These approaches can eliminate the need to extend the gate lines on the isolation regions for contact purposes. Such approaches may also eliminate the need for a separate gate contact (GCN) layer to conduct signals from gate lines or structures. In one embodiment, eliminating the above features is achieved by recessing the contact metal in the trench contact (TCN) and introducing additional dielectric material in the process flow (eg, TILA). The additional dielectric material is included as a trench contact dielectric cap layer with the same gate dielectric material already used for trench contact alignment in a Gate Alignment Contact Process (GAP) process scheme (eg, GILA) Different etching characteristics of the cap layer.

做為代表性製造方案，圖49A到49D繪示依據本發明的一實施例，代表製造具有閘極接觸結構設置在閘極的作用部位之上的半導體結構的方法中之各種操作的剖面視圖。 As a representative fabrication scheme, FIGS. 49A through 49D illustrate cross-sectional views representing various operations in a method of fabricating a semiconductor structure having a gate contact structure disposed over an active site of a gate in accordance with an embodiment of the present invention.

參照圖49A，半導體結構4900被提供於溝槽 接觸(TCN)形成之後。將可領會到，結構4900的特定配置僅被使用於例舉目的，以及各種可能的佈局可以從本文中所述之本發明的實施例中獲利。半導體結構4900包含一或更多個閘極堆疊結構，諸如設置在基板4902之上的閘極堆疊結構4908A到4908E。閘極堆疊結構可以包含閘極電介質層和閘極電極。溝槽接觸，例如，到基板4902之擴散區域的接觸，諸如溝槽接觸4910A到4910C也被包含在結構4900中，而且藉由電介質間隔層4920而與閘極堆疊結構4908A到4908E間隔分開。絕緣蓋層4922可以被設置閘極堆疊結構4908A到4908E上(例如，GILA)，如同也被描述於圖49A中。如同也被描述於圖49A中，接觸阻擋區域或”接觸插塞”，諸如由層間電介質材料所製造的區域4923，可以被包含在接觸形成要被阻擋的區域中。 Referring to FIG. 49A, a semiconductor structure 4900 is provided in the trench After contact (TCN) formation. It will be appreciated that the particular configuration of structure 4900 is used for exemplary purposes only, and that various possible arrangements may benefit from the embodiments of the invention described herein. Semiconductor structure 4900 includes one or more gate stack structures, such as gate stack structures 4908A- 4908E disposed over substrate 4902 . The gate stack structure may include a gate dielectric layer and a gate electrode. Trench contacts, eg, contacts to diffused regions of substrate 4902 , such as trench contacts 4910A- 4910C are also included in structure 4900 and are spaced apart from gate stacks 4908A- 4908E by dielectric spacer 4920 . An insulating cap layer 4922 may be disposed over the gate stacks 4908A-4908E (eg, GILA), as also described in FIG. 49A . As also described in FIG. 49A, contact blocking regions or "contact plugs," such as region 4923 fabricated from interlayer dielectric material, may be included in the region where contact formation is to be blocked.

在一實施例中，提供結構4900涉及接觸圖案的形成，而接觸圖案基本上係與現有的閘極圖案完美地對準，且同時排除需要有極度緊密對位預算的光刻操作之使用。在一個這樣的實施例中，此方法致使能夠使用在本質上為高度選擇性的濕式蝕刻(例如，對上乾式或電漿蝕刻)來產生接觸開口。在一實施例中，藉由利用現有的閘極圖案結合接觸插塞光刻操作來形成接觸圖案。在一個這樣的實施例中，該方法致使能夠排除需要使用其他臨界(critical)光刻操作來產生接觸圖案，如同在其他方法中所使用的。在一實施例中，溝槽接觸柵格不被分開地圖案化，而是被形成在多晶(閘極)線之間。例如，在一個這樣 的實施例中，溝槽接觸柵格被形成在閘極光柵圖案化之後而不是在閘極光柵切割之前。 In one embodiment, providing structure 4900 involves the formation of contact patterns that are substantially perfectly aligned with existing gate patterns while precluding the use of photolithographic operations that require extremely tight alignment budgets. In one such embodiment, the method enables the use of a wet etch that is highly selective in nature (eg, dry or plasma etch on top) to create contact openings. In one embodiment, the contact pattern is formed by using the existing gate pattern combined with a contact plug photolithography operation. In one such embodiment, the method enables the elimination of the need to use other critical photolithographic operations to generate contact patterns, as used in other methods. In an embodiment, the trench contact grid is not patterned separately, but is formed between the poly (gate) lines. For example, in a In an embodiment of the present invention, the trench contact grid is formed after gate grating patterning rather than before gate grating cutting.

此外，可以藉由置換閘極製程來製作閘極堆疊結構4908A到4908E。在此種方案中，諸如多晶矽或氮化矽短柱材料之假性閘極材料可以被去除並且以永久性閘極電極材料來取代。在一個這樣的實施例中，永久性閘極電介質層也被形成於此製程中，而不是被實施自先前的處理中。在一實施例中，藉由乾式蝕刻或濕式蝕刻製程來去除假性閘極。在一個實施例中，假性閘極係由多晶矽或非晶矽所組成並且用包含SF6的乾式蝕刻製程來予以去除。在另一實施例中，假性閘極係由多晶矽或非晶矽所組成並且用包含水性(aqueous)NH4OH或氫氧化四甲銨(tetramethylammonium hydroxide)的濕式蝕刻製程來予以去除。在一個實施例中，假性閘極係由多氮化矽所組成並且用包含水性磷酸(aqueous phosphoric acid)的濕式蝕刻製程來予以去除。 In addition, the gate stack structures 4908A to 4908E may be fabricated by a replacement gate process. In this approach, dummy gate material such as polysilicon or silicon nitride stub material can be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process rather than being implemented from a previous process. In one embodiment, the dummy gates are removed by dry etching or wet etching. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a dry etch process including SF 6 . In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a wet etch process involving aqueous NH 4 OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of polysilicon nitride and is removed using a wet etch process including aqueous phosphoric acid.

在一實施例中，本文中所述的一或更多個方法基本上細思(contemplate)假性和置換閘極製程結合假性和置換接觸製程來達成結構4900。在一個這樣的實施例中，置換接觸製程被實施於置換閘極製程之後，得以讓永久性閘極堆疊的至少一部分能夠進行高溫退火。例如，在一特定之這樣的實施例中，該永久性閘極結構之至少一部分的退火，例如在閘極電介質層被形成之後，被實施於大於約攝氏600度的溫度下。該退火被實施於該永久性接觸的形成之前。 In one embodiment, one or more methods described herein substantially contemplate dummy and replacement gate processes in combination with dummy and replacement contact processes to achieve structure 4900 . In one such embodiment, a replacement contact process is performed after the replacement gate process to allow high temperature annealing of at least a portion of the permanent gate stack. For example, in a particular such embodiment, annealing of at least a portion of the permanent gate structure, eg, after the gate dielectric layer is formed, is performed at a temperature greater than about 600 degrees Celsius. The anneal is performed prior to the formation of the permanent contact.

參照圖49B，結構4900的溝槽接觸4910A到4910C被凹入於間隔層4920之內，以形成具有在間隔層4920和絕緣蓋層4922的頂部表面之下的高度之凹入的溝槽接觸4911A到4911C。絕緣蓋層4924然後被形成在凹入的溝槽接觸4911A到4911C上(例如，TILA)。依據本發明的實施例，在凹入的溝槽接觸4911A到4911C上的絕緣蓋層4924係由具有與閘極堆疊結構4908A到4908E上之絕緣蓋層4922不同的蝕刻特性的材料所組成。如同將在後續的處理操作中所看到的，此種差異可以被利用來選擇性地從4922/4924的其中一者蝕刻4922/4924的另一者。 Referring to FIG. 49B , trench contacts 4910A to 4910C of structure 4900 are recessed within spacer layer 4920 to form recessed trench contacts 4911A having a height below the top surfaces of spacer layer 4920 and insulating cap layer 4922 to 4911C. An insulating cap layer 4924 is then formed over the recessed trench contacts 4911A-4911C (eg, TILA). Insulative capping layer 4924 on recessed trench contacts 4911A-4911C is composed of a material having different etch properties than insulating capping layer 4922 on gate stack structures 4908A-4908E in accordance with an embodiment of the invention. As will be seen in subsequent processing operations, this difference can be exploited to selectively etch one of 4922/4924 from the other 4922/4924.

可以藉由對間隔層4920和絕緣蓋層4922的材料有選擇性的製程來使溝槽接觸4910A到4910C凹入。例如，在一個實施例中，藉由諸如濕式蝕刻製程或乾式蝕刻製程的蝕刻製程來使溝槽接觸4910A到4910C凹入。可以藉由適合來提供共形及密封的層於溝槽接觸4910A到4910C之露出部位上方的製程來形成絕緣蓋層4924。例如，在一個實施例中，藉由化學氣相沉積(CVD)製程來形成絕緣蓋層4924作為在整個結構上方的共形層。該共形層然後例如藉由化學機械拋光(CMP)製程而被平坦化，以提供絕緣蓋層4924材料僅在溝槽接觸4910A到4910C的上方，而且使間隔層4920和絕緣蓋層4922再度暴露出。 Trench contacts 4910A- 4910C may be recessed by processes that are selective to the materials of spacer layer 4920 and insulating cap layer 4922 . For example, in one embodiment, trench contacts 4910A-4910C are recessed by an etch process such as a wet etch process or a dry etch process. Insulating cap layer 4924 may be formed by a process suitable to provide a conformal and hermetic layer over the exposed portions of trench contacts 4910A-4910C. For example, in one embodiment, the insulating cap layer 4924 is formed by a chemical vapor deposition (CVD) process as a conformal layer over the entire structure. The conformal layer is then planarized, such as by a chemical mechanical polishing (CMP) process, to provide insulating cap layer 4924 material only over trench contacts 4910A-4910C, and to re-expose spacer layer 4920 and insulating cap layer 4922. out.

關於針對絕緣蓋層4922/4924之適合的材料組合，在一個實施例中，該對4922/4924的其中一個係由氧化矽所組成而另一個係由氮化矽所組成。在另一實施例 中，該對4922/4924的其中一個係由氧化矽所組成而另一個係由摻雜碳的氮化矽所組成。在另一實施例中，該對4922/4924的其中一個係由氧化矽所組成而另一個係由碳化矽所組成。在另一實施例中，該對4922/4924的其中一個係由氮化矽所組成而另一個係由摻雜碳的氮化矽所組成。在另一實施例中，該對4922/4924的其中一個係由氮化矽所組成而另一個係由碳化矽所組成。在另一實施例中，該對4922/4924的其中一個係由摻雜碳的氮化矽所組成而另一個係由碳化矽所組成。 Regarding a suitable combination of materials for the insulating cap layers 4922/4924, in one embodiment, one of the pair 4922/4924 is composed of silicon oxide and the other is composed of silicon nitride. In another embodiment Among them, one of the pair 4922/4924 is composed of silicon oxide and the other is composed of carbon-doped silicon nitride. In another embodiment, one of the pair 4922/4924 is composed of silicon oxide and the other is composed of silicon carbide. In another embodiment, one of the pair 4922/4924 is composed of silicon nitride and the other is composed of carbon doped silicon nitride. In another embodiment, one of the pair 4922/4924 is composed of silicon nitride and the other is composed of silicon carbide. In another embodiment, one of the pair 4922/4924 is composed of carbon doped silicon nitride and the other is composed of silicon carbide.

參照圖49C，層間電介質(ILD)4930和硬遮罩4932堆疊被形成而且被圖案化來提供，例如，圖案化於圖49B之結構上方的金屬(0)溝槽4934。 Referring to FIG. 49C, interlayer dielectric (ILD) 4930 and hard mask 4932 stacks are formed and patterned to provide, for example, metal (0) trenches 4934 patterned over the structure of FIG. 49B.

層間電介質(ILD)4930可以由適合來電隔離最終被形成於其中的金屬特徵且同時保持前端處理與後端處理間之強健結構的材料所組成。此外，在一實施例中，選擇ILD 4930的組成與針對溝槽接觸電介質蓋層圖案化的介層蝕刻選擇性一致，如同下面關於圖49D所更詳細說明者。在一個實施例中，ILD 4930係由單層或幾層的氧化矽層或者單層或幾層的摻碳氧化物(CDO)材料所組成。然而，在其他實施例中，ILD 4930具有雙層(bi-layer)組成，而ILD 4930的頂部部位係由與ILD 4930之下面的底部部位不同的材料所組成。硬遮罩層4932可由適合來用作為後續的犧牲層之材料所組成。例如，在一個實施例中，硬遮罩層4932實質上係由碳所組成，例如，作為交聯(cross- linked)有機聚合物層。在其他實施例中，氮化矽或摻雜碳的氮化矽層被用作為硬遮罩4932。層間電介質(ILD)4930和硬遮罩4932堆疊可以藉由光刻和蝕刻製程來予以圖案化。 Interlayer dielectric (ILD) 4930 may be composed of a material suitable for electrically isolating metal features ultimately formed therein while maintaining a robust structure between front-end processing and back-end processing. Furthermore, in one embodiment, the composition of the ILD 4930 is selected consistent with via etch selectivity for trench contact dielectric cap patterning, as described in more detail below with respect to FIG. 49D. In one embodiment, the ILD 4930 is composed of a single or several layers of silicon oxide or a single or several layers of carbon doped oxide (CDO) material. However, in other embodiments, the ILD 4930 has a bi-layer composition, and the top portion of the ILD 4930 is composed of a different material than the underlying bottom portion of the ILD 4930 . The hard mask layer 4932 may be composed of a material suitable for use as a subsequent sacrificial layer. For example, in one embodiment, the hard mask layer 4932 consists essentially of carbon, eg, as a cross-link (cross- linked) organic polymer layer. In other embodiments, a silicon nitride or carbon doped silicon nitride layer is used as the hard mask 4932 . The interlayer dielectric (ILD) 4930 and hard mask 4932 stacks can be patterned by photolithography and etching processes.

參照圖49D，介層開口4936(例如，VCT)被形成在層間電介質(ILD)4930中，從金屬(0)溝槽4934延伸到凹入的溝槽接觸4911A到4911C的一或更多者。例如，在圖49D中，介層開口4936被形成來使凹入的溝槽接觸4911A到4911C暴露出。介層開口4936的形成包含層間電介質(ILD)4930和對應之絕緣蓋層4924的個別部位兩者的蝕刻。在一個這樣的實施例中，一部分的絕緣蓋層4922在層間電介質(ILD)4930的圖案化期間被暴露出(例如，在閘極堆疊結構4908B和4908E之上的一部分絕緣蓋層4922被暴露出)。在該實施例中，絕緣蓋層4924被蝕刻來形成針對絕緣蓋層4922而選擇的(亦即，沒有顯著地蝕刻或影響)介層開口4936。 Referring to FIG. 49D , via openings 4936 (eg, VCT) are formed in interlayer dielectric (ILD) 4930 extending from metal (0) trenches 4934 to one or more of recessed trench contacts 4911A-4911C. For example, in FIG. 49D, via openings 4936 are formed to expose recessed trench contacts 4911A-4911C. Formation of via openings 4936 includes etching of both interlayer dielectric (ILD) 4930 and corresponding individual portions of insulating cap layer 4924 . In one such embodiment, a portion of insulating capping layer 4922 is exposed during patterning of interlayer dielectric (ILD) 4930 (eg, a portion of insulating capping layer 4922 is exposed over gate stack structures 4908B and 4908E ). In this embodiment, the insulating cap layer 4924 is etched to form via openings 4936 that are selected for (ie, not significantly etched or affected by) the insulating cap layer 4922 .

在一個實施例中，介層開口圖案最終藉由蝕刻製程而被轉移到絕緣蓋層4924(亦即，溝槽接觸絕緣蓋層)，但沒有蝕刻絕緣蓋層4922(亦即，閘極絕緣蓋層)。絕緣蓋層4924(TILA)可以由下面的任何一個或其組合所組成，包含氧化矽、氮化矽、碳化矽、摻雜碳的氮化矽、摻雜碳的氧化矽、非晶矽、各種金屬氧化物和矽酸鹽，其包含氧化鋯、氧化鉿、氧化鑭、或其組合。該層可以使用下面技術的任何一者來予以沉積，包含CVD、ALD、 PECVD、PVD、HDP輔助CVD、低溫CVD。對應的電漿乾式蝕刻被發展作為化學和物理濺鍍機制的組合。同時發生的聚合物沉積可以被用來控制材料去除率、蝕刻輪廓和膜選擇性。該乾式蝕刻典型上係混和著包含NF3,CHF3,C4F8,HBr和O2等氣體，典型上以在30到100mTorr之範圍中的壓力以及50到1000瓦(Watt)的電漿偏壓(plasma bias)所產生的。該乾式蝕刻可以被工程設計來達成蓋層4924(TILA)與4922(GILA)層之間顯著的蝕刻選擇性，以使在4924(TILA)的乾式蝕刻期間4922(GILA)的損失達最小，而形成到電晶體之源極汲極區域的接觸。 In one embodiment, the via opening pattern is finally transferred to the insulating cap layer 4924 (ie, the trench contacts the insulating cap layer) by an etch process, but the insulating cap layer 4922 (ie, the gate insulating cap layer) is not etched. layer). The insulating cover layer 4924 (TILA) can be composed of any one or combination of the following, including silicon oxide, silicon nitride, silicon carbide, carbon-doped silicon nitride, carbon-doped silicon oxide, amorphous silicon, various Metal oxides and silicates comprising zirconia, hafnium oxide, lanthanum oxide, or combinations thereof. This layer can be deposited using any of the following techniques, including CVD, ALD, PECVD, PVD, HDP assisted CVD, low temperature CVD. The corresponding plasma dry etching was developed as a combination of chemical and physical sputtering mechanisms. Simultaneous polymer deposition can be used to control material removal rate, etch profile and film selectivity. The dry etch is typically mixed with a gas containing NF 3 , CHF 3 , C 4 F 8 , HBr and O 2 , typically at a pressure in the range of 30 to 100 mTorr and a plasma of 50 to 1000 watts (Watt). Generated by the plasma bias. The dry etch can be engineered to achieve significant etch selectivity between the cap layer 4924(TILA) and 4922(GILA) layers so that the loss of 4922(GILA) is minimized during the dry etch of 4924(TILA), while Contacts are formed to the source-drain regions of the transistors.

再次參照圖49D，將領會到類似的方法可以被施行而藉由蝕刻製程來製造最終被轉移到絕緣蓋層4922(亦即，溝槽接觸絕緣蓋層)的介層開口圖案，但沒有蝕刻絕緣蓋層4924(亦即，閘極絕緣蓋層)。 Referring again to FIG. 49D, it will be appreciated that a similar approach can be performed by an etch process to create the via opening pattern that is eventually transferred to the insulating cap layer 4922 (i.e., the trench contacts the insulating cap layer), but without etching the insulating cap layer 4922. Cap layer 4924 (ie, gate insulating cap layer).

為了進一步例示接觸在作用閘極之上(COAG)技術的概念，圖50繪示依據本發明的一實施例，具有包含上覆的絕緣蓋層之溝槽接觸的積體電路結構的平面視圖及對應的剖面視圖。 To further illustrate the concept of contact-on-active-gate (COAG) technology, FIG. 50 shows a plan view of an integrated circuit structure with trench contacts including an overlying insulating cap in accordance with an embodiment of the present invention and Corresponding section view.

參照圖50，積體電路結構5000包含在諸如矽鰭部的半導體基板或鰭部5002上方的閘極線5004。該閘極線5004包含閘極堆疊5005(例如，包含閘極電介質層或堆疊和該閘極電介質層或堆疊上的閘極電極)和該閘極堆疊5005上的閘極絕緣蓋層5006。電介質間隔層5008係沿著該閘極堆疊5005的側壁，而且在一實施例中，係沿著該閘極 絕緣蓋層5006的側壁，如同所描述的。 Referring to FIG. 50 , an integrated circuit structure 5000 includes a gate line 5004 over a semiconductor substrate such as a silicon fin or fin 5002 . The gate line 5004 includes a gate stack 5005 (eg, including a gate dielectric layer or stack and a gate electrode on the gate dielectric layer or stack) and a gate insulating cap layer 5006 on the gate stack 5005 . Dielectric spacers 5008 are along the sidewalls of the gate stack 5005 and, in one embodiment, along the gate The sidewalls of the insulating cap layer 5006 are as described.

溝槽接觸5010係鄰接該閘極線5004的側壁，連同該電介質間隔層5008係在該閘極線5004與該等溝槽接觸5010之間。該等溝槽接觸5010之個別的一些包含導電接觸結構5011和該導電接觸結構5011上的溝槽接觸絕緣蓋層5012。 Trench contacts 5010 are adjacent to the sidewalls of the gate lines 5004 , along with the dielectric spacer 5008 between the gate lines 5004 and the trench contacts 5010 . Individual ones of the trench contacts 5010 include a conductive contact structure 5011 and a trench contact insulating capping layer 5012 on the conductive contact structure 5011 .

再次參照圖50，閘極接觸介層5014係形成在該閘極絕緣蓋層5006的開口中，並且電接觸該閘極堆疊5005。在一實施例中，該閘極接觸介層5014在該半導體基板或鰭部5002之上而且橫向介於該等溝槽接觸5010之間的位置處電接觸該閘極堆疊5005，如同所描述的。在一個這樣的實施例中，該導電接觸結構5011上的溝槽接觸絕緣蓋層5012防止由該閘極接觸介層5014的閘極到源極短路或閘極到汲極短路。 Referring again to FIG. 50 , a gate contact via 5014 is formed in the opening of the gate insulating cap layer 5006 and electrically contacts the gate stack 5005 . In one embodiment, the gate contact via 5014 electrically contacts the gate stack 5005 at a location above the semiconductor substrate or fin 5002 and laterally between the trench contacts 5010, as described. . In one such embodiment, the trench contact insulating capping layer 5012 on the conductive contact structure 5011 prevents a gate-to-source short or a gate-to-drain short from the gate contact via 5014 .

再次參照圖50，溝槽接觸介層5016係形成在該溝槽接觸絕緣蓋層5012的開口中，並且電接觸該等個別的導電接觸結構5011。在一實施例中，該溝槽接觸介層5016在該半導體基板或鰭部5002之上而且橫向鄰接該閘極線5004之閘極堆疊5005的位置處電接觸該等個別的導電接觸結構5011，如同所描述的。在一個這樣的實施例中，該閘極堆疊5005上的該閘極絕緣蓋層5006防止由該溝槽接觸介層5016的源極到閘極短路或汲極到閘極短路。 Referring again to FIG. 50 , trench contact vias 5016 are formed in openings of the trench contact insulating cap layer 5012 and electrically contact the respective conductive contact structures 5011 . In one embodiment, the trench contact via 5016 electrically contacts the respective conductive contact structures 5011 at locations of the gate stack 5005 above the semiconductor substrate or fin 5002 and laterally adjacent to the gate line 5004, as described. In one such embodiment, the gate insulating cap layer 5006 on the gate stack 5005 prevents source-to-gate shorts or drain-to-gate shorts from the trench contact via 5016 .

將領會到介於絕緣閘極蓋層與絕緣溝槽接觸蓋層間之不同的結構關係可以被製造。做為範例，圖51A 到51F繪示依據本發明的一實施例，各種積體電路結構的剖面視圖，其各自具有包含上覆的絕緣蓋層之溝槽接觸並且具有包含上覆的絕緣蓋層之閘極堆疊。 It will be appreciated that different structural relationships between the insulating gate cap and the insulating trench contact cap can be fabricated. As an example, Figure 51A 51F show cross-sectional views of various integrated circuit structures each having a trench contact including an overlying insulating cap and having a gate stack including an overlying insulating cap in accordance with an embodiment of the present invention.

參照圖51A,51B和51C，積體電路結構5100A,5100B和5100C分別包含諸如矽鰭部的鰭部5102。雖然被描述為剖面視圖，將領會到該鰭部5102具有頂部5102A和側壁(進入和離開所示之透視圖的頁面)。第一5104和第二5106閘極電介質層係在該鰭部5102的頂部5102A之上而且橫向鄰接該鰭部5102的側壁。第一5108和第二5110閘極電極係分別在該第一5104和第二5106閘極電介質層之上、在該鰭部5102的頂部5102A之上而且橫向鄰接該鰭部5102的側壁。該第一5108和第二5110閘極電極各自包含諸如功函數設定(workfunction-setting)層的共形導電層5109A，以及在該共形導電層5109A上方的導電性填充材料5109B。該第一5108和第二5110閘極電極兩者皆具有第一側5112和與該第一側5112對立的第二側5114。該第一5108和第二5110閘極電極兩者也具有絕緣蓋部5116，而該絕緣蓋部5116具有頂部表面5118。 51A, 51B and 51C, integrated circuit structures 5100A, 5100B and 5100C respectively include fins 5102 such as silicon fins. Although depicted as a cross-sectional view, it will be appreciated that the fin 5102 has a top 5102A and sidewalls (into and out of the page of the perspective view shown). The first 5104 and second 5106 gate dielectric layers are over the top 5102A of the fin 5102 and laterally adjoin the sidewalls of the fin 5102 . First 5108 and second 5110 gate electrodes are over the first 5104 and second 5106 gate dielectric layers, respectively, over the top 5102A of the fin 5102 and laterally adjoining the sidewalls of the fin 5102 . The first 5108 and second 5110 gate electrodes each comprise a conformal conductive layer 5109A, such as a workfunction-setting layer, and a conductive fill material 5109B over the conformal conductive layer 5109A. Both the first 5108 and second 5110 gate electrodes have a first side 5112 and a second side 5114 opposite the first side 5112 . Both the first 5108 and second 5110 gate electrodes also have an insulating cap 5116 having a top surface 5118 .

第一電介質間隔層5120係鄰接該第一閘極電極5108的第一側5112。第二電介質間隔層5122係鄰接該第二閘極電極5110的第二側5114。半導體源極或汲極區域5124係鄰接該第一5120和第二5122電介質間隔層。溝槽接觸結構5126係在鄰接該第一5120和第二5122電介質間隔層的該半導體源極或汲極區域5124之上。 A first dielectric spacer layer 5120 is adjacent to the first side 5112 of the first gate electrode 5108 . A second dielectric spacer layer 5122 is adjacent to the second side 5114 of the second gate electrode 5110 . A semiconductor source or drain region 5124 adjoins the first 5120 and second 5122 dielectric spacers. A trench contact structure 5126 is over the semiconductor source or drain region 5124 adjoining the first 5120 and second 5122 dielectric spacers.

該溝槽接觸結構5126包含導電結構5130上的絕緣蓋部5128。該溝槽接觸結構5126的該絕緣蓋部5128具有實質上與該第一5108和第二5110閘極電極之絕緣蓋部5116的頂部表面5118共平面的頂部表面5129。在一實施例中，該溝槽接觸結構5126的該絕緣蓋部5128橫向地延伸入該第一5120和第二5122電介質間隔層中的凹部5132內。在這樣的實施例中，該溝槽接觸結構5126的該絕緣蓋部5128懸伸出(overhang)該溝槽接觸結構5126的該導電結構5130上。然而，在其他實施例中，該溝槽接觸結構5126的該絕緣蓋部5128並不橫向地延伸入該第一5120和第二5122電介質間隔層中的凹部5132內，因此，並不懸伸出該溝槽接觸結構5126的該導電結構5130上。 The trench contact structure 5126 includes an insulating cap 5128 on the conductive structure 5130 . The insulating cap portion 5128 of the trench contact structure 5126 has a top surface 5129 that is substantially coplanar with the top surface 5118 of the insulating cap portion 5116 of the first 5108 and second 5110 gate electrodes. In one embodiment, the insulating cap portion 5128 of the trench contact structure 5126 extends laterally into a recess 5132 in the first 5120 and second 5122 dielectric spacers. In such an embodiment, the insulating cap portion 5128 of the trench contact structure 5126 overhangs the conductive structure 5130 of the trench contact structure 5126 . However, in other embodiments, the insulating cap portion 5128 of the trench contact structure 5126 does not extend laterally into the recess 5132 in the first 5120 and second 5122 dielectric spacers, and thus, does not overhang The trench contacts the conductive structure 5130 of the structure 5126 .

將領會到，該溝槽接觸結構5126的該導電結構5130可以不是矩形的，如同圖51A到51C中所描述的。例如，該溝槽接觸結構5126的該導電結構5130可以具有剖面幾何形狀，其類似或相同於針對圖51A之投影圖中所繪示之導電結構5130A所顯示的幾何形狀。 It will be appreciated that the conductive structure 5130 of the trench contact structure 5126 may not be rectangular, as described in FIGS. 51A-51C . For example, the conductive structure 5130 of the trench contact structure 5126 can have a cross-sectional geometry that is similar or identical to the geometry shown for the conductive structure 5130A depicted in the projection view of FIG. 51A .

在一實施例中，該溝槽接觸結構5126的該絕緣蓋部5128具有與該第一5108和第二5110閘極電極之絕緣蓋部5116的組成不同的組成。在一個這樣的實施例中，該溝槽接觸結構5126的該絕緣蓋部5128包含碳化物材料，諸如碳化矽材料。該第一5108和第二5110閘極電極的絕緣蓋部5116包含氮化物材料，諸如氮化矽材料。 In one embodiment, the insulating cap portion 5128 of the trench contact structure 5126 has a different composition than the composition of the insulating cap portion 5116 of the first 5108 and second 5110 gate electrodes. In one such embodiment, the insulating cap portion 5128 of the trench contact structure 5126 comprises a carbide material, such as a silicon carbide material. The insulating caps 5116 of the first 5108 and second 5110 gate electrodes comprise a nitride material, such as a silicon nitride material.

在一實施例中，該第一5108和第二5110閘極 電極的絕緣蓋部5116兩者皆具有在該溝槽接觸結構5126之該絕緣蓋部5128的底部表面5128A下方的底部表面5117A，如同圖51A中所描述的。在另一實施例中，該第一5108和第二5110閘極電極的絕緣蓋部5116兩者皆具有實質上與該溝槽接觸結構5126之該絕緣蓋部5128的底部表面5128B共平面的底部表面5117B，如同圖51B中所描述的。在另一實施例中，該第一5108和第二5110閘極電極的絕緣蓋部5116兩者皆具有在該溝槽接觸結構5126之該絕緣蓋部5128的底部表面5128AC上方的底部表面5117C，如同圖51C中所描述的。 In one embodiment, the first 5108 and second 5110 gates Both the insulating cover portions 5116 of the electrodes have a bottom surface 5117A below a bottom surface 5128A of the insulating cover portion 5128 of the trench contact structure 5126, as depicted in FIG. 51A. In another embodiment, both the insulating caps 5116 of the first 5108 and second 5110 gate electrodes have bottoms that are substantially coplanar with the bottom surface 5128B of the insulating caps 5128 of the trench contact structure 5126 Surface 5117B, as depicted in FIG. 51B. In another embodiment, both the insulating cap portions 5116 of the first 5108 and second 5110 gate electrodes have a bottom surface 5117C above the bottom surface 5128AC of the insulating cap portion 5128 of the trench contact structure 5126, As described in Figure 51C.

在一實施例中，該溝槽接觸結構5126的該導電結構5130包含U形金屬層5134、在整個U形金屬層5134上和在整個U形金屬層5134之上的T形金屬層5136、以及在T形金屬層5136上的第三金屬層5138。該溝槽接觸結構5126的該絕緣蓋部5128係在該第三金屬層5138上。在一個這樣的實施例中，該第三金屬層5138和該U形金屬層5134包含鈦，而且該T形金屬層5136包含鈷。在一特別這樣的實施例中，該T形金屬層5136另包含碳。 In one embodiment, the conductive structure 5130 of the trench contact structure 5126 includes a U-shaped metal layer 5134, a T-shaped metal layer 5136 on and above the entire U-shaped metal layer 5134, and A third metal layer 5138 on the T-shaped metal layer 5136 . The insulating cap portion 5128 of the trench contact structure 5126 is tied on the third metal layer 5138 . In one such embodiment, the third metal layer 5138 and the U-shaped metal layer 5134 comprise titanium, and the T-shaped metal layer 5136 comprises cobalt. In one particular such embodiment, the T-shaped metal layer 5136 further comprises carbon.

在一實施例中，金屬矽化物層5140係直接在該溝槽接觸結構5126的該導電結構5130與該半導體源極或汲極區域5124之間。在一個這樣的實施例中，該金屬矽化物層5140包含鈦和矽。在一特別這樣的實施例中，該半導體源極或汲極區域5124為N型半導體源極或汲極區域。在另一實施例中，該金屬矽化物層5140包含鎳、鉑和矽。在 一特別這樣的實施例中，該半導體源極或汲極區域5124為P型半導體源極或汲極區域。在另一特別這樣的實施例中，該金屬矽化物層5140另包含鍺。 In one embodiment, the metal silicide layer 5140 is directly between the conductive structure 5130 of the trench contact structure 5126 and the semiconductor source or drain region 5124 . In one such embodiment, the metal suicide layer 5140 includes titanium and silicon. In one particular such embodiment, the semiconductor source or drain region 5124 is an N-type semiconductor source or drain region. In another embodiment, the metal silicide layer 5140 includes nickel, platinum and silicon. exist In a particularly such embodiment, the semiconductor source or drain region 5124 is a P-type semiconductor source or drain region. In another particular such embodiment, the metal suicide layer 5140 further comprises germanium.

在一實施例中，參照圖51D，導電介層5150係在該第一閘極電極5108在該鰭部5102的頂部5102A之上的部位上並且被電連接至該第一閘極電極5108在該鰭部5102的頂部5102A之上的部位。該導電介層5150係在該第一閘極電極5108之絕緣蓋部5116中的開口5152中。在一個這樣的實施例中，該導電介層5150係在該溝槽接觸結構5126之該絕緣蓋部5128的一部分上，但是不被電連接至該溝槽接觸結構5126的該導電結構5130。在一特別這樣的實施例中，該導電介層5150係在該溝槽接觸結構5126之該絕緣蓋部5128的腐蝕部位5154中。 In one embodiment, referring to FIG. 51D , a conductive via 5150 is overlaid on the portion of the first gate electrode 5108 above the top 5102A of the fin 5102 and is electrically connected to the first gate electrode 5108 on the fin 5102. The portion above the top 5102A of the fin 5102 . The conductive via layer 5150 is in the opening 5152 in the insulating cap portion 5116 of the first gate electrode 5108 . In one such embodiment, the conductive via 5150 is over a portion of the insulating cover 5128 of the trench contact structure 5126 but is not electrically connected to the conductive structure 5130 of the trench contact structure 5126 . In one particular such embodiment, the conductive via 5150 is in the etched portion 5154 of the insulating cap portion 5128 of the trench contact structure 5126 .

在一實施例中，參照圖51E，導電介層5160係在該溝槽接觸結構5126的一部分上並且被電連接至該溝槽接觸結構5126的一部分。該導電介層係在該溝槽接觸結構5126之該絕緣蓋部5128的開口5162中。在一個這樣的實施例中，該導電介層5160係在該第一5108和第二5110閘極電極之絕緣蓋部5116的一部分上，但是不被電連接至該第一5108和第二5110閘極電極。在一特別這樣的實施例中，該導電介層5160係在該第一5108和第二5110閘極電極之絕緣蓋部5116的腐蝕部位5164中。 In one embodiment, referring to FIG. 51E , a conductive via 5160 is tied over and electrically connected to a portion of the trench contact structure 5126 . The conductive via is in the opening 5162 of the insulating cover 5128 of the trench contact structure 5126 . In one such embodiment, the conductive via 5160 is over a portion of the insulating cap portion 5116 of the first 5108 and second 5110 gate electrodes, but is not electrically connected to the first 5108 and second 5110 gate electrodes. pole electrode. In one particular such embodiment, the conductive via 5160 is in the etched portion 5164 of the insulating cap portion 5116 of the first 5108 and second 5110 gate electrodes.

再次參照圖51E，在一實施例中，該導電介層5160為在和圖51D之導電介層5150相同的結構中的第二 個導電介層。在一個這樣的實施例中，此一第二個導電介層5160係與該導電介層5150相隔離。在另一個這樣的實施例中，此一第二個導電介層5160係與該導電介層5150相合併而形成電短路的接觸5170，如同圖51F中所描述的。 Referring again to FIG. 51E, in one embodiment, the conductive via 5160 is the second second in the same structure as the conductive via 5150 of FIG. a conductive layer. In one such embodiment, the second conductive via 5160 is isolated from the conductive via 5150 . In another of these embodiments, the second conductive via 5160 merges with the conductive via 5150 to form an electrically shorted contact 5170, as depicted in FIG. 51F.

本文中所述的方法和結構可以致能使用其他方法不可能製造或者難以製造之其他結構或裝置的形成。在第一個範例中，圖52A繪示依據本發明的另一實施例，具有設置在閘極的作用部分之上的閘極接觸介層之另一半導體裝置的平面視圖。參照圖52A，半導體結構或裝置5200包含與複數個溝槽接觸5210A及5210B相叉合(interdigitated)的複數個閘極結構5208A到5208C(這些特徵被設置在基板的作用區域上方，未顯示出)。閘極接觸介層5280係形成在閘極結構5208B的作用部位上。閘極接觸介層5280係進一步設置在閘極結構5208C的作用部位上，其耦合閘極結構5208B和5208C。可領會到介於其間的溝槽接觸5210B可以藉由使用溝槽接觸隔離蓋層(例如，TILA)而與接觸5280相隔離。圖52A的接觸組態可以提供更容易使佈局中相鄰的閘極線搭接(strapping)的方法，而不需要編排上金屬化層之搭接的路由，因此致能更小的晶胞面積(cell area)或者較不複雜的接線方案(wiring scheme)或兩者皆可致能。 The methods and structures described herein may enable the formation of other structures or devices that would otherwise be impossible or difficult to fabricate. In a first example, FIG. 52A shows a plan view of another semiconductor device having a gate contact via disposed over an active portion of the gate in accordance with another embodiment of the present invention. Referring to FIG. 52A, a semiconductor structure or device 5200 includes a plurality of gate structures 5208A through 5208C interdigitated with a plurality of trench contacts 5210A and 5210B (these features are disposed over active regions of the substrate, not shown). . Gate contact via 5280 is formed over the active portion of gate structure 5208B. Gate contact via 5280 is further disposed on the active site of gate structure 5208C, which couples gate structures 5208B and 5208C. It can be appreciated that the intervening trench contacts 5210B can be isolated from the contacts 5280 by using a trench contact isolation capping layer (eg, TILA). The contact configuration of Figure 52A can provide an easier means of strapping adjacent gate lines in the layout without the need to route the strapping of the upper metallization layer, thus enabling a smaller cell area (cell area) or a less complex wiring scheme (wiring scheme) or both can be enabled.

在第二個範例中，圖52B繪示依據本發明的另一實施例，具有耦合一對溝槽接觸的閘極接觸介層之另一半導體裝置的平面視圖。參照圖52B，半導體結構或裝 置5250包含與複數個溝槽接觸5260A及5260B相叉合的複數個閘極結構5258A到5258C(這些特徵被設置在基板的作用區域上方，未顯示出)。溝槽接觸介層5290係形成在溝槽接觸5260A上。溝槽接觸介層5290係進一步設置在溝槽接觸5260B上，其耦合溝槽接觸5260A和5260B。可領會到介於其間的閘極結構5208B可以藉由使用閘極隔離蓋層(例如，GILA製程)而與溝槽接觸介層5290相隔離。圖52B的接觸組態可以提供更容易搭接佈局中相鄰的溝槽接觸，而不需要編排上金屬化層之搭接的路由，因此致能更小的晶胞面積或者較不複雜的接線方案或兩者皆可致能。 In a second example, FIG. 52B shows a plan view of another semiconductor device having a gate contact via coupling a pair of trench contacts according to another embodiment of the present invention. Referring to FIG. 52B, the semiconductor structure or device Set 5250 includes a plurality of gate structures 5258A-5258C intersected with a plurality of trench contacts 5260A and 5260B (these features are disposed over active areas of the substrate, not shown). Trench contact via 5290 is formed over trench contact 5260A. Trench contact via 5290 is further disposed on trench contact 5260B, which couples trench contacts 5260A and 5260B. It can be appreciated that the intervening gate structure 5208B can be isolated from the trench contact via 5290 by using a gate isolation cap (eg, GILA process). The contact configuration of FIG. 52B can provide easier bonding of adjacent trench contacts in a layout without the need to route the bonding of the upper metallization layer, thus enabling a smaller cell area or less complex wiring program or both.

用於閘極電極的絕緣蓋層可以使用幾個沉積操作來予以製作，而其結果可以包含多重沉積製程的加工品(artifact)。做為範例，圖53A到53E繪示依據本發明的一實施例，代表製造具有帶有覆蓋之絕緣蓋層的閘極堆疊之積體電路結構的方法中之各種操作的剖面視圖。 The insulating cap layer for the gate electrode can be fabricated using several deposition operations, and the result can contain artifacts of multiple deposition processes. As an example, Figures 53A-53E illustrate cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having a gate stack with an overlying insulating cap layer, in accordance with an embodiment of the present invention.

參照圖53A，起始結構5300包含在基板或鰭部5302上方的閘極堆疊5304。該閘極堆疊5304包含閘極電介質層5306、共形導電層5308、和導電填充材料5310。在一實施例中，該閘極電介質層5306為使用原子層沉積(ALD)製程所形成的高k閘極電介質層，而且共形導電層5308為使用ALD製程所形成功函數層。在一個這樣的實施例中，熱或化學氧化物層5312，諸如熱或化學二氧化矽或氧化矽層，係在基板或鰭部5302與閘極電介質層5306之間。諸如氮化矽間隔層之電介質間隔層5314係鄰接該閘極 堆疊5304的側壁。該電介質閘極堆疊5304和該電介質間隔層5314被收容在層間電介質(ILD)層5316中。在一實施例中，該閘極堆疊5304係使用置換閘極和置換閘極電介質處理方案所形成。遮罩5318被圖案化於該閘極堆疊5304和ILD層5316的上方，以提供使該閘極堆疊5304暴露出的開口5320。 Referring to FIG. 53A , a starting structure 5300 includes a gate stack 5304 over a substrate or fin 5302 . The gate stack 5304 includes a gate dielectric layer 5306 , a conformal conductive layer 5308 , and a conductive fill material 5310 . In one embodiment, the gate dielectric layer 5306 is a high-k gate dielectric layer formed using an atomic layer deposition (ALD) process, and the conformal conductive layer 5308 is a work function layer formed using an ALD process. In one such embodiment, a thermal or chemical oxide layer 5312 , such as a thermal or chemical silicon dioxide or silicon oxide layer, is tied between the substrate or fin 5302 and the gate dielectric layer 5306 . A dielectric spacer 5314, such as a silicon nitride spacer, is adjacent to the gate The side walls of the stack 5304. The dielectric gate stack 5304 and the dielectric spacer layer 5314 are received in an interlayer dielectric (ILD) layer 5316 . In one embodiment, the gate stack 5304 is formed using a replacement gate and replacement gate dielectric processing scheme. A mask 5318 is patterned over the gate stack 5304 and ILD layer 5316 to provide an opening 5320 exposing the gate stack 5304 .

參照圖53B，使用選擇性蝕刻製程，包含閘極電介質層5306、共形導電層5308、和導電填充材料5310的該閘極堆疊5304相對於電介質間隔層5314和層5316而被凹入。遮罩5318然後被去除。該凹入提供在凹入的閘極堆疊5324上方的凹洞(cavity)5322。 Referring to FIG. 53B , the gate stack 5304 comprising gate dielectric layer 5306 , conformal conductive layer 5308 , and conductive fill material 5310 is recessed relative to dielectric spacer layer 5314 and layer 5316 using a selective etch process. Mask 5318 is then removed. The recess provides a cavity 5322 above the recessed gate stack 5324 .

在另一實施例中，未被描述出，共形導電層5308和導電填充材料5310相對於電介質間隔層5314和層5316而被凹入，但是閘極電介質層5306並未被凹入或者僅被最低程度地凹入。可領會到，在其他實施例中，基於高蝕刻選擇性的無遮罩(maskless)法被使用於該凹入。 In another embodiment, not depicted, conformal conductive layer 5308 and conductive fill material 5310 are recessed relative to dielectric spacer layer 5314 and layer 5316, but gate dielectric layer 5306 is not recessed or is only recessed. Minimally recessed. It can be appreciated that in other embodiments, a maskless method based on high etch selectivity is used for the recess.

參照圖53C，用來製造閘極絕緣蓋層之多重沉積製程中的第一沉積製程被實施。第一沉積製程被用來形成與圖53B之結構共形的第一絕緣層5326。在一實施例中，該第一絕緣層5326包含矽和氮，例如，該第一絕緣層5326為氮化矽(Si3N4)層、富含矽的氮化矽層、貧含矽的氮化矽層、或摻雜碳的氮化矽層。在一實施例中，該第一絕緣層5326僅局部地填補該凹入之閘極堆疊5324上方的凹洞5322，如同所描述的。 Referring to FIG. 53C, the first deposition process of the multiple deposition processes used to fabricate the gate insulating cap layer is performed. A first deposition process is used to form a first insulating layer 5326 conformal to the structure of Figure 53B. In one embodiment, the first insulating layer 5326 includes silicon and nitrogen. For example, the first insulating layer 5326 is a silicon nitride (Si 3 N 4 ) layer, a silicon-rich silicon nitride layer, or a silicon-poor silicon nitride layer. A silicon nitride layer, or a carbon-doped silicon nitride layer. In one embodiment, the first insulating layer 5326 only partially fills the cavity 5322 above the recessed gate stack 5324, as described.

參照圖53D，該第一絕緣層5326受到回蝕(etch-back)製程，諸如各向異性蝕刻製程，以提供絕緣蓋層的第一部位5328。絕緣蓋層的第一部位5328僅局部地填補該凹入之閘極堆疊5324上方的凹洞5322。 Referring to FIG. 53D, the first insulating layer 5326 is subjected to an etch-back process, such as an anisotropic etching process, to provide a first portion 5328 of the insulating capping layer. The first portion 5328 of the insulating cap only partially fills the cavity 5322 above the recessed gate stack 5324 .

參照圖53E，額外之交替的沉積製程和回蝕製程被實施，直到凹洞5322被填滿該凹入的閘極堆疊5324上方的絕緣閘極蓋部結構5330為止。接縫5332在剖面分析中可以是明確的，而且可以指示用於絕緣閘極蓋部結構5330之交替的沉積製程和回蝕製程的次數。在圖53E中所示的範例中，三組接縫5332A,5332B和5332C的出現指示用於絕緣閘極蓋部結構5330之四次交替的沉積製程和回蝕製程。在一實施例中，由接縫5332所分開之絕緣閘極蓋部結構5330的材料5330A,5330B,5330C和5330D皆具有完全或實質相同的組成。 Referring to FIG. 53E , additional alternating deposition and etch-back processes are performed until the cavity 5322 is filled with the insulating gate cap structure 5330 above the recessed gate stack 5324 . The seam 5332 may be unambiguous in the cross-sectional analysis and may indicate the number of alternating deposition processes and etch-back processes used for the insulating gate cap structure 5330 . In the example shown in FIG. 53E , the presence of three sets of seams 5332A, 5332B, and 5332C indicates four alternating deposition and etch-back processes for the insulating gate cap structure 5330 . In one embodiment, the materials 5330A, 5330B, 5330C, and 5330D of the insulating gate cap structure 5330 separated by the seam 5332 all have identical or substantially the same composition.

如同本發明全文所述，基板可以由半導體材料所組成，該半導體材料可以耐受的住製造過程，且電荷可以遷移於其中。在一實施例中，本文中所述的基板為塊狀基板，其可以由結晶矽、摻雜有電荷載體的矽/鍺或鍺層所組成，該電荷載體諸如但不限於磷、砷、硼或其組合，以形成作用區域。在一個實施例中，此一塊狀基板中之矽原子的濃度係大於97%。在另一實施例中，塊狀基板係由生長在不同的結晶基板頂上之磊晶層所組成，例如，生長在摻雜硼之塊狀矽單結晶(mono-crystalline)基板頂上的矽磊晶層。塊狀基板可以替換地由III-V族材料所組成。 在一實施例中，塊狀基板係由III-V族材料所組成，諸如但不限於氮化鎵、磷化鎵、砷化鎵、磷化銦、銻化銦、砷化銦鎵、砷化鋁鎵、磷化銦鎵、或其組合。在一個實施例中，塊狀基板係由III-V族材料所組成，而且該電荷載體摻雜劑原子為諸如但不限於碳、矽、鍺、氧、硫、硒或碲。 As described throughout this disclosure, the substrate can be composed of a semiconductor material that can withstand the fabrication process and into which charges can migrate. In one embodiment, the substrates described herein are bulk substrates, which may consist of crystalline silicon, silicon/germanium or germanium layers doped with charge carriers such as but not limited to phosphorous, arsenic, boron or a combination thereof to form an active area. In one embodiment, the concentration of silicon atoms in the monolithic substrate is greater than 97%. In another embodiment, the bulk substrate consists of epitaxial layers grown on top of different crystalline substrates, for example, silicon epitaxial layers grown on top of boron-doped bulk silicon mono-crystalline substrates. layer. The bulk substrate may alternatively consist of III-V materials. In one embodiment, the bulk substrate is composed of III-V materials such as but not limited to GaN, GaP, GaAs, InP, InSb, InGaAs, InGaAs, Aluminum gallium, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate is composed of III-V materials and the charge carrier dopant atoms are such as but not limited to carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

如同本發明全文所述，諸如淺溝槽隔離區域或子鰭部隔離區域的隔離區域可以由適合來最終地電隔離的材料組成，或有助於隔離永久性閘極結構的部分與下面的塊狀基板，或者隔離在下面的塊狀基板內所形成的作用區域(例如，隔離的鰭部作用區域)的材料。例如，在一個實施例中，隔離區域係由電介質材料的一或更多層所組成，諸如但不限於二氧化矽、氮氧化矽、氮化矽、摻雜碳的氮化矽、或其組合。 As described throughout this disclosure, isolation regions such as shallow trench isolation regions or sub-fin isolation regions may be composed of materials suitable for ultimately electrically isolating, or helping to isolate portions of the permanent gate structure from underlying bulk shaped substrates, or materials that isolate active areas (eg, isolated fin active areas) formed within an underlying bulk substrate. For example, in one embodiment, the isolation region is composed of one or more layers of dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, carbon-doped silicon nitride, or combinations thereof .

如同本發明全文所述，閘極線或閘極結構可以由閘極電極堆疊所組成，該閘極電極堆疊包含閘極電介質層及閘極電極層。在一實施例中，該閘極電極堆疊的閘極電極係由金屬閘極所組成而且該閘極電介質層係由高k材料所組成。例如，在一個實施例中，該閘極電介質層係由一材料所組成，該材料諸如但不限於氧化鉿、氮氧化鉿、矽化鉿、氧化鑭、氧化鋯、矽化鋯、氧化鉭、鈦酸鋇鍶、鈦酸鋇、鈦酸鍶、氧化釔、氧化鋁、氧化鉛鈧鉭、鈮酸鉛鋅、或其組合。此外，一部分的閘極電介質層可包含從半導體基板的頂部幾層所形成的原生氧化物(native oxide)層。在一實施例中，該閘極電介質層係由頂部高k部 位和由半導體材料的氧化物所組成的下部部位所組成。在一個實施例中，該閘極電介質層係由氧化鉿的頂部部位和二氧化矽或氮氧化矽的底部部位所組成。在有些施行中，該閘極電介質的一部分為”U”形結構，其包含實質上平行於基板之表面的底部部位和實質上垂直於基板之頂部表面的兩個側壁部位。 As described throughout this disclosure, the gate line or gate structure may consist of a gate electrode stack comprising a gate dielectric layer and a gate electrode layer. In one embodiment, the gate electrode of the gate electrode stack is composed of a metal gate and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicide, lanthanum oxide, zirconium oxide, zirconium silicide, tantalum oxide, titanate barium strontium, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof. Additionally, a portion of the gate dielectric layer may include a native oxide layer formed from the top layers of the semiconductor substrate. In one embodiment, the gate dielectric layer consists of a top high-k portion The bit and the lower part consist of an oxide of the semiconductor material. In one embodiment, the gate dielectric layer consists of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U" shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.

在一個實施例中，該閘極電極係由金屬層所組成，該金屬層諸如但不限於金屬氮化物、金屬碳化物、金屬矽化物、金屬鋁化物、鉿、鋯、鈦、鉭、鋁、釕、鈀、鉑、鈷、鎳或導電金屬氧化物。在一特定實施例中，該閘極電極係由形成在金屬功函數設定層上方的非功函數設定填充材料所組成。該閘極電極層可以由P型功函數金屬或N型功函數金屬組成，視該電晶體即將為PMOS電晶體或NMOS電晶體而定。在有些施行中，該閘極電極層可以由兩層以上之金屬層的堆疊組成，其中，一或更多層金屬層為功函數金屬層而且至少一個金屬層為導電填充層。針對PMOS電晶體，可以被使用於該閘極電極的金屬包含不限於釕、鈀、鉑、鈷、鎳、以及導電金屬氧化物，例如，氧化釕。P型金屬層將致能具有介於約4.9eV與約5.2eV間之功函數的PMOS閘極電極的形成。針對NMOS電晶體，可以被使用於該閘極電極的金屬包含但不限於鉿、鋯、鈦、鉭、鋁、這些金屬的合金、以及這些金屬的碳化物，諸如碳化鉿、碳化鋯、碳化鈦、碳化鉭、和碳化鋁。N型金屬層將致能具有介於約3.9eV與約4.2eV間之功函數 的NMOS閘極電極的形成。在有些施行中，該閘極電極可以由”U”形結構組成，其包含實質上平行於基板之表面的底部部位和實質上垂直於基板之頂部表面的兩個側壁部位。在另一施行中，形成該閘極電極之該等金屬層的至少其中一者可以僅是平面層，其實質上平行於基板的頂部表面而且並不包含實質上垂直於基板之頂部表面的側壁部位。在本發明的其他施行中，該閘極電極可以由U形結構以及平面、非U形的結構的組合組成。例如，該閘極電極可以由形成在一或更多個平面、非U形層頂上的一或更多個U形金屬層組成。 In one embodiment, the gate electrode is composed of a metal layer such as but not limited to metal nitride, metal carbide, metal silicide, metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, Ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-workfunction setting fill material formed over the metal workfunction setting layer. The gate electrode layer can be composed of P-type work function metal or N-type work function metal, depending on whether the transistor will be a PMOS transistor or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include but are not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide , tantalum carbide, and aluminum carbide. The N-type metal layer will enable a work function between about 3.9eV and about 4.2eV Formation of NMOS gate electrodes. In some implementations, the gate electrode may consist of a "U" shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may be only a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewalls that are substantially perpendicular to the top surface of the substrate. parts. In other implementations of the invention, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

如同本發明全文所述，與閘極線或電極堆疊相關聯的間隔層可以由適合來最終電隔離，或有助於隔離永久性閘極結構與相鄰的導電接觸(諸如，自對準接觸)的材料所組成。例如，在一個實施例中，該等間隔層係由電介質材料所組成，諸如但不限於二氧化矽、氮氧化矽、氮化矽、或摻雜碳的氮化矽。 As described throughout the present invention, the spacer layer associated with the gate line or electrode stack can be formed by suitable for ultimate electrical isolation, or to help isolate the permanent gate structure from adjacent conductive contacts (such as self-aligned contact ) made of materials. For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

在一實施例中，本文中所述的方法可以涉及接觸圖案的形成，其與現有的閘極圖案非常良好地對準且同時排除需要極度緊密對位預算的光刻操作之使用。在一個這樣的實施例中，此方法致使能夠使用在本質上為高度選擇性的濕式蝕刻(例如，對上乾式或電漿蝕刻)來產生接觸開口。在一實施例中，藉由利用現有的閘極圖案結合接觸插塞光刻操作來形成接觸圖案。在一個這樣的實施例中，該方法致使能夠排除需要使用其他臨界(critical)光刻 操作來產生接觸圖案，如同在其他方法中所使用的。在一實施例中，溝槽接觸柵格不被分開地圖案化，而是被形成在多晶(閘極)線之間。例如，在一個這樣的實施例中，溝槽接觸柵格被形成在閘極光柵圖案化之後而不是在閘極光柵切割之前。 In an embodiment, the methods described herein may involve the formation of contact patterns that align very well with existing gate patterns while precluding the use of photolithographic operations that require extremely tight alignment budgets. In one such embodiment, the method enables the use of a wet etch that is highly selective in nature (eg, dry or plasma etch on top) to create contact openings. In one embodiment, the contact pattern is formed by using the existing gate pattern combined with a contact plug photolithography operation. In one such embodiment, the method enables the elimination of the need to use other critical lithographic Operate to generate contact patterns, as used in other methods. In an embodiment, the trench contact grid is not patterned separately, but is formed between the poly (gate) lines. For example, in one such embodiment, the trench contact grid is formed after gate grating patterning rather than before gate grating cutting.

此外，閘極堆疊結構可以藉由置換閘極製程來予以製造。在此一方案中，諸如多晶矽或氮化矽短柱材料的假性閘極材料被去除並且以永久性閘極電極材料來取代。在一個這樣的實施例中，永久性閘極電介質層也被形成於此製程中，而不是被實施自先前的處理中。在一實施例中，藉由乾式蝕刻或濕式蝕刻製程來去除假性閘極。在一個實施例中，假性閘極係由多晶矽或非晶矽所組成並且用包含SF6的乾式蝕刻製程來予以去除。在另一實施例中，假性閘極係由多晶矽或非晶矽所組成並且用包含水性NH4OH或氫氧化四甲銨的濕式蝕刻製程來予以去除。在一個實施例中，假性閘極係由多氮化矽組成並且用包含水性磷酸的濕式蝕刻製程來予以去除。 In addition, the gate stack structure can be fabricated by a replacement gate process. In this approach, dummy gate material such as polysilicon or silicon nitride stub material is removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process rather than being implemented from a previous process. In one embodiment, the dummy gates are removed by dry etching or wet etching. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a dry etch process including SF 6 . In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a wet etch process involving aqueous NH 4 OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of polysilicon nitride and is removed using a wet etch process including aqueous phosphoric acid.

在一實施例中，本文中所述的一或更多個方法基本上細思假性和置換閘極製程結合假性和置換接觸製程來達成結構。在一個這樣的實施例中，置換接觸製程被實施於置換閘極製程之後，得以讓永久性閘極堆疊的至少一部分能夠進行高溫退火。例如，在一特定這樣的實施例中，該永久性閘極堆疊之至少一部分的退火，例如在閘極電介質層被形成之後，被實施於大於約攝氏600度的溫度 下。該退火被實施於該永久性接觸的形成之前。 In one embodiment, one or more methods described herein substantially contemplate dummy and replacement gate processes in combination with dummy and replacement contact processes to achieve the structure. In one such embodiment, a replacement contact process is performed after the replacement gate process to allow high temperature annealing of at least a portion of the permanent gate stack. For example, in one particular such embodiment, annealing of at least a portion of the permanent gate stack, such as after the gate dielectric layer is formed, is performed at a temperature greater than about 600 degrees Celsius Down. The anneal is performed prior to the formation of the permanent contact.

在有些實施例中，半導體結構或裝置的配置將閘極接觸放置在閘極線的部位之上或者將閘極堆疊放置在隔離區域之上。然而，此種配置可以被視為無效率的佈局空間使用。在另一實施例中，半導體裝置具有接觸閘極電極形成在作用區域之上的部位之接觸結構。通常，在(例如，除了)形成閘極接觸結構(諸如，介層)於閘極的作用部位之上並且在和溝槽接觸介層同一層中之前(以外)，本發明的一或更多個實施例包含首先使用閘極對準溝槽接觸製程。此一製程可被施行來形成用於半導體結構製作(例如，積體電路製作)的溝槽接觸。在一實施例中，溝槽接觸圖案被形成為對準現有的閘極圖案。相較之下，其他的方法典型上涉及具有光刻接觸圖案和現有閘極圖案之緊密對位的額外光刻操作與選擇性接觸蝕刻相結合。例如，另一製程可包含具有接觸特徵之分離圖案化的多晶(閘極)柵格的圖案化。 In some embodiments, the configuration of the semiconductor structure or device places the gate contact over the location of the gate line or places the gate stack over the isolation region. However, this configuration can be considered an inefficient use of layout space. In another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed over the active area. Typically, before (eg, in addition to) forming a gate contact structure (such as a via) over the active site of the gate and in the same layer as the trench contact via, one or more of the present invention One embodiment involves using a gate-aligned trench contact process first. Such a process may be performed to form trench contacts for semiconductor structure fabrication (eg, integrated circuit fabrication). In one embodiment, trench contact patterns are formed to align with existing gate patterns. In contrast, other approaches typically involve additional photolithographic operations with close alignment of the photolithographic contact pattern and the existing gate pattern combined with selective contact etching. For example, another process may include patterning of a separately patterned poly (gate) grid with contact features.

將領會到，並非上面所述之製程的所有態樣需要被實行來落入本發明之實施例的精神和範疇之內。例如，在一個實施例中，假性閘極並非總是需要被形成在製作閘極接觸於該等閘極堆疊的作用部位之上之前。上面所述的閘極堆疊可以真正是如同起初所形成的永久性閘極堆疊。而且，本文中所述的製程可以被用來製作一個或複數個半導體裝置。該等半導體裝置可以是電晶體或類似的裝置。例如，在一實施例中，該等半導體裝置為用於邏輯或 記憶體的金屬-氧化物半導體(MOS)電晶體，或者雙極性電晶體。再者，在一實施例中，該等半導體裝置具有三維架構，諸如三閘極裝置、獨立存取的雙閘極裝置、或FIN-FET。一或更多個實施例可能特別有用於以10奈米(10nm)技術節點或次10奈米(10nm)技術節點來製作半導體裝置。 It will be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the invention. For example, in one embodiment, dummy gates do not always need to be formed prior to making gate contacts over the active sites of the gate stacks. The gate stack described above may indeed be a permanent gate stack as initially formed. Furthermore, the processes described herein may be used to fabricate one or more semiconductor devices. The semiconductor devices may be transistors or similar devices. For example, in one embodiment, the semiconductor devices are used for logic or Metal-oxide-semiconductor (MOS) transistors for memory, or bipolar transistors. Furthermore, in one embodiment, the semiconductor devices have a three-dimensional architecture, such as a triple-gate device, an independent access dual-gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at 10 nanometer (10 nm) or sub-10 nanometer (10 nm) technology nodes.

針對FEOL層或結構製作的額外或中介操作可以包含標準的微電子製作過程，諸如光刻、蝕刻、薄膜沉積、平坦化(諸如，化學機械拋光(CMP))、擴散、度量衡(metrology)、犧牲層的使用、蝕刻停止層的使用、平坦化停止層的使用、或者任何其他與微電子組件製作的相關動作。再者，將領會到，針對先前處理流程所說明的製程操作可以用替代的順序來實行，並不是每一個操作需要被實施或額外的製程操作可以被實施，或者兩者皆可。 Additional or intermediate operations for FEOL layer or structure fabrication may include standard microelectronic fabrication processes such as photolithography, etching, thin film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, sacrificial layers, use of etch stop layers, use of planarization stop layers, or any other action associated with microelectronic assembly fabrication. Furthermore, it will be appreciated that the process operations described for the previous process flows may be performed in alternate orders and that not every operation need be performed or additional process operations may be performed, or both.

將領會到在上面的代表性FEOL實施例中，在一實施例中，10奈米節點或次10奈米節點處理被直接施行於製作方案和所得結構中作為技術驅動程式(technology driver)。在其他實施例中，FEOL考量可以藉由BEOL 10奈米或次10奈米處理要求來加以驅動。例如，針對FEOL層和裝置的材料選擇和佈局可能需要考慮到(accommodate)BEOL處理。在一個這樣的實施例中，材料選擇和閘極堆疊架構的選擇係考量到BEOL層的高密度金屬化，例如，藉由BEOL層的高密度金屬化來減少形成在FEOL層中但是被耦合在一起之電晶體結構中的邊緣電容(fringe capacitance)。 It will be appreciated that in the above representative FEOL embodiments, in one embodiment, 10nm node or sub-10nm node processing is implemented directly into the fabrication scheme and resulting structure as a technology driver. In other embodiments, FEOL considerations may be driven by BEOL 10nm or sub-10nm processing requirements. For example, material selection and layout for FEOL layers and devices may need to accommodate BEOL processing. In one such embodiment, the choice of material and gate stack architecture takes into account the high-density metallization of the BEOL layer, for example, by reducing the density of metallization formed in the FEOL layer but coupled in the BEOL layer. The fringe capacitance in common transistor structures.

積體電路的後段(BEOL)層通常包含導電的 微電子結構，其在此技術中被稱為介層，以使介層上方的金屬線或其他互連部電聯接到該介層下方的金屬線或其他互連部。介層可以藉由光刻製程來予以形成。代表性地，光阻層可以被旋轉塗覆在電介質層之上，該光阻層可以經由圖案化後的遮罩而被暴露於圖案化後的光化輻射(artinic radiation)，而後暴露層可以被顯影以便形成開口於該光阻層中。接著，用於該介層的開口可以藉由使用該光阻層中的該開口作為蝕刻遮罩而被蝕刻於該電介質層中。此開口被稱為介層開口。最後，可以用一或更多種金屬或其他導電材料來填充該介層開口而形成該介層。 Back-of-the-line (BEOL) layers of integrated circuits typically contain conductive A microelectronic structure, referred to in the art as a via, such that metal lines or other interconnects above the via are electrically coupled to metal lines or other interconnects below the via. The via layer can be formed by photolithography process. Typically, a photoresist layer can be spin-coated over the dielectric layer, the photoresist layer can be exposed to patterned actinic radiation via a patterned mask, and the exposed layer can then be is developed to form openings in the photoresist layer. Next, an opening for the via can be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is called a via opening. Finally, the via can be formed by filling the via opening with one or more metals or other conductive materials.

對於至少某些類型的積體電路(例如，先進的微電子、晶片組組件、繪圖晶片等)而言，介層的尺寸和間隙已經逐漸地減小，而且預期在未來，介層的尺寸和間隙將會繼續逐漸地減小。當藉由此等光刻製程來圖案化具有非常小的間距之非常小的介層時，它們本身出現幾種挑戰。其中一個這樣的挑戰為介層與上覆的互連部之間的重疊，以及介層與下面的著陸(landing)互連部之間的重疊一般需要被控制於介層間距的四分之一之等級的高耐受度(high tolerance)。當介層間距的尺寸隨著時間而越來越小時，重疊耐受度傾向隨著他們而以甚至比光刻儀器能夠跟上之速率更高的速率來縮放尺寸。 For at least some types of integrated circuits (e.g., advanced microelectronics, chipset assemblies, graphics wafers, etc.), the size and clearance of vias have gradually decreased, and it is expected that in the future, the size and spacing of vias will The gap will continue to gradually decrease. Such photolithographic processes inherently present several challenges when very small vias with very small pitches are patterned. One such challenge is that the overlap between the via and the overlying interconnect, and the overlap between the via and the underlying landing interconnect typically needs to be controlled to a quarter of the via pitch High tolerance of the grade (high tolerance). As the dimensions of via pitches get smaller and smaller over time, the overlay tolerance tends to scale with them at a rate even higher than lithography tools can keep up with.

另一個這樣的挑戰為該介層開口的臨界尺寸一般傾向比光刻掃描器之解析度能力更快地縮放。縮小技術存在以使介層開口的臨界尺寸縮小。然而，縮小量傾向 受到最小的介層間距，以及受到縮小製程為光學鄰近修正(optical proximity correction(OPC))中性的能力所限，而且傾向不顯著地妥協線寬粗糙度(line width roughness(LWR))或臨界尺寸均勻度(critical dimension uniformity(CDU))，或者兩者皆有。又一個這樣的挑戰為光阻的LWR或CDU或兩者的特性一般需要隨著介層開口的臨界尺寸減小而改善，以便保持臨界尺寸預算之相同的整體分數(overall fraction)。 Another such challenge is that the critical dimensions of the via openings generally tend to scale faster than the resolution capabilities of lithographic scanners. Scaling techniques exist to shrink the critical dimensions of via openings. However, shrinkage tends to Limited by the minimum via spacing and by the ability to shrink the process to be optical proximity correction (OPC) neutral, and tend not to significantly compromise line width roughness (LWR) or critical Critical dimension uniformity (CDU), or both. Yet another such challenge is that the LWR or CDU or both characteristics of a photoresist generally need to improve as the CD of via openings decreases in order to maintain the same overall fraction of the CD budget.

在後段(BEOL)金屬互連結構的金屬線中，針對考量金屬線間之非導電間隔層或中斷(稱為”插塞”，”電介質插塞”或”金屬線末端”)的放置及縮放，上面的因素也是有關的。因此，在用以製作金屬線、金屬介層、及電介質插塞的後段金屬化製造技術領域中也需要改善。 Placement and scaling to account for non-conductive spacer layers or interruptions (called "plugs", "dielectric plugs" or "metal line ends") between metal lines in metal lines in back-end-of-line (BEOL) metal interconnect structures , the above factors are also relevant. Accordingly, there is also a need for improvements in the field of back-end metallization fabrication techniques for forming metal lines, metal vias, and dielectric plugs.

在另一態樣中，間距四等分法被施行來圖案化電介質層中的溝槽以形成BEOL互連結構。依據本發明的實施例，在BEOL製作方案中，間距分割被實施來製作金屬線。實施例可以致能金屬層之間距的持續縮放超過目前光刻儀器的解析度能力。 In another aspect, pitch quartering is performed to pattern trenches in the dielectric layer to form BEOL interconnect structures. According to an embodiment of the present invention, in a BEOL fabrication scheme, pitch division is implemented to fabricate metal lines. Embodiments may enable continued scaling of the pitch between metal layers beyond the resolution capabilities of current lithography tools.

圖54為依據本發明的一實施例，用來製作用於互連結構之溝槽的間距四等分法5400的示意圖。 FIG. 54 is a schematic diagram of a pitch quartering method 5400 used to fabricate trenches for interconnect structures in accordance with one embodiment of the present invention.

參照圖54，於操作(a)，使用直接光刻術來形成骨幹(backbone)特徵5402。例如，光阻層或堆疊可以被圖案化而且圖案被轉印成硬遮罩材料而最終形成骨幹特徵 5402。用來形成骨幹特徵5402的該光阻層或堆疊可以使用諸如193浸沒式光刻法之標準的光刻處理技術來予以圖案化。第一間隔層特徵5404然後可以被形成鄰接該骨幹特徵5402的側壁。 Referring to FIG. 54, in operation (a), backbone features 5402 are formed using direct photolithography. For example, a photoresist layer or stack can be patterned and the pattern transferred into a hard mask material to ultimately form backbone features 5402. The photoresist layer or stack used to form backbone features 5402 can be patterned using standard photolithographic processing techniques such as 193 immersion photolithography. A first spacer feature 5404 may then be formed adjacent to the sidewall of the backbone feature 5402 .

於操作(b)，該骨幹特徵5402被去除而僅留下該第一間隔層特徵5404剩下。在此階段，該第一間隔層特徵5404實際上為半間距遮罩，例如，代表間距二等分製程。該第一間隔層特徵5404不是可以直接被使用於間距四等分製程，就是該第一間隔層特徵5404的圖案可以首先被轉印成新的硬遮罩材料，而後者方法被描述出。 In operation (b), the backbone feature 5402 is removed leaving only the first spacer layer feature 5404 remaining. At this stage, the first spacer layer feature 5404 is actually a half pitch mask, eg, representing a pitch bisecting process. Either the first spacer feature 5404 can be used directly in the pitch quartering process, or the pattern of the first spacer feature 5404 can first be transferred to a new hard mask material, the latter method being described.

於操作(c)，該第一間隔層特徵5404的圖案被轉印成新的硬遮罩材料而形成第一間隔層特徵5404’。第二間隔層特徵5406然後被形成鄰接該第一間隔層特徵5404’的側壁。 In operation (c), the pattern of the first spacer layer feature 5404 is transferred to a new hard mask material to form the first spacer layer feature 5404'. A second spacer feature 5406 is then formed adjacent to the sidewalls of the first spacer feature 5404'.

於操作(d)，該第一間隔層特徵5404’被去除而僅留下該第二間隔層特徵5406剩下。在此階段，該第二間隔層特徵5406實際上為四分之一間距遮罩，例如，代表間距四等分製程。 In operation (d), the first spacer layer feature 5404' is removed leaving only the second spacer layer feature 5406 remaining. At this stage, the second spacer layer feature 5406 is actually a quarter pitch mask, eg, representing a pitch quartering process.

於操作(e)，該第二間隔層特徵5406被用作為遮罩來圖案化電介質或硬遮罩層中的複數個溝槽5408。該等溝槽最終可以用導電材料來填充而形成積體電路之金屬化層中的導電互連部。具有標示“B”的溝槽5408相當於骨幹特徵5402。具有標示“S”的溝槽5408相當於第一間隔層特徵5404或5404’。具有標示“C”的溝槽5408相當於骨幹特 徵5402之間的互補區域5407。 In operation (e), the second spacer layer feature 5406 is used as a mask to pattern the plurality of trenches 5408 in the dielectric or hard mask layer. The trenches can eventually be filled with conductive material to form conductive interconnects in the metallization layers of the integrated circuit. Grooves 5408 with a designation "B" correspond to backbone features 5402 . A trench 5408 with an "S" designation corresponds to the first spacer feature 5404 or 5404'. Grooves 5408 with designation "C" correspond to the backbone Complementary regions 5407 between features 5402.

將領會到，因為圖54之該等溝槽5408的個別一些具有圖案化原點(origin)，其對應於圖54之骨幹特徵5402、第一間隔層特徵5404或5404’、或互補區域5407的其中一者，所以在積體電路之金屬化層中最終形成的導電互連部中，此等特徵之寬度及/或間距的差異可能呈現為間距四等分製程的加工品。做為範例，圖55A繪示依據本發明的一實施例，使用間距四等分方案所製作之金屬化層的剖面視圖。 It will be appreciated that since individual ones of the trenches 5408 of FIG. For one, differences in the width and/or pitch of these features may appear as artifacts of the pitch quartering process in the resulting conductive interconnects in the metallization layers of the integrated circuit. As an example, FIG. 55A shows a cross-sectional view of a metallization layer fabricated using a pitch quartering scheme in accordance with one embodiment of the present invention.

參照圖55A，積體電路結構5500包含基板5502之上的層間電介質(ILD)層5504。複數條導電互連線5506係在該ILD層5504中，而且該複數條導電互連線5506之個別的一些藉由該ILD層5504的部位而互相間隔分開。該複數條導電互連線5506之個別的一些包含導電阻障層5508和導電填充材料5510。 Referring to FIG. 55A , an integrated circuit structure 5500 includes an interlayer dielectric (ILD) layer 5504 over a substrate 5502 . A plurality of conductive interconnect lines 5506 are in the ILD layer 5504 , and individual ones of the plurality of conductive interconnect lines 5506 are spaced apart from each other by portions of the ILD layer 5504 . Individual ones of the plurality of conductive interconnect lines 5506 include a conductive barrier layer 5508 and a conductive fill material 5510 .

參照圖54和55A兩者，導電互連線5506B係形成在具有源自骨幹特徵5402之圖案的溝槽中。導電互連線5506S係形成在具有源自第一間隔層特徵5404或5404’之圖案的溝槽中。導電互連線5506C係形成在具有源自骨幹特徵5402間之互補區域5407的圖案的溝槽中。 Referring to both FIGS. 54 and 55A , conductive interconnect lines 5506B are formed in trenches having a pattern derived from backbone features 5402 . Conductive interconnect lines 5506S are formed in trenches having patterns derived from first spacer layer features 5404 or 5404'. Conductive interconnect lines 5506C are formed in trenches having a pattern originating from complementary regions 5407 between backbone features 5402 .

再次參照圖55A，在一實施例中，該複數條導電互連線5506包含具有寬度(W1)的第一互連線5506B。第二互連線5506S係緊鄰接該第一互連線5506B，該第二互連線5506S具有與該第一互連線5506B之寬度(W1)不同的 寬度(W2)。第三互連線5506C係緊鄰接該第二互連線5506S，該第三互連線5506C具有寬度(W3)。第四互連線(第二個5506S)係緊鄰接該第三互連線5506C，該第四互連線具有與該第二互連線5506S之寬度(W2)相同的寬度(W2)。第五互連線(第二個5506B)係緊鄰接該第四互連線(第二個5506S)，該第五互連線(第二個5506B)具有與該第一互連線5506B之寬度(W1)相同的寬度(W1)。 Referring again to FIG. 55A, in one embodiment, the plurality of conductive interconnect lines 5506 includes a first interconnect line 5506B having a width (W1). The second interconnection line 5506S is immediately adjacent to the first interconnection line 5506B, and the second interconnection line 5506S has a width (W1) different from that of the first interconnection line 5506B. Width (W2). The third interconnection line 5506C is immediately adjacent to the second interconnection line 5506S, and the third interconnection line 5506C has a width (W3). A fourth interconnection line (second 5506S) is immediately adjacent to the third interconnection line 5506C, the fourth interconnection line having the same width (W2) as the width (W2) of the second interconnection line 5506S. The fifth interconnect line (second 5506B) is immediately adjacent to the fourth interconnect line (second 5506S), the fifth interconnect line (second 5506B) has the same width as the first interconnect line 5506B (W1) same width as (W1).

在一實施例中，該第三互連線5506C的寬度(W3)係不同於該第一互連線5506B的寬度(W1)。在一個這樣的實施例中，該第三互連線5506C的寬度(W3)係不同於該第二互連線5506S的寬度(W2)。在另一個這樣的實施例中，該第三互連線5506C的寬度(W3)係相同於該第二互連線5506S的寬度(W2)。在另一實施例中，該第三互連線5506C的寬度(W3)係相同於該第一互連線5506B的寬度(W1)。 In one embodiment, the width (W3) of the third interconnection line 5506C is different from the width (W1) of the first interconnection line 5506B. In one such embodiment, the width (W3) of the third interconnect line 5506C is different than the width (W2) of the second interconnect line 5506S. In another of these embodiments, the width (W3) of the third interconnection line 5506C is the same as the width (W2) of the second interconnection line 5506S. In another embodiment, the width (W3) of the third interconnection line 5506C is the same as the width (W1) of the first interconnection line 5506B.

在一實施例中，該第一互連線5506B與該第三互連線5506C之間的間距(P1)係相同於該第二互連線5506S與該第四互連線(第二個5506S)之間的間距(P2)。在另一實施例中，該第一互連線5506B與該第三互連線5506C之間的間距(P1)係不同於該第二互連線5506S與該第四互連線(第二個5506S)之間的間距(P2)。 In one embodiment, the pitch (P1) between the first interconnection 5506B and the third interconnection 5506C is the same as that between the second interconnection 5506S and the fourth interconnection (the second 5506S ) between the spacing (P2). In another embodiment, the pitch (P1) between the first interconnection 5506B and the third interconnection 5506C is different from that between the second interconnection 5506S and the fourth interconnection (the second 5506S) between the pitch (P2).

再次參照圖55A，在另一實施例中，該複數條導電互連線5506包含具有寬度(W1)的第一互連線5506B。第二互連線5506S係緊鄰接該第一互連線5506B， 該第二互連線5506S具有寬度(W2)。第三互連線5506C係緊鄰接該第二互連線5506S，該第三互連線5506C具有與該第一互連線5506B之寬度(W1)不同的寬度(W3)。第四互連線(第二個5506S)係緊鄰接該第三互連線5506C，該第四互連線具有與該第二互連線5506S之寬度(W2)相同的寬度(W2)。第五互連線(第二個5506B)係緊鄰接該第四互連線，該第五互連線(第二個5506B)具有與該第一互連線5506B之寬度(W1)相同的寬度(W1)。 Referring again to FIG. 55A, in another embodiment, the plurality of conductive interconnect lines 5506 includes a first interconnect line 5506B having a width (W1). The second interconnection line 5506S is immediately adjacent to the first interconnection line 5506B, The second interconnection line 5506S has a width (W2). The third interconnection line 5506C is immediately adjacent to the second interconnection line 5506S, and the third interconnection line 5506C has a width (W3) different from the width (W1) of the first interconnection line 5506B. A fourth interconnection line (second 5506S) is immediately adjacent to the third interconnection line 5506C, the fourth interconnection line having the same width (W2) as the width (W2) of the second interconnection line 5506S. The fifth interconnection (second 5506B) is immediately adjacent to the fourth interconnection, the fifth interconnection (second 5506B) has the same width as the width (W1) of the first interconnection 5506B (W1).

在一實施例中，該第二互連線5506S的寬度(W2)係不同於該第一互連線5506B的寬度(W1)。在一個這樣的實施例中，該第三互連線5506C的寬度(W3)係不同於該第二互連線5506S的寬度(W2)。在另一個這樣的實施例中，該第三互連線5506C的寬度(W3)係相同於該第二互連線5506S的寬度(W2)。 In one embodiment, the width (W2) of the second interconnection line 5506S is different from the width (W1) of the first interconnection line 5506B. In one such embodiment, the width (W3) of the third interconnect line 5506C is different than the width (W2) of the second interconnect line 5506S. In another of these embodiments, the width (W3) of the third interconnection line 5506C is the same as the width (W2) of the second interconnection line 5506S.

在一實施例中，該第二互連線5506S的寬度(W2)係相同於該第一互連線5506B的寬度(W1)。在一實施例中，該第一互連線5506B與該第三互連線5506C之間的間距(P1)係相同於該第二互連線5506S與該第四互連線(第二個5506S)之間的間距(P2)。在一實施例中，該第一互連線5506B與該第三互連線5506C之間的間距(P1)係不同於該第二互連線5506S與該第四互連線(第二個5506S)之間的間距(P2)。 In one embodiment, the width ( W2 ) of the second interconnection line 5506S is the same as the width ( W1 ) of the first interconnection line 5506B. In one embodiment, the pitch (P1) between the first interconnection 5506B and the third interconnection 5506C is the same as that between the second interconnection 5506S and the fourth interconnection (the second 5506S ) between the spacing (P2). In one embodiment, the pitch (P1) between the first interconnection 5506B and the third interconnection 5506C is different from that between the second interconnection 5506S and the fourth interconnection (the second 5506S ) between the spacing (P2).

圖55B繪示依據本發明的一實施例，在使用間距四等分方案所製作之金屬層上方之使用間距二等分方 案所製作之金屬層的剖面視圖。 FIG. 55B illustrates the use of pitch bisecting squares above a metal layer fabricated using the pitch quartering scheme, in accordance with one embodiment of the present invention. A cross-sectional view of the fabricated metal layer.

參照圖55B，積體電路結構5550包含基板5552上方的第一層間電介質(ILD)層5554。第一複數條導電互連線5556係在該第一ILD層5554中，而且該第一複數條導電互連線5556之個別的一些藉由該第一ILD層5554的部位而互相間隔分開。該複數條導電互連線5556之個別的一些包含導電阻障層5558和導電填充材料5560。該積體電路結構5550另包含基板5552上方的第二層間電介質(ILD)層5574。第二複數條導電互連線5576係在該第二ILD層5574中，而且該第二複數條導電互連線5576之個別的一些藉由該第二ILD層5574的部位而互相間隔分開。該複數條導電互連線5576之個別的一些包含導電阻障層5578和導電填充材料5580。 Referring to FIG. 55B , an integrated circuit structure 5550 includes a first interlayer dielectric (ILD) layer 5554 over a substrate 5552 . A first plurality of conductive interconnect lines 5556 are in the first ILD layer 5554 , and individual ones of the first plurality of conductive interconnect lines 5556 are spaced apart from each other by portions of the first ILD layer 5554 . Individual ones of the plurality of conductive interconnect lines 5556 include a conductive barrier layer 5558 and a conductive fill material 5560 . The integrated circuit structure 5550 further includes a second interlayer dielectric (ILD) layer 5574 over the substrate 5552 . A second plurality of conductive interconnect lines 5576 is in the second ILD layer 5574 , and individual ones of the second plurality of conductive interconnect lines 5576 are spaced apart from each other by portions of the second ILD layer 5574 . Individual ones of the plurality of conductive interconnect lines 5576 include a conductive barrier layer 5578 and a conductive fill material 5580 .

依據本發明的實施例，再次參照圖55B，製作積體電路結構的方法包含形成在基板5552上方之第一層間電介質(ILD)層5554中並且藉由在基板5552上方之第一層間電介質(ILD)層5554而間隔分開的第一複數條導電互連線5556。該第一複數條導電互連線5556係使用以間隔層為基礎的間距四等分製程，例如，相關於圖54之操作(a)到(e)所說明的方法來予以形成的。第二複數條導電互連線5576係形成在該第一ILD層5554上方的第二ILD層5574中並且藉由在該第一ILD層5554上方的第二ILD層5574而間隔分開。該第二複數條導電互連線5576係使用以間隔層為基礎的間距二等分製程，例如，相關於圖54之操作(a)及 (b)所說明的方法來予以形成的。 In accordance with an embodiment of the present invention, referring again to FIG. 55B , a method of fabricating an integrated circuit structure includes forming in a first interlayer dielectric (ILD) layer 5554 over a substrate 5552 and by (ILD) layer 5554 and a first plurality of conductive interconnect lines 5556 spaced apart. The first plurality of conductive interconnect lines 5556 are formed using a spacer-based pitch quartering process, eg, the method described with respect to operations (a) through (e) of FIG. 54 . A second plurality of conductive interconnect lines 5576 is formed in a second ILD layer 5574 over the first ILD layer 5554 and spaced apart by the second ILD layer 5574 over the first ILD layer 5554 . The second plurality of conductive interconnection lines 5576 use a spacer-based pitch bisecting process, for example, operations (a) and (b) to be formed by the method described.

在一實施例中，第一複數條導電互連線5556具有小於40奈米的緊鄰線之間的間距(P1)。第二複數條導電互連線5576具有44奈米以上的緊鄰線之間的間距(P2)。在一實施例中，以間隔層為基礎的間距四等分製程和以間隔層為基礎的間距二等分製程係基於浸沒式193nm光刻製程。 In one embodiment, the first plurality of conductive interconnect lines 5556 has a pitch (P1) between immediately adjacent lines of less than 40 nm. The second plurality of conductive interconnect lines 5576 has a pitch (P2) between immediately adjacent lines of 44 nm or more. In one embodiment, the spacer-based pitch quartering process and the spacer-based pitch bisecting process are based on an immersion 193 nm photolithography process.

在一實施例中，該第一複數條導電互連線5554之個別的一些包含第一導電阻障襯墊5558和第一導電填充材料5560。該第二複數條導電互連線5576之個別的一些包含第二導電阻障襯墊5578和第二導電填充材料5580。在一個這樣的實施例中，該第一導電填充材料5560的組成與該第二導電填充材料5580的組成不同。在另一實施例中，該第一導電填充材料5560的組成與該第二導電填充材料5580的組成相同。 In one embodiment, individual ones of the first plurality of conductive interconnect lines 5554 include a first conductive barrier liner 5558 and a first conductive fill material 5560 . Individual ones of the second plurality of conductive interconnect lines 5576 include second conductive barrier liners 5578 and second conductive fill material 5580 . In one such embodiment, the composition of the first conductive fill material 5560 is different than the composition of the second conductive fill material 5580 . In another embodiment, the composition of the first conductive filling material 5560 is the same as that of the second conductive filling material 5580 .

雖然未描述出，在一實施例中，該方法另包含形成在該第二ILD層5574上方的第三ILD層中並且藉由在該第二ILD層5574上方的第三ILD層而間隔分開的第三複數條導電互連線。該第三複數條導電互連線在沒有使用間距分割的情況下被形成。 Although not depicted, in one embodiment, the method further includes forming in a third ILD layer over the second ILD layer 5574 and spaced apart by the third ILD layer over the second ILD layer 5574. A third plurality of conductive interconnect lines. The third plurality of conductive interconnect lines are formed without using pitch division.

雖然未描述出，在一實施例中，該方法另包含在形成該第二複數條導電互連線5576之前，先形成在該第一ILD層5554上方的第三ILD層中並且藉由在該第一ILD層5554上方的第三ILD層而間隔分開的第三複數條導電互 連線。該第三複數條導電互連線係使用以間隔層為基礎的間距四等分製程來予以形成的。在一個這樣的實施例中，在形成該第二複數條導電互連線5576之後，第四複數條導電互連線係形成在該第二ILD層5574上方的第四ILD層中並且藉由在該第二ILD層5574上方的第四ILD層而間隔分開。該第四複數條導電互連線係使用以間隔層為基礎的間距二等分製程來予以形成的。在一實施例中，此一方法另包含形成在該第四ILD層上方的第五ILD層中並且藉由在該第四ILD層上方的第五ILD層而間隔分開的第五複數條導電互連線，該第五複數條導電互連線係使用以間隔層為基礎的間距二等分製程來予以形成的。第六複數條導電互連線然後被形成在該第五ILD層上方的第六ILD層中並且藉由在該第五ILD層上方的第六ILD層而間隔分開，該第六複數條導電互連線係使用以間隔層為基礎的間距二等分製程來予以形成的。第七複數條導電互連線然後被形成在該第六ILD層上方的第七ILD層中並且藉由在該第六ILD層上方的第七ILD層而間隔分開。該第七複數條導電互連線在沒有使用間距分割的情況下被形成。 Although not shown, in one embodiment, the method further includes forming a third ILD layer above the first ILD layer 5554 before forming the second plurality of conductive interconnect lines 5576 and by The third plurality of conductive interconnects separated by the third ILD layer above the first ILD layer 5554 connection. The third plurality of conductive interconnect lines are formed using a spacer-based pitch quartering process. In one such embodiment, after forming the second plurality of conductive interconnect lines 5576, a fourth plurality of conductive interconnect lines are formed in a fourth ILD layer over the second ILD layer 5574 and by The fourth ILD layer above the second ILD layer 5574 is spaced apart. The fourth plurality of conductive interconnections are formed using a spacer-based pitch bisecting process. In one embodiment, the method further includes forming a fifth plurality of conductive interconnects in a fifth ILD layer over the fourth ILD layer and spaced apart by the fifth ILD layer over the fourth ILD layer. and interconnecting lines, the fifth plurality of conductive interconnecting lines are formed using a spacer-based pitch bisecting process. A sixth plurality of conductive interconnect lines is then formed in a sixth ILD layer above the fifth ILD layer and spaced apart by a sixth ILD layer above the fifth ILD layer, the sixth plurality of conductive interconnect lines The connections are formed using a spacer-based pitch bisecting process. A seventh plurality of conductive interconnect lines is then formed in a seventh ILD layer over the sixth ILD layer and spaced apart by the seventh ILD layer over the sixth ILD layer. The seventh plurality of conductive interconnect lines are formed without using pitch division.

在另一態樣中，金屬線組成改變於金屬化層之間。此一配置可被稱為異質金屬化層。在一實施例中，銅被使用做為用於相對較大互連線的導電填充材料，而鈷被使用做為用於相對較小互連線的導電填充材料。具有鈷作為填充材料之較小的線可以提供減小的電遷移(electromigration)且同時保持低電阻率(resistivity)。鈷代 替銅使用於較小的互連線可以對付具有縮放銅線的問題，其中，導電阻障層消耗較大量的互連體積(interconnect volume)而且銅減少，基本上阻礙了通常與銅互連線相關聯的優點好處。 In another aspect, the metal line composition changes between metallization layers. Such a configuration may be referred to as a heterogeneous metallization layer. In one embodiment, copper is used as the conductive fill material for relatively larger interconnect lines and cobalt is used as the conductive fill material for relatively smaller interconnect lines. Smaller wires with cobalt as the fill material can provide reduced electromigration while maintaining low resistivity. cobalt generation Replacing copper for smaller interconnects can address the problem of having scaling copper where the conductive barrier layer consumes a larger amount of interconnect volume and the copper is reduced, essentially preventing Associated advantages benefits.

在第一範例中，圖56A繪示依據本發明的一實施例，積體電路結構的剖面視圖，該積體電路結構具有帶有金屬線組成的金屬化層係在帶有不同金屬線組成的金屬化層上方。 In a first example, FIG. 56A shows a cross-sectional view of an integrated circuit structure having a metallization layer with a metal line composition tied to a metal line composition with a different metal line composition in accordance with an embodiment of the present invention. above the metallization layer.

參照圖56A，積體電路結構5600包含第一複數條導電互連線5606，該第一複數條導電互連線5606係在基板5602上方的第一層間電介質(ILD)層5604中，並且藉由在基板5602上方之第一層間電介質(ILD)層5604而被間隔分開。該等導電互連線5606A的其中一條被顯示為具有在下面的介層5607。該第一複數條導電互連線5606之個別的一些包含沿著第一導電填充材料5610之側壁和底部的第一導電阻障層5608。 Referring to FIG. 56A , an integrated circuit structure 5600 includes a first plurality of conductive interconnect lines 5606 in a first interlayer dielectric (ILD) layer 5604 over a substrate 5602 and by are spaced apart by a first interlayer dielectric (ILD) layer 5604 over a substrate 5602 . One of the conductive interconnect lines 5606A is shown with a via 5607 underneath. Individual ones of the first plurality of conductive interconnect lines 5606 include a first conductive barrier layer 5608 along the sidewalls and bottom of the first conductive fill material 5610 .

第二複數條導電互連線5616係在該第一ILD層5604上方的第二ILD層5614中，並且藉由該第一ILD層5604上方的第二ILD層5614而被間隔分開。該等導電互連線5616A的其中一條被顯示為具有在下面的介層5617。該第二複數條導電互連線5616之個別的一些包含沿著第二導電填充材料5620之側壁和底部的第二導電阻障層5618。該第二導電填充材料5620的組成和該第一導電填充材料5610的組成不同。 A second plurality of conductive interconnect lines 5616 are in the second ILD layer 5614 above the first ILD layer 5604 and are spaced apart by the second ILD layer 5614 above the first ILD layer 5604 . One of the conductive interconnect lines 5616A is shown with a via 5617 underneath. Individual ones of the second plurality of conductive interconnect lines 5616 include a second conductive barrier layer 5618 along the sidewalls and bottom of the second conductive filling material 5620 . The composition of the second conductive filling material 5620 is different from that of the first conductive filling material 5610 .

在一實施例中，該第二導電填充材料5620基本上由銅組成，而且該第一導電填充材料5610基本上由鈷組成。在一個這樣的實施例中，該第一導電阻障材料5608的組成和該第二導電阻障材料5618的組成不同。在另一個這樣的實施例中，該第一導電阻障材料5608的組成和該第二導電阻障材料5618的組成相同。 In one embodiment, the second conductive fill material 5620 consists essentially of copper, and the first conductive fill material 5610 consists essentially of cobalt. In one such embodiment, the composition of the first conductive barrier material 5608 and the composition of the second conductive barrier material 5618 are different. In another of these embodiments, the composition of the first conductive barrier material 5608 and the composition of the second conductive barrier material 5618 are the same.

在一實施例中，該第一導電填充材料5610包含具有摻雜劑雜質原子之第一濃度的銅，而且該第二導電填充材料5620包含具有摻雜劑雜質原子之第二濃度的銅。該摻雜劑雜質原子之第二濃度係低於該摻雜劑雜質原子之第一濃度。在一個這樣的實施例中，該摻雜劑雜質原子係選自由鋁(Al)和錳(Mn)組成的群組中。在一實施例中，該第一導電填充材料5610和該第二導電填充材料5620具有相同的組成。在一實施例中，該第一導電填充材料5610和該第二導電填充材料5620具有不同的組成。 In one embodiment, the first conductive fill material 5610 includes copper with a first concentration of dopant impurity atoms, and the second conductive fill material 5620 includes copper with a second concentration of dopant impurity atoms. The second concentration of dopant impurity atoms is lower than the first concentration of dopant impurity atoms. In one such embodiment, the dopant impurity atoms are selected from the group consisting of aluminum (Al) and manganese (Mn). In one embodiment, the first conductive filling material 5610 and the second conductive filling material 5620 have the same composition. In one embodiment, the first conductive filling material 5610 and the second conductive filling material 5620 have different compositions.

再次參照圖56A，該第二ILD層5614係在蝕刻停止層5622上。該導電介層5617係在該第二ILD層5614中以及在該蝕刻停止層5622的開口中。在一實施例中，該第一和第二ILD層5604和5614包含矽、碳及氧，而且該蝕刻停止層5622包含矽及氮。在一實施例中，該第一複數條導電互連線5606之個別的一些具有第一寬度(W1)，而且該第二複數條導電互連線5616之個別的一些具有大於第一寬度(W1)的第二寬度(W2)。 Referring again to FIG. 56A , the second ILD layer 5614 is on top of the etch stop layer 5622 . The conductive via layer 5617 is in the second ILD layer 5614 and in the opening of the etch stop layer 5622 . In one embodiment, the first and second ILD layers 5604 and 5614 include silicon, carbon, and oxygen, and the etch stop layer 5622 includes silicon and nitrogen. In one embodiment, individual ones of the first plurality of conductive interconnection lines 5606 have a first width (W1), and individual ones of the second plurality of conductive interconnection lines 5616 have a width greater than the first width (W1 ) of the second width (W2).

在第二範例中，圖56B繪示依據本發明的一 實施例，積體電路結構的剖面視圖，該積體電路結構具有帶有金屬線組成的金屬化層係耦合至帶有不同金屬線組成的金屬化層。 In a second example, Figure 56B shows a Embodiments are cross-sectional views of an integrated circuit structure having a metallization layer with a metal line composition coupled to a metallization layer with a different metal line composition.

參照圖56B，積體電路結構5650包含第一複數條導電互連線5656，該第一複數條導電互連線5656係在基板5652上方的第一層間電介質(ILD)層5654中，並且藉由在基板5652上方之第一層間電介質(ILD)層5654而被間隔分開。該等導電互連線5656A的其中一條被顯示為具有在下面的介層5657。該第一複數條導電互連線5656之個別的一些包含沿著第一導電填充材料5660之側壁和底部的第一導電阻障層5658。 Referring to FIG. 56B , an integrated circuit structure 5650 includes a first plurality of conductive interconnect lines 5656 in a first interlayer dielectric (ILD) layer 5654 over a substrate 5652 and by are spaced apart by a first interlayer dielectric (ILD) layer 5654 above the substrate 5652 . One of the conductive interconnect lines 5656A is shown with a via 5657 underneath. Individual ones of the first plurality of conductive interconnect lines 5656 include a first conductive barrier layer 5658 along the sidewalls and bottom of the first conductive fill material 5660 .

第二複數條導電互連線5666係在該第一ILD層5654上方的第二ILD層5664中，並且藉由該第一ILD層5654上方的第二ILD層5664而被間隔分開。該等導電互連線5666A的其中一條被顯示為具有在下面的介層5667。該第二複數條導電互連線5666之個別的一些包含沿著第二導電填充材料5670之側壁和底部的第二導電阻障材料5668。該第二導電填充材料5670的組成和該第一導電填充材料5660的組成不同。 A second plurality of conductive interconnect lines 5666 are in a second ILD layer 5664 above the first ILD layer 5654 and are spaced apart by the second ILD layer 5664 above the first ILD layer 5654 . One of the conductive interconnect lines 5666A is shown with a via 5667 underneath. Individual ones of the second plurality of conductive interconnect lines 5666 include second conductive barrier material 5668 along sidewalls and bottom of second conductive fill material 5670 . The composition of the second conductive filling material 5670 is different from that of the first conductive filling material 5660 .

在一實施例中，該導電介層5657係在該第一複數條導電互連線5656之個別的一個5656B上並且電耦合至該第一複數條導電互連線5656之個別的一個5656B，其使該第二複數條導電互連線5666之個別的一個5666A電耦合至該第一複數條導電互連線5656之個別的一個5656B。 在一實施例中，該第一複數條導電互連線5656之個別的一些係沿著第一方向5698(例如，進入或離開頁面)，而且該第二複數條導電互連線5666之個別的一些係沿著與該第一方向5698正交的第二方向5699，如同所描述的。在一實施例中，該導電介層5667包含沿著第二導電填充材料5670之側壁和底部的該第二導電阻障層5668，如同所描述的。 In one embodiment, the conductive via layer 5657 is on a respective one 5656B of the first plurality of conductive interconnection lines 5656 and is electrically coupled to a respective one 5656B of the first plurality of conductive interconnection lines 5656, which A respective one 5666A of the second plurality of conductive interconnect lines 5666 is electrically coupled to a respective one 5656B of the first plurality of conductive interconnect lines 5656 . In one embodiment, individual ones of the first plurality of conductive interconnect lines 5656 are along the first direction 5698 (eg, entering or leaving the page), and individual ones of the second plurality of conductive interconnect lines 5666 Some are along a second direction 5699 that is orthogonal to the first direction 5698, as described. In one embodiment, the conductive via layer 5667 includes the second conductive barrier layer 5668 along the sidewalls and bottom of the second conductive fill material 5670, as described.

在一實施例中，該第二ILD層5664係在該第一ILD層5654上的蝕刻停止層5672上。該導電介層5667係在該第二ILD層5664中以及在該蝕刻停止層5672的開口中。在一實施例中，該第一和第二ILD層5654和5664包含矽、碳及氧，而且該蝕刻停止層5672包含矽及氮。在一實施例中，該第一複數條導電互連線5656之個別的一些具有第一寬度(W1)，而且該第二複數條導電互連線5666之個別的一些具有大於第一寬度(W1)的第二寬度(W2)。 In one embodiment, the second ILD layer 5664 is on the etch stop layer 5672 on the first ILD layer 5654 . The conductive via 5667 is in the second ILD layer 5664 and in the opening of the etch stop layer 5672 . In one embodiment, the first and second ILD layers 5654 and 5664 include silicon, carbon, and oxygen, and the etch stop layer 5672 includes silicon and nitrogen. In one embodiment, individual ones of the first plurality of conductive interconnection lines 5656 have a first width (W1), and individual ones of the second plurality of conductive interconnection lines 5666 have a width greater than the first width (W1 ) of the second width (W2).

在一實施例中，該第二導電填充材料5670基本上由銅組成，而且該第一導電填充材料5660基本上由鈷組成。在一個這樣的實施例中，該第一導電阻障層5658的組成和該第二導電阻障層5668的組成不同。在另一個這樣的實施例中，該第一導電阻障層5658的組成和該第二導電阻障層5668的組成相同。 In one embodiment, the second conductive fill material 5670 consists essentially of copper, and the first conductive fill material 5660 consists essentially of cobalt. In one such embodiment, the composition of the first conductive barrier layer 5658 and the composition of the second conductive barrier layer 5668 are different. In another of these embodiments, the composition of the first conductive barrier layer 5658 and the composition of the second conductive barrier layer 5668 are the same.

在一實施例中，該第一導電填充材料5660包含具有摻雜劑雜質原子之第一濃度的銅，而且該第二導電填充材料5670包含具有摻雜劑雜質原子之第二濃度的銅。該摻雜劑雜質原子之第二濃度係低於該摻雜劑雜質原子之 第一濃度。在一個這樣的實施例中，該摻雜劑雜質原子係選自由鋁(Al)和錳(Mn)組成的群組中。在一實施例中，該第一導電填充材料5660和該第二導電填充材料5670具有相同的組成。在一實施例中，該第一導電填充材料5660和該第二導電填充材料5670具有不同的組成。 In one embodiment, the first conductive fill material 5660 includes copper with a first concentration of dopant impurity atoms, and the second conductive fill material 5670 includes copper with a second concentration of dopant impurity atoms. The second concentration of the dopant impurity atoms is lower than the concentration of the dopant impurity atoms first concentration. In one such embodiment, the dopant impurity atoms are selected from the group consisting of aluminum (Al) and manganese (Mn). In one embodiment, the first conductive filling material 5660 and the second conductive filling material 5670 have the same composition. In one embodiment, the first conductive filling material 5660 and the second conductive filling material 5670 have different compositions.

圖57A到57C繪示依據本發明的一實施例，具有適合相關於圖56A和56B所述之結構的各種阻障襯墊和導電覆蓋結構配置之個別互連線的剖面視圖。 Figures 57A-57C illustrate cross-sectional views of individual interconnect lines with various barrier liner and conductive cap structure configurations suitable for the structures described with respect to Figures 56A and 56B, in accordance with one embodiment of the present invention.

參照圖57A，電介質層5701中的互連線5700包含導電阻障材料5702和導電填充材料5704。該導電阻障材料5702包含遠離該導電填充材料5704的外層5706和接近該導電填充材料5704的內層5708。在一實施例中，該導電填充材料包含鈷，該外層5706包含鈦和氮，且該內層5708包含鎢、氮和碳。在一個這樣的實施例中，該外層5706具有約2奈米的厚度，且該內層5708具有約0.5奈米的厚度。在另一實施例中，該導電填充材料包含鈷，該外層5706包含鉭，且該內層5708包含釕。在一個這樣的實施例中，該外層5706另包含氮。 Referring to FIG. 57A , an interconnect line 5700 in a dielectric layer 5701 includes a conductive barrier material 5702 and a conductive fill material 5704 . The conductive barrier material 5702 includes an outer layer 5706 remote from the conductive fill material 5704 and an inner layer 5708 proximate to the conductive fill material 5704 . In one embodiment, the conductive fill material includes cobalt, the outer layer 5706 includes titanium and nitrogen, and the inner layer 5708 includes tungsten, nitrogen, and carbon. In one such embodiment, the outer layer 5706 has a thickness of about 2 nanometers and the inner layer 5708 has a thickness of about 0.5 nanometers. In another embodiment, the conductive fill material includes cobalt, the outer layer 5706 includes tantalum, and the inner layer 5708 includes ruthenium. In one such embodiment, the outer layer 5706 further comprises nitrogen.

參照圖57B，電介質層5721中的互連線5720包含導電阻障材料5722和導電填充材料5724。導電蓋層5730係在該導電填充材料5724的頂部上。在一個這樣的實施例中，該導電蓋層5730係進一步在該導電阻障材料5722的頂部上，如同所描述的。在另一實施例中，該導電蓋層5730不在該導電阻障材料5722的頂部上。在一實施例中， 該導電蓋層5730基本上由鈷組成，且該導電填充材料5724基本上由銅組成。 Referring to FIG. 57B , interconnect lines 5720 in dielectric layer 5721 include conductive barrier material 5722 and conductive fill material 5724 . On top of the conductive fill material 5724 a conductive cap layer 5730 is tied. In one such embodiment, the conductive cap layer 5730 is further on top of the conductive barrier material 5722, as described. In another embodiment, the conductive cap layer 5730 is not on top of the conductive barrier material 5722 . In one embodiment, The conductive cap layer 5730 consists essentially of cobalt, and the conductive fill material 5724 consists essentially of copper.

參照圖57C，電介質層5741中的互連線5740包含導電阻障材料5742和導電填充材料5744。該導電阻障材料5742包含遠離該導電填充材料5744的外層5746和接近該導電填充材料5744的內層5748。導電蓋層5750係在該導電填充材料5744的頂部上。在一個實施例中，該導電蓋層5750係僅在該導電填充材料5744的頂部上。然而，在另一實施例中，該導電蓋層5750係進一步在該導電阻障材料5742之該內層5748的頂部上，亦即，在位置5752處。在一個這樣的實施例中，該導電蓋層5750係進一步在該導電阻障材料5742之該外層5746的頂部上，亦即，在位置5754處。 Referring to FIG. 57C , interconnect lines 5740 in dielectric layer 5741 include conductive barrier material 5742 and conductive fill material 5744 . The conductive barrier material 5742 includes an outer layer 5746 remote from the conductive fill material 5744 and an inner layer 5748 proximate to the conductive fill material 5744 . On top of the conductive fill material 5744 a conductive cap layer 5750 is tied. In one embodiment, the conductive cap layer 5750 is only on top of the conductive fill material 5744 . However, in another embodiment, the conductive cap layer 5750 is further on top of the inner layer 5748 of the conductive barrier material 5742 , ie, at location 5752 . In one such embodiment, the conductive cap layer 5750 is further on top of the outer layer 5746 of the conductive barrier material 5742 , ie, at location 5754 .

在一實施例中，參照圖57B和57C，製作積體電路結構的方法包含形成在基板上方的層間電介質(ILD)層5721或5741。複數條導電互連線5720或5740係形成在該ILD層的溝槽中並且藉由該ILD層而被間隔分開，該複數條導電互連線5720或5740之個別的一些係在該等溝槽之對應的一些中。該複數條導電互連線的形成係藉由首先形成導電阻障材料5722或5724在該等溝槽的底部和側壁上，而後分別形成導電填充材料5724或5744在該導電阻障材料5722或5742上，並且填滿該等溝槽，其中，該導電阻障材料5722或5742係分別沿著該導電填充材料5730或5750的底部以及沿著其側壁。該導電填充材料5724或5744然後 用包含氧及碳的氣體來予以處理。在用包含氧及碳的氣體來處理該導電填充材料5724或5744的頂部之後，導電蓋層5730或5750分別被形成在該導電填充材料5724或5744的頂部上。 In one embodiment, referring to FIGS. 57B and 57C , a method of fabricating an integrated circuit structure includes forming an interlayer dielectric (ILD) layer 5721 or 5741 over a substrate. A plurality of conductive interconnect lines 5720 or 5740 are formed in trenches of the ILD layer and are spaced apart by the ILD layer, individual ones of the plurality of conductive interconnect lines 5720 or 5740 are formed in the trenches. Some of the corresponding ones. The plurality of conductive interconnects are formed by first forming conductive barrier material 5722 or 5724 on the bottom and sidewalls of the trenches, and then forming conductive filling material 5724 or 5744 on the conductive barrier material 5722 or 5742, respectively. and fill the trenches, wherein the conductive barrier material 5722 or 5742 is along the bottom and sidewalls of the conductive fill material 5730 or 5750, respectively. The conductive fill material 5724 or 5744 is then Treat with a gas containing oxygen and carbon. After treating the top of the conductive fill material 5724 or 5744 with a gas comprising oxygen and carbon, a conductive cap layer 5730 or 5750 is formed on top of the conductive fill material 5724 or 5744, respectively.

在一個實施例中，用包含氧及碳的氣體來處理該導電填充材料5724或5744的頂部包含用一氧化碳(CO)來處理該導電填充材料5724或5744的頂部。在一個實施例中，該導電填充材料5724或5744包含銅，而且形成導電蓋層5730或5750在該導電填充材料5724或5744的頂部上包含使用化學氣相沉積法(CVD)來形成含鈷層。在一個實施例中，導電蓋層5730或5750被形成在該導電填充材料5724或5744的頂部上，但是不在該導電阻障材料5722或5742的頂部上。 In one embodiment, treating the top of the conductive fill material 5724 or 5744 with a gas comprising oxygen and carbon includes treating the top of the conductive fill material 5724 or 5744 with carbon monoxide (CO). In one embodiment, the conductive fill material 5724 or 5744 comprises copper, and forming the conductive cap layer 5730 or 5750 on top of the conductive fill material 5724 or 5744 comprises using chemical vapor deposition (CVD) to form a cobalt-containing layer . In one embodiment, a conductive cap layer 5730 or 5750 is formed on top of the conductive fill material 5724 or 5744 , but not on top of the conductive barrier material 5722 or 5742 .

在一個實施例中，形成該導電阻障材料5722或5744含形成第一導電層在該等溝槽的底部和側壁上，該第一導電層包含鉭。首先使用原子層沉積法(ALD)來形成該第一導電層的第一部位，而後使用物理氣相沉積法(PVD)來形成該第一導電層的第二部位。在一個這樣的實施例中，形成該導電阻障材料另包含形成第二導電層在該等溝槽的底部和側壁上的該第一導電層上，該第二導電層包含釕，而且該導電填充材料包含銅。在一個實施例中，該第一導電層另包含氮。 In one embodiment, forming the conductive barrier material 5722 or 5744 includes forming a first conductive layer on the bottom and sidewalls of the trenches, the first conductive layer comprising tantalum. First, atomic layer deposition (ALD) is used to form a first portion of the first conductive layer, and then physical vapor deposition (PVD) is used to form a second portion of the first conductive layer. In one such embodiment, forming the conductive barrier material further comprises forming a second conductive layer on the first conductive layer on the bottom and sidewalls of the trenches, the second conductive layer includes ruthenium, and the conductive The filler material contains copper. In one embodiment, the first conductive layer further includes nitrogen.

圖58繪示依據本發明的一實施例，積體電路結構的剖面視圖，該積體電路結構具有帶有金屬線組成和 間距的四個金屬化層係在帶有不同金屬線組成和較小間距的兩個金屬化層上方。 58 illustrates a cross-sectional view of an integrated circuit structure having metal line components and Four metallization layers of pitch are superimposed on two metallization layers with different metal line compositions and smaller pitches.

參照圖58，積體電路結構5800包含第一複數條導電互連線5804，該第一複數條導電互連線5804係在基板5801上方的第一層間電介質(ILD)層5802中，並且藉由在基板5801上方的第一層間電介質(ILD)層5802而被間隔分開。該第一複數條導電互連線5804之個別的一些包含沿著第一導電填充材料5808之側壁和底部的第一導電阻障層5806。該第一複數條導電互連線5804之個別的一些係沿著第一方向5898(例如，進入或離開頁面)。 Referring to FIG. 58, an integrated circuit structure 5800 includes a first plurality of conductive interconnect lines 5804 in a first interlayer dielectric (ILD) layer 5802 above a substrate 5801, and by are spaced apart by a first interlayer dielectric (ILD) layer 5802 over a substrate 5801 . Individual ones of the first plurality of conductive interconnect lines 5804 include a first conductive barrier layer 5806 along sidewalls and bottom of a first conductive fill material 5808 . Individual ones of the first plurality of conductive interconnect lines 5804 are along a first direction 5898 (eg, into or out of a page).

第二複數條導電互連線5814係在該第一ILD層5802上方的第二ILD層5812中，並且藉由該第一ILD層5802上方的第二ILD層5812而被間隔分開。該第二複數條導電互連線5814之個別的一些包含沿著該第一導電填充材料5808之側壁和底部的第一導電阻障層5806。該第二複數條導電互連線5814之個別的一些係沿著與該第一方向5898正交的第二方向5899。 A second plurality of conductive interconnect lines 5814 are in the second ILD layer 5812 above the first ILD layer 5802 and are spaced apart by the second ILD layer 5812 above the first ILD layer 5802 . Individual ones of the second plurality of conductive interconnect lines 5814 include a first conductive barrier layer 5806 along sidewalls and bottom of the first conductive fill material 5808 . Individual ones of the second plurality of conductive interconnect lines 5814 are along a second direction 5899 orthogonal to the first direction 5898 .

第三複數條導電互連線5824係在該第二ILD層5812上方的第三ILD層5822中，並且藉由該第二ILD層5812上方的第三ILD層5822而被間隔分開。該第三複數條導電互連線5824之個別的一些包含沿著該第二導電填充材料5828之側壁和底部的第二導電阻障層5826。該第二導電填充材料5828的組成和該第一導電填充材料5808的組成不同。該第三複數條導電互連線5824之個別的一些係沿著該 第一方向5898。 A third plurality of conductive interconnect lines 5824 are in the third ILD layer 5822 above the second ILD layer 5812 and are spaced apart by the third ILD layer 5822 above the second ILD layer 5812 . Individual ones of the third plurality of conductive interconnect lines 5824 include a second conductive barrier layer 5826 along sidewalls and bottom of the second conductive fill material 5828 . The composition of the second conductive filling material 5828 is different from the composition of the first conductive filling material 5808 . Individual ones of the third plurality of conductive interconnect lines 5824 are along the 5898 for the first direction.

第四複數條導電互連線5834係在該第三ILD層5822上方的第四ILD層5832中，並且藉由該第三ILD層5822上方的第四ILD層5832而被間隔分開。該第四複數條導電互連線5834之個別的一些包含沿著該第二導電填充材料5828之側壁和底部的第二導電阻障層5826。該第四複數條導電互連線5834之個別的一些係沿著該第二方向5899。 A fourth plurality of conductive interconnect lines 5834 are in the fourth ILD layer 5832 above the third ILD layer 5822 and are spaced apart by the fourth ILD layer 5832 above the third ILD layer 5822 . Individual ones of the fourth plurality of conductive interconnect lines 5834 include a second conductive barrier layer 5826 along sidewalls and bottom of the second conductive fill material 5828 . Individual ones of the fourth plurality of conductive interconnect lines 5834 are along the second direction 5899 .

第五複數條導電互連線5844係在該第四ILD層5832上方的第五ILD層5842中，並且藉由該第四ILD層5832上方的第五ILD層5842而被間隔分開。該第五複數條導電互連線5844之個別的一些包含沿著該第二導電填充材料5828之側壁和底部的第二導電阻障層5826。該第五複數條導電互連線5844之個別的一些係沿著該第一方向5898。 A fifth plurality of conductive interconnect lines 5844 is in the fifth ILD layer 5842 above the fourth ILD layer 5832 and is spaced apart by the fifth ILD layer 5842 above the fourth ILD layer 5832 . Individual ones of the fifth plurality of conductive interconnect lines 5844 include a second conductive barrier layer 5826 along sidewalls and bottom of the second conductive fill material 5828 . Individual ones of the fifth plurality of conductive interconnect lines 5844 are along the first direction 5898 .

第六複數條導電互連線5854係在該第五ILD層上方的第六ILD層5852中，並且藉由該第五ILD層上方的第六ILD層5852而被間隔分開。該第六複數條導電互連線5854之個別的一些包含沿著該第二導電填充材料5828之側壁和底部的第二導電阻障層5826。該第六複數條導電互連線5854之個別的一些係沿著該第二方向5899。 A sixth plurality of conductive interconnect lines 5854 is in the sixth ILD layer 5852 above the fifth ILD layer and is spaced apart by the sixth ILD layer 5852 above the fifth ILD layer. Individual ones of the sixth plurality of conductive interconnect lines 5854 include a second conductive barrier layer 5826 along sidewalls and bottom of the second conductive fill material 5828 . Individual ones of the sixth plurality of conductive interconnect lines 5854 are along the second direction 5899 .

在一實施例中，該第二導電填充材料5828基本上由銅組成，而且該第一導電填充材料5808基本上由鈷組成。在一實施例中，該第一導電填充材料5808包含具有摻雜劑雜質原子之第一濃度的銅，而且該第二導電填充材料5828包含具有摻雜劑雜質原子之第二濃度的銅，該摻雜 劑雜質原子之第二濃度係低於該摻雜劑雜質原子之第一濃度。 In one embodiment, the second conductive fill material 5828 consists essentially of copper, and the first conductive fill material 5808 consists essentially of cobalt. In one embodiment, the first conductive fill material 5808 includes copper with a first concentration of dopant impurity atoms, and the second conductive fill material 5828 includes copper with a second concentration of dopant impurity atoms, the doping The second concentration of dopant impurity atoms is lower than the first concentration of dopant impurity atoms.

在一實施例中，該第一導電阻障層5806的組成和該第二導電阻障層5826的組成不同。在另一實施例中，該第一導電阻障層5806和該第二導電阻障層5826具有相同的組成。 In one embodiment, the composition of the first conductive barrier layer 5806 is different from the composition of the second conductive barrier layer 5826 . In another embodiment, the first conductive barrier layer 5806 and the second conductive barrier layer 5826 have the same composition.

在一實施例中，第一導電介層5819係在該第一複數條導電互連線5804之個別的一個5804A上並且電耦合至該第一複數條導電互連線5804之個別的一個5804A。該第二複數條導電互連線5814之個別的一個5814A係在該第一導電介層5819上並且電耦合至該第一導電介層5819。 In one embodiment, a first conductive via layer 5819 is on and electrically coupled to a respective one 5804A of the first plurality of conductive interconnection lines 5804 . A respective one 5814A of the second plurality of conductive interconnection lines 5814 is on the first conductive via layer 5819 and is electrically coupled to the first conductive via layer 5819 .

第二導電介層5829係在該第二複數條導電互連線5814之個別的一個5814B上並且電耦合至該第二複數條導電互連線5814之個別的一個5814B。該第三複數條導電互連線5824之個別的一個5824A係在該第二導電介層5829上並且電耦合至該第二導電介層5829。 A second conductive via layer 5829 is on and electrically coupled to a respective one 5814B of the second plurality of conductive interconnection lines 5814 . A respective one 5824A of the third plurality of conductive interconnection lines 5824 is on the second conductive via layer 5829 and is electrically coupled to the second conductive via layer 5829 .

第三導電介層5839係在該第三複數條導電互連線5824之個別的一個5824B上並且電耦合至該第三複數條導電互連線5824之個別的一個5824B。該第四複數條導電互連線5834之個別的一個5834A係在該第三導電介層5839上並且電耦合至該第三導電介層5839。 A third conductive via layer 5839 is on and electrically coupled to a respective one 5824B of the third plurality of conductive interconnection lines 5824 . A respective one 5834A of the fourth plurality of conductive interconnection lines 5834 is on the third conductive via layer 5839 and is electrically coupled to the third conductive via layer 5839 .

第四導電介層5849係在該第四複數條導電互連線5834之個別的一個5834B上並且電耦合至該第四複數條導電互連線5834之個別的一個5834B。該第五複數條導 電互連線5844之個別的一個5844A係在該第四導電介層5849上並且電耦合至該第四導電介層5849。 A fourth conductive via layer 5849 is on and electrically coupled to a respective one 5834B of the fourth plurality of conductive interconnection lines 5834 . The fifth plural guide A respective one 5844A of the electrical interconnects 5844 is over the fourth conductive via 5849 and is electrically coupled to the fourth conductive via 5849 .

第五導電介層5859係在該第五複數條導電互連線5844之個別的一個5844B上並且電耦合至該第五複數條導電互連線5844之個別的一個5844B。該第六複數條導電互連線5854之個別的一個5854A係在該第五導電介層5859上並且電耦合至該第五導電介層5859。 A fifth conductive via layer 5859 is on and electrically coupled to a respective one 5844B of the fifth plurality of conductive interconnect lines 5844 . A respective one 5854A of the sixth plurality of conductive interconnection lines 5854 is on the fifth conductive via layer 5859 and is electrically coupled to the fifth conductive via layer 5859 .

在一個實施例中，該第一導電介層5819包含沿著第一導電填充材料5808之側壁和底部的第一導電阻障層5806。該第二5829、第三5839、第四5849和第五5859導電介層包含沿著第二導電填充材料5828之側壁和底部的第二導電阻障層5826。 In one embodiment, the first conductive via layer 5819 includes a first conductive barrier layer 5806 along sidewalls and bottom of the first conductive filling material 5808 . The second 5829 , third 5839 , fourth 5849 and fifth 5859 conductive vias include a second conductive barrier layer 5826 along the sidewalls and bottom of the second conductive filling material 5828 .

在一實施例中，該第一5802、第二5812、第三5822、第四5832、第五5842和第六5852ILD層係藉由相鄰ILD層之間的對應蝕刻停止層5890而互相分開。在一實施例中，該第一5802、第二5812、第三5822、第四5832、第五5842和第六5852ILD層包含矽、碳及氧。 In one embodiment, the first 5802, second 5812, third 5822, fourth 5832, fifth 5842, and sixth 5852 ILD layers are separated from each other by corresponding etch stop layers 5890 between adjacent ILD layers. In one embodiment, the first 5802, second 5812, third 5822, fourth 5832, fifth 5842 and sixth 5852 ILD layers comprise silicon, carbon and oxygen.

在一實施例中，該第一5804和第二5814複數條導電互連線具有第一寬度(W1)。第三5824、第四5834、第五5844和第六5854的複數條導電互連線之個別的一些具有大於第一寬度(W1)的第二寬度(W2)。 In one embodiment, the first 5804 and second 5814 plurality of conductive interconnect lines have a first width (W1). Individual ones of the plurality of conductive interconnect lines of the third 5824, fourth 5834, fifth 5844 and sixth 5854 have a second width (W2) greater than the first width (W1).

圖59A到59D繪示依據本發明的一實施例，具有底部導電層之各種互連線和介層配置的剖面視圖。 59A to 59D illustrate cross-sectional views of various interconnect and via configurations with bottom conductive layers in accordance with one embodiment of the present invention.

參照圖59A和59B，積體電路結構5900包含 在基板5902上方的層間電介質(ILD)層5904。導電介層5906係在該ILD層5904中的第一溝槽5908中。導電互連線5910係在該導電介層5906的上方並且電耦合至該導電介層5906。該導電互連線5910係在該ILD層5904中的第二溝槽5912中。該第二溝槽5912具有比該第一溝槽5908之開口5909更大的開口5913。 Referring to Figures 59A and 59B, an integrated circuit structure 5900 comprising An interlayer dielectric (ILD) layer 5904 over the substrate 5902 . A conductive via 5906 is embedded in a first trench 5908 in the ILD layer 5904 . A conductive interconnect 5910 is tied over and electrically coupled to the conductive via 5906 . The conductive interconnect line 5910 is tied in the second trench 5912 in the ILD layer 5904 . The second trench 5912 has an opening 5913 that is larger than the opening 5909 of the first trench 5908 .

在一實施例中，該導電介層5906和該導電互連線5910包含在該第一溝槽5908之底部上的第一導電阻障層5914，但是並不沿著該第一溝槽5908的側壁，而且不沿著該第二溝槽5912的底部和側壁。第二導電阻障層5916係在該第一溝槽5908之底部上的該第一導電阻障層5914上。該第二導電阻障層5916係進一步沿著該第一溝槽5908的側壁，而且進一步沿著該第二溝槽5912的底部和側壁。第三導電阻障層5918係在該第一溝槽5908之底部上的該第二導電阻障層5916上。該第三導電阻障層5918係進一步在沿著該第一溝槽5908的側壁而且沿著該第二溝槽5912的底部和側壁的該第二導電阻障層5916上。導電填充材料5920係在該第三導電阻障層5918上，而且填充該第一溝槽5908和該第二溝槽5912。該第三導電阻障層5918係沿著該導電填充材料5920的底部而且沿著該導電填充材料5920的側壁。 In one embodiment, the conductive via 5906 and the conductive interconnect 5910 include a first conductive barrier layer 5914 on the bottom of the first trench 5908 but not along the sidewalls, and not along the bottom and sidewalls of the second trench 5912. A second conductive barrier layer 5916 is on the first conductive barrier layer 5914 on the bottom of the first trench 5908 . The second conductive barrier layer 5916 is further along the sidewalls of the first trench 5908 , and further along the bottom and sidewalls of the second trench 5912 . A third conductive barrier layer 5918 is on the second conductive barrier layer 5916 on the bottom of the first trench 5908 . The third conductive barrier layer 5918 is further on the second conductive barrier layer 5916 along the sidewalls of the first trench 5908 and along the bottom and sidewalls of the second trench 5912 . A conductive fill material 5920 is attached to the third conductive barrier layer 5918 and fills the first trench 5908 and the second trench 5912 . The third conductive barrier layer 5918 is along the bottom of the conductive fill material 5920 and along the sidewalls of the conductive fill material 5920 .

在一個實施例中，該第一導電阻障層5914和該第三導電阻障層5918具有相同的組成，而且該第二導電阻障層5916的組成和該第一導電阻障層5914和該第三導電阻障層5918的組成不同。在一個這樣的實施例中，該第一 導電阻障層5914和該第三導電阻障層5918包含釕，而且該第二導電阻障層5916包含鉭。在一特別這樣的實施例中，該第二導電阻障層5916另包含氮。在一實施例中，該導電填充材料5920基本上由銅組成。 In one embodiment, the first conductive barrier layer 5914 and the third conductive barrier layer 5918 have the same composition, and the second conductive barrier layer 5916 has the same composition as the first conductive barrier layer 5914 and the The composition of the third conductive barrier layer 5918 is different. In one such embodiment, the first The conductive barrier layer 5914 and the third conductive barrier layer 5918 comprise ruthenium, and the second conductive barrier layer 5916 comprises tantalum. In one particular such embodiment, the second conductive barrier layer 5916 further comprises nitrogen. In one embodiment, the conductive fill material 5920 consists essentially of copper.

在一實施例中，導電蓋層5922係在該導電填充材料5920的頂部上。在一個這樣的實施例中，該導電蓋層5922係不在該第二導電阻障層5916的頂部上，而且不在該第三導電阻障層5918的頂部上。然而，在另一實施例中，該導電蓋層5922係進一步在該第三導電阻障層5918的頂部上，例如，在位置5924處。在一個這樣的實施例中，該導電蓋層5922仍進一步在該第二導電阻障層5916的頂部上，例如，在位置5926處。在一實施例中，該導電蓋層5922基本上由鈷組成，而且該導電填充材料5920基本上由銅組成。 In one embodiment, a conductive cap layer 5922 is tied on top of the conductive fill material 5920 . In one such embodiment, the conductive cap layer 5922 is not on top of the second conductive barrier layer 5916 and is not on top of the third conductive barrier layer 5918 . However, in another embodiment, the conductive cap layer 5922 is further on top of the third conductive barrier layer 5918 , eg, at location 5924 . In one such embodiment, the conductive cap layer 5922 is still further on top of the second conductive barrier layer 5916 , eg, at location 5926 . In one embodiment, the conductive cap layer 5922 consists essentially of cobalt, and the conductive fill material 5920 consists essentially of copper.

參照圖59C和59D，在一實施例中，該導電介層5906係在該ILD層5904下方之第二ILD層5952中的第二導電互連線5950上，而且電連接至在該ILD層5904下方之第二ILD層5952中的第二導電互連線5950。該第二導電互連線5950包含導電填充材料5954和其上的導電蓋部5956。蝕刻停止層5958可以在該導電蓋部5956之上，如同所描述的。 59C and 59D, in one embodiment, the conductive via layer 5906 is on the second conductive interconnection 5950 in the second ILD layer 5952 below the ILD layer 5904, and is electrically connected to the second conductive interconnect line 5950 in the ILD layer 5904. The second conductive interconnect line 5950 in the second ILD layer 5952 below. The second conductive interconnect 5950 includes a conductive fill material 5954 and a conductive cap 5956 thereon. An etch stop layer 5958 may be over the conductive cap 5956, as described.

在一個實施例中，該導電介層5906的該第一導電阻障層5914係在該第二導電互連線5950之導電蓋部5956的開口5960中，如同圖59C中所描述的。在一個這樣 的實施例中，該導電介層5906的該第一導電阻障層5914包含釕，而且該第二導電互連線5950的該導電蓋部5956包含鈷。 In one embodiment, the first conductive barrier layer 5914 of the conductive via layer 5906 is in the opening 5960 of the conductive cap portion 5956 of the second conductive interconnect 5950, as depicted in FIG. 59C. in one such In an embodiment, the first conductive barrier layer 5914 of the conductive via layer 5906 includes ruthenium, and the conductive cap portion 5956 of the second conductive interconnect 5950 includes cobalt.

在另一實施例中，該導電介層5906的該第一導電阻障層5914係在該第二導電互連線5950之導電蓋部5956的一部位中，如同圖59D中所描述的。在一個這樣的實施例中，該導電介層5906的該第一導電阻障層5914包含釕，而且該第二導電互連線5950的該導電蓋部5956包含鈷。在一特別的實施例中，雖然未被描述出，該導電介層5906的該第一導電阻障層5914係在進入該第二導電互連線5950之該導電蓋部5956內但是並未貫穿該第二導電互連線5950之該導電蓋部5956的凹部上。 In another embodiment, the first conductive barrier layer 5914 of the conductive via layer 5906 is in a portion of the conductive cap portion 5956 of the second conductive interconnect 5950, as depicted in FIG. 59D. In one such embodiment, the first conductive barrier layer 5914 of the conductive via layer 5906 includes ruthenium, and the conductive cap portion 5956 of the second conductive interconnect line 5950 includes cobalt. In a particular embodiment, although not depicted, the first conductive barrier layer 5914 of the conductive via layer 5906 is within the conductive cap portion 5956 that enters the second conductive interconnect line 5950 but does not pass through On the concave portion of the conductive cover portion 5956 of the second conductive interconnection line 5950 .

在另一態樣中，BEOL金屬化層具有非平面形貌，諸如介於導電線與收容該等導電線的ILD層之間的段差高度(step-height)差。在一實施例中，上覆的蝕刻停止層係形成與該形貌共形並且呈現該形貌。在一實施例中，該形貌有助於將上覆的介層蝕刻製程導引向該等導電線以阻礙導電介層的”非著陸性(non-landedness)”。 In another aspect, the BEOL metallization layer has a non-planar topography, such as a step-height difference between the conductive lines and the ILD layer housing the conductive lines. In one embodiment, an overlying etch stop layer is formed conformal to and exhibits the topography. In one embodiment, the topography helps direct the overlying via etch process toward the conductive lines to hinder the "non-landedness" of the conductive via.

在蝕刻停止層形貌的第一範例中，圖60A到60D繪示依據本發明的一實施例，針對BEOL金屬化層之凹入線形貌之結構配置的剖面視圖。 In a first example of an etch stop topography, FIGS. 60A to 60D show cross-sectional views of structural configurations for a concave line topography of a BEOL metallization layer in accordance with an embodiment of the present invention.

參照圖60A，積體電路結構6000包含複數條導電互連線6006，該複數條導電互連線6006係在基板6002上方的層間電介質(ILD)層6004中，並且藉由在基板6002 上方的層間電介質(ILD)層6004而被間隔開。該複數條導電互連線6006的其中一者代表性地被顯示為耦合至下面的介層6007。該複數條導電互連線6006之個別的一些具有在該ILD層6004之上表面6010下方的上表面6008。蝕刻停止層6012係在該ILD層6004和該複數條導電互連線6006上而且與該ILD層6004和該複數條導電互連線6006共形。該蝕刻停止層6012具有非平面的上表面，而該非平面的上表面具有在該ILD層6004之上的最上部位6014和在該複數條導電互連線6006之上的非平面上表面的最下部位6016。 Referring to FIG. 60A , an integrated circuit structure 6000 includes a plurality of conductive interconnect lines 6006 in an interlayer dielectric (ILD) layer 6004 above a substrate 6002 , and via the substrate 6002 The upper interlayer dielectric (ILD) layer 6004 is spaced apart. One of the plurality of conductive interconnect lines 6006 is representatively shown coupled to an underlying via 6007 . Individual ones of the plurality of conductive interconnect lines 6006 have an upper surface 6008 below an upper surface 6010 of the ILD layer 6004 . An etch stop layer 6012 is overlying and conformal with the ILD layer 6004 and the plurality of conductive interconnect lines 6006 . The etch stop layer 6012 has a non-planar upper surface with an uppermost portion 6014 over the ILD layer 6004 and a lowermost portion of the non-planar upper surface over the plurality of conductive interconnect lines 6006 Site 6016.

導電介層6018係在該複數條導電互連線6006之個別的一個6006A上，並且電耦合至該複數條導電互連線6006之個別的一個6006A。該導電介層6018係在該蝕刻停止層6012的開口6020中。該開口6020係在該複數條導電互連線6006的個別一個6006A之上，但是不在該ILD層6014之上。該導電介層6018係在該蝕刻停止層6012上方的第二ILD層6022中。在一個實施例中，該第二ILD層6022係在該蝕刻停止層6012上並且與該蝕刻停止層6012共形，如同圖60A中所描述的。 A conductive via 6018 is on and electrically coupled to a respective one 6006A of the plurality of conductive interconnect lines 6006 . The conductive via 6018 is in the opening 6020 of the etch stop layer 6012 . The opening 6020 is over a respective one 6006A of the plurality of conductive interconnect lines 6006 , but not over the ILD layer 6014 . The conductive via layer 6018 is in the second ILD layer 6022 above the etch stop layer 6012 . In one embodiment, the second ILD layer 6022 is overlying and conformal to the etch stop layer 6012, as depicted in FIG. 60A.

在一實施例中，該導電介層6018的中心6024係與該複數條導電互連線6006之個別一個6006A的中心6026對準，如同圖60A中所描述的。然而，在另一實施例中，該導電介層6018的中心6024係與該複數條導電互連線6006之個別一個6006A的中心6026偏離，如同圖60B中所描述的。 In one embodiment, the center 6024 of the conductive via 6018 is aligned with the center 6026 of an individual 6006A of the plurality of conductive interconnect lines 6006, as depicted in FIG. 60A. However, in another embodiment, the center 6024 of the conductive via 6018 is offset from the center 6026 of an individual 6006A of the plurality of conductive interconnect lines 6006, as depicted in FIG. 60B.

在一實施例中，該複數條導電互連線6006之個別的一些包含沿著導電填充材料6030之側壁和底部的阻障層6028。在一個實施例中，該阻障層6028和該導電填充材料6030兩者皆具有在該ILD層6004之上表面6010下方的最上表面，如同圖60A,60B和60C中所描述的。在一特別這樣的實施例中，該阻障層6028的最上表面係在該導電填充材料6030之最上表面的上方，如同圖60C中所描述的。在另一實施例中，該導電填充材料6030具有在該ILD層6004之上表面6010下方的最上表面，而且該阻障層6028具有與該ILD層6004之上表面6010共平面的最上表面，如同圖60D中所描述的。 In one embodiment, individual ones of the plurality of conductive interconnect lines 6006 include a barrier layer 6028 along the sidewalls and bottom of the conductive fill material 6030 . In one embodiment, both the barrier layer 6028 and the conductive fill material 6030 have an uppermost surface below the upper surface 6010 of the ILD layer 6004, as depicted in Figures 60A, 60B and 60C. In one particular such embodiment, the uppermost surface of the barrier layer 6028 is above the uppermost surface of the conductive fill material 6030, as depicted in FIG. 60C. In another embodiment, the conductive fill material 6030 has an uppermost surface below the upper surface 6010 of the ILD layer 6004, and the barrier layer 6028 has an uppermost surface coplanar with the upper surface 6010 of the ILD layer 6004, as described in Figure 60D.

在一實施例中，該ILD層6004包含矽、碳及氧，而且該蝕刻停止層6012包含矽及氮。在一實施例中，該複數條導電互連線6006之個別一些的上表面6008係在該ILD層6004之上表面6010的下方在0.5到1.5奈米之範圍中的量。 In one embodiment, the ILD layer 6004 includes silicon, carbon, and oxygen, and the etch stop layer 6012 includes silicon and nitrogen. In one embodiment, upper surfaces 6008 of individual ones of the plurality of conductive interconnect lines 6006 are below the upper surface 6010 of the ILD layer 6004 by an amount in the range of 0.5 to 1.5 nm.

共同參照圖60A到60D，依據本發明的實施例，製作積體電路結構的方法包含形成複數條導電互連線，該複數條導電互連線係在基板6002上方之第一層間電介質(ILD)層6004中並且藉由在基板6002上方之第一層間電介質(ILD)層6004而間隔分開的。該複數條導電互連線相對於該第一ILD層而被凹入，以提供該複數條導電互連線之個別一些6006，其具有在該第一ILD層6004之上表面6010下方的上表面。在使該複數條導電互連線凹入之後， 蝕刻停止層6012被形成在該第一ILD層6004和該複數條導電互連線6006上而且與該第一ILD層6004和該複數條導電互連線6006共形。該蝕刻停止層6012具有非平面的上表面，而該非平面的上表面具有在該第一ILD層6004之上的最上部位6016和在該複數條導電互連線6006之上的非平面上表面的最下部位6014。第二ILD層6022係形成在該蝕刻停止層6012上。介層溝槽被蝕刻於該第二ILD層6022中。在該蝕刻期間，該蝕刻停止層6012指引(direct)該第二ILD層6022中之該介層溝槽的位置。該蝕刻停止層6012被蝕刻穿過該介層溝槽而形成該蝕刻停止層6012中的開口6020。該開口6020係在該複數條導電互連線6006的個別一個6006A之上，但是不在該第一ILD層6004之上。導電介層6018係形成在該介層溝槽中以及該蝕刻停止層6012中的該開口6020中。該導電介層6018係在該複數條導電互連線6006的個別一個6006A上，而且電耦合至該複數條導電互連線6006的個別一個6006A。 Referring collectively to FIGS. 60A through 60D , in accordance with an embodiment of the present invention, a method of fabricating an integrated circuit structure includes forming a plurality of conductive interconnect lines tied to a first interlayer dielectric (ILD) over a substrate 6002 . ) layer 6004 and spaced apart by a first interlayer dielectric (ILD) layer 6004 above the substrate 6002. The plurality of conductive interconnect lines are recessed relative to the first ILD layer to provide individual ones 6006 of the plurality of conductive interconnect lines having upper surfaces below the upper surface 6010 of the first ILD layer 6004 . After recessing the plurality of conductive interconnect lines, An etch stop layer 6012 is formed on and conformal with the first ILD layer 6004 and the plurality of conductive interconnect lines 6006 . The etch stop layer 6012 has a non-planar upper surface with an uppermost portion 6016 over the first ILD layer 6004 and a non-planar upper surface over the plurality of conductive interconnect lines 6006 The lowest part is 6014. A second ILD layer 6022 is formed on the etch stop layer 6012 . Via trenches are etched into the second ILD layer 6022 . During the etch, the etch stop layer 6012 directs the location of the via trench in the second ILD layer 6022 . The etch stop layer 6012 is etched through the via trench to form an opening 6020 in the etch stop layer 6012 . The opening 6020 is over a respective one 6006A of the plurality of conductive interconnect lines 6006 , but not over the first ILD layer 6004 . A conductive via 6018 is formed in the via trench and in the opening 6020 in the etch stop layer 6012 . The conductive via layer 6018 is on and electrically coupled to a respective one 6006A of the plurality of conductive interconnect lines 6006 .

在一個實施例中，該複數條導電互連線6006之個別的一些包含沿著導電填充材料6030之側壁和底部的阻障層6028，而且使該複數條導電互連線凹入包含使阻障層6028和導電填充材料6030兩者皆凹入，如同圖60A到60C中所描述的。在另一實施例中，該複數條導電互連線6006之個別的一些包含沿著導電填充材料6030之側壁和底部的阻障層6028，而且使該複數條導電互連線凹入包含使導電填充材料6030凹入但是實質上不使阻障層6028凹入， 如同圖60D中所描述的。在一實施例中，該蝕刻停止層6012重新指引(re-direct)光刻未對準的(mis-aligned)介層溝槽圖案。在一實施例中，使該複數條導電互連線6006凹入包含相對於該第一ILD層6004而凹入在0.5到1.5奈米之範圍中的量。 In one embodiment, individual ones of the plurality of conductive interconnect lines 6006 include a barrier layer 6028 along the sidewalls and bottom of the conductive fill material 6030, and recessing the plurality of conductive interconnect lines includes making the barrier layer 6028 Both layer 6028 and conductive fill material 6030 are recessed, as described in Figures 60A-60C. In another embodiment, individual ones of the plurality of conductive interconnect lines 6006 include a barrier layer 6028 along the sidewalls and bottom of the conductive fill material 6030, and recessing the plurality of conductive interconnect lines includes making conductive The fill material 6030 recesses but does not substantially recess the barrier layer 6028, As described in Figure 60D. In one embodiment, the etch stop layer 6012 re-directs lithographically mis-aligned via trench patterns. In one embodiment, recessing the plurality of conductive interconnect lines 6006 includes recessing relative to the first ILD layer 6004 by an amount in the range of 0.5 to 1.5 nm.

在蝕刻停止層形貌的第二範例中，圖61A到61D繪示依據本發明的一實施例，針對BEOL金屬化層之階梯線(stepped line)形貌之結構配置的剖面視圖。 In a second example of etch stop topography, FIGS. 61A to 61D show cross-sectional views of structural configurations for stepped line topography of BEOL metallization layers according to an embodiment of the present invention.

參照圖61A，積體電路結構6100包含複數條導電互連線6106，該複數條導電互連線6106係在基板6102上方的層間電介質(ILD)層6104中，並且藉由在基板6102上方的層間電介質(ILD)層6104而被間隔分開。該複數條導電互連線6106的其中一者代表性地被顯示為耦合至下面的介層6107。該複數條導電互連線6106之個別的一些具有在該ILD層6104之上表面6110下方的上表面6108。蝕刻停止層6112係在該ILD層6104和該複數條導電互連線6106上而且與該ILD層6104和該複數條導電互連線6106共形。該蝕刻停止層6112具有非平面的上表面，而該非平面的上表面具有在該ILD層6104之上的非平面上表面的最下部位6114和在該複數條導電互連線6106之上的非平面上表面的最上部位6116。 Referring to FIG. 61A , an integrated circuit structure 6100 includes a plurality of conductive interconnects 6106 in an interlayer dielectric (ILD) layer 6104 above a substrate 6102 and via an interlayer dielectric (ILD) layer 6104 above the substrate 6102 . Dielectric (ILD) layers 6104 are spaced apart. One of the plurality of conductive interconnect lines 6106 is representatively shown coupled to an underlying via 6107 . Individual ones of the plurality of conductive interconnect lines 6106 have an upper surface 6108 below an upper surface 6110 of the ILD layer 6104 . An etch stop layer 6112 is overlying and conformal with the ILD layer 6104 and the plurality of conductive interconnect lines 6106 . The etch stop layer 6112 has a non-planar upper surface, and the non-planar upper surface has a lowermost portion 6114 of the non-planar upper surface over the ILD layer 6104 and a non-planar upper surface over the plurality of conductive interconnect lines 6106. The uppermost part 6116 of the upper surface of the plane.

導電介層6118係在該複數條導電互連線6106之個別的一個6106A上，並且電耦合至該複數條導電互連線6106之個別的一個6106A。該導電介層6118係在該蝕刻 停止層6112的開口6120中。該開口6120係在該複數條導電互連線6106的個別一個6106A之上，但是不在該ILD層6114之上。該導電介層6118係在該蝕刻停止層6112上方的第二ILD層6122中。在一個實施例中，該第二ILD層6122係在該蝕刻停止層6112上並且與該蝕刻停止層6112共形，如同圖61A中所描述的。 A conductive via layer 6118 is on and electrically coupled to a respective one 6106A of the plurality of conductive interconnect lines 6106 . The conductive via layer 6118 is in the etched In the opening 6120 of the stop layer 6112 . The opening 6120 is over a respective one 6106A of the plurality of conductive interconnect lines 6106 , but not over the ILD layer 6114 . The conductive via layer 6118 is in the second ILD layer 6122 above the etch stop layer 6112 . In one embodiment, the second ILD layer 6122 is overlying and conformal to the etch stop layer 6112, as depicted in FIG. 61A.

在一實施例中，該導電介層6118的中心6124係與該複數條導電互連線6106之個別一個6106A的中心6126對準，如同圖61A中所描述的。然而，在另一實施例中，該導電介層6118的中心6124係與該複數條導電互連線6106之個別一個6106A的中心6126偏離，如同圖61B中所描述的。 In one embodiment, the center 6124 of the conductive via 6118 is aligned with the center 6126 of an individual 6106A of the plurality of conductive interconnect lines 6106, as depicted in FIG. 61A. However, in another embodiment, the center 6124 of the conductive via layer 6118 is offset from the center 6126 of an individual one 6106A of the plurality of conductive interconnect lines 6106, as depicted in FIG. 61B.

在一實施例中，該複數條導電互連線6106之個別的一些包含沿著導電填充材料6130之側壁和底部的阻障層6128。在一個實施例中，該阻障層6128和該導電填充材料6130兩者皆具有在該ILD層6104之上表面6110上方的最上表面，如同圖61A,61B和61C中所描述的。在一特別這樣的實施例中，該阻障層6128的最上表面係在該導電填充材料6130之最上表面的下方，如同圖61C中所描述的。在另一實施例中，該導電填充材料6130具有在該ILD層6104之上表面6110上方的最上表面，而且該阻障層6128具有與該ILD層6104之上表面6110共平面的最上表面，如同圖61D中所描述的。 In one embodiment, individual ones of the plurality of conductive interconnect lines 6106 include a barrier layer 6128 along the sidewalls and bottom of the conductive fill material 6130 . In one embodiment, both the barrier layer 6128 and the conductive fill material 6130 have an uppermost surface above the upper surface 6110 of the ILD layer 6104, as depicted in Figures 61A, 61B and 61C. In one particular such embodiment, the uppermost surface of the barrier layer 6128 is below the uppermost surface of the conductive fill material 6130, as depicted in FIG. 61C. In another embodiment, the conductive fill material 6130 has an uppermost surface above the upper surface 6110 of the ILD layer 6104, and the barrier layer 6128 has an uppermost surface coplanar with the upper surface 6110 of the ILD layer 6104, as described in Figure 61D.

在一實施例中，該ILD層6104包含矽、碳及 氧，而且該蝕刻停止層6112包含矽及氮。在一實施例中，該複數條導電互連線6106之個別一些的上表面6108係在該ILD層6004之上表面6110的上方在0.5到1.5奈米之範圍中的量。 In one embodiment, the ILD layer 6104 includes silicon, carbon, and Oxygen, and the etch stop layer 6112 includes silicon and nitrogen. In one embodiment, upper surfaces 6108 of individual ones of the plurality of conductive interconnect lines 6106 are above the upper surface 6110 of the ILD layer 6004 by an amount in the range of 0.5 to 1.5 nm.

共同參照圖61A到61D，依據本發明的實施例，製作積體電路結構的方法包含形成複數條導電互連線6106，該複數條導電互連線6106係在基板6102上方之第一層間電介質(ILD)層中並且藉由在基板6102上方之第一層間電介質(ILD)層而間隔分開的。該第一ILD層6104相對於該複數條導電互連線6106而被凹入，以提供該複數條導電互連線6106之個別一些，其具有在該第一ILD層6104之上表面6110上方的上表面6108。在使該第一ILD層6104凹入之後，蝕刻停止層6112被形成在該第一ILD層6104和該複數條導電互連線6106上而且與該第一ILD層6104和該複數條導電互連線6106共形。該蝕刻停止層6112具有非平面的上表面，而該非平面的上表面具有在該第一ILD層6104之上的非平面上表面的最下部位6114和在該複數條導電互連線6106之上的非平面上表面的最上部位6116。第二ILD層6122係形成在該蝕刻停止層6112上。介層溝槽被蝕刻於該第二ILD層6122中。在該蝕刻期間，該蝕刻停止層6112指引(direct)該第二ILD層6122中之該介層溝槽的位置。該蝕刻停止層6112被蝕刻穿過該介層溝槽而形成該蝕刻停止層6112中的開口6120。該開口6120係在該複數條導電互連線6106的個別一個6106A之上，但是不在該第一ILD層6104 之上。導電介層6118係形成在該介層溝槽中以及該蝕刻停止層6112中的該開口6120中。該導電介層6118係在該複數條導電互連線6106的個別一個6106A上，而且電耦合至該複數條導電互連線6106的個別一個6106A。 Referring collectively to FIGS. 61A through 61D , in accordance with an embodiment of the present invention, a method of fabricating an integrated circuit structure includes forming a plurality of conductive interconnect lines 6106 over a first interlayer dielectric over a substrate 6102 . (ILD) layer and spaced apart by a first interlayer dielectric (ILD) layer above the substrate 6102 . The first ILD layer 6104 is recessed relative to the plurality of conductive interconnect lines 6106 to provide individual ones of the plurality of conductive interconnect lines 6106 with 6108 on the upper surface. After recessing the first ILD layer 6104, an etch stop layer 6112 is formed on the first ILD layer 6104 and the plurality of conductive interconnect lines 6106 and in contact with the first ILD layer 6104 and the plurality of conductive interconnect lines Line 6106 is conformal. The etch stop layer 6112 has a non-planar upper surface with a lowermost portion 6114 of the non-planar upper surface over the first ILD layer 6104 and over the plurality of conductive interconnect lines 6106 The uppermost portion 6116 of the non-planar upper surface of . A second ILD layer 6122 is formed on the etch stop layer 6112 . Vias trenches are etched into the second ILD layer 6122 . During the etch, the etch stop layer 6112 directs the location of the via trench in the second ILD layer 6122 . The etch stop layer 6112 is etched through the via trench to form an opening 6120 in the etch stop layer 6112 . The opening 6120 is over a respective one 6106A of the plurality of conductive interconnect lines 6106, but not over the first ILD layer 6104 above. A conductive via 6118 is formed in the via trench and in the opening 6120 in the etch stop layer 6112 . The conductive via layer 6118 is on and electrically coupled to a respective one 6106A of the plurality of conductive interconnect lines 6106 .

在一個實施例中，該複數條導電互連線6106之個別的一些包含沿著導電填充材料6130之側壁和底部的阻障層6128，而且使該第一ILD層6104凹入包含使阻障層6128和導電填充材料6130兩者皆凹入，如同圖61A到61C中所描述的。在另一實施例中，該複數條導電互連線6106之個別的一些包含沿著導電填充材料6130之側壁和底部的阻障層6128，而且使該第一ILD層6104凹入包含相對於導電填充材料6130但是不相對於阻障層6128而凹入，如同圖61D中所描述的。在一實施例中，其中，該蝕刻停止層6112重新指引(re-direct)光刻未對準的(mis-aligned)介層溝槽圖案。在一實施例中，使該第一ILD層6104凹入包含相對於該複數條導電互連線6106而凹入在0.5到1.5奈米之範圍中的量。 In one embodiment, individual ones of the plurality of conductive interconnect lines 6106 include a barrier layer 6128 along the sidewalls and bottom of the conductive fill material 6130, and recessing the first ILD layer 6104 includes making the barrier layer Both 6128 and conductive fill material 6130 are recessed, as described in Figures 61A-61C. In another embodiment, individual ones of the plurality of conductive interconnect lines 6106 include barrier layers 6128 along the sidewalls and bottom of conductive fill material 6130, and the first ILD layer 6104 is recessed to include a conductive The fill material 6130 is however not recessed relative to the barrier layer 6128 as depicted in Figure 61D. In one embodiment, the etch stop layer 6112 re-directs the lithography mis-aligned via trench pattern. In one embodiment, recessing the first ILD layer 6104 includes recessing relative to the plurality of conductive interconnect lines 6106 by an amount in the range of 0.5 to 1.5 nm.

在另一態樣中，說明用以圖案化金屬線端的技術。為了提供上下文，在先進的半導體製造的節點中，可以藉由線光柵(line grating)、線端、和介層之分開的圖案化製程來創建下層互連(lower level interconnect)。然而，複合圖案的保真度(fidelity)可能傾向隨著介層侵蝕線端而劣化，且反之亦然。本文中所述的實施例提供消除相關之鄰近規則(proximity rule)的線端製程(也稱為插塞製 程)。實施例可以允許介層能夠被放置在線端處而且大的線端能夠搭接過(strap across)線端。 In another aspect, techniques for patterning metal line ends are described. To provide context, at nodes of advanced semiconductor fabrication, lower level interconnects may be created by separate patterning processes of line gratings, line terminations, and vias. However, the fidelity of the composite pattern may tend to degrade as the vias erode the line ends, and vice versa. Embodiments described herein provide end-of-line processing (also known as plug-based processing) that eliminates the associated proximity rules. Procedure). Embodiments may allow vias to be placed at line ends and large line ends to strap across line ends.

為了提供進一步的上下文，圖62A繪示依據本發明的一實施例，沿著金屬化層之平面視圖的a-a’軸線所取出之平面視圖和對應的剖面視圖。圖62B繪示依據本發明的一實施例，線端或插塞的剖面視圖。圖62C繪示依據本發明的一實施例，線端或插塞的另一剖面視圖。 To provide further context, Figure 62A shows a plan view and corresponding cross-sectional view taken along the a-a' axis of the plan view of the metallization layer, in accordance with one embodiment of the present invention. Figure 62B shows a cross-sectional view of a wire end or plug according to one embodiment of the present invention. Figure 62C illustrates another cross-sectional view of a wire end or plug in accordance with one embodiment of the present invention.

參照圖62A，金屬化層6200包含形成在電介質層6204中的金屬線6202。該等金屬線6202可以被耦合至下面的介層6203。該電介質層6204可包含線端或插塞區域6205。參照圖62B，該電介質層6204的線端或插塞區域6205可以藉由圖案化硬遮罩層6210在該電介質層6204上，而後蝕刻該電介質層6204之露出的部位來予以製作。該電介質層6204之露出的部位可以被蝕刻到適合形成線溝槽6206的深度，或者被進一步蝕刻到適合形成介層溝槽6208的深度。參照圖62C，鄰接該線端或插塞6205之對立側壁的兩個介層可以被製作於單一大的曝光(exposure)6216而最終形成線溝槽6212和介層溝槽6214。 Referring to FIG. 62A , metallization layer 6200 includes metal lines 6202 formed in dielectric layer 6204 . The metal lines 6202 may be coupled to the underlying via 6203 . The dielectric layer 6204 may include line termination or plug regions 6205 . Referring to FIG. 62B , the terminal or plug regions 6205 of the dielectric layer 6204 can be fabricated by patterning a hard mask layer 6210 on the dielectric layer 6204 and then etching the exposed portions of the dielectric layer 6204 . The exposed portion of the dielectric layer 6204 can be etched to a depth suitable for forming line trenches 6206 , or further etched to a depth suitable for forming via trenches 6208 . Referring to FIG. 62C , two vias adjacent to opposing sidewalls of the line termination or plug 6205 can be fabricated in a single large exposure 6216 to ultimately form line trenches 6212 and via trenches 6214 .

然而，再次參照圖62A到62C，保真度問題及/或硬遮罩腐蝕問題可能會導致不完美的圖案化體制(regime)。相較之下，本文中所述的一或更多個實施例包含涉及在溝槽和介層圖案化製程後之線端電介質(插塞)的建構之製程流程的施行。 However, referring again to Figures 62A-62C, fidelity issues and/or hard mask erosion issues may result in an imperfect patterning regime. In contrast, one or more embodiments described herein include the implementation of a process flow involving the construction of line termination dielectrics (plugs) after the trench and via patterning process.

在一態樣中，然後，本文中所述的一或更多 個實施例係有關用以建構非導電間隔層或中斷部於金屬線(稱為”線端”、”插塞”或”切割部”)之間的方法，而且在有些實施例中，相關的導電介層。導電介層，按照定義，被用來使金屬圖案著陸於先前的層上。在此脈絡下，因為藉由光刻設備的對準有賴於較小的程度(lesser extent)，所以本文中所述的實施例致能更強健的互連製作方案。此種互連製作方案可以被用來放鬆對對準/曝光的制約，可以被用來改善電接觸(例如，藉由減小介層電阻)，並且可以被用來減少在其他方面用以使用習知方法來圖案化此等特徵所需要的總製程操作及處理時間。 In one aspect, then, one or more of the Several embodiments relate to methods for constructing non-conductive spacers or interruptions between metal lines (referred to as "line stubs," "plugs," or "cuts"), and in some embodiments, related conductive interlayer. Conductive vias, by definition, are used to land metal patterns on previous layers. In this context, the embodiments described herein enable more robust interconnect fabrication schemes because the alignment by the lithographic apparatus depends on a lesser extent. Such interconnect fabrication schemes can be used to relax alignment/exposure constraints, can be used to improve electrical contact (for example, by reducing via resistance), and can be used to reduce the need for The total process operations and processing time required to pattern such features using conventional methods.

圖63A到63F繪示依據本發明的一實施例，代表插塞最後處理方案中之各種操作的平面視圖和對應的剖面視圖。 63A-63F illustrate plan views and corresponding cross-sectional views representing various operations in a plug finishing scheme, in accordance with one embodiment of the present invention.

參照圖63A，製作積體電路結構的方法包含形成線溝槽6306於在下面的金屬化層6300上方所形成之層間電介質(ILD)材料層6302的上部部位6304中。介層溝槽6308被形成在該ILD材料層6302的下部部位6310中。該介層溝槽6308使下面的金屬化層6300的金屬線6312暴露出。 Referring to FIG. 63A , a method of fabricating an integrated circuit structure includes forming line trenches 6306 in upper portions 6304 of an interlayer dielectric (ILD) material layer 6302 formed over an underlying metallization layer 6300 . A via trench 6308 is formed in a lower portion 6310 of the ILD material layer 6302 . The via trench 6308 exposes the metal line 6312 of the underlying metallization layer 6300 .

參照圖63B，犧牲材料6314被形成在該ILD材料層6302的上方以及在該線溝槽6306和該介層溝槽6308中。該犧牲材料6314可以具有形成於其上的硬遮罩6315，如同圖63B中所描述的。在一個實施例中，該犧牲材料6314包含碳。 Referring to FIG. 63B , sacrificial material 6314 is formed over the ILD material layer 6302 and in the line trench 6306 and the via trench 6308 . The sacrificial material 6314 may have a hard mask 6315 formed thereon, as described in FIG. 63B. In one embodiment, the sacrificial material 6314 includes carbon.

參照圖63C，該犧牲材料6314被圖案化而使 該線溝槽6306中之該犧牲材料6314的連續性中斷，例如，用以提供開口6316於該犧牲材料6314中。 Referring to Figure 63C, the sacrificial material 6314 is patterned such that The continuity of the sacrificial material 6314 in the line trench 6306 is interrupted, for example, to provide an opening 6316 in the sacrificial material 6314 .

參照圖63D，該犧牲材料6314中的開口6316用電介質材料來填充而形成電介質插塞6318。在一實施例中，在用電介質材料來填充該犧牲材料6314中的開口6316之後，該硬遮罩6315被去除以提供該電介質插塞6318，該電介質插塞6318具有在該ILD材料層6302之上表面6322上方的上表面6320，如同圖63D中所描述的。該犧牲材料6314被去除而留下該電介質插塞6318剩下。 Referring to FIG. 63D , the opening 6316 in the sacrificial material 6314 is filled with a dielectric material to form a dielectric plug 6318 . In one embodiment, after filling the opening 6316 in the sacrificial material 6314 with dielectric material, the hard mask 6315 is removed to provide the dielectric plug 6318 having Upper surface 6320 above upper surface 6322, as depicted in FIG. 63D. The sacrificial material 6314 is removed leaving the dielectric plug 6318 remaining.

在一實施例中，用電介質材料來填充該犧牲材料6314中的開口6316包含用金屬氧化物材料來填充。在一個這樣的實施例中，該金屬氧化物材料為氧化鋁。在一實施例中，用電介質材料來填充該犧牲材料6314中的開口6316包含使用原子層沉積法(ALD)來填充。 In one embodiment, filling the opening 6316 in the sacrificial material 6314 with a dielectric material includes filling with a metal oxide material. In one such embodiment, the metal oxide material is alumina. In one embodiment, filling the opening 6316 in the sacrificial material 6314 with a dielectric material includes filling using atomic layer deposition (ALD).

參照圖63E，該線溝槽6306和該介層溝槽6308用導電材料6324來填充。在一實施例中，該導電材料6324被形成在該電介質插塞6318和該ILD層6302的上方且在該電介質插塞6318和該ILD層6302之上。 Referring to FIG. 63E , the line trench 6306 and the via trench 6308 are filled with a conductive material 6324 . In one embodiment, the conductive material 6324 is formed over and over the dielectric plug 6318 and the ILD layer 6302 .

參照圖63F，該導電材料6324和該電介質插塞6318被平坦化，以提供平坦化後的電介質插塞6318’，其使該線溝槽6306中之該導電材料6324的連續性中斷。 Referring to FIG. 63F , the conductive material 6324 and the dielectric plug 6318 are planarized to provide a planarized dielectric plug 6318' that interrupts the continuity of the conductive material 6324 in the line trench 6306.

再次參照圖63F，依據本發明的實施例，積體電路結構6350包含在基板之上的層間電介質(ILD)層6302。導電互連線6324係在該ILD層6302中的溝槽6306 中。該導電互連線6324具有第一部位6324A和第二部位6324B，該第一部位6324A係橫向鄰接於該第二部位6324B。電介質插塞6318’係在該導電互連線6324的該第一部位6324A與該第二部位6324B之間，並且橫向鄰接於該導電互連線6324的該第一部位6324A及該第二部位6324B。雖然未被描繪出，在一實施例中，該導電互連線6324包含導電阻障襯墊和導電填充材料，其代表性材料係如上所述。在一個這樣的實施例中，該導電填充材料包含鈷。 Referring again to FIG. 63F, an integrated circuit structure 6350 includes an interlayer dielectric (ILD) layer 6302 over a substrate, in accordance with an embodiment of the present invention. Conductive interconnects 6324 are tied to trenches 6306 in the ILD layer 6302 middle. The conductive interconnect 6324 has a first portion 6324A and a second portion 6324B, the first portion 6324A is laterally adjacent to the second portion 6324B. A dielectric plug 6318' is between the first portion 6324A and the second portion 6324B of the conductive interconnect 6324 and is laterally adjacent to the first portion 6324A and the second portion 6324B of the conductive interconnect 6324 . Although not depicted, in one embodiment, the conductive interconnect line 6324 includes a conductive barrier liner and a conductive fill material, representative materials of which are described above. In one such embodiment, the conductive fill material includes cobalt.

在一實施例中，該電介質插塞6318’包含金屬氧化物材料。在一個這樣的實施例中，該金屬氧化物材料為氧化鋁。在一實施例中，該電介質插塞6318’係與該導電互連線6324的該第一部位6324A及該第二部位6324B直接相接觸。 In one embodiment, the dielectric plug 6318' comprises a metal oxide material. In one such embodiment, the metal oxide material is alumina. In one embodiment, the dielectric plug 6318' is in direct contact with the first portion 6324A and the second portion 6324B of the conductive interconnect 6324.

在一實施例中，該電介質插塞6318’具有實質上與該導電互連線6324的底部6324C共平面的底部6318A。在一實施例中，第一導電介層6326係在該ILD層6302中的溝槽6308中。在一個這樣的實施例中，該第一導電介層6326係在該導電互連線6324之底部6324C的下方，並且該第一導電介層6326係電耦合於該導電互連線6324的該第一部位6324A。 In one embodiment, the dielectric plug 6318' has a bottom 6318A that is substantially coplanar with a bottom 6324C of the conductive interconnect line 6324. In one embodiment, the first conductive via layer 6326 is in the trench 6308 in the ILD layer 6302 . In one such embodiment, the first conductive via 6326 is beneath the bottom 6324C of the conductive interconnect 6324, and the first conductive via 6326 is electrically coupled to the first conductive interconnect 6324. One part 6324A.

在一實施例中，第二導電介層6328係在該ILD層6302中的第三溝槽6330中。該第二導電介層6328係在該導電互連線6324之底部6324C的下方，並且該第二導 電介層6328係電耦合於該導電互連線6324的該第二部位6324B。 In one embodiment, the second conductive via layer 6328 is in the third trench 6330 in the ILD layer 6302 . The second conductive via 6328 is under the bottom 6324C of the conductive interconnect 6324, and the second conductive A dielectric layer 6328 is electrically coupled to the second portion 6324B of the conductive interconnect line 6324 .

電介質插塞可以使用諸如化學氣相沉積製程的填充製程來予以形成。加工品可以保留在所製作的電介質插塞中。做為範例，圖64A繪示依據本發明的一實施例，具有接縫於其中之導電線插塞的剖面視圖。 The dielectric plug may be formed using a fill process such as a chemical vapor deposition process. Artifacts may remain in the fabricated dielectric plug. As an example, FIG. 64A shows a cross-sectional view of a plug having conductive threads seamed therein, according to one embodiment of the present invention.

參照圖64A，電介質插塞6418具有大約垂直的接縫6400，其和該導電互連線6324的該第一部位6324A與該導電互連線6324的該第二部位6324B大約等距離。 Referring to FIG. 64A , the dielectric plug 6418 has an approximately vertical seam 6400 approximately equidistant from the first portion 6324A of the conductive interconnect line 6324 and the second portion 6324B of the conductive interconnect line 6324 .

可領會到，具有和它們被收容於其中之ILD材料的組成不同之組成的電介質插塞可以僅被包含在選擇金屬化層上，諸如在下金屬化層中。做為範例，圖64B繪示依據本發明的一實施例，包含導電線插塞在下金屬線位置處之金屬化層堆疊的剖面視圖。 It can be appreciated that dielectric plugs having a different composition than the ILD material in which they are housed may be included only on selective metallization layers, such as in lower metallization layers. As an example, FIG. 64B shows a cross-sectional view of a metallization layer stack including conductive line plugs at lower metal line locations in accordance with one embodiment of the present invention.

參照圖64B，積體電路結構6450包含第一複數條導電互連線6456，該第一複數條導電互連線6456係在基板6452上方的第一層間電介質(ILD)層6454中，而且藉由在基板6452上方的第一層間電介質(ILD)層6454而被間隔分開。該第一複數條導電互連線6456之個別的一些具有被一或更多個電介質插塞6458所中斷的連續性。在一實施例中，該一或更多個電介質插塞6458包含與該ILD層6452之材料不同的材料。第二複數條導電互連線6466係在該第一ILD層6454上方的第二ILD層6464中，而且藉由在該第一ILD層6454上方的第二ILD層6464而被間隔分開。在一 實施例中，該第二複數條導電互連線6466之個別的一些具有被該第二ILD層6464中的一或更多個部位6468所中斷的連續性。可領會到，如同所描述的，其他金屬化層可以被包含在該積體電路結構6450中。 Referring to FIG. 64B, an integrated circuit structure 6450 includes a first plurality of conductive interconnect lines 6456 in a first interlayer dielectric (ILD) layer 6454 above a substrate 6452 and by are spaced apart by a first interlayer dielectric (ILD) layer 6454 over a substrate 6452 . Individual ones of the first plurality of conductive interconnect lines 6456 have continuity interrupted by one or more dielectric plugs 6458 . In one embodiment, the one or more dielectric plugs 6458 comprise a different material than that of the ILD layer 6452 . A second plurality of conductive interconnect lines 6466 are in a second ILD layer 6464 above the first ILD layer 6454 and are spaced apart by the second ILD layer 6464 above the first ILD layer 6454 . In a In an embodiment, individual ones of the second plurality of conductive interconnect lines 6466 have continuity interrupted by one or more locations 6468 in the second ILD layer 6464 . It can be appreciated that other metallization layers may be included in the integrated circuit structure 6450 as described.

在一個實施例中，該一或更多個電介質插塞6458包含金屬氧化物材料。在一個這樣的實施例中，該金屬氧化物材料為氧化鋁。在一個實施例中，該第一ILD層6454和該第二ILD層6464(且因此，該第二ILD層6464中的該一或更多個部位6468)包含摻雜碳的氧化矽材料。 In one embodiment, the one or more dielectric plugs 6458 include a metal oxide material. In one such embodiment, the metal oxide material is alumina. In one embodiment, the first ILD layer 6454 and the second ILD layer 6464 (and thus, the one or more locations 6468 in the second ILD layer 6464) comprise a carbon-doped silicon oxide material.

在一個實施例中，該第一複數條導電互連線6456之個別的一些包含第一導電阻障襯墊6456A和第一導電填充材料6456B。該第二複數條導電互連線6466之個別的一些包含第二導電阻障襯墊6466A和第二導電填充材料6466B。在一個這樣的實施例中，該第一導電填充材料6456B的組成和該第二導電填充材料6466B的組成不同。在一特別這樣的實施例中，該第一導電填充材料6456B包含鈷，而該第二導電填充材料6466B包含銅。 In one embodiment, individual ones of the first plurality of conductive interconnect lines 6456 include a first conductive barrier liner 6456A and a first conductive fill material 6456B. Individual ones of the second plurality of conductive interconnect lines 6466 include a second conductive barrier liner 6466A and a second conductive fill material 6466B. In one such embodiment, the composition of the first conductive fill material 6456B is different from the composition of the second conductive fill material 6466B. In one particular such embodiment, the first conductive fill material 6456B includes cobalt and the second conductive fill material 6466B includes copper.

在一個實施例中，該第一複數條導電互連線6456具有第一間距(P1，如同類似層6470中所示)。該第二複數條導電互連線6466具有第二間距(P2，如同類似層6480中所示)。該第二間距(P2)大於該第一間距(P1)。在一個實施例中，該第一複數條導電互連線6456之個別的一些具有第一寬度(W1，如同類似層6470中所示)。該第二複數條導電互連線6466之個別的一些具有第二寬度(W2，如同 類似層6480中所示)。該第二寬度(W2)大於該第一寬度(W1)。 In one embodiment, the first plurality of conductive interconnect lines 6456 has a first pitch (P1, as shown in similar layer 6470). The second plurality of conductive interconnect lines 6466 has a second pitch (P2, as shown in similar layer 6480). The second pitch (P2) is greater than the first pitch (P1). In one embodiment, individual ones of the first plurality of conductive interconnect lines 6456 have a first width (W1, as shown in similar layer 6470). Individual ones of the second plurality of conductive interconnection lines 6466 have a second width (W2, as similar to that shown in layer 6480). The second width (W2) is greater than the first width (W1).

可領會到，上面相關於後段(BEOL)結構及處理所述的該等層和材料可以被形成在下面的半導體基板或結構上以及在下面的半導體基板或結構上方，諸如積體電路之下面的裝置層。在一實施例中，下面的半導體基板代表被用來製造積體電路的一般工件物件。該半導體基板常常包含晶圓或一塊矽或者另一半導體材料。適合的半導體基板包含但不限於單晶矽、多晶矽和絕緣層上覆矽(SOI)、以及由其他半導體材料所形成之類似的基板，諸如包含鍺、碳、或III-V族材料的基板。視製造階段而定，該半導體基板常常包含電晶體、積體電路、等等。該基板也可包含半導體材料、金屬、電介質、摻雜劑、以及一般在半導體基板中發現到的其他材料。此外，所描述的該等結構可以被製作在下面的下層互連層上。 It will be appreciated that the layers and materials described above with respect to back-end-of-line (BEOL) structures and processing may be formed on and over underlying semiconductor substrates or structures, such as underlying integrated circuits. device layer. In one embodiment, the underlying semiconductor substrate represents a typical workpiece object used to fabricate integrated circuits. The semiconductor substrate often comprises a wafer or a piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, monocrystalline silicon, polycrystalline silicon, and silicon-on-insulator (SOI), and similar substrates formed from other semiconductor materials, such as those containing germanium, carbon, or III-V materials. Depending on the stage of fabrication, the semiconductor substrate often includes transistors, integrated circuits, and the like. The substrate may also contain semiconductor materials, metals, dielectrics, dopants, and other materials typically found in semiconductor substrates. Additionally, the structures described can be fabricated on underlying underlying interconnect layers.

雖然針對選擇操作而詳細地說明製作BEOL金屬化層之金屬化層或金屬化層的部分之先前的方法，可領會到用於製作之額外或中間的操作可包含標準的微電子製作製程，諸如光刻、蝕刻、薄膜沉積、平坦化(諸如，化學機械拋光(CMP))、擴散、度量衡學、犧牲層的使用、蝕刻停止層的使用、平坦化停止層的使用、或者和微電子組件製作任何其他相關的動作。而且，可領會到針對先前的製程流程所說明的製程操作可以用替換的順序來實行，並非每一個操作都必須被實施或額外的製程操作可以被實 施，或者兩者皆有。 While previous methods of fabricating metallization layers or portions of metallization layers for BEOL metallization layers have been described in detail for select operations, it can be appreciated that additional or intermediate operations for fabrication may include standard microelectronic fabrication processes such as Photolithography, etching, thin film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, use of sacrificial layers, use of etch stop layers, use of planarization stop layers, or microelectronic component fabrication any other related actions. Furthermore, it can be appreciated that the process operations described for the preceding process flows may be performed in alternate orders, not that every operation must be performed or that additional process operations may be performed. give, or both.

在一實施例中，如同本說明書全文所使用者，層間電介質(ILD)材料係由電介質或絕緣材料的層所組成或者包含電介質或絕緣材料的層。適合之電介質材料的範例包含但不限於矽的氧化物(例如，二氧化矽(SiO2))、摻雜之矽的氧化物、氟化之矽的氧化物、摻雜碳之矽的氧化物、本技藝中所已知之各種的低k電介質材料、及其組合。該層間電介質材料可以藉由下列技術來予以形成的，諸如，例如化學氣相沉積(CVD)、物理氣相沉積(PVD)、或藉由其他沉積方法。 In one embodiment, as used throughout this specification, an interlayer dielectric (ILD) material consists of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (eg, silicon dioxide (SiO 2 )), oxides of doped silicon, oxides of fluorinated silicon, oxides of carbon-doped silicon , various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

在一實施例中，如同也在本說明書全文所使用者，金屬線或互連線材料(以及介層材料)係由一或更多個金屬或其他導電結構所組成。一般的範例為銅線及結構的使用，其可以或可以不包含介於銅與周圍的ILD材料之間的阻障層。如同本文中所使用者，該術語金屬包含合金、堆疊、以及多種金屬的其他組合。例如，該等金屬互連線可包含不同金屬或合金的阻障層(例如，包含Ta,TaN,Ti或TiN之一或多者的層)、堆疊、等等。因此，該等互連線可為單一材料層、或者可由幾個層來予以形成，其包含導電襯墊層及填充層。任何適合的沉積製程，諸如電鍍、化學氣相沉積或物理氣相沉積，可以被用來形成互連線。在一實施例中，該等互連線係由導電材料所組成，諸如但不限於，Cu,Al,Ti,Zr,Hf,V,Ru,Co,Ni,Pd,Pt,W,Ag,Au或其合金。該等互連線在此技藝中有時也被稱為跡線、 配線、線路、金屬、或者僅僅就是互連。 In one embodiment, as also used throughout this specification, metal line or interconnect material (and via material) is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures, which may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of metals. For example, the metal interconnects may comprise barrier layers (eg, layers comprising one or more of Ta, TaN, Ti, or TiN), stacks, etc. of different metals or alloys. Thus, the interconnects may be a single layer of material, or may be formed of several layers, including conductive pad layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form the interconnect lines. In one embodiment, the interconnections are made of conductive materials such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or its alloys. These interconnect lines are also sometimes referred to in the art as traces, traces, Wiring, wiring, metal, or just interconnects.

在一實施例中，如同也在本說明書全文所使用者，硬遮罩材料係由與該層間電介質材料不同的電介質材料所組成。在一個實施例中，不同的硬遮罩材料可以被使用在不同的區域中，以便將不同的生長或蝕刻選擇性提供給彼此以及給下面的電介質和金屬層。在有些實施例中，硬遮罩層包含矽的氮化物層(例如，氮化矽層)或矽的氧化物層，或者兩者皆有，或其組合。其他適合的材料可包含以碳為基礎的材料。在另一實施例中，硬遮罩材料包含金屬物種。例如，硬遮罩或其他上覆材料可包含鈦或其他金屬的氮化物層(例如，氮化鈦)。可能較少量的其他材料(諸如，氧)可以被包含在這些層的一或多者中。或者，視特別的施行而可以使用本技藝中所已知之其他的硬遮罩層。該等硬遮罩層可以藉由CVD,PVD或者藉由其他的沉積方法來予以形成。 In one embodiment, as also used throughout this specification, the hard mask material is composed of a different dielectric material than the ILD material. In one embodiment, different hard mask materials may be used in different regions to provide different growth or etch selectivities to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer includes a silicon nitride layer (eg, a silicon nitride layer) or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, the hard mask material includes metal species. For example, a hard mask or other overlying material may include a nitride layer of titanium or other metal (eg, titanium nitride). Other materials, such as oxygen, may be included in one or more of these layers, possibly in lesser amounts. Alternatively, other hard mask layers known in the art may be used depending on the particular implementation. The hard mask layers can be formed by CVD, PVD or by other deposition methods.

在一實施例中，如同也在本說明書全文所使用者，光刻操作係使用193nm浸沒式光刻法(193i)、極紫外線(EUV)光刻法或電子束直寫式(EBDW)光刻法等等來予以實施。正型(positive tone)或負型(negative tone)光阻可以被使用。在一個實施例中，光刻遮罩為由形貌遮罩(topographic masking)部分、抗反射塗覆(anti-reflective coating(ARC))層、以及光阻層所組成的三層遮罩。在一特別這樣的實施例中，該形貌遮罩部分為碳硬遮罩(CHM)層，且該抗反射塗覆層為矽ARC層。 In one embodiment, as also used throughout this specification, the lithography operation uses 193nm immersion lithography (193i), extreme ultraviolet (EUV) lithography, or electron beam direct writing (EBDW) lithography law etc. to be implemented. Either positive tone or negative tone photoresist can be used. In one embodiment, the photolithographic mask is a three-layer mask consisting of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In one particular such embodiment, the topography mask portion is a carbon hard mask (CHM) layer and the antireflective coating layer is a silicon ARC layer.

在另一態樣中，本文中所述的一或更多個實施例係有關具有內部節點跨接線(jumper)的記憶體位元單元(bit cell)。特別的實施例可包含在先進的自對準製程技術中施行記憶體位元單元之有佈局效率(layout-efficient)的技術。實施例可以有關10奈米或更小的技術節點。實施例可以提供藉由利用在作用閘極之上的接觸(COAG)或積極的(aggressive)金屬1(M1)間距縮放或者上述兩者來發展在相同的著陸區(footprint)內具有改進性能之記憶體位元單元的能力。實施例可包含或有關使得在相對於先前的技術節點相同或更小的著陸區中具有更高性能的位元單元成為可能的位元單元佈局。 In another aspect, one or more embodiments described herein relate to memory bit cells having internal node jumpers. Particular embodiments may include implementing layout-efficient techniques for memory bit cells in advanced self-aligned process techniques. Embodiments may pertain to 10 nanometer or smaller technology nodes. Embodiments may provide for the development of devices with improved performance within the same footprint by utilizing contact over active gate (COAG) or aggressive metal 1 (M1) pitch scaling, or both. The capacity of memory bit cells. Embodiments may include or relate to bitcell layouts that enable higher performance bitcells in the same or smaller footprint relative to previous technology nodes.

依據本發明的實施例，更高的金屬層(金屬1或M1)跨接線被施行來連接內部節點，而不是使用傳統的閘極-溝槽接觸-閘極接觸(poly-tcn-polycon)連接。在一實施例中，在作用閘極之上的接觸(COAG)整合方案與金屬跨接線相結合來連接內部節點減輕或完全消除生長更高性能的位元單元之著陸區的需求。亦即，改進的電晶體比值(transistor ratio)可以被達成。在一實施例中，此種方法致使積極的縮放能夠針對10奈米(10nm)技術節點提供每一電晶體之改善的成本。內部節點M1跨接線可以被施行於10nm技術中的SRAM,RF和雙埠(Dual Port)位元單元中來提供非常緊密的佈局。 In accordance with an embodiment of the present invention, higher metal level (Metal 1 or M1) jumpers are implemented to connect internal nodes instead of using conventional gate-trenches-gate-contact (poly-tcn-polycon) connections . In one embodiment, a contact-on-active-gate (COAG) integration scheme combined with metal jumpers to connect internal nodes alleviates or completely eliminates the need to grow landing regions for higher performance bitcells. That is, an improved transistor ratio can be achieved. In one embodiment, such an approach enables aggressive scaling to provide improved cost per transistor for the 10 nanometer (10 nm) technology node. Internal node M1 jumpers can be implemented in SRAM, RF and Dual Port bit cells in 10nm technology to provide very tight placement.

做為比較範例，圖65繪示記憶單元(memory cell)之單元佈局(cell layout)的第一視圖。 As a comparative example, FIG. 65 shows a first view of a cell layout of a memory cell.

參照圖65，代表性14奈米(14nm)佈局6500包含位元單元6502。該位元單元6502包含閘極或多晶線6504和金屬1(M1)線6506。在所示的範例中，該多晶線6504具有1x間距，且該M1線6506具有1x間距。在一特別實施例中，該多晶線6504具有70nm間距，且該M1線6506具有70nm間距。 Referring to FIG. 65 , a representative 14 nanometer (14 nm) layout 6500 includes a bitcell 6502 . The bitcell 6502 includes a gate or poly line 6504 and a metal 1 (M1) line 6506 . In the example shown, the poly lines 6504 have a 1x pitch and the M1 lines 6506 have a 1x pitch. In a particular embodiment, the polylines 6504 have a pitch of 70nm and the M1 lines 6506 have a pitch of 70nm.

對比於圖65，圖66繪示依據本發明的一實施例，針對具有內部節點跨接線之記憶單元之單元佈局的第一視圖。 In contrast to FIG. 65, FIG. 66 shows a first view of a cell layout for a memory cell with internal node jumpers in accordance with an embodiment of the present invention.

參照圖66，代表性10奈米(10nm)佈局6600包含位元單元6602。該位元單元6602包含閘極或多晶線6604和金屬1(M1)線6606。在所示的範例中，該多晶線6604具有1x間距，且該M1線6606具有0.67x間距。結果為重疊的線6605，其包含直接在多晶線之上的M1線。在一特別實施例中，該多晶線6604具有54nm間距，且該M1線6606具有36nm間距。 Referring to FIG. 66 , a representative 10 nanometer (10 nm) layout 6600 includes a bitcell 6602 . The bitcell 6602 includes a gate or poly line 6604 and a metal 1 (M1) line 6606 . In the example shown, the poly lines 6604 have a 1x pitch and the M1 lines 6606 have a 0.67x pitch. The result is an overlapping line 6605, which includes the M1 line directly above the poly line. In a particular embodiment, the polylines 6604 have a pitch of 54nm and the M1 lines 6606 have a pitch of 36nm.

相較於佈局6500，在佈局6600中，該M1間距小於閘極間距，每第三條線騰出一條額外的線(6605)(例如，對於每兩條多晶線而言，有三條M1線)。該”騰出的”M1線在本文中被稱為內部節點跨接線。該內部節點跨接線可以被使用於閘極到閘極(多晶到多晶)互連或者使用於溝槽接觸到溝槽接觸互連。在一實施例中，接觸到多晶係經由在作用閘極之上的接觸(COAG)配置來予以達成，其致能內部節點跨接線的製作。 Compared to layout 6500, in layout 6600, the M1 pitch is smaller than the gate pitch, freeing up an extra line (6605) for every third line (e.g., for every two poly lines, there are three M1 lines ). This "free" M1 line is referred to herein as an internal node jumper. The internal node jumpers may be used for gate-to-gate (poly-to-poly) interconnects or for trench-contact-to-trench contact interconnections. In one embodiment, access to poly is achieved via a contact over active gate (COAG) configuration, which enables the fabrication of internal node jumpers.

更普遍地參照圖66，在一實施例中，積體電路結構包含在基板上的記憶體位元單元6602。該記憶體位元單元6602包含沿著該基板之第二方向2平行的第一及第二閘極線6604。該第一及第二閘極線6604具有沿著該基板之第一方向(1)的第一間距，該第一方向(1)垂直於該第二方向(2)。第一、第二及第三互連線6606係在該第一及第二閘極線6604之上。該第一、第二及第三互連線6606係沿著該基板之第二方向(2)而平行。該第一、第二及第三互連線6606具有沿著該第一方向的第二間距，其中，該第二間距小於該第一間距。在一個實施例中，該第一、第二及第三互連線6606的其中一者為用於該記憶體位元單元6602的內部節點跨接線。 Referring more generally to FIG. 66, in one embodiment, an integrated circuit structure includes memory bit cells 6602 on a substrate. The memory bit cell 6602 includes first and second gate lines 6604 parallel along the second direction 2 of the substrate. The first and second gate lines 6604 have a first pitch along a first direction (1) of the substrate, which is perpendicular to the second direction (2). First, second and third interconnect lines 6606 are above the first and second gate lines 6604 . The first, second and third interconnect lines 6606 are parallel along the second direction (2) of the substrate. The first, second and third interconnection lines 6606 have a second pitch along the first direction, wherein the second pitch is smaller than the first pitch. In one embodiment, one of the first, second and third interconnect lines 6606 is an internal node jumper for the memory bitcell 6602 .

如同在本發明全文可應用者，該等閘極線6604可以被稱為在形成光柵結構的軌道上。因此，本文中所述之光柵狀圖案可具有以恆定的間距間隔且具有恆定寬度的閘極線或互連線。該圖案可以藉由間距二分法或間距四分法，或者其他的間距分割法來予以製作。 As may be applicable throughout this disclosure, the gate lines 6604 may be referred to as being on tracks forming a grating structure. Accordingly, the grating-like pattern described herein may have gate or interconnect lines spaced at a constant pitch and having a constant width. The pattern can be made by pitch bisection or pitch quartering, or other pitch division methods.

做為比較範例，圖67繪示記憶單元之單元佈局6700的第二視圖。 As a comparative example, FIG. 67 shows a second view of a cell layout 6700 of a memory cell.

參照圖67，14nm位元單元6502係顯示具有N-擴散6702(例如，P型摻雜的作用區域，諸如，下面的基板之摻雜硼的擴散區域)和P-擴散6704(例如，N型摻雜的作用區域，諸如，下面的基板之摻雜磷或砷或兩者的擴散區域)，且為了清楚起見M1線被去除。位元單元102的佈局 6700包含閘極或多晶線6504、溝槽接觸6706、閘極接觸6708(特別針對14nm節點)以及接觸介層6710。 Referring to FIG. 67, a 14nm bitcell 6502 is shown having an N-diffusion 6702 (e.g., a P-type doped active region, such as a boron-doped diffusion region of the underlying substrate) and a P-diffusion 6704 (e.g., an N-type doped active regions, such as diffused regions of the underlying substrate doped with phosphorus or arsenic or both), and the M1 line is removed for clarity. Layout of bit cell 102 6700 includes gate or polyline 6504 , trench contact 6706 , gate contact 6708 (specifically for the 14nm node), and contact via 6710 .

對比於圖67，圖68繪示依據本發明的一實施例，針對具有內部節點跨接線之記憶單元之單元佈局6800的第二視圖。 In contrast to FIG. 67, FIG. 68 shows a second view of a cell layout 6800 for a memory cell with internal node jumpers in accordance with an embodiment of the present invention.

參照圖68，該10nm位元單元6602係顯示具有N-擴散6802(例如，P型摻雜的作用區域，諸如，下面的基板之摻雜硼的擴散區域)和P-擴散6804(例如，N型摻雜的作用區域，諸如，下面的基板之摻雜磷或砷或兩者的擴散區域)，且為了清楚起見M1線被去除。位元單元202的佈局6800包含閘極或多晶線6604、溝槽接觸6806、閘極介層6808(特別針對10nm節點)以及溝槽接觸介層6710。 Referring to FIG. 68, the 10 nm bit cell 6602 is shown with N-diffusion 6802 (e.g., P-type doped active region, such as a boron-doped diffusion region of the underlying substrate) and P-diffusion 6804 (e.g., N type doped active regions, such as diffused regions of the underlying substrate doped with phosphorus or arsenic or both), and the M1 line is removed for clarity. Layout 6800 of bitcell 202 includes gate or polyline 6604 , trench contact 6806 , gate via 6808 (specifically for the 10 nm node), and trench contact via 6710 .

比較佈局6700和6800，依據本發明的實施例中，在該14nm佈局中，該等內部節點僅藉由閘極接觸(GCN)來予以連接。由於多晶到GCN空間限制，提升性能的佈局不能夠被創建於相同的著陸區中。在該10nm佈局中，該設計允許使接觸(VCG)著陸在該閘極上以消除多晶接觸(poly contact)的需求。在一個實施例中，該配置致能使用M1來連接內部節點，其允許14nm著陸區內之額外的作用區域密度(例如，增加鰭部的數量)。在該10nm佈局中，當使用COAG架構時，擴散區域之間的間隙可以被做得更小，因為它們不受溝槽接觸到閘極接觸的間隙所限制。在一實施例中，圖67的佈局6700被稱為112(1個鰭部上拉(pull-up)、1個鰭部通過閘(pass gate)、2個鰭部下拉 (pull down))配置。對比之下，圖68的佈局6800被稱為122(1個鰭部上拉(pull-up)、2個鰭部通過閘(pass gate)、2個鰭部下拉(pull down))配置，在一特別實施例中，其係在和圖67的112佈局相同的著陸區之內。在一實施例中，相較於該112配置，該122配置提供改進的性能。 Comparing layouts 6700 and 6800, in an embodiment in accordance with the invention, in the 14nm layout, the internal nodes are only connected by gate contacts (GCN). Due to poly-to-GCN space constraints, performance-boosting layouts cannot be created in the same landing zone. In the 10nm layout, the design allows contact (VCG) to land on the gate to eliminate the need for poly contacts. In one embodiment, this configuration enables the use of M1 to connect internal nodes, which allows for additional active area density (eg, increased number of fins) within the 14nm landing zone. In this 10nm layout, when using the COAG architecture, the gaps between diffusion regions can be made smaller because they are not limited by the trench contact-to-gate contact gap. In one embodiment, the layout 6700 of FIG. 67 is referred to as 112 (1 fin pull-up, 1 fin pass gate, 2 fins pull-down (pull down)) configuration. In contrast, the layout 6800 of FIG. 68 is referred to as a 122 (1 fin pull-up, 2 fins pass gate, 2 fins pull down) configuration, in In a particular embodiment, it is within the same landing zone as layout 112 of FIG. 67 . In one embodiment, the 122 configuration provides improved performance over the 112 configuration.

做為比較範例，圖69繪示記憶單元之單元佈局6900的第三視圖。 As a comparative example, FIG. 69 shows a third view of a cell layout 6900 of a memory cell.

參照圖69，該14nm位元單元6502係顯示具有金屬0(M0)線6902，且為了清楚起見多晶線被去除。也顯示具有金屬1(M1)線6506、接觸介層6710、介層0結構6904。 Referring to Figure 69, the 14nm bitcell 6502 is shown with metal 0 (MO) lines 6902 and the poly lines removed for clarity. Also shown are metal 1 (M1) lines 6506, contact vias 6710, and via 0 structures 6904.

對比於圖69，圖70繪示依據本發明的一實施例，針對具有內部節點跨接線之記憶單元之單元佈局7000的第三視圖。 In contrast to FIG. 69 , FIG. 70 shows a third view of a cell layout 7000 for memory cells with internal node jumpers in accordance with an embodiment of the present invention.

參照圖70，該10nm位元單元6602係顯示具有金屬0(M0)線7002，且為了清楚起見多晶線被去除。也顯示具有金屬1(M1)線6606、閘極介層6808、溝槽接觸介層6810、以及介層0結構7004。比較圖69和圖70，依據本發明的一實施例，對於該14nm佈局而言，該等內部節點僅藉由閘極接觸(GCN)來予以連接，而對於該10nm佈局而言，該等內部節點的其中一者藉由使用M1跨接線來予以連接。 Referring to Figure 70, the 10 nm bit cell 6602 is shown with metal 0 (M0) lines 7002, and the poly lines removed for clarity. Also shown are metal 1 (M1 ) lines 6606 , gate vias 6808 , trench contact vias 6810 , and via0 structures 7004 . Comparing FIG. 69 and FIG. 70, according to an embodiment of the present invention, for the 14nm layout, the internal nodes are only connected by gate contacts (GCN), while for the 10nm layout, the internal nodes One of the nodes is connected by using an M1 jumper.

共同參照圖66,68和70，依據本發明的一實施例，積體電路結構包含在基板上的記憶體位元單元 6602。該記憶體位元單元6602包含沿著該基板之第一方向(1)平行的第一(頂部6802)、第二(頂部6804)、第三(底部6804)及第四(底部6802)作用區域。第一(左側6604)及第二(右側6604)閘極線係在該第一、第二、第三及第四作用區域6802/6804之上。該第一及第二閘極線6604係沿著該基板之第二方向(2)平行，該第二方向(2)垂直於該第一方向(1)。第一(遠的左側6606)、第二(近的左側6606)及第三(近的右側6606)互連線係在該第一及第二閘極線6604之上。該第一、第二及第三互連線6606係沿著該基板之第二方向(2)而平行。 Referring collectively to Figures 66, 68 and 70, according to one embodiment of the present invention, an integrated circuit structure includes memory bit cells on a substrate 6602. The memory bitcell 6602 includes first (top 6802), second (top 6804), third (bottom 6804) and fourth (bottom 6802) active regions parallel along a first direction (1) of the substrate. First (left side 6604) and second (right side 6604) gate lines are tied over the first, second, third and fourth active regions 6802/6804. The first and second gate lines 6604 are parallel along the second direction (2) of the substrate, and the second direction (2) is perpendicular to the first direction (1). Above the first and second gate lines 6604 are first (far left 6606 ), second (near left 6606 ) and third (near right 6606 ) interconnect lines. The first, second and third interconnect lines 6606 are parallel along the second direction (2) of the substrate.

在一實施例中，該第一(遠的左側6606)及第二(近的左側6606)互連線係在該第一及第二閘極線6604在該第一、第二、第三及第四作用區域6802/6804的其中一者或多者之上的位置處(例如，在所謂的”作用閘極”位置處)電連接至該第一及第二閘極線6604。在一個實施例中，該第一(遠的左側6606)及第二(近的左側6606)互連線藉由垂直地介於該第一及第二互連線6606與該第一及第二閘極線6604間之中介的(intervening)複數條互連線7004而被電連接至該第一及第二閘極線6604。該中介的複數條互連線7004係沿著該基板之第一方向(1)而平行。 In one embodiment, the first (far left 6606) and second (near left 6606) interconnect lines are tied to the first and second gate lines 6604 between the first, second, third and A location above one or more of the fourth active regions 6802/6804 (eg, at a so-called “active gate” location) is electrically connected to the first and second gate lines 6604 . In one embodiment, the first (far left 6606) and second (near left 6606) interconnect lines are connected vertically between the first and second interconnect lines 6606 and the first and second Intervening a plurality of interconnection lines 7004 between the gate lines 6604 is electrically connected to the first and second gate lines 6604 . The intervening plurality of interconnect lines 7004 are parallel along the first direction (1) of the substrate.

在一實施例中，該第三互連線(近的右側6606)使該記憶體位元單元6602的一對閘極電極電耦合在一起，該對閘極電極係包含在該第一及第二閘極線6604中。在另一實施例中，該第三互連線(近的右側6606)使該 記憶體位元單元6602的一對溝槽接觸電耦合在一起，該對溝槽接觸係包含在複數條溝槽接觸線6806中。在一實施例中，該第三互連線(近的右側6606)為內部節點跨接線。 In one embodiment, the third interconnect (near right side 6606) electrically couples together a pair of gate electrodes of the memory bit cell 6602, the pair of gate electrodes included in the first and second Gate line 6604. In another embodiment, the third interconnect (near right side 6606) makes the A pair of trench contacts of memory bitcell 6602 are electrically coupled together, the pair of trench contacts being included in plurality of trench contact lines 6806 . In one embodiment, the third interconnect line (near right side 6606) is an internal node jumper.

在一實施例中，該第一作用區域(頂部6802)為P型摻雜的作用區域(例如，用以提供用於NMOS裝置的N-擴散)，該第二作用區域(頂部6804)為N型摻雜的作用區域(例如，用以提供用於PMOS裝置的P-擴散)，該第三作用區域(底部6804)為N型摻雜的作用區域(例如，用以提供用於PMOS裝置的P-擴散)，以及該第四作用區域(底部6802)為N型摻雜的作用區域(例如，用以提供用於NMOS裝置的N-擴散)。在一實施例中，該第一、第二、第三及第四作用區域6802/6804係在矽鰭部中。在一實施例中，該記憶體位元單元6602包含基於單個矽鰭部的上拉(pull-up)電晶體、基於兩個矽鰭部的通過閘電晶體、以及基於兩個矽鰭部的下拉(pull-down)電晶體。 In one embodiment, the first active region (top 6802) is a P-type doped active region (eg, to provide N-diffusion for NMOS devices), and the second active region (top 6804) is N Type doped active region (for example, to provide P-diffusion for PMOS devices), the third active region (bottom 6804) is N-type doped active region (for example, to provide P-diffusion for PMOS devices) P-diffusion), and the fourth active region (bottom 6802) is an N-type doped active region (eg, to provide N-diffusion for NMOS devices). In one embodiment, the first, second, third and fourth active regions 6802/6804 are in silicon fins. In one embodiment, the memory bitcell 6602 includes a single silicon fin based pull-up transistor, a two silicon fin based pass gate transistor, and a two silicon fin based pull-up transistor. (pull-down) transistor.

在一實施例中，該第一及第二閘極線6604與沿著該基板之第二方向(2)平行之複數條溝槽接觸線6806的個別一些交替。該複數條溝槽接觸線6806包含該記憶體位元單元6602的溝槽接觸。該第一及第二閘極線6604包含該記憶體位元單元6602的閘極電極。 In one embodiment, the first and second gate lines 6604 alternate with individual ones of the plurality of trench contact lines 6806 parallel along the second direction (2) of the substrate. The plurality of trench contact lines 6806 comprise trench contacts of the memory bitcell 6602 . The first and second gate lines 6604 comprise the gate electrodes of the memory bit cell 6602 .

在一實施例中，該第一及第二閘極線6604具有沿著該第一方向(1)的第一間距。該第一、第二及第三互連線6606具有沿著該第二方向(2)的第二間距。在一個這樣的實施例中，該第二間距小於該第一間距。在一特定 這樣的實施例中，該第一間距係在50奈米到60奈米的範圍中，且該第二間距係在30奈米到40奈米的範圍中。在一特別這樣的實施例中，該第一間距為54奈米，且該第二間距為36奈米。 In one embodiment, the first and second gate lines 6604 have a first distance along the first direction (1). The first, second and third interconnection lines 6606 have a second pitch along the second direction (2). In one such embodiment, the second pitch is smaller than the first pitch. in a specific In such an embodiment, the first pitch is in the range of 50 nm to 60 nm and the second pitch is in the range of 30 nm to 40 nm. In one particular such embodiment, the first pitch is 54 nm and the second pitch is 36 nm.

本文中所述之實施例可以被施行來在與先前技術節點相對相同的位元單元著陸區內提供增加數量的鰭部，相對於先前世代的技術節點記憶體位元單元，其提高較小的技術節點記憶體位元單元的性能。做為範例，圖71A和71B分別繪示依據本發明的一實施例，針對6個電晶體(6T)靜態隨機存取記憶體(SRAM)的位元單元佈局和示意圖。 Embodiments described herein can be implemented to provide an increased number of fins within relatively the same bitcell land area as prior technology nodes, which improves small technology relative to previous generation technology node memory bitcells. The performance of the node's memory bits. As an example, FIGS. 71A and 71B respectively show the layout and schematic diagram of a bit cell for a 6-transistor (6T) SRAM according to an embodiment of the present invention.

參照圖71A和71B，位元單元佈局7102包含沿著該方向(2)平行的閘極線7104(其也可以被稱為多晶線)於其中。溝槽接觸線7106與該等閘極線7104交替。該等閘極線7104和溝槽接觸線7106係在於NMOS擴散區域7108(例如，P型摻雜的作用區域，諸如，下面的基板之摻雜硼的擴散區域)和PMOS擴散區域7110(例如，N型摻雜的作用區域，諸如，下面的基板之摻雜磷或砷或兩者的擴散區域)，它們係沿著方向(1)而平行。在一實施例中，該NMOS擴散區域7108兩者各自包含兩個矽鰭部。該PMOS擴散區域7110兩者各自包含一個矽鰭部。 Referring to Figures 71A and 71B, a bitcell layout 7102 includes gate lines 7104 (which may also be referred to as polylines) parallel therein along the direction (2). Trench contact lines 7106 alternate with the gate lines 7104 . The gate lines 7104 and trench contact lines 7106 are located between the NMOS diffusion region 7108 (e.g., the active region of P-type doping, such as the boron-doped diffusion region of the underlying substrate) and the PMOS diffusion region 7110 (e.g., Active regions of N-type doping, such as diffusion regions of the underlying substrate doped with phosphorus or arsenic or both), are parallel along direction (1). In one embodiment, the NMOS diffusion regions 7108 each include two silicon fins. The PMOS diffusion regions 7110 each include a silicon fin.

再次參照圖71A和71B，NMOS通過閘電晶體7112、NMOS下拉電晶體7114、和PMOS上拉電晶體7116係形成自該等閘極線7104和該NMOS擴散區域7108以及該 PMOS擴散區域7110。同樣所描述者為字線(WL)7118、內部節點7120及7126、位元線(bit line(BL))7122、位元線橫槓(bit line bar(BLB))7124、SRAM VCC 7128、以及VSS 7130。 Referring again to FIGS. 71A and 71B, NMOS pass gate transistor 7112, NMOS pull-down transistor 7114, and PMOS pull-up transistor 7116 are formed from the gate line 7104 and the NMOS diffusion region 7108 and the PMOS diffusion region 7110. Also depicted are word line (WL) 7118, internal nodes 7120 and 7126, bit line (BL) 7122, bit line bar (BLB) 7124, SRAM VCC 7128, and VSS 7130.

在一實施例中，到該位元單元佈局7102之該第一及第二閘極線7104的接觸被做成到該第一及第二閘極線7104的作用閘極位置。在一實施例中，該6T SRAM位元單元7104包含內部節點跨接線，諸如，如上所述。 In one embodiment, contacts to the first and second gate lines 7104 of the bitcell layout 7102 are made to the active gate locations of the first and second gate lines 7104 . In one embodiment, the 6T SRAM bitcell 7104 includes internal node jumpers, such as described above.

在一實施例中，本文中所述之佈局係與包含一致的鰭部修整遮罩之一致的插塞和遮罩圖案相容。佈局可以與非EUV製程相容。除此之外，佈局可以僅需要使用中間的鰭部修整遮罩。相較於其他佈局，本文中所述之實施例就面積而言可以致能密度的增加。實施例可以被施行來在先進的自對準製程技術中提供有佈局效率(layout-efficient)的記憶體施行。就晶粒面積或記憶體性能或者上述兩者而言可以實現優點。電路技術可以藉由此等佈局方法來予以唯一獨特地致能。 In one embodiment, the layout described herein is compatible with a uniform plug and mask pattern including a uniform fin trim mask. The layout can be compatible with non-EUV process. Besides that, the layout may only need to use the intermediate fin trim mask. Embodiments described herein may enable increased density in terms of area compared to other layouts. Embodiments may be implemented to provide layout-efficient memory implementations in advanced self-aligned process technologies. Advantages may be realized in terms of die area or memory performance or both. Circuit technology can be uniquely and uniquely enabled by such layout methods.

本文中所述之一或更多個實施例係有關當平行的互連線(例如，金屬1線)和閘極線係未對準時的多重版本庫元件處理(multi version library cell handling)。實施例可以有關10奈米或更小的技術節點。實施例可以包含或有關相對於先前技術節點在相同或更小的著陸區中做成有可能更高性能的單元佈局。在一實施例中，上覆閘極線的互連線被製作成相對於在下面的閘極線具有增加的密度。 此種實施例可以致能接腳命中(pin hit)的增加、增加的路由(routing)可能性、或增加對單元接腳的接達(access)。實施例可以被施行來提供大於6%的塊級(block level)密度。 One or more embodiments described herein relate to multi version library cell handling when parallel interconnect lines (eg, Metal 1 lines) and gate lines are misaligned. Embodiments may pertain to 10 nanometer or smaller technology nodes. Embodiments may include or relate to making potentially higher performance cell layouts in the same or smaller footprint relative to prior technology nodes. In one embodiment, the interconnect lines overlying the gate lines are fabricated with increased density relative to the underlying gate lines. Such embodiments may enable increased pin hits, increased routing possibilities, or increased access to cell pins. Embodiments may be implemented to provide block level densities greater than 6%.

為了提供上下文，閘極線和下一個平行層的互連(典型上被稱為金屬1，而金屬0層正交運行於金屬1與閘極線之間)。然而，在一實施例中，金屬1線的間距被做得不同於，例如，小於該等閘極線的間距。用於各個單元(cell)的兩個標準單元版本(例如，兩個不同的單元圖案)被做得可供來適應間距上的差異。所選擇的特別版本遵循遵守於塊級的規則放置。如果不適當地選擇，則髒對位(dirty registration(DR))可能會發生。依據本發明的一實施例，具有相對於在下面的閘極線之增加的間距密度的較高金屬層(例如，金屬1或M1)被施行。在一實施例中，此種方法致使積極的縮放能夠針對例如10奈米(10nm)技術節點提供每一電晶體之改善的成本。 To provide context, the interconnection of the gate line and the next parallel layer (typically referred to as Metal 1, with the Metal 0 layer running orthogonally between Metal 1 and the gate line). However, in one embodiment, the pitch of the metal 1 lines is made different, eg, smaller than the pitch of the gate lines. Two standard cell versions (eg, two different cell patterns) for each cell are made available to accommodate differences in pitch. Selected special editions are placed following the rules observed at the block level. If not chosen properly, dirty registration (DR) may occur. According to one embodiment of the invention, a higher metal layer (eg, Metal 1 or M1 ) is implemented with increased pitch density relative to the underlying gate lines. In one embodiment, such an approach enables aggressive scaling to provide improved cost per transistor for, for example, a 10 nanometer (10 nm) technology node.

圖72繪示依據本發明的一實施例，針對相同標準單元之兩個不同佈局的剖面視圖。 Figure 72 shows a cross-sectional view of two different layouts for the same standard cell, according to an embodiment of the present invention.

參照圖72的部位(a)，一組閘極線7204A覆蓋在基板7202A上面。一組金屬1(M1)互連部7206A覆蓋在該組閘極線7204A上面。該組金屬1(M1)互連部7206A具有比該組閘極線7204A更緊的間距。然而，最外側的金屬1(M1)互連部7206A具有與最外側的閘極線7204A的外部對準。為了命名目的，如同本發明全文所使用的，圖72之部位(a)的對準後的配置被稱為具有偶(even(E))對準。 Referring to part (a) of FIG. 72 , a group of gate lines 7204A covers the substrate 7202A. A set of metal 1 (M1) interconnects 7206A overlies the set of gate lines 7204A. The set of metal 1 (M1) interconnects 7206A has a tighter pitch than the set of gate lines 7204A. However, the outermost metal 1 (M1) interconnect 7206A has an outer alignment with the outermost gate line 7204A. For nomenclature purposes, as used throughout this disclosure, the aligned configuration of site (a) of Figure 72 is said to have an even (E) alignment.

對比於部位(a)，參照圖72的部位(b)，一組閘極線7204B覆蓋在基板7202B上面。一組金屬1(M1)互連部7206B覆蓋在該組閘極線7204B上面。該組金屬1(M1)互連部7206B具有比該組閘極線7204B更緊的間距。然而，最外側的金屬1(M1)互連部7206B具有與最外側的閘極線7204B的外部對準。為了命名目的，如同本發明全文所使用的，圖72之部位(b)的非對準後的配置被稱為具有奇(odd(O))對準。 Compared with part (a), referring to part (b) of FIG. 72 , a group of gate lines 7204B covers the substrate 7202B. A set of metal 1 (M1) interconnects 7206B overlies the set of gate lines 7204B. The set of metal 1 (M1) interconnects 7206B has a tighter pitch than the set of gate lines 7204B. However, the outermost metal 1 (M1) interconnect 7206B has an outer alignment with the outermost gate line 7204B. For nomenclature purposes, as used throughout this disclosure, the non-aligned configuration of site (b) of FIG. 72 is said to have odd (O) alignment.

圖73繪示依據本發明的一實施例，表示偶(even(E))或奇(odd(O))名稱之四個不同單元配置的平面視圖。 Figure 73 shows a plan view of four different cell configurations representing even (E) or odd (O) designations, in accordance with an embodiment of the present invention.

參照圖73的部位(a)，單元7300A具有閘極(多晶)線7302A和金屬1(M1)線7304A。該單元7300A被命名為EE單元，因為單元7300A的左側和單元7300A的右側具有對準的閘極線7302A和M1線7304A。對比之下，參照圖73的部位(b)，單元7300B具有閘極(多晶)線7302B和金屬1(M1)線7304B。該單元7300B被命名為OO單元，因為單元7300B的左側和單元7300B的右側具有非對準的閘極線7302B和M1線7304B。 Referring to section (a) of FIG. 73, cell 7300A has a gate (poly) line 7302A and a metal 1 (M1) line 7304A. This cell 7300A is named EE cell because the left side of cell 7300A and the right side of cell 7300A have aligned gate line 7302A and M1 line 7304A. In contrast, referring to location (b) of FIG. 73, cell 7300B has gate (poly) line 7302B and metal 1 (M1) line 7304B. This cell 7300B is named OO cell because the left side of cell 7300B and the right side of cell 7300B have non-aligned gate line 7302B and M1 line 7304B.

參照圖73的部位(c)，單元7300C具有閘極(多晶)線7302C和金屬1(M1)線7304C。該單元7300C被命名為EO單元，因為單元7300C的左側具有對準的閘極線7302C和M1線7304C，但是單元7300C的右側具有非對準的閘極線7302C和M1線7304C。對比之下，參照圖73的部位(d)， 單元7300D具有閘極(多晶)線7302D和金屬1(M1)線7304D。該單元7300D被命名為OE單元，因為單元7300D的左側具有非對準的閘極線7302D和M1線7304D，但是單元7300D的右側具有對準的閘極線7302D和M1線7304D。 Referring to section (c) of FIG. 73, cell 7300C has gate (poly) line 7302C and metal 1 (M1) line 7304C. This cell 7300C is named the EO cell because the left side of cell 7300C has aligned gate line 7302C and M1 line 7304C, but the right side of cell 7300C has non-aligned gate line 7302C and M1 line 7304C. In contrast, referring to part (d) of FIG. 73, Cell 7300D has a gate (poly) line 7302D and a metal 1 (M1) line 7304D. This cell 7300D is named OE cell because the left side of cell 7300D has non-aligned gate line 7302D and M1 line 7304D, but the right side of cell 7300D has aligned gate line 7302D and M1 line 7304D.

作為放置所選擇之第一或第二版本的標準單元類型的基礎，圖74繪示依據本發明的一實施例，塊級多晶柵格(poly grid)的平面視圖。參照圖74，塊級多晶柵格7400包含沿著方向7404平行運行的閘極線7402。所命名的單元佈局界線7406和7408被顯示運行於第二、正交的方向。該等閘極線7402在偶(even(E))與奇(odd(O))名稱之間交替。 FIG. 74 shows a plan view of a block-level poly grid, according to an embodiment of the present invention, as a basis for placing the selected first or second version of the standard cell type. Referring to FIG. 74 , a block-level polygrid 7400 includes gate lines 7402 running in parallel along a direction 7404 . Named cell layout boundaries 7406 and 7408 are shown running in a second, orthogonal direction. The gate lines 7402 alternate between even (E) and odd (O) designations.

圖75繪示依據本發明的一實施例，基於具有不同版本之標準單元的代表性可接受(通過(pass))佈局。參照圖75，佈局7500包含類型7300C/7300D的三個單元，如同在界線7406與7408之間從左到右按照順序放置：7300D，毗連第一個7300C且與間隔開第二個7300C。介於7300C與7300D之間的選擇係基於在對應的閘極線7402上之E或O名稱的對準。該佈局7500也包含類型7300A/7300B的單元，如同在界線7408下方從左到右按照順序放置：第一個7300A與第二個7300A間隔開。介於7300A與7300B之間的選擇係基於在對應的閘極線7402上之E或O名稱的對準。佈局7500從在該佈局7500中沒有髒對位(DR)發生的意義上為通過單元(pass cell)。將領會到，p是指功率，且a,b,c或o為代表性接腳(pin)。在該配置7500中，功率線p彼 此在界線7408上排成隊。 Figure 75 illustrates a representative acceptable (pass) layout based on standard cells having different versions, according to one embodiment of the present invention. Referring to FIG. 75 , layout 7500 includes three cells of type 7300C/7300D as placed in order from left to right between boundaries 7406 and 7408 : 7300D, adjacent to the first 7300C and spaced apart from the second 7300C. The selection between 7300C and 7300D is based on the alignment of the E or O designation on the corresponding gate line 7402 . The layout 7500 also contains cells of type 7300A/7300B, as placed in order from left to right below the boundary line 7408: the first 7300A is spaced from the second 7300A. The selection between 7300A and 7300B is based on the alignment of the E or O designation on the corresponding gate line 7402 . Layout 7500 is a pass cell in the sense that no dirty bit (DR) occurs in this layout 7500 . It will be appreciated that p refers to power and a, b, c or o are representative pins. In this configuration 7500, the power lines p to This is lined up on boundary 7408.

更普遍地參照圖75，依據本發明的一實施例，積體電路結構包含複數條閘極線7402，該複數條閘極線7402係沿著基板的第一方向而平行且沿著與該第一方向正交的第二方向具有間距。單元類型的第一版本7300C係在該複數條閘極線7402的第一部位之上。該單元類型的第一版本7300C包含沿著該第二方向具有第二間距的第一複數條互連線，該第二間距小於該第一間距。該單元類型的第二版本7300D係在該複數條閘極線7402沿著該第二方向橫向鄰接於該單元類型之第一版本7300C的第二部位之上。該單元類型的第二版本7300D包含沿著該第二方向具有該第二間距的第二複數條互連線。該單元類型的第二版本7300D在結構上與該單元類型之第一版本7300C不同。 Referring more generally to FIG. 75 , in accordance with an embodiment of the present invention, an integrated circuit structure includes a plurality of gate lines 7402 parallel to and along a first direction of the substrate along with the second gate line 7402 . A second direction orthogonal to one direction has a pitch. A first version 7300C of a cell type is over a first portion of the plurality of gate lines 7402 . The first version 7300C of the cell type includes a first plurality of interconnect lines with a second pitch along the second direction, the second pitch being smaller than the first pitch. The second version 7300D of the cell type is over a second portion of the plurality of gate lines 7402 laterally adjacent to the first version 7300C of the cell type along the second direction. The second version 7300D of the cell type includes a second plurality of interconnect lines with the second pitch along the second direction. The second version 7300D of the unit type is structurally different from the first version 7300C of the unit type.

在一實施例中，該單元類型的第一版本7300C之該第一複數條互連線的個別一些沿著該第一方向在該單元類型之第一版本7300C的第一邊緣處(例如，左側邊緣)與該複數條閘極線7402之個別的一些對準，但是並未沿著該第二方向在該單元類型之第一版本7300C的第二邊緣處(例如，右側邊緣)與該複數條閘極線7402之個別的一些對準。在一個這樣的實施例中，該單元類型的第一版本7300C為NAND單元的第一版本。該單元類型的第二版本7300D之該第二複數條互連線的個別一些沿著該第一方向在該單元類型之第二版本7300D的第一邊緣處(例如，左側邊緣)並未與該複數條閘極線7402之個別的一些對準， 但是的確沿著該第二方向在該單元類型之第二版本7300D的第二邊緣處(例如，右側邊緣)與該複數條閘極線7402之個別的一些對準。在一個這樣的實施例中，該單元類型的第二版本7300D為NAND單元的第二版本。 In one embodiment, individual ones of the first plurality of interconnect lines of the first version 7300C of the cell type are at a first edge (eg, left side) of the first version 7300C of the cell type along the first direction. edges) are aligned with individual ones of the plurality of gate lines 7402, but are not aligned with the plurality of gate lines 7402 along the second direction at the second edge (e.g., the right edge) of the first version 7300C of the cell type Individual ones of the gate lines 7402 are aligned. In one such embodiment, the first version 7300C of the cell type is a first version of a NAND cell. Individual ones of the second plurality of interconnect lines of the second version 7300D of the cell type are not connected to the first edge (eg, left edge) of the second version 7300D of the cell type along the first direction. Individual ones of the plurality of gate lines 7402 are aligned, But it does align with individual ones of the plurality of gate lines 7402 along the second direction at a second edge (eg, right edge) of the second version 7300D of the cell type. In one such embodiment, the second version 7300D of the cell type is a second version of a NAND cell.

在另一實施例中，該第一及第二版本係選自單元類型7300A和7300B。該單元類型的第一版本7300A之該第一複數條互連線的個別一些沿著該第一方向在該單元類型之第一版本7300A沿著第二方向的兩個邊緣處與該複數條閘極線7402之個別的一些對準。在一個實施例中，該單元類型的第一版本7300A為反相器單元的第一版本。可領會到該單元類型的第二版本7300B之該第二複數條互連線的個別一些沿著該第一方向在該單元類型之第二版本7300B沿著第二方向的兩個邊緣處並不與該複數條閘極線7402之個別的一些對準。在一個實施例中，該單元類型的第二版本7300B為反相器單元的第二版本。 In another embodiment, the first and second versions are selected from unit types 7300A and 7300B. Individual ones of the first plurality of interconnect lines of the first version 7300A of the cell type along the first direction are connected to the plurality of gates at both edges of the first version 7300A of the cell type along the second direction. Individual ones of polar lines 7402 are aligned. In one embodiment, the first version 7300A of the cell type is a first version of an inverter cell. It can be appreciated that individual ones of the second plurality of interconnect lines of the second version 7300B of the cell type are not located along the first direction at both edges of the second version 7300B of the cell type along the second direction. Aligned with individual ones of the plurality of gate lines 7402 . In one embodiment, the second version of the cell type 7300B is a second version of an inverter cell.

圖76繪示依據本發明的一實施例，基於具有不同版本之標準單元的代表性不可接受(未通過(fail))佈局。參照圖76，佈局7600包含類型7300C/7300D的三個單元，如同在界線7406與7408之間從左到右按照順序放置：7300D，毗連第一個7300C且與間隔開第二個7300C。介於7300C與7300D之間的適當選擇係基於在對應的閘極線7402上之E或O名稱的對準，如同所示者。然而，該佈局7600也包含類型7300A/7300B的單元，如同在界線7408下方從左到右按照順序放置：第一個7300A與第二個7300A 間隔開。佈局7600與佈局7500的不同在於第二個7300A將一條線向左移。雖然介於7300A與7300B之間的選擇應該基於在對應的閘極線7402上之E或O名稱的對準，但是並不是，而且第二個單元7300A並未對準，其中一個結果為未對準的功率(p)線。佈局7600為未通過的單元，因為髒對位(DR)發生在該佈局7600中。 Figure 76 illustrates a representative unacceptable (fail) layout based on standard cells having different versions, in accordance with one embodiment of the present invention. Referring to Figure 76, layout 7600 includes three cells of type 7300C/7300D, as placed in order from left to right between boundaries 7406 and 7408: 7300D, adjacent to the first 7300C and spaced apart from the second 7300C. The proper selection between 7300C and 7300D is based on the alignment of the E or O designation on the corresponding gate line 7402, as shown. However, this layout 7600 also contains units of type 7300A/7300B as placed in order from left to right below boundary 7408: first 7300A with second 7300A Spaced out. Layout 7600 differs from layout 7500 in that the second 7300A shifts a line to the left. While the selection between 7300A and 7300B should be based on the alignment of the E or O designation on the corresponding gate line 7402, it is not, and the second cell 7300A is misaligned, one of the results being misalignment standard power (p) line. Layout 7600 is a failing cell because a dirty bit (DR) occurs in this layout 7600 .

圖77繪示依據本發明的一實施例，基於具有不同版本之標準單元的另一代表性可接受(通過)佈局。參照圖77，佈局7700包含類型7300C/7300D的三個單元，如同在界線7406與7408之間從左到右按照順序放置：7300D，毗連第一個7300C且與間隔開第二個7300C。介於7300C與7300D之間的選擇係基於在對應的閘極線7402上之E或O名稱的對準。該佈局7700也包含類型7300A/7300B的單元，如同在界線7408下方從左到右按照順序放置：7300A與7300B間隔開。在佈局7600中，7300B的位置和7300A的位置相同，但是選擇到的單元7300B係基於在對應的閘極線7402上之O名稱的適當對準。佈局7700從在該佈局7700中沒有髒對位(DR)發生的意義上為通過單元。將領會到，p是指功率，且a,b,c或o為代表性接腳。在該配置7700中，功率線p彼此在界線7408上排成隊。 Figure 77 illustrates another representative acceptable (passed) placement based on standard cells with different versions, in accordance with an embodiment of the present invention. Referring to Figure 77, layout 7700 includes three cells of type 7300C/7300D, as placed in order from left to right between boundaries 7406 and 7408: 7300D, adjacent to the first 7300C and spaced apart from the second 7300C. The selection between 7300C and 7300D is based on the alignment of the E or O designation on the corresponding gate line 7402 . The layout 7700 also contains cells of type 7300A/7300B as placed in order from left to right below boundary 7408: 7300A spaced apart from 7300B. In layout 7600, the location of 7300B is the same as the location of 7300A, but the selected cell 7300B is based on the proper alignment of the O designation on the corresponding gate line 7402. Layout 7700 is a pass cell in the sense that no dirty bits (DR) occur in this layout 7700. It will be appreciated that p refers to power and a, b, c or o are representative pins. In this configuration 7700 , power lines p line up with each other on boundary 7408 .

共同參照圖76和77，製作積體電路結構之布局的方法包含將沿著第一方向平行之複數條閘極線7402交替的一些命名為沿著第二方向的偶(E)或奇(O)。然後，為在該複數條閘極線7402之上的一單元類型選擇位置。該方 法也包含在該單元類型的第一版本與該單元類型的第二版本之間視位置而選擇，該第二版本在結構上與該第一版本不同，其中，該單元類型之選擇到的版本針對沿著該第二方向在該單元類型之邊緣處的互連而具有偶(E)或奇(O)名稱，且其中，該單元類型之該等邊緣的名稱與該複數條閘極線在該等互連下方之個別一些的名稱相匹配。 Referring collectively to FIGS. 76 and 77, a method of making a layout of an integrated circuit structure includes designating alternate ones of a plurality of parallel gate lines 7402 along a first direction as even (E) or odd (O) along a second direction. ). Then, a location is selected for a cell type above the plurality of gate lines 7402 . the party The method also includes positionally selecting between a first version of the unit type and a second version of the unit type, the second version being structurally different from the first version, wherein the selected version of the unit type have even (E) or odd (O) designations for interconnects along the second direction at the edges of the cell type, and wherein the designations of the edges of the cell type are associated with the plurality of gate lines at The individual names below the interconnects match.

在另一態樣中，一或更多個實施例係有關包含在場效電晶體(FET)架構中之以鰭部為基礎的結構上之金屬電阻器的製作。在一實施例中，由於更快速的資料轉移率需要高速IOs，所以此等精密電阻器被施行為系統單晶片(SoC)技術的基本組件。此等電阻器由於具有低變異和接近零的溫度係數之特性而可以致能高速類比電路(諸如，CSI/SERDES)和縮放的IO架構的實現。在一個實施例中，本文中所述的電阻器為可調諧的電阻器。 In another aspect, one or more embodiments relate to the fabrication of metal resistors on fin-based structures included in field effect transistor (FET) architectures. In one embodiment, these precision resistors are implemented as basic components of system-on-chip (SoC) technology since faster data transfer rates require high-speed IOs. These resistors can enable the implementation of high speed analog circuits (such as CSI/SERDES) and scaled IO architectures due to their low variation and near zero temperature coefficient. In one embodiment, the resistors described herein are tunable resistors.

為了提供上下文，在目前製程技術中所使用的傳統電阻器典型上落在兩種類別的其中一者中：一般電阻器和精密電阻器。一般電阻器，諸如溝槽接觸電阻器，係成本中價位的(cost-neutral)但是可能會受苦於高變異，其係由於所利用之製作方法中固有的變異或該等電阻器之相關大的溫度係數，或者上述兩者皆有。精密電阻器可以緩解變異和溫度係數的問題，但是常常以需要較高的製程成本和增加的製作操作數量作為代價。目前正在證明在高k/金屬閘極製程技術中多晶矽精密電阻器的整合愈來愈困難。 To provide context, conventional resistors used in current process technologies typically fall into one of two categories: general resistors and precision resistors. Typical resistors, such as trench contact resistors, are cost-neutral but may suffer from high variation due to inherent variation in the fabrication method utilized or the relative largeness of such resistors temperature coefficient, or both. Precision resistors can alleviate the problems of variation and temperature coefficient, but often at the expense of requiring higher process costs and increased number of fabrication operations. Integration of polysilicon precision resistors in high-k/metal gate process technologies is proving increasingly difficult.

依據實施例，以鰭部為基礎的薄膜電阻器(TFRs)被說明。在一個實施例中，此等電阻器具有接近零的溫度係數。在一個實施例中，此等電阻器展現由於尺寸控制而減少的變異。依據本發明的一或更多個實施例，積體精密電阻器被製作於鰭式FET(fin-FET)電晶體架構。將領會到在高k/金屬閘極製程技術中所使用的傳統電阻器典型上為鎢溝槽接觸(TCN)、井電阻器、或多晶矽精密電阻器。由於所使用之製作製程的變異，此等電阻器不是增加製程成本或複雜性，就是受苦於高變異及不良的溫度係數。對比之下，在一實施例中，鰭式積體薄膜電阻器的製造致能成本中價位、良好的(接近零)溫度係數、以及低變異來替代已知方法。 According to an embodiment, fin-based thin film resistors (TFRs) are described. In one embodiment, the resistors have a near-zero temperature coefficient. In one embodiment, the resistors exhibit reduced variation due to dimensional control. According to one or more embodiments of the present invention, integrated precision resistors are fabricated in a fin-FET (fin-FET) transistor architecture. It will be appreciated that conventional resistors used in high-k/metal gate process technologies are typically tungsten trench contact (TCN), well resistors, or polysilicon precision resistors. Due to the variation in the fabrication process used, these resistors either add to process cost or complexity, or suffer from high variation and poor temperature coefficients. In contrast, in one embodiment, the fabrication of fin-based SIRTs enables mid-cost, good (near-zero) temperature coefficient, and low variation to replace known methods.

為了提供進一步上下文，目前最新技術的精密電阻器已經使用二維(2D)金屬薄膜或高度摻雜的多晶線來予以製作。此等電阻器傾向被離散化成固定值的模板(template)，且因此，難以達成更細粒度的電阻值。 To provide further context, state-of-the-art precision resistors have been fabricated using two-dimensional (2D) metal films or highly doped polycrystalline wires. These resistors tend to be discretized into templates of fixed values, and thus, it is difficult to achieve finer grained resistance values.

對付上面問題的一或多者，依據本發明的一或更多個實施例，使用鰭式骨幹之高密度精密電阻器(諸如，矽鰭式骨幹)的設計被說明於本文中。在一個實施例中，此種高密度精密電阻器的優點包含高密度可以藉由鰭部集積密度(fin packing density)來予以達成。除此之外，在一個實施例中，此種電阻器被整合在和作用電晶體同一層上，導致緊密電路的製作。矽鰭式骨幹的使用可允許高的集積密度以及提供控制電阻器之電阻的多重自由度 (degrees of freedom)。因此，在一特定實施例中，鰭式圖案化製程的靈活性起槓桿作用而提供寬廣範圍的電阻值，導致可調諧的精密電阻器製作。 Addressing one or more of the above issues, in accordance with one or more embodiments of the present invention, the design of high density precision resistors using fin backbones, such as silicon fin backbones, is described herein. In one embodiment, the advantages of such high density precision resistors include that high density can be achieved by fin packing density. Additionally, in one embodiment, such resistors are integrated on the same layer as the active transistors, resulting in the fabrication of compact circuits. The use of silicon fin backbones allows for high packing densities and provides multiple degrees of freedom in controlling the resistance of the resistors (degrees of freedom). Thus, in a particular embodiment, the flexibility of the fin patterning process is leveraged to provide a wide range of resistance values, resulting in tunable precision resistor fabrication.

做為以鰭部為基礎之精密電阻器的代表性幾何，圖78繪示依據本發明的一實施例，以鰭部為基礎之薄膜電阻器結構的局部切割平面視圖和對應的剖面視圖，其中，該剖面視圖係沿著局部切割平面視圖的a到a’軸線所取下的。 As a representative geometry of a fin-based precision resistor, FIG. 78 shows a partially cut plan view and corresponding cross-sectional view of a fin-based thin film resistor structure in accordance with an embodiment of the present invention, wherein , the sectional view is taken along the a to a' axis of the partial cut plan view.

參照圖78，積體電路結構7800包含突出穿過基板7804上方之溝槽隔離區域7814的半導體鰭部7802。在一個實施例中，該半導體鰭部7802從該基板7804突出並且與該基板7804係連續的，如同所描繪的。該半導體鰭部具有頂部表面7805、第一末端7806(因為在局部切割平面視圖中該鰭部被覆蓋住，所以在此視圖中被顯示為虛線)、第二末端7808(因為在局部切割平面視圖中該鰭部被覆蓋住，所以在此視圖中被顯示為虛線)、以及在該第一末端7806與該第二末端7808之間的一對側壁7807。將領會到，在此局部切割平面視圖中，該等側壁7807確實被層7812所覆蓋。 Referring to FIG. 78 , an integrated circuit structure 7800 includes a semiconductor fin 7802 protruding through a trench isolation region 7814 above a substrate 7804 . In one embodiment, the semiconductor fin 7802 protrudes from and is continuous with the substrate 7804, as depicted. The semiconductor fin has a top surface 7805, a first end 7806 (shown as a dashed line in this view because the fin is covered in the partial cut plan view), a second end 7808 (because in the partial cut plan view The fin is covered, so shown as dashed lines in this view), and a pair of sidewalls 7807 between the first end 7806 and the second end 7808 . It will be appreciated that the sidewalls 7807 are indeed covered by the layer 7812 in this partial cut plan view.

隔離層7812係與該半導體鰭部7802的該頂部表面7805、該第一末端7806、該第二末端7808、以及該對側壁7807共形。金屬電阻器層7810係與和該半導體鰭部7802的該頂部表面7805(金屬電阻器層部位7810A)、該第一末端7806(金屬電阻器層部位7810B)、該第二末端 7808(金屬電阻器層部位7810C)、以及該對側壁7807(金屬電阻器層部位7810D)共形的該隔離層7814共形。在一特別實施例中，該金屬電阻器層7810包含鄰接於該等側壁7807之有腳的特徵7810E，如同所描繪的。該隔離層7812使該金屬電阻器層7810與該半導體鰭部7802電隔離，且因而使該金屬電阻器層7810與該基板7804電隔離。 The isolation layer 7812 is conformal with the top surface 7805 , the first end 7806 , the second end 7808 , and the pair of sidewalls 7807 of the semiconductor fin 7802 . Metal resistor layer 7810 is associated with the top surface 7805 (metal resistor layer location 7810A) of the semiconductor fin 7802, the first end 7806 (metal resistor layer location 7810B), the second end 7808 (metal resistor layer site 7810C), and the isolation layer 7814 conforms to the pair of sidewalls 7807 (metal resistor layer site 7810D). In a particular embodiment, the metal resistor layer 7810 includes footed features 7810E adjacent the sidewalls 7807, as depicted. The isolation layer 7812 electrically isolates the metal resistor layer 7810 from the semiconductor fin 7802 , and thus electrically isolates the metal resistor layer 7810 from the substrate 7804 .

在一實施例中，該金屬電阻器層7810係由適合提供接近零之溫度係數的材料所組成，因為該金屬電阻器層部位7810之電阻在由其所製作之薄膜電阻器(TFR)的整個操作溫度範圍上並不明顯地改變。在一實施例中，該金屬電阻器層7810為氮化鈦(TiN)層。在另一實施例中，該金屬電阻器層7810為鎢(W)金屬層。將領會到，其他金屬也可以被使用於該金屬電阻器層7810來代替氮化鈦(TiN)或鎢(W)，或者與氮化鈦(TiN)或鎢(W)相組合。在一實施例中，該金屬電阻器層7810具有約在2至5奈米之範圍中的厚度。在一實施例中，該金屬電阻器層7810具有約在100至100,000歐姆/平方(ohms/square)之範圍中的電阻率。 In one embodiment, the metal resistor layer 7810 is composed of a material suitable for providing a near-zero temperature coefficient because the resistance of the metal resistor layer portion 7810 is the largest in the entire thin film resistor (TFR) fabricated therefrom. The operating temperature range does not change significantly. In one embodiment, the metal resistor layer 7810 is a titanium nitride (TiN) layer. In another embodiment, the metal resistor layer 7810 is a tungsten (W) metal layer. It will be appreciated that other metals may also be used for the metal resistor layer 7810 instead of or in combination with titanium nitride (TiN) or tungsten (W). In one embodiment, the metal resistor layer 7810 has a thickness approximately in the range of 2-5 nm. In one embodiment, the metal resistor layer 7810 has a resistivity approximately in the range of 100 to 100,000 ohms/square (ohms/square).

在一實施例中，陽極電極和陰極電極被電連接至該金屬電阻器層7810，其代表性實施例參考圖84而被更詳細地說明於下。在一個這樣的實施例中，該金屬電阻器層7810、該陽極電極、以及該陰極電極形成精密薄膜電阻器(TFR)被動裝置。在一實施例中，基於圖78之該結構7800的該TFR允許基於鰭部7802高度、鰭部7802寬度、金屬電阻器層7810厚度以及鰭部7802總長度之電阻的精準控 制。這些自由度可讓電路設計者能夠達成所選擇的電阻值。除此之外，因為電阻器圖案化係以鰭部為基礎的，所以按照電晶體密度的比例等級，高密度係可能的。 In one embodiment, the anode and cathode electrodes are electrically connected to the metal resistor layer 7810, a representative embodiment of which is described in more detail below with reference to FIG. 84 . In one such embodiment, the metal resistor layer 7810, the anode electrode, and the cathode electrode form a precision thin film resistor (TFR) passive device. In one embodiment, the TFR based on the structure 7800 of FIG. 78 allows precise control of resistance based on fin 7802 height, fin 7802 width, metal resistor layer 7810 thickness, and total fin 7802 length system. These degrees of freedom allow the circuit designer to achieve the chosen resistor value. In addition, since the resistor patterning is fin-based, high densities are possible on a scaled scale of transistor density.

在一實施例中，目前最新技術的finFET處理操作被用來提供適合來製作以鰭部為基礎之電阻器的鰭部。此種方法的優點可在於其高密度和接近於該作用電晶體，致能容易整合進電路中。而且下面之鰭部之幾何上的靈活性允許寬廣範圍的電阻值。在一代表性處理方案中，首先使用骨幹光刻和間隔層化(spacerization)法來圖案化鰭部。該鰭部然後用隔離氧化物來予以覆蓋，其被凹入以設定該電阻器的高度。絕緣氧化物然後被共形地沉積在該鰭部上，以使導電膜與該下面的基板(諸如，下面的矽基板)分開。金屬或高度摻雜的多晶矽膜然後被沉積在該鰭部上。該膜然後被間隔層化以創建該精密電阻器。 In one embodiment, state-of-the-art finFET processing operations are used to provide fins suitable for fabricating fin-based resistors. An advantage of this approach may be its high density and proximity to the active transistors, enabling easy integration into circuits. Also the geometrical flexibility of the underlying fins allows a wide range of resistance values. In a representative processing scheme, the fins are first patterned using backbone lithography and spacerization. The fin is then covered with isolation oxide, which is recessed to set the height of the resistor. An insulating oxide is then conformally deposited on the fins to separate the conductive film from the underlying substrate, such as the underlying silicon substrate. A metal or highly doped polysilicon film is then deposited on the fins. The film is then spacer layered to create the precision resistor.

在該代表性處理方案中，圖79至83繪示依據本發明的一實施例，代表製作以鰭部為基礎之薄膜電阻器結構的方法中之各種操作的平面視圖和對應的剖面視圖。 In this representative processing scheme, FIGS. 79-83 illustrate plan views and corresponding cross-sectional views representing various operations in a method of fabricating a fin-based thin film resistor structure in accordance with an embodiment of the present invention.

參照圖79，沿著該平面視圖的b到b’軸線所取下的平面視圖和對應的剖面視圖繪示在形成骨幹模板結構7902於半導體基板7801上之後的製程流程階段。側壁間隔層(spacer layer)7904然後被形成與該骨幹模板結構7902的側壁表面共形。在一實施例中，在該骨幹模板結構7902的圖案化之後，共形的氧化物材料被沉積而後被各向異性蝕刻(間隔層化)以提供該側壁間隔層7904。 Referring to FIG. 79 , the plan view and the corresponding cross-sectional view taken along the b to b' axis of the plan view show stages of the process flow after the backbone template structure 7902 is formed on the semiconductor substrate 7801 . A sidewall spacer layer 7904 is then formed to conform to the sidewall surfaces of the backbone formwork structure 7902 . In one embodiment, following patterning of the backbone template structure 7902 , a conformal oxide material is deposited and then anisotropically etched (spacerized) to provide the sidewall spacers 7904 .

參照圖80，平面視圖繪示在例如藉由光刻遮罩及曝光製程以使該側壁間隔層7904的區域7906曝光之後的製程流程階段。該側壁間隔層7904之包含在該區域7906的部位然後藉由蝕刻製程來予以去除。去除後的該等部位為將被使用於最終的鰭部界定的那些部位。 Referring to FIG. 80 , a plan view is shown at a stage of the process flow after exposing the region 7906 of the sidewall spacer 7904 , eg, by a photolithographic masking and exposure process. The portion of the sidewall spacer 7904 included in the region 7906 is then removed by an etching process. The removed locations are those that will be used in the final fin definition.

參照圖81，沿著該平面視圖的c到c’軸線所取下的平面視圖和對應的剖面視圖繪示在去除該側壁間隔層7904之包含在圖80之區域7906中的該等部位以形成鰭部圖案化遮罩(例如，氧化物鰭部圖案化遮罩)之後的製程流程階段。該骨幹模板結構7902然後被去除而且剩餘的圖案化遮罩被用作為蝕刻遮罩來圖案化該基板7801。在圖案化該基板7801而後去除該鰭部圖案化遮罩後，半導體鰭部7802就維持從現在已經被圖案化的半導體基板7804突出並且與現在已經被圖案化的半導體基板7804係連續的。該半導體鰭部7802具有頂部表面7805、第一末端7806、第二末端7808、以及在該第一末端與該第二末端之間的一對側壁7807，如同上面相關於圖78所述者。 Referring to FIG. 81 , the plan view taken along the c to c' axis of the plan view and the corresponding cross-sectional view are shown at the locations included in the region 7906 of FIG. 80 where the sidewall spacer 7904 is removed to form A process flow stage following a fin patterning mask (eg, an oxide fin patterning mask). The backbone template structure 7902 is then removed and the remaining patterning mask is used as an etch mask to pattern the substrate 7801 . After patterning the substrate 7801 and then removing the fin patterning mask, the semiconductor fins 7802 remain protruding from and continuous with the now patterned semiconductor substrate 7804 . The semiconductor fin 7802 has a top surface 7805, a first end 7806, a second end 7808, and a pair of sidewalls 7807 between the first end and the second end, as described above with respect to FIG. 78 .

參照圖82，沿著該平面視圖的d到d’軸線所取下的平面視圖和對應的剖面視圖繪示在形成溝槽隔離層7814之後的製程流程階段。在一實施例中，藉由沉積絕緣材料而後凹入來界定該鰭部高度(Hsi)以界定鰭部高度而形成該溝槽隔離層7814。 Referring to FIG. 82 , the plan view and the corresponding cross-sectional view taken along the d to d' axis of the plan view show a stage of the process flow after the trench isolation layer 7814 is formed. In one embodiment, the trench isolation layer 7814 is formed by depositing an insulating material and then recessing to define the fin height (Hsi).

參照圖83，沿著該平面視圖的e到e’軸線所取下的平面視圖和對應的剖面視圖繪示在形成隔離層7812 之後的製程流程階段。在一實施例中，藉由化學氣相沉積(CVD)製程來形成該隔離層7812。該隔離層7812係形成與該半導體鰭部7802的該頂部表面7805、該第一末端7806、該第二末端7808、以及該一對側壁7807共形。該金屬電阻器層7810然後被形成與和該半導體鰭部7802的該頂部表面、該第一末端、該第二末端、以及該對側壁共形的該隔離層7812共形。 Referring to FIG. 83 , a plan view and corresponding cross-sectional view taken along the e to e' axis of the plan view are shown during the formation of the isolation layer 7812. subsequent stages of the process flow. In one embodiment, the isolation layer 7812 is formed by a chemical vapor deposition (CVD) process. The isolation layer 7812 is formed conformally with the top surface 7805 , the first end 7806 , the second end 7808 , and the pair of sidewalls 7807 of the semiconductor fin 7802 . The metal resistor layer 7810 is then formed conformal to the isolation layer 7812 conformal to the top surface, the first end, the second end, and the pair of sidewalls of the semiconductor fin 7802 .

在一實施例中，該金屬電阻器層7810係使用毯覆(blanket)沉積及後續的各向異性蝕刻製程來予以形成。在一實施例中，該金屬電阻器層7810係使用原子層沉積法(ALD)來予以形成。在一實施例中，該金屬電阻器層7810係形成至在2至5奈米之範圍中的厚度。在一實施例中，該金屬電阻器層7810為或者包含氮化鈦(TiN)層或鎢(W)金屬層。在一實施例中，該金屬電阻器層7810被形成具有在100至100,000歐姆/平方(ohms/square)之範圍中的電阻率。 In one embodiment, the metal resistor layer 7810 is formed using blanket deposition followed by an anisotropic etch process. In one embodiment, the metal resistor layer 7810 is formed using atomic layer deposition (ALD). In one embodiment, the metal resistor layer 7810 is formed to a thickness in the range of 2 to 5 nm. In one embodiment, the metal resistor layer 7810 is or includes a titanium nitride (TiN) layer or a tungsten (W) metal layer. In one embodiment, the metal resistor layer 7810 is formed to have a resistivity in the range of 100 to 100,000 ohms/square (ohms/square).

在後續的處理操作中，一對陽極或陰極電極可以被形成而且電連接至圖83之結構的該金屬電阻器層7810。做為範例，圖84繪示依據本發明的一實施例，以鰭部為基礎之薄膜電阻器結構的平面視圖，該結構具有針對陽極或陰極電極接觸的各種代表性位置。 In subsequent processing operations, a pair of anode or cathode electrodes may be formed and electrically connected to the metal resistor layer 7810 of the structure of FIG. 83 . As an example, FIG. 84 shows a plan view of a fin-based thin film resistor structure with various representative locations for anode or cathode electrode contacts in accordance with an embodiment of the present invention.

參照圖84，第一陽極或陰極電極，例如8400,8402,8404,8406,8408,8410的其中一者，被電連接至該金屬電阻器層7810。第二陽極或陰極電極，例如 8400,8402,8404,8406,8408,8410的另一者，被電連接至該金屬電阻器層7810。在一實施例中，該金屬電阻器層7810、該陽極電極、和該陰極電極形成精密薄膜電阻器(TFR)被動裝置。該精密TFR被動裝置可被調諧，因為電阻可以基於該第一陽極或陰極電極與該第二陽極或陰極電極之間的距離來做選擇。該等選項的提供係藉由形成各種的真正電極，例如8400,8402,8404,8406,8408,8410以及其他的可能性，而後基於互連電路來選擇該真正的配對。或者，單個陽極或陰極配對可以被形成，連同其各自的位置被選擇於該TFR裝置的製作期間。在任一情況下，在一實施例中，該陽極或陰極電極之其中一個的位置係在該鰭部7802的末端處(例如，位置8400或8402)，在該鰭部7802的轉角處(例如，位置8404,8406或8408)，或者在轉角間之轉變的中心(例如，位置8410)。 Referring to FIG. 84 , a first anode or cathode electrode, such as one of 8400 , 8402 , 8404 , 8406 , 8408 , 8410 , is electrically connected to the metal resistor layer 7810 . A second anode or cathode electrode, such as The other of 8400, 8402, 8404, 8406, 8408, 8410 is electrically connected to the metal resistor layer 7810. In one embodiment, the metal resistor layer 7810, the anode electrode, and the cathode electrode form a precision thin film resistor (TFR) passive device. The precision TFR passive device can be tuned because resistance can be selected based on the distance between the first anode or cathode electrode and the second anode or cathode electrode. These options are provided by forming various real electrodes such as 8400, 8402, 8404, 8406, 8408, 8410 and other possibilities, and then selecting the real pair based on the interconnection circuit. Alternatively, a single anode or cathode pair can be formed, with their respective positions selected during fabrication of the TFR device. In either case, in one embodiment, the location of one of the anode or cathode electrodes is at the end of the fin 7802 (e.g., location 8400 or 8402), at the corner of the fin 7802 (e.g., position 8404, 8406, or 8408), or the center of transition between corners (eg, position 8410).

在一代表性實施例中，該第一陽極或陰極電極被電連接至該金屬電阻器層7810，接近該半導體鰭部7802的第一末端7806，例如在位置8400處。該第二陽極或陰極電極被電連接至該金屬電阻器層7810，接近該半導體鰭部7802的第二末端7808，例如在位置8402處。 In a representative embodiment, the first anode or cathode electrode is electrically connected to the metal resistor layer 7810 proximate to the first end 7806 of the semiconductor fin 7802 , such as at location 8400 . The second anode or cathode electrode is electrically connected to the metal resistor layer 7810 near the second end 7808 of the semiconductor fin 7802 , for example at location 8402 .

在另一代表性實施例中，該第一陽極或陰極電極被電連接至該金屬電阻器層7810，接近該半導體鰭部7802的第一末端7806，例如在位置8400處。該第二陽極或陰極電極被電連接至該金屬電阻器層7810，遠離該半導體鰭部7802的第二末端7808，例如在位置8410,8408,8406或 8404處。 In another representative embodiment, the first anode or cathode electrode is electrically connected to the metal resistor layer 7810 proximate to the first end 7806 of the semiconductor fin 7802 , such as at location 8400 . The second anode or cathode electrode is electrically connected to the metal resistor layer 7810, away from the second end 7808 of the semiconductor fin 7802, for example at locations 8410, 8408, 8406 or 8404 places.

在另一代表性實施例中，該第一陽極或陰極電極被電連接至該金屬電阻器層7810，遠離該半導體鰭部7802的第一末端7806，例如在位置8404或8406處。該第二陽極或陰極電極被電連接至該金屬電阻器層7810，遠離該半導體鰭部7802的第二末端7808，例如在位置8410或8408處。 In another representative embodiment, the first anode or cathode electrode is electrically connected to the metal resistor layer 7810 away from the first end 7806 of the semiconductor fin 7802 , such as at location 8404 or 8406 . The second anode or cathode electrode is electrically connected to the metal resistor layer 7810 away from the second end 7808 of the semiconductor fin 7802 , for example at location 8410 or 8408 .

更明確地說，依據本發明的一或更多個實施例，以鰭部為基礎之電晶體架構的形貌特徵被用作為用來製作嵌入式電阻器的基礎。在一個實施例中，精密電阻器被製作在鰭部結構上。在一特定實施例中，此種方法致能諸如精密電阻器之被動組件的非常高密度整合。 More specifically, topographical features of fin-based transistor architectures are used as the basis for fabricating embedded resistors in accordance with one or more embodiments of the present invention. In one embodiment, precision resistors are fabricated on the fin structure. In a particular embodiment, this approach enables very high density integration of passive components such as precision resistors.

將領會到，各種的鰭部幾何形狀係適合用來製作以鰭部為基礎的精密電阻器。圖85A至85D繪示依據本發明的一實施例，用以製作以鰭部為基礎之精密電阻器的各種鰭部幾何形狀的平面視圖。 It will be appreciated that various fin geometries are suitable for making fin-based precision resistors. 85A-85D illustrate plan views of various fin geometries used to fabricate fin-based precision resistors in accordance with one embodiment of the present invention.

在一實施例中，參照圖85A至85C，半導體鰭部7802為非線形的(non-linear)半導體鰭部。在一個實施例中，該半導體鰭部7802突出穿過基板上方的溝槽隔離區域。金屬電阻器層7810係與和該非線形半導體鰭部7802共形的隔離層(未顯示出)共形。在一個實施例中，二或更多個陽極或陰極電極8400被電連接至該金屬電阻器層7810，藉由圖85A至85C中的虛線圓形來顯示代表性的選項位置。 In one embodiment, referring to FIGS. 85A to 85C , the semiconductor fins 7802 are non-linear semiconductor fins. In one embodiment, the semiconductor fin 7802 protrudes through the trench isolation region above the substrate. Metal resistor layer 7810 is conformal to an isolation layer (not shown) conformal to the nonlinear semiconductor fin 7802 . In one embodiment, two or more anode or cathode electrodes 8400 are electrically connected to the metal resistor layer 7810, representative option locations are shown by dashed circles in FIGS. 85A-85C.

非線形的鰭部幾何形狀包含一或更多個轉角，諸如但不限於單個轉角(例如，L形)、兩個轉角(例如，U形)、四個轉角(例如，S形)、或六個轉角(例如，圖78的結構)。在一實施例中，該非線形的鰭部幾何形狀為開放(open)結構幾何形狀。在另一實施例中，該非線形的鰭部幾何形狀為封閉(closed)結構幾何形狀。 Non-linear fin geometries include one or more corners, such as, but not limited to, a single corner (e.g., L-shape), two corners (e.g., U-shape), four corners (e.g., S-shape), or six Corners (for example, the structure of Figure 78). In one embodiment, the nonlinear fin geometry is an open structure geometry. In another embodiment, the non-linear fin geometry is a closed structure geometry.

做為用於非線形鰭部幾何形狀之開放結構幾何形狀的代表性實施例，圖85A繪示具有一個轉角來提供開放結構L形幾何形狀的非線形鰭部。圖85B繪示具有兩個轉角來提供開放結構U形幾何形狀的非線形鰭部。在開放結構的情況中，該非線形的半導體鰭部7802具有頂部表面、第一末端、第二末端、以及在該第一末端與該第二末端之間的一對側壁。金屬電阻器層7810係與和該頂部表面、該第一末端、該第二末端、以及在該第一末端與該第二末端之間的該一對側壁共形的隔離層(未顯示出)共形。 As a representative example of an open structure geometry for a nonlinear fin geometry, FIG. 85A shows a nonlinear fin with one corner to provide an open structure L-shaped geometry. Figure 85B depicts a non-linear fin with two corners to provide an open structure U-shape geometry. In the case of an open structure, the nonlinear semiconductor fin 7802 has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. Metal resistor layer 7810 is an isolation layer (not shown) conformal to the top surface, the first end, the second end, and the pair of sidewalls between the first end and the second end conformal.

在一特定實施例中，再次參照圖85A和85B，第一陽極或陰極電極被電連接至該金屬電阻器層7810，接近開放結構非線形半導體鰭部的第一末端，以及第二陽極或陰極電極被電連接至該金屬電阻器層7810，接近該開放結構非線形半導體鰭部的第二末端。在另一特定實施例中，第一陽極或陰極電極被電連接至該金屬電阻器層7810，接近開放結構非線形半導體鰭部的第一末端，以及第二陽極或陰極電極被電連接至該金屬電阻器層7810，遠離該開放結構非線形半導體鰭部的第二末端。在另一特 定實施例中，第一陽極或陰極電極被電連接至該金屬電阻器層7810，遠離開放結構非線形半導體鰭部的第一末端，以及第二陽極或陰極電極被電連接至該金屬電阻器層7810，遠離該開放結構非線形半導體鰭部的第二末端。 In a particular embodiment, referring again to FIGS. 85A and 85B , a first anode or cathode electrode is electrically connected to the metal resistor layer 7810, proximate to the first end of the open structure nonlinear semiconductor fin, and a second anode or cathode electrode. is electrically connected to the metal resistor layer 7810 near the second end of the open structure nonlinear semiconductor fin. In another particular embodiment, a first anode or cathode electrode is electrically connected to the metal resistor layer 7810, proximate to the first end of the open structure nonlinear semiconductor fin, and a second anode or cathode electrode is electrically connected to the metal resistor layer 7810. The resistor layer 7810 is remote from the second end of the open structure nonlinear semiconductor fin. in another special In certain embodiments, a first anode or cathode electrode is electrically connected to the metal resistor layer 7810 away from the first end of the open structure nonlinear semiconductor fin, and a second anode or cathode electrode is electrically connected to the metal resistor layer 7810, away from the second end of the open structure nonlinear semiconductor fin.

做為用於非線形鰭部幾何形狀之封閉結構幾何形狀的代表性實施例，圖85C繪示具有四個轉角來提供封閉結構方形或矩形幾何形狀的非線形鰭部。在封閉結構的情況中，該非線形的半導體鰭部7802具有頂部表面和一對側壁，特別是內側壁及外側壁。然而，該封閉結構並不包含露出的第一和第二末端。金屬電阻器層7810係與和該鰭部7802之該頂部表面、該內側壁、及該外側壁共形的隔離層(未顯示出)共形。 As a representative example of a closed structure geometry for a nonlinear fin geometry, FIG. 85C shows a nonlinear fin with four corners to provide a closed structure square or rectangular geometry. In the case of a closed structure, the nonlinear semiconductor fin 7802 has a top surface and a pair of sidewalls, particularly an inner sidewall and an outer sidewall. However, the closed structure does not include exposed first and second ends. Metal resistor layer 7810 is conformal to an isolation layer (not shown) that conforms to the top surface, the inner sidewall, and the outer sidewall of the fin 7802 .

在另一實施例中，參照圖85D，半導體鰭部7802線形的(linear)半導體鰭部。在一個實施例中，該半導體鰭部7802突出穿過基板上方的溝槽隔離區域。金屬電阻器層7810係與和該線形半導體鰭部7802共形的隔離層(未顯示出)共形。在一個實施例中，二或更多個陽極或陰極電極8400被電連接至該金屬電阻器層7810，藉由圖85D中的虛線圓形來顯示代表性的選項位置。 In another embodiment, referring to FIG. 85D , the semiconductor fin 7802 is a linear semiconductor fin. In one embodiment, the semiconductor fin 7802 protrudes through the trench isolation region above the substrate. The metal resistor layer 7810 is conformal to an isolation layer (not shown) that is conformal to the linear semiconductor fins 7802 . In one embodiment, two or more anode or cathode electrodes 8400 are electrically connected to the metal resistor layer 7810, representative option locations are shown by dashed circles in FIG. 85D.

在另一態樣中，依據本發明的一實施例，用於使用光刻之高解析度相位偏移遮罩(PSM)製作的新結構被說明。此種PSM遮罩可以被用於一般(直接)的光刻或互補的光刻。 In another aspect, according to an embodiment of the present invention, a new structure for fabrication of high-resolution phase-shift masks (PSMs) using lithography is described. Such a PSM mask can be used for general (direct) lithography or complementary lithography.

微影術(photolithography)一般被使用在製造 過程中來形成圖案於光阻層中。在微影製程中，光阻層被沉積在將要被蝕刻的底層(underlying layer)之上。典型上，該底層為半導體層，但是也可以是任何類型的硬遮罩或電介質材料。該光阻層然後經由光罩或標線片(reticle)而被選擇性地暴露於輻射。該光阻然後被顯影，而且在「正」光阻的情況中，該光阻之暴露於輻射的那些部位被去除。 Photolithography is generally used in the manufacture of process to form a pattern in the photoresist layer. In lithography, a photoresist layer is deposited over the underlying layer to be etched. Typically, this bottom layer is a semiconductor layer, but could be any type of hard mask or dielectric material. The photoresist layer is then selectively exposed to radiation via a photomask or reticle. The photoresist is then developed and, in the case of a "positive" photoresist, those parts of the photoresist exposed to radiation are removed.

被用來圖案化該晶圓的該光罩或標線片被放置在微影曝光工具內，一般被稱為「步進器(stepper)」或「掃描器(scanner)」。在步進器或掃描器機器中，該光罩或標線片被放置在輻射源與晶圓之間。該光罩或標線片典型上係由放置在石英基板上之圖案化後的鉻(吸收層)所形成。輻射實質上未衰減地通過該光罩或標線片之石英部位在沒有鉻的位置處。相反地，輻射並未通過該遮罩的鉻部位。因為入射在該遮罩上的輻射不是全部通過該等石英部位就是全部被該等鉻部位所阻擋，所以此類型的遮罩被稱為二元(binary)遮罩。在輻射選擇性地通過該遮罩之後，該遮罩上的圖案藉由將該遮罩的影像經由一系列透鏡而投影在該光阻中而被轉移到該光阻內。 The reticle or reticle used to pattern the wafer is placed within a lithography exposure tool, commonly referred to as a "stepper" or "scanner". In a stepper or scanner machine, the reticle or reticle is placed between the radiation source and the wafer. The reticle or reticle is typically formed of patterned chromium (absorber layer) placed on a quartz substrate. Radiation passes substantially unattenuated through the quartz portion of the reticle or reticle at locations free of chromium. Instead, radiation does not pass through the chrome portion of the mask. Because the radiation incident on the mask either all passes through the quartz parts or is completely blocked by the chrome parts, this type of mask is called a binary mask. After radiation selectively passes through the mask, the pattern on the mask is transferred into the photoresist by projecting an image of the mask into the photoresist through a series of lenses.

隨著該光罩或標線片上的特徵變得愈來愈靠近在一起，繞射效應開始生效於當該遮罩上之特徵的尺寸可以和光源的波長比較時。繞射使投影在該光阻上的影像模糊，其導致不良的解析度。 As the features on the reticle or reticle get closer together, diffraction effects come into play when the dimensions of the features on the mask are comparable to the wavelength of the light source. Diffraction blurs the image projected on the photoresist, which leads to poor resolution.

防止繞射圖案與該光阻之所想要的圖案化互 相干擾的一個方法在於用被稱為移位器(shifter)的透明層來覆蓋該光罩或標線片中之選擇到的開口。該移位器使該等暴露光(exposing ray)組的其中一組偏移而與另一相鄰組不同相位，其使繞射對干涉圖案無效。此方法被稱為相位偏移遮罩(PSM)法。儘管如此，在遮罩生產中減少缺陷和增加產能之替換的遮罩製作方案為光刻製程發展的重要焦點區域(focus area)。 prevent the diffraction pattern from interacting with the desired patterning of the photoresist One method of phase interference is to cover selected openings in the reticle or reticle with a transparent layer called a shifter. The shifter shifts one of the sets of exposing rays out of phase with the other adjacent set, which renders diffraction ineffective for interference patterns. This method is known as the Phase Shift Mask (PSM) method. Nonetheless, alternative mask fabrication solutions that reduce defects and increase throughput in mask production are an important focus area for lithography process development.

本發明的一或更多個實施例係有關製作光刻遮罩和結果光刻遮罩的方法。為了提供上下文，符合由半導體工業所提出之積極的裝置縮放目標的必要條件停駐於以高保真度來圖案化更小特徵之光刻遮罩的能力。然而，使愈來愈小之特徵圖案化的方法呈現針對遮罩製作之難以克服的挑戰。在這方面，目前被廣泛使用的光刻遮罩有賴相位偏移遮罩(PSM)技術的概念來圖案化特徵。然而，減少缺陷且同時產生愈來愈小的圖案仍然是遮罩製作上最大障礙的其中之一。相位偏移遮罩的使用可能會有幾個缺點。第一，相位偏移遮罩的設計是相當複雜的程序，其需要顯著的資源。第二，因為相位偏移遮罩的本質，難以檢查瑕疵是否出現在該相位偏移遮罩中。相位偏移遮罩的此等缺陷出自被利用來製造該遮罩本身之目前的整合方案。有些相位偏移遮罩採用繁重且有點容易發生瑕疵的方法來圖案化厚的吸光材料，而後將該圖案轉移到有助於相位偏移的二次圖層(secondary layer)。為了使問題複雜化，該吸收層(absorber layer)遭受電漿蝕刻兩次，因此電漿蝕刻 之不想要的結果，諸如負載效應、反應離子蝕刻延遲、充電及可重現的效應，導致遮罩製造上的缺陷。 One or more embodiments of the invention relate to methods of making lithographic masks and resulting lithographic masks. To provide context, a requirement to meet the aggressive device scaling goals set forth by the semiconductor industry resides in the ability to pattern a lithographic mask of smaller features with high fidelity. However, methods of patterning smaller and smaller features present formidable challenges for mask fabrication. In this regard, currently widely used lithographic masks rely on the concept of phase shift mask (PSM) technology to pattern features. However, reducing defects while producing smaller and smaller patterns remains one of the biggest hurdles in mask fabrication. The use of phase shift masks can have several disadvantages. First, the design of phase shift masks is a rather complex procedure that requires significant resources. Second, because of the nature of the phase shift mask, it is difficult to check whether artifacts are present in the phase shift mask. These deficiencies of phase shift masks arise from the current integration schemes exploited to manufacture the masks themselves. Some phase shift masks take the heavy and somewhat flaw-prone approach of patterning thick light-absorbing material and then transferring that pattern to a secondary layer that facilitates phase shifting. To complicate matters, the absorber layer is subjected to the plasma etch twice, so the plasma etch Unwanted effects such as loading effects, RIE delays, charging, and reproducible effects lead to defects in mask fabrication.

為了致能裝置縮放，製作無缺陷光刻遮罩之材料和新穎整合技術的創新仍然是高度優先的。因此，為了利用相位偏移遮罩技術的全部好處，可能需要新穎的整合方案，其使用(i)以高保真度來圖案化移位器層，以及(ii)圖案化吸收層僅一次而且在製作的最後階段期間。除此之外，此種製作方案也可提供其他的優點，諸如，材料選擇上的彈性、減少在製作期間的基板損壞、以及增加遮罩製作的生產量。 To enable device scaling, innovations in materials for making defect-free photolithographic masks and novel integration techniques remain high priorities. Therefore, to exploit the full benefits of the phase-shift mask technique, novel integration schemes using (i) patterning the shifter layer with high fidelity, and (ii) patterning the absorber layer only once and at During the final stages of production. Besides, this fabrication scheme may also provide other advantages, such as flexibility in material selection, reduced substrate damage during fabrication, and increased throughput of mask fabrication.

圖86繪示依據本發明的一實施例，光刻遮罩結構8601的剖面視圖。該光刻遮罩8601包含晶粒中(in-die)區域8610、框架區域8620及晶粒框架介面區域8630。該晶粒框架介面區域8630包含該晶粒中區域8610和該框架區域8620的鄰接部位。該晶粒中區域8610包含直接設置在基板8600上之圖案化後的移位器層8606，其中，該圖案化後的移位器層8606具有特徵，而該等特徵具有側壁。該框架區域8620包圍該晶粒中區域8610並且包含直接設置在該基板8600上之圖案化後的吸收層8602。 Figure 86 shows a cross-sectional view of a photolithographic mask structure 8601 in accordance with one embodiment of the present invention. The lithography mask 8601 includes an in-die region 8610 , a frame region 8620 and a die-frame interface region 8630 . The die frame interface region 8630 includes the adjoining portion of the die in-die region 8610 and the frame region 8620 . The in-die region 8610 includes a patterned shifter layer 8606 disposed directly on the substrate 8600, wherein the patterned shifter layer 8606 has features, and the features have sidewalls. The frame region 8620 surrounds the in-die region 8610 and includes a patterned absorber layer 8602 disposed directly on the substrate 8600 .

該晶粒框架介面區域8630，係設置在該基板8600上，包含雙層堆疊8640。該雙層堆疊8640包含上層8604，係設置在該下層圖案化後的移位器層8606上。該雙層堆疊8640的上層8604係由和該框架區域8620之圖案化後的吸收層8602相同的材料所組成。 The die frame interface region 8630 is disposed on the substrate 8600 and includes a double layer stack 8640 . The bilayer stack 8640 includes an upper layer 8604 disposed on the lower patterned shifter layer 8606 . The upper layer 8604 of the bilayer stack 8640 is composed of the same material as the patterned absorber layer 8602 of the frame region 8620 .

在一實施例中，該圖案化後的移位器層8606之該等特徵的最上表面8608具有和晶粒框架介面區域之特徵的最上表面8612之高度不同以及和該框架區域之該等特徵的最上表面8614之高度不同的高度。此外，在一實施例中，該晶粒框架介面區域之該等特徵的最上表面8612的高度與該框架區域之該等特徵的最上表面8614的高度不同。該相位偏移層8606之典型厚度的範圍係從40nm到100nm，而該吸收層之典型厚度的範圍係從30nm到100nm。在一實施例中，該框架區域8620中之該吸收層8602的厚度為50nm，設置在該晶粒框架介面區域8630中之該移位器層8606上之該吸收層8604的組合厚度為120nm，而且該框架區域中之該吸收層的厚度為70nm。在一實施例中，該基板8600為石英，該圖案化後的移位器層包含諸如但不限於矽化鉬、鉬-氮氧化矽、鉬-氮化矽、氮氧化矽、或氮化矽的材料，而且該吸收材料為鉻。 In one embodiment, the uppermost surface 8608 of the features of the patterned shifter layer 8606 has a different height than the uppermost surface 8612 of the features of the die frame interface region and the height of the features of the frame region. The height of the uppermost surface 8614 varies in height. Furthermore, in one embodiment, the height of the uppermost surface 8612 of the features of the die frame interface region is different from the height of the uppermost surface 8614 of the features of the frame region. Typical thicknesses of the phase shift layer 8606 range from 40 nm to 100 nm, while typical thicknesses of the absorber layer range from 30 nm to 100 nm. In one embodiment, the thickness of the absorbing layer 8602 in the frame region 8620 is 50 nm, the combined thickness of the absorbing layer 8604 disposed on the shifter layer 8606 in the die frame interface region 8630 is 120 nm, And the thickness of the absorbing layer in the frame region is 70 nm. In one embodiment, the substrate 8600 is quartz, and the patterned shifter layer includes materials such as but not limited to molybdenum silicide, molybdenum-silicon oxynitride, molybdenum-silicon nitride, silicon oxynitride, or silicon nitride. material, and the absorbent material is chromium.

本文中所揭示的實施例可以被用來製造各種不同類型的積體電路或微電子裝置。此等積體電路的範例包含但不限於處理器、晶片組組件、圖形處理器、數位信號處理器、微控制器等等。在其他實施例中，半導體記憶體可以被製造。況且，該等積體電路或其他的微電子裝置可以被使用於此技藝中所已知之各式各樣的電子裝置。例如，在電腦系統中(例如，桌上型、膝上型、伺服器)、蜂巢式電話、個人電子等等。積體電路可以和系統中的匯流排及其他組件相耦接。例如，處理器可以藉由一或多條匯 流排而被耦接至記憶體、晶片組等等。處理器、記憶體、和晶片組之各者可以使用本文中所揭示的方法來予以製造。 Embodiments disclosed herein may be used to fabricate various types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memory can be fabricated. Moreover, such integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art. For example, in computer systems (eg, desktops, laptops, servers), cellular phones, personal electronics, and the like. Integrated circuits can be coupled to bus bars and other components in the system. For example, a processor may, via one or more sinks The bus is coupled to memory, chipsets, and so on. Each of the processor, memory, and chipsets can be fabricated using the methods disclosed herein.

圖87繪示依據本發明的一個實作的計算裝置8700。該計算裝置8700收容板8702。該板8702可包含許多組件，其包含但不限於處理器7904和至少一個通訊晶片8706。該處理器8704被實體及電耦接至該板8702。在一些實作中，該至少一個通訊晶片8706也被實體及電耦接至該板8702。在其他實作中，該通訊晶片8706為該處理器8704的部分。 Figure 87 illustrates a computing device 8700 according to one implementation of the present invention. The computing device 8700 houses a board 8702 . The board 8702 may contain a number of components including, but not limited to, a processor 7904 and at least one communication chip 8706 . The processor 8704 is physically and electrically coupled to the board 8702. In some implementations, the at least one communication chip 8706 is also physically and electrically coupled to the board 8702 . In other implementations, the communication chip 8706 is part of the processor 8704 .

視其應用而定，計算裝置8700可包含可以或可以不被實體及電耦接至該板8702的其他組件。這些其他組件包含但不限於揮發性記憶體(例如，DRAM)、非揮發性記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位信號處理器、加密處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音頻編碼解碼器、視頻編碼解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速計、陀螺儀、揚聲器、相機、以及大量儲存裝置(諸如，硬碟機、光碟(CD)、數位多功能碟片(DVD)、等等)。 Depending on its application, computing device 8700 may include other components that may or may not be physically and electrically coupled to the board 8702 . These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, encryption processors, chipsets, antennas , displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and Mass storage devices (such as hard drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

該通訊晶片8706致能將資料從該計算裝置8700轉移出或者將資料轉移至該計算裝置8700的無線通訊。術語「無線」及其衍生詞可以被用來描述電路、裝置、系統、方法、技術、通訊通道、等等，其可以經由調 變後之電磁輻射透過非固態媒體來通訊資料。該術語並不隱含相關裝置並不含有任何導線，雖然在有些實施例中它們可能不是不含有任何導線。該通訊晶片8706可以施行許多無線標準或協定的任何一者，其包含但不限於Wi-Fi(IEEE 802.11系列)、Wi-MAX(IEEE 802.16系列)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其衍生物、以及被稱為3G,4G,5G及未來世代之任何其他的無線協定。該計算裝置8700可以包含複數個通訊晶片8706。例如，第一通訊晶片8706可以專用於較短程的無線通訊(諸如，Wi-Fi和藍芽)，且第二通訊晶片8706可以專用於較長程的無線通訊(諸如，GPS,EDGE,GPRS,CDMA,WiMAX,LTE,Ev-DO等等)。 The communication chip 8706 enables wireless communication to transfer data to and from the computing device 8700 . The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which can be The transformed electromagnetic radiation communicates data through non-solid media. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not be. The communication chip 8706 can implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), Wi-MAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocol known as 3G, 4G, 5G and future generations. The computing device 8700 may include a plurality of communication chips 8706 . For example, the first communication chip 8706 can be dedicated to shorter range wireless communication (such as Wi-Fi and Bluetooth), and the second communication chip 8706 can be dedicated to longer range wireless communication (such as GPS, EDGE, GPRS, CDMA , WiMAX, LTE, Ev-DO, etc.).

該計算裝置8700的該處理器8704包含封裝在該處理器8704內的積體電路晶粒。在本發明之實施例的一些實作中，該處理器的積體電路晶粒包含一或多個結構，諸如依據本發明之實作所建立的積體電路結構。術語「處理器」可以指任何裝置或裝置的部分，其處理來自暫存器或記憶體(或兩者)的電子資料，以將該電子資料轉變成可以被儲存在暫存器或記憶體(或兩者)的其他電子資料。 The processor 8704 of the computing device 8700 includes an integrated circuit die packaged within the processor 8704 . In some implementations of embodiments of the invention, the integrated circuit die of the processor includes one or more structures, such as integrated circuit structures built in accordance with implementations of the invention. The term "processor" may refer to any device or portion of a device that processes electronic data from either register or memory (or both) to convert that electronic data into or both) other electronic materials.

該通訊晶片8706也包含封裝在該通訊晶片8706內的積體電路晶粒。依據本發明的另一實作，該通訊晶片的積體電路晶粒係依據本發明的實作來予以建立。 The communication chip 8706 also includes integrated circuit dies packaged within the communication chip 8706 . According to another implementation of the present invention, the integrated circuit die of the communication chip is built according to the implementation of the present invention.

在其他實作中，收容在該計算裝置8700內的 另一組件可含有依據本發明之實施例的實作所建立的積體電路晶粒。 In other implementations, the computing device 8700 houses Another device may contain an integrated circuit die built in accordance with the implementation of an embodiment of the present invention.

在各種實施例中，該計算裝置8700可以為膝上型、小筆電(netbook)、筆記型電腦、超筆電(ultrabook)、智慧型手機、平板電腦、個人數位助理(PDA)、超級行動個人電腦(ultramobile PC)、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器、或數位錄影機。在其他實作中，該計算裝置8700可以為處理資料的任何其他電子裝置。 In various embodiments, the computing device 8700 may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra mobile Personal computer (ultramobile PC), mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder . In other implementations, the computing device 8700 can be any other electronic device that processes data.

圖88繪示包含本發明的一或更多個實施例的中介層8800。該中介層8800為用來使第一基板8802橋接至第二基板8804的中介基板。該第一基板8802可為例如積體電路晶粒。該第二基板8804可為例如記憶體模組、電腦主機板、或另一積體電路晶粒。通常，該中介層8800的目的在於將連接擴散至更寬的間距或者將連接重新路由至不同的連接。例如，中介層8800可以使積體電路晶粒耦接至球狀柵格陣列(BGA)8806，其隨後可以被連接至該第二基板8804。在有些實施例中，該第一和第二基板8802/8804係附接至該中介層8800的相反側。在其他實施例中，該第一和第二基板8802/8804係附接至該中介層8800的同一側。而且在其他實施例中，三或更多個基板可以經由該中介層8800而互連。 Figure 88 illustrates an interposer 8800 incorporating one or more embodiments of the present invention. The interposer 8800 is an intervening substrate used to bridge the first substrate 8802 to the second substrate 8804 . The first substrate 8802 can be, for example, an integrated circuit die. The second substrate 8804 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of the interposer 8800 is to spread connections to wider pitches or to reroute connections to different connections. For example, the interposer 8800 may couple the integrated circuit die to a ball grid array (BGA) 8806 , which may then be connected to the second substrate 8804 . In some embodiments, the first and second substrates 8802 / 8804 are attached to opposite sides of the interposer 8800 . In other embodiments, the first and second substrates 8802 / 8804 are attached to the same side of the interposer 8800 . Also in other embodiments, three or more substrates may be interconnected via the interposer 8800 .

該中介層8800可以由環氧樹脂、玻璃纖維強 化環氧樹脂、陶瓷材料、或者諸如聚醯亞胺的聚合物材料所形成。在其他實作中，該中介層可以由交替的剛性或撓性材料所形成，其可包含使用於半導體基板中之上面所述相同的材料，諸如矽、鍺、以及其他III-V族和第IV族材料。 The interposer 8800 can be made of epoxy, fiberglass epoxy resin, ceramic material, or polymer material such as polyimide. In other implementations, the interposer may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and III Group IV materials.

該中介層可以包含金屬互連8808及通孔(vias)8810，其包含但不限於矽穿孔(TSV)8812。該中介層8800可另包含嵌入式裝置8814，其包含被動及主動裝置。此等裝置包含但不限於電容器、解耦電容器、電阻器、電感器、熔斷器材(fuse)、二極體、變壓器、感測器、以及靜電放電(ESD)裝置。諸如射頻(RF)裝置、功率放大器、功率管理裝置、天線、陣列、感測器、及MEMS裝置之更複雜的裝置也可以被形成在該中介層8800上。依據本發明的實施例，本文中所揭示的設備或處理器可以被使用於中介層8800的製作或者被使用於中介層8800中所包含之組件的製作。 The interposer may include metal interconnects 8808 and vias 8810 including but not limited to through silicon vias (TSVs) 8812 . The interposer 8800 may additionally include embedded devices 8814, including passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 8800 . Devices or processors disclosed herein may be used in the fabrication of interposer 8800 or in the fabrication of components contained in interposer 8800 in accordance with embodiments of the present invention.

圖89為依據本發明的一實施例，使用依據本文中所述之一或多個製程所製作或者包含本文中所述之一或多個特徵的積體電路(IC)之行動計算平台8900。 89 illustrates a mobile computing platform 8900 using an integrated circuit (IC) fabricated according to one or more of the processes described herein or incorporating one or more of the features described herein, in accordance with an embodiment of the invention.

該行動計算平台8900可以為針對電子資料顯示、電子資料處理、及無線電子資料傳輸所組構的任何可攜式裝置。例如，行動計算平台8900可以為平板電腦、智慧型手機、膝上型電腦等等的任何一者，而且包含顯示螢幕8905，在代表性實施例中的顯示螢幕8905為觸控螢幕 (電容式、電感式、電阻式、等等)、晶片級數(SoC)或封裝組件級整合系統8910、及電池8913。如同所繪示者，由更高電晶體集積密度(packing density)所致能之系統8910中的整合等級越大，行動計算平台8900可以由電池8913或非揮發儲存器(諸如，固態驅動器)所佔據的部位越大，或者用於改善平台功能性之電晶體邏輯閘數越大。類似地，系統8910中之各電晶體的載子遷移率越大，該功能性越大。因此，本文中所述之技術可以致能行動計算平台8900中的性能和形狀因素(form factor)改善。 The mobile computing platform 8900 can be any portable device configured for electronic data display, electronic data processing, and wireless electronic data transmission. For example, mobile computing platform 8900 can be any one of a tablet, smartphone, laptop, etc., and includes display screen 8905, which in a representative embodiment is a touch screen (capacitive, inductive, resistive, etc.), chip-on-chip (SoC) or package-level integrated system 8910 , and battery 8913 . As shown, the greater the level of integration in the system 8910 enabled by higher transistor packing density, the mobile computing platform 8900 can be powered by a battery 8913 or non-volatile storage such as a solid state drive The larger the area occupied, or the larger the number of transistor logic gates used to improve platform functionality. Similarly, the greater the carrier mobility of each transistor in system 8910, the greater the functionality. Accordingly, the techniques described herein may enable performance and form factor improvements in the mobile computing platform 8900 .

該整合系統8910被進一步繪示於擴大的視圖8920中。在代表性實施例中，封裝裝置8977包含依據本文中所述之一或多個製程所製作或者包含本文中所述之一或多個特徵的至少一個記憶體晶片(例如，RAM)、或至少一個處理器晶片(例如，多核心微處理器及/或圖形處理器)。該封裝裝置8977連同功率管理積體電路(PMIC)8915、RF(無線)積體電路(RFIC)8925、以及其控制器8911的一或多者一起被進一步耦接至該板8960，該RF(無線)積體電路(RFIC)8925包含寬頻帶RF(無線)發射器及/或接收器(例如，包含數位基頻且類比前端模組另包含發射路徑上的功率放大器和接收路徑上的低雜訊放大器)。在功能上，PMIC 8915實施電池功率調整、DC到DC轉換、等等，且因此具有耦接至電池8913的輸入以及具有將電流供應提供給所有其他功能模組的輸出。如同所進一步繪示者，在該代表性實施例中，RFIC 8925具有耦接至天線的輸出以提供 來施行許多無線標準或協定的任何一者，其包含但不限於Wi-Fi(IEEE 802.11系列)、Wi-MAX(IEEE 802.16系列)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其衍生物、以及被稱為3G,4G,5G及未來世代之任何其他的無線協定。在替代的實作中，這些板級模組個字可以被整合於耦接至該封裝裝置8977之該封裝組件基板之分開的IC上，或者可以被整合於耦接至該封裝裝置8977之該封裝組件基板的單個IC(SoC)內。 The integrated system 8910 is further depicted in an enlarged view 8920 . In a representative embodiment, packaged device 8977 includes at least one memory die (eg, RAM) fabricated according to one or more of the processes described herein or includes one or more of the features described herein, or at least A processor chip (eg, multi-core microprocessor and/or graphics processor). The packaged device 8977 is further coupled to the board 8960 along with one or more of a power management integrated circuit (PMIC) 8915, an RF (wireless) integrated circuit (RFIC) 8925, and a controller 8911 thereof, the RF( Wireless) integrated circuit (RFIC) 8925 includes a wideband RF (wireless) transmitter and/or receiver (e.g., includes a digital baseband and an analog front-end module that also includes a power amplifier on the transmit path and a low-noise amplifier). Functionally, the PMIC 8915 implements battery power regulation, DC to DC conversion, etc., and thus has an input coupled to the battery 8913 and an output providing a current supply to all other functional modules. As further illustrated, in the representative embodiment, the RFIC 8925 has an output coupled to an antenna to provide to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), Wi-MAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocol known as 3G, 4G, 5G and future generations. In alternative implementations, the board-level modules can be integrated on a separate IC coupled to the package substrate of the package device 8977, or can be integrated on the IC coupled to the package device 8977. Packaged within a single IC (SoC) on a component substrate.

在另一態樣中，半導體封裝組件被用來保護積體電路(IC)晶片或晶粒，而且也被用來提供具有到外部電路之電氣介面的晶粒。隨著更小的電子裝置之需求的增加，半導體封裝組件被設計成更加精簡小巧而且必須支援更大的電路密度。此外，更高性能裝置的需求導致需要改進半導體封裝組件，其致使能夠和後續的組裝處理相容之薄的封裝外型及低的整體翹曲(warpage)。 In another aspect, a semiconductor package is used to protect an integrated circuit (IC) die or die, and is also used to provide the die with an electrical interface to external circuitry. As the demand for smaller electronic devices increases, semiconductor packages are designed to be more compact and must support greater circuit density. Additionally, the need for higher performance devices has led to a need for improved semiconductor packaging assemblies that result in thin package profiles and low overall warpage that are compatible with subsequent assembly processes.

在一實施例中，打線接合至陶瓷或有機封裝組件基板被使用。在另一實施例中，C4製程被用來將晶粒安裝在陶瓷或有機封裝組件基板。特別是，C4焊球(solder ball)連接可以被施行來提供半導體裝置與基板之間的覆晶(flip chip)互連。覆晶或控制塌陷高度晶片連接(C4)為使用於半導體裝置的一種安裝類型，諸如積體電路(IC)晶片、MEMS或組件，其使用焊點凸塊(solder bump)而不是焊線(wire bond)。焊點凸塊被沉積在C4墊塊(pad)上，位在該基 板封裝組件的頂側上。為了將半導體裝置安裝於基板，其被翻轉過來而以作用側面向下在安裝區上。焊點凸塊被用來使半導體裝置直接連接至基板。 In one embodiment, wire bonding to a ceramic or organic package substrate is used. In another embodiment, a C4 process is used to mount the die on a ceramic or organic package substrate. In particular, C4 solder ball connections may be implemented to provide flip chip interconnections between the semiconductor device and the substrate. Flip Chip or Controlled Collapse Height Die Attach (C4) is a type of mounting used for semiconductor devices, such as integrated circuit (IC) wafers, MEMS or components, that uses solder bumps instead of wire bonds bond). Solder bumps are deposited on the C4 pad, located on the base board on the top side of the package assembly. In order to mount the semiconductor device on the substrate, it is turned over with the active side down on the mounting area. Solder bumps are used to directly connect semiconductor devices to substrates.

圖90繪示依據本發明的一實施例，覆晶安裝之晶粒的剖面視圖。 FIG. 90 illustrates a cross-sectional view of a flip-chip mounted die in accordance with one embodiment of the present invention.

參照圖90，依據本發明的一實施例，設備9000包含晶粒9002，諸如依據本文中所述之一或多個製程所製作或者包含本文中所述之一或多個特徵的積體電路(IC)。該晶粒9002包含金屬化墊塊9004在其上。諸如陶瓷或有機基板的封裝組件基板9006包含連接9008在其上。該晶粒9002及封裝組件基板9006藉由焊球9010而被電連接耦合至該金屬化墊塊9004和該等連接9008。底部填充材料9012圍繞該等焊球9010。 Referring to FIG. 90, according to an embodiment of the present invention, a device 9000 includes a die 9002, such as an integrated circuit ( IC). The die 9002 includes metallized pads 9004 thereon. A package substrate 9006, such as a ceramic or organic substrate, has connections 9008 thereon. The die 9002 and package substrate 9006 are electrically coupled to the metallization pad 9004 and the connections 9008 by solder balls 9010 . An underfill material 9012 surrounds the solder balls 9010 .

處理覆晶可能類似於習知的IC製作，帶有少許幾個額外的操作。接近製造過程的結束，附接墊塊被金屬化而使它們更能接受焊料。這典型上由幾個處理組成。小點的焊料然後被沉積在各金屬化墊塊上。該等晶片然後照正常從晶圓被切割出。為了使該覆晶附接於電路中，晶片被倒反而使焊點向下連接至下面的電子或電路板上的連接器(接頭(connector))。焊料然後被再熔化以產生電連接，典型上使用超音波或者回流焊接(reflow solder)製程。這也留下小的空間在晶片的電路與下面的安裝之間。在大部分的情況中，電絕緣黏著然後被「底部填充」以提供更強的機械連接、提供熱橋(heat bridge)、以及確保焊 接接頭(solder joint)由於晶片與該系統之其他部分的差別加熱(differential heating)而不受應力。 Processing flip chip may be similar to conventional IC fabrication with a few additional operations. Near the end of the manufacturing process, the attachment pads are metallized to make them more receptive to solder. This typically consists of several treatments. Small dots of solder are then deposited on each metallization pad. The chips are then diced from the wafer as normal. To attach the flip chip in a circuit, the die is inverted so that the solder joints connect down to connectors (connectors) on the underlying electronics or circuit board. The solder is then remelted to make the electrical connection, typically using an ultrasonic or reflow soldering process. This also leaves little space between the die's circuitry and the underlying mounting. In most cases, the electrical insulation is adhered and then "underfilled" to provide a stronger mechanical connection, to provide a heat bridge, and to secure solder joints. The solder joints are not stressed due to differential heating of the wafer and the rest of the system.

在其他實施例中，依據本發明的一實施例，更新的封裝及晶粒到晶粒(die-to-die)互連法，諸如矽穿孔(TSV)和矽中介層，被施行來結合依據本文中所述之一或多個製程所製作或者包含本文中所述之一或多個特徵的積體電路(IC)以製作高性能多晶片模組(MCM)及系統級封裝組件(System in Package(SiP))。 In other embodiments, newer packaging and die-to-die interconnection methods, such as through-silicon vias (TSVs) and silicon interposers, are implemented in accordance with an embodiment of the present invention to combine Integrated circuits (ICs) manufactured by one or more processes described herein or comprising one or more features described herein to manufacture high-performance multi-chip modules (MCMs) and system-in-package assemblies (System in Package (SiP)).

因此，本發明的實施例包含先進的積體電路結構製作。 Accordingly, embodiments of the present invention encompass advanced integrated circuit structure fabrication.

雖然特定的實施例已被說明於上，但是這些並不打算限制本發明的範疇，即使是僅針對特別的特徵來說明單一個實施例的情況。本發明所提供之特徵的範例係舉例說明性而非限制性的，除非另外有所陳述。上面的說明意欲涵蓋諸如對於熟悉本發明的人士而言將會是顯而易知的替換、變型、以及等同物。 While specific embodiments have been described above, these are not intended to limit the scope of the invention, even if only a single embodiment is described with respect to particular features. The examples of features provided herein are illustrative and not restrictive unless otherwise stated. The above description is intended to cover such alternatives, modifications, and equivalents as would be obvious to those skilled in the invention.

本發明的範疇包含本文中所揭示之任一特徵或特徵的組合(不論是明確或隱含的)、或其任何概括，不論其是否減輕本文中所對付之任一問題或所有問題。因此，新的申請專利範圍可以在本發明的執行期間構想出任何此等特徵的組合。特別是，參考附加的申請專利範圍，附屬項申請專利範圍的特徵可以和獨立項申請專利範圍的那些特徵相結合，而且個別獨立項申請專利範圍的特徵可以用任何適當的方式來組合，而不是僅為附加申請專利範 圍中所列舉之特定組合中者。 The scope of the invention includes any feature or combination of features disclosed herein, whether express or implicit, or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, the new claims may contemplate any combination of such features during the performance of the invention. In particular, with reference to the appended claims, features of the dependent claims may be combined with those of the independent claims, and features of the individual independent claims may be combined in any suitable manner, rather than For additional patent applications only in the specific combination listed in the circle.

下面的範例與其他實施例有關。不同實施例的各種特徵可以和被包含來適合各種不同應用的一些特徵以及被排除來適合各種不同應用的其他特徵做各式各樣的組合。 The following examples relate to other embodiments. The various features of the different embodiments can be combined in various combinations with some features included for a variety of different applications and other features excluded for a variety of different applications.

範例實施例1：一種製造積體電路結構的方法包含形成複數個鰭部，該複數個鰭部之個別的一些沿著第一方向。該方法也包含形成複數個閘極結構於該複數個鰭部之上，該等閘極結構之個別的一些沿著與該第一方向正交的第二方向。該方法也包含形成電介質材料結構於該複數個閘極結構之相鄰的一些之間。該方法也包含去除該複數個閘極結構之其中一個閘極結構的部位以使該複數個鰭部之各者的部位暴露出。該方法也包含去除該複數個鰭部之各者的該露出部位。該方法也包含形成絕緣層於該複數個鰭部之各者的該去除部位的位置中。 Example Embodiment 1: A method of fabricating an integrated circuit structure includes forming a plurality of fins, individual ones of the plurality of fins are along a first direction. The method also includes forming a plurality of gate structures on the plurality of fins, individual ones of the gate structures are along a second direction orthogonal to the first direction. The method also includes forming a dielectric material structure between adjacent ones of the plurality of gate structures. The method also includes removing portions of one of the plurality of gate structures to expose portions of each of the plurality of fins. The method also includes removing the exposed portion of each of the plurality of fins. The method also includes forming an insulating layer in the location of the removed location of each of the plurality of fins.

範例實施例2：範例實施例1的該方法，其中，去除該複數個閘極結構之該其中一個閘極結構的部位包括使用比該複數個閘極結構之該其中一個閘極結構的部位之寬度更寬的光刻窗口。 Example Embodiment 2: The method of Example Embodiment 1, wherein removing the portion of the one of the plurality of gate structures comprises using a portion of the one of the plurality of gate structures that is larger than the portion of the one of the plurality of gate structures Lithography window with wider width.

範例實施例3：範例實施例1或2的該方法，其中，去除該複數個鰭部之各者的該露出部位包括蝕刻至比該複數個鰭部之高度更少的深度。 Example Embodiment 3: The method of Example Embodiment 1 or 2, wherein removing the exposed portion of each of the plurality of fins includes etching to a depth less than a height of the plurality of fins.

範例實施例4：範例實施例3的該方法，其中，該深度係大於該複數個鰭部中之源極或汲極的深度。 Example embodiment 4: the method of example embodiment 3, wherein the depth is greater than a depth of a source or a drain in the plurality of fins.

範例實施例5：範例實施例1、2、3或4的該方法，其中，該複數個鰭部包括矽而且與矽基板的一部位係連續的。 Example Embodiment 5: The method of Example Embodiments 1, 2, 3, or 4, wherein the plurality of fins includes silicon and is continuous with a portion of the silicon substrate.

範例實施例6：一種積體電路結構包含包括矽的鰭部，該鰭部沿著第一方向具有最長的尺寸。隔離結構使該鰭部的第一上部部位與該鰭部的第二上部部位沿著該第一方向分開，該隔離結構沿著該第一方向具有中心。第一閘極結構係在該鰭部的該第一上部部位之上，該第一閘極結構沿著與該第一方向正交的第二方向具有最長的尺寸，其中，該第一閘極結構的中心與該隔離結構的該中心沿著該第一方向間隔開一間距。第二閘極結構係在該鰭部的該第一上部部位之上，該第二閘極結構沿著該第二方向具有最長的尺寸，其中，該第二閘極結構的中心與該第一閘極結構的該中心沿著該第一方向間隔開該間距。第三閘極結構係在該鰭部的該第二上部部位之上，該第三閘極結構沿著該第二方向具有最長的尺寸，其中，該第三閘極結構的中心與該隔離結構的該中心沿著該第一方向間隔開該間距。 Example Embodiment 6: An integrated circuit structure includes a fin comprising silicon, the fin having a longest dimension along a first direction. An isolation structure separates the first upper portion of the fin from the second upper portion of the fin along the first direction, the isolation structure having a center along the first direction. Over the first upper portion of the fin is a first gate structure, the first gate structure having a longest dimension along a second direction orthogonal to the first direction, wherein the first gate The center of the structure is spaced apart from the center of the isolation structure by a distance along the first direction. A second gate structure is overlying the first upper portion of the fin, the second gate structure having a longest dimension along the second direction, wherein a center of the second gate structure is aligned with the first The centers of the gate structures are spaced apart by the distance along the first direction. A third gate structure is over the second upper portion of the fin, the third gate structure having a longest dimension along the second direction, wherein a center of the third gate structure is aligned with the isolation structure The centers of are spaced apart by the distance along the first direction.

範例實施例7：範例實施例6的該積體電路結構，其中，該第一閘極結構、該第二閘極結構及該第三閘極結構各自包括閘極電極，該閘極電極係在高k閘極電介質層的側壁上並且在高k閘極電介質層的側壁之間。 Example Embodiment 7: The integrated circuit structure of Example Embodiment 6, wherein the first gate structure, the second gate structure, and the third gate structure each include a gate electrode connected to On and between sidewalls of the high-k gate dielectric layer.

範例實施例8：範例實施例7的該積體電路結構，其中，該第一閘極結構、該第二閘極結構及該第三閘 極結構各自另包括絕緣蓋部，該絕緣蓋部係在該閘極電極上以及在該高k閘極電介質層的該等側壁上。 Example Embodiment 8: The integrated circuit structure of Example Embodiment 7, wherein the first gate structure, the second gate structure and the third gate The pole structures each further include an insulating cap tied over the gate electrode and over the sidewalls of the high-k gate dielectric layer.

範例實施例9：範例實施例6、7或8的該積體電路結構，另包括：第一磊晶半導體區域，該第一磊晶半導體區域係在該鰭部的該第一上部部位上，在該第一閘極結構與該隔離結構之間；第二磊晶半導體區域，該第二磊晶半導體區域係在該鰭部的該第一上部部位上，在該第一閘極結構與該第二閘極結構之間；以及第三磊晶半導體區域，該第三磊晶半導體區域係在該鰭部的該第二上部部位上，在該第三閘極結構與該隔離結構之間。 Example embodiment 9: the integrated circuit structure of example embodiments 6, 7 or 8, further comprising: a first epitaxial semiconductor region attached to the first upper portion of the fin, Between the first gate structure and the isolation structure; a second epitaxial semiconductor region on the first upper portion of the fin, between the first gate structure and the between the second gate structures; and a third epitaxial semiconductor region on the second upper portion of the fin between the third gate structure and the isolation structure.

範例實施例10：範例實施例9的該積體電路結構，其中，該第一、該第二及該第三磊晶半導體區域包括矽和鍺。 Example Embodiment 10: The integrated circuit structure of Example Embodiment 9, wherein the first, the second and the third epitaxial semiconductor regions comprise silicon and germanium.

範例實施例11：範例實施例9的該積體電路結構，其中，該第一、該第二及該第三磊晶半導體區域包括矽。 Example Embodiment 11: The integrated circuit structure of Example Embodiment 9, wherein the first, the second and the third epitaxial semiconductor regions comprise silicon.

範例實施例12：範例實施例6、7、8、9、10或11的該積體電路結構，其中，該隔離結構誘發應力於該鰭部的該第一上部部位上以及於該鰭部的該第二上部部位上。 Example Embodiment 12: The integrated circuit structure of Example Embodiments 6, 7, 8, 9, 10 or 11, wherein the isolation structure induces stress on the first upper portion of the fin and on the fin on the second upper part.

範例實施例13：範例實施例12的該積體電路結構，其中，該應力為壓縮應力。 Example Embodiment 13: The integrated circuit structure of Example Embodiment 12, wherein the stress is compressive stress.

範例實施例14：範例實施例12的該積體電路結構，其中，該應力為伸張應力。 Example Embodiment 14: The integrated circuit structure of Example Embodiment 12, wherein the stress is tensile stress.

範例實施例15：範例實施例6、7、8、9、10、11、12、13或14的該積體電路結構，其中，該隔離結構具有實質上與該第一閘極結構的頂部、與該第二閘極結構的頂部、以及與該第三閘極結構的頂部共平面的頂部。 Example Embodiment 15: The integrated circuit structure of Example Embodiments 6, 7, 8, 9, 10, 11, 12, 13 or 14, wherein the isolation structure has a top, A top coplanar with the top of the second gate structure and with the top of the third gate structure.

範例實施例16：一種製造積體電路結構的方法包含形成包括矽的鰭部，該鰭部沿著第一方向具有最長的尺寸。該方法也包含形成使該鰭部的第一上部部位與該鰭部的第二上部部位沿著該第一方向分開的隔離結構，該隔離結構沿著該第一方向具有中心。該方法也包含形成第一閘極結構於該鰭部的該第一上部部位之上，該第一閘極結構沿著與該第一方向正交的第二方向具有最長的尺寸，其中，該第一閘極結構的中心與該隔離結構的該中心沿著該第一方向間隔開一間距。該方法也包含形成第二閘極結構於該鰭部的該第一上部部位之上，該第二閘極結構沿著該第二方向具有最長的尺寸，其中，該第二閘極結構的中心與該第一閘極結構的該中心沿著該第一方向間隔開該間距。該方法也包含形成第三閘極結構於該鰭部的該第二上部部位之上，該第三閘極結構沿著該第二方向具有最長的尺寸，其中，該第三閘極結構的中心與該隔離結構的該中心沿著該第一方向間隔開該間距。 Example Embodiment 16: A method of fabricating an integrated circuit structure includes forming a fin comprising silicon, the fin having a longest dimension along a first direction. The method also includes forming an isolation structure separating the first upper portion of the fin from the second upper portion of the fin along the first direction, the isolation structure having a center along the first direction. The method also includes forming a first gate structure over the first upper portion of the fin, the first gate structure having a longest dimension along a second direction orthogonal to the first direction, wherein the first gate structure has a longest dimension along a second direction orthogonal to the first direction, wherein the The center of the first gate structure is spaced apart from the center of the isolation structure by a distance along the first direction. The method also includes forming a second gate structure over the first upper portion of the fin, the second gate structure having a longest dimension along the second direction, wherein a center of the second gate structure The distance is spaced apart from the center of the first gate structure along the first direction. The method also includes forming a third gate structure over the second upper portion of the fin, the third gate structure having a longest dimension along the second direction, wherein a center of the third gate structure spaced apart from the center of the isolation structure along the first direction by the distance.

範例實施例17：範例實施例16的該方法，其中，該第一閘極結構、該第二閘極結構及該第三閘極結構各自包括閘極電極，該閘極電極係在高k閘極電介質層的側壁上並且在高k閘極電介質層的側壁之間。 Example Embodiment 17: The method of Example Embodiment 16, wherein the first gate structure, the second gate structure, and the third gate structure each include a gate electrode connected to a high-k gate on the sidewalls of the high-k gate dielectric layer and between the sidewalls of the high-k gate dielectric layer.

範例實施例18：範例實施例17的該方法，其中，該第一閘極結構、該第二閘極結構及該第三閘極結構各自另包括絕緣蓋部，該絕緣蓋部係在該閘極電極上以及在該高k閘極電介質層的該等側壁上。 Example Embodiment 18: The method of Example Embodiment 17, wherein each of the first gate structure, the second gate structure, and the third gate structure further comprises an insulating cap attached to the gate electrode and on the sidewalls of the high-k gate dielectric layer.

範例實施例19：範例實施例16、17或18的該方法，另包括：形成第一磊晶半導體區域在該鰭部的該第一上部部位上，在該第一閘極結構與該隔離結構之間；形成第二磊晶半導體區域在該鰭部的該第一上部部位上，在該第一閘極結構與該第二閘極結構之間；以及形成第三磊晶半導體區域在該鰭部的該第二上部部位上，在該第三閘極結構與該隔離結構之間。 Example Embodiment 19: The method of Example Embodiment 16, 17 or 18, further comprising: forming a first epitaxial semiconductor region on the first upper portion of the fin, between the first gate structure and the isolation structure forming a second epitaxial semiconductor region on the first upper portion of the fin, between the first gate structure and the second gate structure; and forming a third epitaxial semiconductor region on the fin On the second upper portion of the portion, between the third gate structure and the isolation structure.

範例實施例20：範例實施例19的該方法，其中，該第一、該第二及該第三磊晶半導體區域包括矽和鍺。 Example Embodiment 20: The method of Example Embodiment 19, wherein the first, the second and the third epitaxial semiconductor regions comprise silicon and germanium.

範例實施例21：範例實施例19的該方法，其中，該第一、該第二及該第三磊晶半導體區域包括矽。 Example Embodiment 21: The method of Example Embodiment 19, wherein the first, the second and the third epitaxial semiconductor regions comprise silicon.

100‧‧‧起始結構 100‧‧‧starting structure

102‧‧‧層間電介質(ILD)層 102‧‧‧Interlayer dielectric (ILD) layer

104‧‧‧硬遮罩材料層 104‧‧‧hard mask material layer

106‧‧‧圖案化後的遮罩 106‧‧‧patterned mask

108‧‧‧間隔層 108‧‧‧interval layer

Claims (10)

一種積體電路結構，包括：包括矽的鰭部，該鰭部沿著第一方向具有最長的尺寸；隔離結構，使該鰭部的第一上部部位與該鰭部的第二上部部位沿著該第一方向分開，該隔離結構沿著該第一方向具有中心，該隔離結構沿著與該第一方向正交的第二方向具有最長的尺寸，並且該隔離結構沿著該第二方向具有與第二末端相對立的第一末端；在該鰭部的該第一上部部位之上的第一閘極結構，該第一閘極結構沿著該第二方向具有最長的尺寸，其中，該第一閘極結構的中心與該隔離結構的該中心沿著該第一方向間隔開一間距；在該鰭部的該第一上部部位之上的第二閘極結構，該第二閘極結構沿著該第二方向具有最長的尺寸，其中，該第二閘極結構的中心與該第一閘極結構的該中心沿著該第一方向間隔開該間距；在該鰭部的該第二上部部位之上的第三閘極結構，該第三閘極結構沿著該第二方向具有最長的尺寸，其中，該第三閘極結構的中心與該隔離結構的該中心沿著該第一方向間隔開該間距；沿著該第二方向的第四閘極結構，該第四閘極結構與該隔離結構的該第一末端直接實體接觸；以及 沿著該第二方向的第五閘極結構，該第五閘極結構與該隔離結構的該第二末端直接實體接觸。 An integrated circuit structure comprising: a fin comprising silicon, the fin having a longest dimension along a first direction; an isolation structure such that a first upper portion of the fin is aligned with a second upper portion of the fin along The first direction is separated, the isolation structure has a center along the first direction, the isolation structure has a longest dimension along a second direction orthogonal to the first direction, and the isolation structure has a length along the second direction a first end opposite the second end; a first gate structure over the first upper portion of the fin, the first gate structure having a longest dimension along the second direction, wherein the The center of the first gate structure is spaced apart from the center of the isolation structure by a pitch along the first direction; a second gate structure over the first upper portion of the fin, the second gate structure having a longest dimension along the second direction, wherein the center of the second gate structure is spaced apart from the center of the first gate structure by the spacing along the first direction; a third gate structure above the upper portion, the third gate structure having a longest dimension along the second direction, wherein the center of the third gate structure and the center of the isolation structure are along the first a direction spaced apart by the spacing; a fourth gate structure along the second direction, the fourth gate structure being in direct physical contact with the first end of the isolation structure; and A fifth gate structure along the second direction is in direct physical contact with the second end of the isolation structure. 如請求項1的積體電路結構，其中，該第一閘極結構、該第二閘極結構及該第三閘極結構各自包括閘極電極，該閘極電極係在高k閘極電介質層的側壁上並且在高k閘極電介質層的側壁之間。 The integrated circuit structure of claim 1, wherein each of the first gate structure, the second gate structure, and the third gate structure includes a gate electrode, and the gate electrode is attached to a high-k gate dielectric layer on the sidewalls of and between the sidewalls of the high-k gate dielectric layer. 如請求項2的積體電路結構，其中，該第一閘極結構、該第二閘極結構及該第三閘極結構各自另包括絕緣蓋部，該絕緣蓋部係在該閘極電極上以及在該高k閘極電介質層的該等側壁上。 The integrated circuit structure according to claim 2, wherein each of the first gate structure, the second gate structure, and the third gate structure further comprises an insulating cover portion attached to the gate electrode and on the sidewalls of the high-k gate dielectric layer. 如請求項1的積體電路結構，另包括：第一磊晶半導體區域，該第一磊晶半導體區域係在該鰭部的該第一上部部位上，在該第一閘極結構與該隔離結構之間；第二磊晶半導體區域，該第二磊晶半導體區域係在該鰭部的該第一上部部位上，在該第一閘極結構與該第二閘極結構之間；以及第三磊晶半導體區域，該第三磊晶半導體區域係在該鰭部的該第二上部部位上，在該第三閘極結構與該隔離結構之間。 The integrated circuit structure according to claim 1, further comprising: a first epitaxial semiconductor region, the first epitaxial semiconductor region is attached to the first upper part of the fin, and the isolation between the first gate structure and the between the structures; a second epitaxial semiconductor region on the first upper portion of the fin between the first gate structure and the second gate structure; and a second epitaxial semiconductor region Three epitaxial semiconductor regions, the third epitaxial semiconductor region is on the second upper portion of the fin between the third gate structure and the isolation structure. 如請求項4的積體電路結構，其中，該第一、該第二及該第三磊晶半導體區域包括矽和鍺。 The integrated circuit structure of claim 4, wherein the first, the second and the third epitaxial semiconductor regions comprise silicon and germanium. 如請求項4的積體電路結構，其中，該第一、該第二及該第三磊晶半導體區域包括矽。 The integrated circuit structure of claim 4, wherein the first, the second and the third epitaxial semiconductor regions comprise silicon. 如請求項1的積體電路結構，其中，該隔離結構誘發應力於該鰭部的該第一上部部位上以及於該鰭部的該第二上部部位上。 The integrated circuit structure of claim 1, wherein the isolation structure induces stress on the first upper portion of the fin and on the second upper portion of the fin. 如請求項7的積體電路結構，其中，該應力為壓縮應力。 The integrated circuit structure of claim 7, wherein the stress is compressive stress. 如請求項7的積體電路結構，其中，該應力為伸張應力。 The integrated circuit structure of claim 7, wherein the stress is tensile stress. 如請求項1的積體電路結構，其中，該隔離結構具有頂部，該頂部實質上與該第一閘極結構的頂部、與該第二閘極結構的頂部、以及與該第三閘極結構的頂部共平面。 The integrated circuit structure of claim 1, wherein the isolation structure has a top substantially connected to the top of the first gate structure, to the top of the second gate structure, and to the third gate structure coplanar at the top.
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US20200335625A1 (en) 2020-10-22
EP3493269A1 (en) 2019-06-05
CN109860295A (en) 2019-06-07
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US10756204B2 (en) 2020-08-25
TW201935614A (en) 2019-09-01
US10985267B2 (en) 2021-04-20

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