TWI805336B - Semiconductor structure and the method for forming the same - Google Patents

Abstract

The present disclosure provides a method for forming a semiconductor structure, including: providing a substrate; forming contact openings on the substrate, and sidewalls of the contact openings are disposed with a dielectric liner; and forming a bit line structure on the substrate, and the bit line structure spans the contact openings in a first direction, wherein the dielectric liner surrounds the bit line structure in the contact openings and extends into the bit line structure above a top surface of the substrate.

Description

Semiconductor structures and methods of forming them

The present invention relates to semiconductor structures and methods of forming the same, and more particularly to semiconductor structures with dielectric liners and methods of forming the same.

Dynamic Random Access Memory (DRAM) is widely used in consumer electronic products. In order to increase the device density in the DRAM and improve its overall performance, its manufacturing technology is currently striving towards the miniaturization of the device size.

However, as component sizes shrink, many challenges arise. For example, when forming the active area of a memory device, due to the different deposition rates of materials in the active area on surfaces with different components, the part with a faster deposition rate will be sealed earlier, and contact will occur in the formed active area. seam. The above seams may be rounded due to recrystallization in subsequent thermal processes and form voids with circular cross-sections, resulting in increased resistance of the subsequently formed bit line structure.

A method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of contact openings on the substrate, and a dielectric liner is provided on the sidewalls of the contact openings; and forming a bit line structure on the substrate, and the bit line structure is The first direction spans across the contact opening, wherein the dielectric liner surrounds the bit line structure within the contact opening and extends into the bit line structure over the top surface of the substrate.

A semiconductor structure comprising: a substrate having a plurality of contact openings; a dielectric liner disposed on a plurality of sidewalls of the contact openings; and a bit line structure disposed on the substrate and spanning the contact openings in a first direction, Wherein the dielectric liner surrounds the bit line structure within the contact opening and extends into the bit line structure above the top surface of the substrate.

FIG. 1A shows a cross-sectional view of an intermediate stage in the fabrication process of semiconductor structure 10 . In some embodiments, semiconductor structure 10 is part of a dynamic random access memory (DRAM) array. However, it should be understood that those skilled in the art can also apply the disclosed structure and forming method to other types of memory devices.

First, a substrate 100 is provided. The substrate 100 may be an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In some embodiments, the substrate 100 may be a semiconductor-on-insulator (SOI) substrate.

In some embodiments, the substrate 100 including the conductive portion 102 and the isolation portion 104 can be formed by forming an isolation component on the conductive substrate 100 . The conductive parts 102 can be used to electrically connect with the subsequently formed bit line structure (eg, the bit line structure 190 in FIG. 10A ), and the isolation parts 104 can be arranged alternately with the conductive parts 102 . Although the conductive portion 102 is shown not exposed on the topmost surface of the substrate 100 in FIG. 1A , in other examples, the conductive portion 102 may also be exposed on the topmost surface of the substrate 100 .

In some embodiments, the conductive portion 102 includes a conductive material, such as silicon, germanium, silicon carbide, gallium arsenide, other suitable materials, or combinations thereof. In some embodiments, the isolation portion 104 includes nitride or oxide, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a combination thereof. In some embodiments, the isolation portion 104 is a shallow trench isolation (shallow trench isolation, STI) structure of the substrate 100 . The isolation portion 104 can be formed through a deposition process (such as chemical vapor deposition (chemical vapor deposition, CVD)), a patterning process (such as a lithography process and an etching process), a planarization process (such as a chemical mechanical polish, CMP), or any suitable process.

Next, a cover layer 110 may be formed on the substrate 100 to protect the components in the substrate 100 from being damaged by subsequent processes. In some embodiments, the cap layer 110 includes a nitride layer 112 and an oxide layer 114 . The nitride layer 112 includes, for example, silicon nitride or silicon oxynitride. The oxide layer 114 includes, for example, a silicon oxide layer formed of tetraethoxysilane (tetraethylorthosilicate, TEOS). The method for forming the nitride layer 112 and the oxide layer 114 may be a physical vapor deposition (physical vapor deposition, PVD) process, a chemical vapor deposition process, an atomic layer deposition (atomic layer deposition, ALD) process, or any suitable deposition. Process. In one embodiment, the oxide layer 114 is formed by In-Situ Steam Generation (ISSG).

Next, a semiconductor material 120 may be formed over the substrate 100 . In some embodiments, the semiconductor material 120 is separated from the substrate 100 . For example, the capping layer 110 can separate the semiconductor material 120 from the substrate 100 . In some embodiments, the semiconductor material 120 includes, for example, polysilicon.

Next, an oxide layer 122 and a mask layer 124 are sequentially formed on the semiconductor material 120 . In some embodiments, oxide layer 122 is used as a barrier layer for subsequent etching back of conductive material (eg, conductive material 150 ). The oxide layer 122 may include, for example, tetraethoxysilane (TEOS), and the mask layer 124 may include any suitable mask material, such as photoresist. The formation of the mask layer 124 may include firstly forming a mask material on the oxide layer 122 , and then performing a patterning process on the mask material to form the patterned mask layer 124 . In some embodiments, the pattern of the mask layer 124 is selected according to the cross-sectional shape of the opening to be formed later (such as the first opening 130 shown in Figures 1A and 1B), and the pattern of the mask layer 124 is substantially Corresponds to the shape of the subsequently formed contact opening (see contact opening 180 in FIG. 10B ).

Continuing to refer to FIG. 1A , an etching process can be performed to form a plurality of first openings 130 through the semiconductor material 120 on the substrate 100 , and the shape and position of the first openings 130 can be aligned with the pattern of the mask layer 124 . The above etching process may include, for example, dry etching or wet etching. The first opening 130 may extend into a part of the substrate 100 , and the conductive portion 102 in the substrate 100 may be exposed in the first opening 130 .

FIG. 1B shows a top view of the semiconductor structure 10 corresponding to FIG. 1A, wherein FIG. 1A corresponds to section AA' in FIG. 1B. As shown in FIG. 1B , the positions of the first openings 130 can form an array in the semiconductor structure 10 , and each first opening 130 defines the position of the active region of the semiconductor structure 10 . It should be noted that although each of the first openings 130 is shown as having a circular cross-section in FIG. 1B , the present disclosure does not specifically limit the cross-sectional shape of the first openings 130 . For example, each first opening 130 may also have a rectangle, a polygon, an ellipse, an irregular shape, or other suitable cross-sectional shapes.

As shown in FIG. 2 , after the first opening 130 is formed, the mask layer 124 may be removed to expose the top surface of the oxide layer 122 . A method for removing the mask layer 124 may include, for example, an etching process or an ashing process. In one embodiment, an ashing process may be used to remove the mask layer 124 including organic components.

Referring to FIG. 3, a dielectric material 140 can then be conformally deposited in the first opening 130, and the dielectric material 140 can be along the top surface of the oxide layer 122, the sidewalls of the first opening 130, and the first opening 130. bottom extension. In some embodiments, the sidewalls of the first opening 130 include sidewalls of the capping layer 110 , the semiconductor material 120 , and the oxide layer 122 . The dielectric material 140 may include, for example, silicon nitride, or other materials that are not easily etched away in subsequent processes. For example, the dielectric material 140 may be a material having an etch selectivity to the oxide layer 122 so as not to be easily removed during subsequent etching processes of the oxide layer 122 . The forming method of the dielectric material 140 may include physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable methods, or combinations thereof.

Referring to FIG. 4 , after depositing the dielectric material 140 , an anisotropic etching process may be performed to remove the dielectric material 140 at the bottom of the first opening 130 . In this way, a dielectric spacer 142 may be formed on the sidewalls of the first opening 130 (including the sidewalls of the semiconductor material 120 ) to expose the substrate 100 . By exposing the substrate 100 , especially the conductive portion 102 of the substrate 100 through the first opening 130 , the subsequently formed bit line structure can be electrically connected to the substrate 100 in the active region of the semiconductor structure 10 . In some embodiments, portions of the dielectric material 140 on the oxide layer 122 are also removed by the anisotropic etching process. In some embodiments, the aforementioned anisotropic etching process includes a dry etching process, such as a reactive ion etching (RIE) process.

Referring to FIG. 5 , after forming the dielectric spacer layer 142 , a conductive material 150 may be formed on the substrate 100 and in the first opening 130 , and the semiconductor material 120 and the conductive material 150 are separated by the dielectric spacer layer 142 . By forming the dielectric spacer 142 on the sidewalls of the first opening 130 , the conductive material 150 can have a uniform deposition rate in the first opening 130 . Compared with the embodiments of the present disclosure, if the conductive material 150 is directly filled in the first opening 130 without the dielectric spacer 142 , a conductive material with a seam therein may be formed.

For example, in an embodiment in which the conductive material 150 includes doped polysilicon and the substrate 100 and the semiconductor material 120 include polysilicon, the conductive material 150 has a higher thickness on the sidewalls of the substrate 100 and the semiconductor material 120 than on the capping layer 110 or the oxide layer 122. With a faster deposition rate, the portion with a faster deposition rate will seal earlier and form a seam inside the conductive material 150 . The above seams may be rounded due to recrystallization in subsequent thermal processes and form voids with circular cross-sections, resulting in increased resistance of the subsequently formed bit line structure.

In some embodiments, the conductive material 150 includes doped polysilicon, metal, metal nitride, other suitable conductive materials, or a combination thereof. The formation of the conductive material 150 includes filling the conductive material 150 in the first opening 130, and the forming method may include, for example, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, electron beam evaporation, electroplating, or any suitable deposition process. In some embodiments, excess conductive material 150 is formed over first opening 130 and oxide layer 122 .

Referring to FIG. 6 , after forming the conductive material 150 , an appropriate planarization process and an etch back process may be used to remove excess conductive material 150 above the top surface of the oxide layer 122 . In some embodiments, portions of conductive material 150 between the sidewalls of oxide layer 122 are also removed, and dielectric spacer layer 142 remains on the sidewalls of oxide layer 122 . In some embodiments, the conductive material 150 is etched back to substantially the same level as the top surface of the semiconductor material 120 .

Referring to FIG. 7 , the oxide layer 122 is removed leaving portions of the dielectric spacer layer 142 protruding from the top surfaces of the conductive material 150 and the semiconductor material 120 . The above removal process may include, for example, a dry etching or a wet etching process. In some embodiments, the removal is performed using a wet etching process, and the used etchant includes hydrofluoric acid (HF), nitric acid (HNO ₃ ), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), hydrochloric acid (HCl), ammonia (NH ₃ ), other suitable etchant, or a combination of the foregoing. In one embodiment, the oxide layer 122 including TEOS may be etched using an etchant including dilute hydrofluoric acid (dilute HF, DHF) to remove the oxide layer 122 .

Referring to FIG. 8A , the dielectric spacer layer 142 is removed above the protruding portion of the top surface of the conductive material 150 and the semiconductor material 120 . The top surface of the dielectric spacer layer 142 after the removal process is substantially coplanar with the top surfaces of the conductive material 150 and the semiconductor material 120 . The above removal process may include, for example, a dry etching or a wet etching process. In some embodiments, the above removal is performed using a wet etching process, and the used etchant includes hydrofluoric acid (HF), nitric acid (HNO ₃ ), sulfuric acid (H ₂ SO ₄ ), phosphoric acid (H ₃ PO ₄ ), hydrochloric acid (HCl), ammonia (NH ₃ ), other suitable etchant, or a combination of the foregoing. In one embodiment, the dielectric spacer 142 comprising silicon nitride may be etched using an etchant comprising phosphoric acid to remove portions of the dielectric spacer 142 protruding from the top surfaces of the conductive material 150 and the semiconductor material 120 .

FIG. 8B shows a top view of the semiconductor structure 10 corresponding to FIG. 8A, wherein FIG. 8A corresponds to section AA' in FIG. 8B. As shown in FIG. 8B, the positions of the dielectric spacer layer 142 and the conductive material 150 can form an array in the top view of the semiconductor structure 10 perpendicular to the z direction, and the dielectric spacer layer 142 defines the active region of the semiconductor structure 10. Location.

Next, referring to FIG. 9 , an adhesive layer 160 , a silicon nitride layer 162 , and a hard mask layer 170 are sequentially formed on the semiconductor material 120 , the dielectric spacer layer 142 , and the conductive material 150 . In some embodiments, the hard mask layer 170 includes a silicon oxide layer 172 , a carbon layer 174 , a silicon oxynitride layer 176 , and a polysilicon layer 178 . The adhesion layer 160 can be used to reduce the resistance of the subsequently formed bit line structure, the silicon nitride layer 162 can be used as a hard mask for the gate contact of the peripheral circuit area (not shown) of the semiconductor structure 10, and the hard mask Individual layers in layer 170 may be patterned in multiple patterning processes or used as etch masks.

The material of the adhesive layer 160 may include titanium, titanium nitride, other suitable materials, or a combination thereof. The formation method of the adhesive layer 160 may include physical vapor deposition, chemical vapor deposition, atomic layer deposition, electron beam evaporation, electroplating, or other suitable methods, or a combination thereof. The formation method of the silicon nitride layer 162 may include physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable methods, or a combination thereof.

10A and 10B respectively illustrate a cross-sectional view and a top view of the semiconductor structure 10 . It should be noted that Fig. 10A is a sectional view corresponding to section AA' in Fig. 10B, and Fig. 10B is a top view corresponding to section BB' in Fig. 10A. As shown in Figures 10A and 10B, various etching processes can be performed to form a contact opening 180 exposing the substrate 100 and a bit line structure 190 on the substrate 100, and the bit line structure 190 spans a plurality of contact openings 180 in the y direction . For clarity, the location of the bit line structure 190 is shown in dashed lines in FIG. 10B. In addition, the portion of the dielectric spacer 142 that does not intersect the bit line structure 190 and is higher than the substrate 100 is also removed during the above etching process, thereby forming the dielectric liner 144 disposed on the sidewall of the contact opening 180 . . In some embodiments, dielectric liner 144 surrounds bit line structure 190 within contact opening 180 , and the portion of dielectric liner 144 that intersects bit line structure 190 (see FIG. 10B ) is on top of substrate 100 . Above the surface extends into a bit line structure 190 (not shown).

The conductive material 150 and the semiconductor material 120 may be etched in the above etching process to form the bit line structure 190 on the substrate 100, and the conductive material 150 and the semiconductor material 120 are respectively etched to form the contacts 192 and 190 of the bit line structure 190. semiconductor layer 194 . As shown in FIG. 10A , the contact 192 may be disposed directly above the contact opening 180 , and the semiconductor layer 194 may be disposed above the substrate 100 (directly above the substrate 100 including the portion other than the contact opening 180 ). Referring to FIG. 10B, the semiconductor layer 194 and the contact 192 are separated by a part of the dielectric liner 144, wherein the above-mentioned part is the intersection of the dielectric liner 144 and the bit line structure 190, and the bit line structure 190 is in the In the y direction, it is in physical contact with the dielectric liner 144 .

In some embodiments, the bit line structure 190 further includes an adhesive layer 160 and a silicon nitride layer 162 on the contacts 192 and the semiconductor layer 194 . The contact 192 may be connected to the substrate 100 at the bottom surface of the contact opening 180 , especially electrically connected to the conductive portion 102 . In some embodiments, the bit line structure 190 further includes a capping layer 110 under the semiconductor layer 194 , and the substrate 100 and the semiconductor layer 194 are separated from each other.

Continue to refer to Figures 10A, 10B. In some embodiments, the dielectric liner 144 completely covers the sidewalls of the contact opening 180 . In some embodiments, the portion of the dielectric liner 144 that intersects the bit line structure 190 is flush with the top surface of the contact 192 . In some embodiments, the portion of the dielectric liner 144 that does not intersect the bit line structure 190 is flush with the top surface of the substrate 100 . In some embodiments, there is a space in the contact opening 180 between the bit line structure 190 and the dielectric liner 144 in the x-direction.

In summary, the present disclosure provides a semiconductor structure and a method for forming the same, wherein a dielectric spacer layer is formed on the semiconductor structure before depositing the conductive material for the active region of the memory device. By forming a dielectric spacer layer to cover the surface of the structure surrounding the active area, the conductive material can grow at a consistent rate on the surface, preventing defects such as seams from forming in the active area. In this way, voids can be avoided in the subsequently formed bit line structure, the resistance of the bit line structure can be reduced, and the yield rate of the memory device can be improved.

The features of several embodiments are summarized above, so that those skilled in the art of the present invention can understand the viewpoints of the embodiments of the present invention more easily. Those skilled in the art of the present invention should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and/or advantages as the embodiments described herein. Those who have ordinary knowledge in the technical field of the present invention should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and can be made without departing from the spirit and scope of the present invention. Changes, substitutions and substitutions of all kinds.

10:Semiconductor structure 100: Substrate 102: Conductive part 104: Isolation Department 110: cover layer 112: Nitride layer 114,122: oxide layer 120: Semiconductor materials 124: mask layer 130: first opening 140: Dielectric material 142: Dielectric spacer 144: Dielectric lining 150: conductive material 160: Adhesive layer 162: silicon nitride layer 170: hard mask layer 172: Silicon oxide layer 174: carbon layer 176: silicon oxynitride layer 178: polysilicon layer 180: contact opening 190: Bit line structure 192: contact piece 194: semiconductor layer AA',BB': profile x,y,z: direction

1A, 2-7, 8A, 9, and 10A are cross-sectional views illustrating different stages of the fabrication process of a semiconductor structure according to some embodiments of the present disclosure. FIG. 1B is a top view of the semiconductor structure corresponding to FIG. 1A according to some embodiments of the present disclosure. FIG. 8B is a top view of the semiconductor structure corresponding to FIG. 8A according to some embodiments of the present disclosure. FIG. 10B is a top view of the semiconductor structure corresponding to FIG. 10A according to some embodiments of the present disclosure.

10:Semiconductor structure

100: Substrate

102: Conductive part

104: Isolation Department

110: cover layer

112: Nitride layer

114: oxide layer

144: Dielectric lining

160: Adhesive layer

162: silicon nitride layer

180: contact opening

190: Bit line structure

192: contact piece

194: semiconductor layer

BB': profile

x,z: direction

Claims (15)

A method of forming a semiconductor structure, comprising: providing a substrate; A plurality of contact openings are formed on the substrate, and a dielectric liner is disposed on sidewalls of the contact openings; and forming a bit line structure on the substrate, and the bit line structure straddles the contact openings in a first direction, Wherein the dielectric liner surrounds the bit line structure within the contact openings and extends into the bit line structure above the top surface of the substrate. The method for forming a semiconductor structure such as claim 1 further includes: forming a semiconductor material over the substrate; forming a dielectric spacer on sidewalls of the semiconductor material; and A conductive material is formed on the substrate, and the semiconductor material and the conductive material are separated by the dielectric spacer layer. The method for forming a semiconductor structure according to claim 2 further includes etching the conductive material and the semiconductor material to respectively form a contact and a semiconductor layer of the bit line structure. The method for forming a semiconductor structure according to claim 2, further comprising removing the dielectric spacer layer above the conductive material and the top surface of the semiconductor material. The method for forming a semiconductor structure such as claim 2 further includes: forming a plurality of first openings through the semiconductor material on the substrate; and forming the dielectric spacer on sidewalls of the first openings, Wherein the conductive material is filled in the first openings. The method for forming a semiconductor structure according to claim 5, wherein the forming of the dielectric spacer layer comprises: conformally depositing a dielectric material within the first openings; and A portion of the dielectric material is removed to expose the substrate at the bottom of the first openings. The method for forming a semiconductor structure as claimed in item 5 further includes: A portion of the dielectric spacer that does not intersect the bit line structure and is higher than the substrate is removed to form the dielectric liner. The method for forming a semiconductor structure according to claim 1 further includes performing an etching process to form the contact openings, and the contact openings expose the substrate. A semiconductor structure comprising: A substrate having a plurality of contact openings; a dielectric liner disposed on sidewalls of the contact openings; and a bit line structure disposed on the substrate and across the contact openings in a first direction, Wherein the dielectric liner surrounds the bit line structure within the contact openings and extends into the bit line structure above a top surface of the substrate. The semiconductor structure of claim 9, wherein the dielectric liner completely covers the sidewalls of the contact openings. The semiconductor structure according to claim 9, wherein the bit line structure comprises: A contact element is arranged directly above the contact openings; and A semiconductor layer is disposed above the substrate and separated from the contact by the dielectric liner. The semiconductor structure of claim 11, wherein the portion of the dielectric liner intersecting the bit line structure is flush with the top surface of the contact. The semiconductor structure of claim 9, wherein portions of the dielectric liner that do not intersect the bit line structure are flush with the top surface of the substrate. The semiconductor structure of claim 9, wherein the bit line structure is in physical contact with the dielectric liner in the first direction. The semiconductor structure according to claim 9, wherein there is a space between the bit line structure and the dielectric liner in a second direction, and the second direction is perpendicular to the first direction.

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