TWI805069B - High-frequency component test device and method thereof - Google Patents

High-frequency component test device and method thereof Download PDF

Info

Publication number
TWI805069B
TWI805069B TW110142087A TW110142087A TWI805069B TW I805069 B TWI805069 B TW I805069B TW 110142087 A TW110142087 A TW 110142087A TW 110142087 A TW110142087 A TW 110142087A TW I805069 B TWI805069 B TW I805069B
Authority
TW
Taiwan
Prior art keywords
key
test
pad
transmission line
abcd
Prior art date
Application number
TW110142087A
Other languages
Chinese (zh)
Other versions
TW202242430A (en
Inventor
李思翰
張傑
梅芃翌
Original Assignee
財團法人工業技術研究院
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 財團法人工業技術研究院 filed Critical 財團法人工業技術研究院
Priority to CN202111457916.6A priority Critical patent/CN115248364A/en
Priority to US17/559,371 priority patent/US20220341978A1/en
Publication of TW202242430A publication Critical patent/TW202242430A/en
Application granted granted Critical
Publication of TWI805069B publication Critical patent/TWI805069B/en

Links

Images

Abstract

A high-frequency component test device includes a test key and a test module. The test key include a front-level key and a back-level key arranged symmetrically, and the front-level key and the back-level key have the same electrical length and characteristic impedance. The test module is used to measure S parameter of the front-level key and the back-level key connected directly and S parameter of a structure where a device under test (DUT) is added between the front-level key and the back-level key. The test module calculates in the frequency domain and converts the S parameter into an ABCD parameter matrix, and then uses a matrix root-opening operation and an inverse matrix operation to obtain ABCD parameter of a de-embedded DUT.

Description

高頻元件測試裝置及其測試方法 High-frequency component testing device and testing method thereof

本發明是有關於一種測試裝置,且特別是有關於一種高頻元件測試裝置及其測試方法。 The present invention relates to a testing device, and in particular to a high-frequency component testing device and a testing method thereof.

傳統的高頻元件量測及校正方式多以SOLT、TRL為主,SOLT需要短路(Short)、開路(Open)、負載(Load)、直通(Thru)四個校正模塊(calibration kits),而TRL則需直通(Thru)、反射(Reflect)、線路(Line)三種測試鍵。此外,在上述校正技術中,通常又針對特定的量測要求(如寬帶頻率或晶圓上探測)分成不同的校正方法,造成校正時步驟較為繁瑣。 Traditional high-frequency component measurement and calibration methods are mostly based on SOLT and TRL. SOLT requires four calibration kits (Short), Open, Load, and Thru, while TRL Three test keys are required: Thru, Reflect, and Line. In addition, in the above calibration techniques, different calibration methods are usually divided into different calibration methods for specific measurement requirements (such as broadband frequency or on-wafer detection), resulting in cumbersome calibration steps.

另外,以SOLT、TRL為主的校正方法,容易因為每一次的量測而產生誤差,例如下針深度不同或是下針的位置偏移,都會影響校正結果,為了避免因校正誤差而導致待測物的量測失準,有必要提出改善之道。 In addition, SOLT and TRL-based calibration methods are prone to errors due to each measurement, such as different needle depths or position offsets, which will affect the calibration results. It is necessary to propose a way to improve the measurement inaccuracy of the measured object.

本發明係有關於一種高頻元件測試裝置及其測試方法,用以減少校正誤差。 The invention relates to a high-frequency component testing device and a testing method thereof, which are used to reduce correction errors.

根據本發明之一方面,提出一種高頻元件測試裝置,包括測試鍵以及一測試模組。測試鍵包括對稱排列的一前級鍵及一後級鍵,其具有一致的電氣長度及特性阻抗。測試模組用以量測該前級鍵與該後級鍵直通連接的S參數及加入一待測物於該前級鍵與該後級鍵之間的結構的S參數。 According to one aspect of the present invention, a high-frequency component testing device is provided, including a test key and a test module. The test keys include a front-stage key and a rear-stage key arranged symmetrically, which have the same electrical length and characteristic impedance. The test module is used to measure the S parameters of the direct connection between the previous key and the subsequent key and the S parameter of the structure with an object to be tested between the previous key and the subsequent key.

根據本發明之一方面,提出一種高頻元件測試方法,包括下列步驟。提供測試鍵,該測試鍵包括對稱排列的一前級鍵及一後級鍵,其具有前後一致的電氣長度及特性阻抗。量測該前級鍵與該後級鍵直通連接的S參數及加入一待測物於該前級鍵與該後級鍵之間的結構的S參數。以頻域計算並將該S參數轉換成ABCD參數矩陣,再以開根運算得到該前級鍵與該後級鍵的ABCD參數矩陣。根據該前級鍵與該後級鍵的ABCD參數矩陣的反矩陣計算一去嵌入的該待測物的ABCD參數。 According to one aspect of the present invention, a high-frequency component testing method is provided, including the following steps. The test key is provided, and the test key includes a front-stage key and a rear-stage key arranged symmetrically, which have consistent electrical length and characteristic impedance. Measuring the S-parameters of the direct connection between the preceding key and the subsequent key and the S-parameters of the structure in which an analyte is added between the preceding key and the subsequent key. Calculate in the frequency domain and convert the S parameter into an ABCD parameter matrix, and then obtain the ABCD parameter matrix of the previous key and the subsequent key through root operation. A de-embedded ABCD parameter of the analyte is calculated according to the inverse matrix of the ABCD parameter matrix of the previous key and the subsequent key.

為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式詳細說明如下: In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given in detail with the accompanying drawings as follows:

100:高頻元件測試裝置 100: High-frequency component testing device

101:去嵌入平面 101: De-embedding planes

102:待測物 102: The object to be tested

105:測試鍵 105: Test key

110:前級鍵 110: front key

120:後級鍵 120: Back stage key

112:第一傳輸線 112: The first transmission line

122:第二傳輸線 122: Second transmission line

130:測試模組 130: Test module

第1及2圖分別繪示依照本發明一實施例之高頻元件測試裝置的示意圖;第3圖繪示依照本發明一實施例之高頻元件測試方法的流程圖;及第4A至4D圖分別繪示依照本發明一實施例之高頻元件測試裝置 的特性驗證的示意圖。 Figures 1 and 2 are schematic diagrams of a high-frequency component testing device according to an embodiment of the present invention; Figure 3 is a flow chart of a high-frequency component testing method according to an embodiment of the present invention; and Figures 4A to 4D Respectively show a high-frequency component testing device according to an embodiment of the present invention Schematic diagram of the feature verification.

下面將結合本申請實施例中的附圖,對本申請實施例中的技術方案進行清楚、完整地描述,顯然,所描述的實施例是本申請一部分實施例,而不是全部的實施例。此外,所描述的特徵、結構或特性可以以任何合適的方式結合在一個或更多實施例中。在下面的描述中,提供許多具體細節從而給出對本申請的實施例的充分理解。然而,本領域具有通常知識者將意識到,可以實踐本申請的技術方案而沒有特定細節中的一個或更多,或者可以採用其它的方法、裝置、步驟等。在其它情況下,不詳細示出或描述公知方法、裝置、實現或者操作以避免模糊本申請的各方面。 The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of the embodiments of the application. However, those skilled in the art will appreciate that the technical solutions of the present application can be practiced without one or more of the specific details, or other methods, devices, steps, etc. can be used. In other instances, well-known methods, apparatus, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the application.

在本實施例中,散射參數(S參數)用以表示射頻發射器、微波器等元件的高頻性能。目前的S參數測試裝置會產生很大的寄生效應,使得對高頻元件進行測試所直接獲取的S參數無法準確表示該高頻元件的性能。因此,在本實施例中的測試裝置設置測試鍵來定義高頻元件的去嵌入平面101,即定義本徵元件(待測物102)與寄生元件(測試裝置100)之間的平面,如第2圖所示,通過去除測試裝置在高頻工作狀態下帶來的寄生效應,從而得到準確的本徵傳輸參數。 In this embodiment, the scattering parameters (S parameters) are used to represent the high frequency performance of components such as radio frequency transmitters and microwaves. The current S-parameter test device will produce a large parasitic effect, so that the S-parameters directly obtained by testing the high-frequency component cannot accurately represent the performance of the high-frequency component. Therefore, the testing device in this embodiment sets the test key to define the de-embedding plane 101 of the high-frequency component, that is, defines the plane between the intrinsic component (the object under test 102) and the parasitic component (testing device 100), as shown in the first As shown in Figure 2, accurate intrinsic transmission parameters can be obtained by removing the parasitic effects brought about by the test device under high-frequency operating conditions.

請參照第1及2圖,其分別繪示依照本發明一實施例之高頻元件測試裝置100的示意圖。在第1圖中,高頻元件測試裝 置100包括測試鍵105以及一測試模組130,此測試鍵105包括對稱的一前級鍵110及一後級鍵120,前級鍵110與後級鍵120具有一致的電氣長度及特性阻抗。在一實施例中,前級鍵110與後級鍵120的特性阻抗例如為50歐姆,但不以此為限。前級鍵110與後級鍵120例如以接地-信號線-接地(ground-signal-ground,GSG)組態設置。在另一實施例中,前級鍵110與後級鍵120例如以接地-信號線(GS)、接地-信號線-接地-信號線-接地(GSGSG)或其他合適的測試組態設置。測試模組130例如為網路分析儀(network analyzer)。 Please refer to FIG. 1 and FIG. 2 , which respectively illustrate a schematic view of a high-frequency component testing device 100 according to an embodiment of the present invention. In Figure 1, the high-frequency component test device The device 100 includes a test key 105 and a test module 130. The test key 105 includes a symmetrical front key 110 and a rear key 120. The front key 110 and the rear key 120 have the same electrical length and characteristic impedance. In one embodiment, the characteristic impedance of the front key 110 and the back key 120 is, for example, 50 ohms, but it is not limited thereto. The front-stage key 110 and the subsequent-stage key 120 are configured in a ground-signal-ground (GSG) configuration, for example. In another embodiment, the front-stage key 110 and the subsequent-stage key 120 are set in a ground-signal line (GS), ground-signal line-ground-signal line-ground (GSGSG) or other suitable test configurations. The test module 130 is, for example, a network analyzer.

前級鍵110包括第一傳輸線112,後級鍵120包括第二傳輸線122。第一傳輸線112與第二傳輸線122具有相同的電氣長度及材料,使前後兩側的傳輸參數大致上相等。在第2圖中,待測物102連接於二傳輸線112、122之間。待測物102與第一傳輸線112及第二傳輸線122之間分別形成一去嵌入平面101(垂直於紙面),使待測物102連接於兩個去嵌入平面101之間,去嵌入平面101的左側結構和右側結構均具有一本徵傳輸參數(intrinsic transmission parameter),透過本徵傳輸參數以及受測結構的傳輸參數,用以推導待測物102的本徵傳輸參數。在一實施例中,本徵傳輸參數例如以ABCD參數表示。 The previous stage key 110 includes a first transmission line 112 , and the subsequent stage key 120 includes a second transmission line 122 . The first transmission line 112 and the second transmission line 122 have the same electrical length and material, so that the transmission parameters of the front and rear sides are substantially equal. In FIG. 2 , the DUT 102 is connected between two transmission lines 112 , 122 . A de-embedding plane 101 (perpendicular to the paper surface) is formed between the object under test 102 and the first transmission line 112 and the second transmission line 122, so that the object under test 102 is connected between the two de-embedding planes 101, and the de-embedding plane 101 Both the left structure and the right structure have an intrinsic transmission parameter, and the intrinsic transmission parameter of the object under test 102 is derived through the intrinsic transmission parameter and the transmission parameter of the structure under test. In an embodiment, the intrinsic transmission parameters are represented by ABCD parameters, for example.

在本實施例中,透過參數轉換模組將S參數轉換為ABCD參數,其中前級鍵110與後級鍵120直通連接時S參數可用ABCD參數表示,以參數矩陣

Figure 110142087-A0305-02-0006-1
表示。例如在前級鍵110與後 級鍵120直通連接時,在二端口網路的一端輸入總電壓V1及總電流I1,在二端口網路的另一端輸出總電壓V2及總電流I2,其中V1=AV2+BI2,I1=CV2+DI2,以公式
Figure 110142087-A0305-02-0007-2
表示,其中A、B、C和D用以表示輸入電壓V1、輸出電壓V2、輸入電流I1和輸出電流I2的關係。 In this embodiment, the S parameters are converted into ABCD parameters through the parameter conversion module. When the front key 110 and the back key 120 are directly connected, the S parameters can be represented by ABCD parameters, and the parameter matrix
Figure 110142087-A0305-02-0006-1
express. For example, when the front key 110 is directly connected with the back key 120, the total voltage V1 and the total current I1 are input at one end of the two-port network, and the total voltage V2 and the total current I2 are output at the other end of the two-port network, where V1 =AV2+BI2, I1=CV2+DI2, with the formula
Figure 110142087-A0305-02-0007-2
Indicates that A, B, C and D are used to represent the relationship between input voltage V1, output voltage V2, input current I1 and output current I2.

本實施例的測試模組130可根據ABCD參數矩陣的開根運算以得到前級鍵110與後級鍵120的ABCD參數,計算公式(1)如下:[Dem]=[PAD][PAD],其中[PAD]為前級鍵110與後級鍵120的ABCD參數矩陣,[Dem]為前級鍵110與後級鍵120直通連接時的ABCD參數矩陣。由於本實施例的前級鍵110與後級鍵120具有一致的電氣長度及特性阻抗,前級鍵110與後級鍵120的ABCD參數矩陣相同,因此只要對二測試鍵110、120直通連接時的ABCD參數矩陣[Dem]進行開根運算,即可得到前級鍵110與後級鍵120的ABCD參數矩陣[PAD],由公式(1)可得知:[PAD]=

Figure 110142087-A0305-02-0007-3
The test module 130 of this embodiment can obtain the ABCD parameters of the previous key 110 and the subsequent key 120 according to the root operation of the ABCD parameter matrix. The calculation formula (1) is as follows: [Dem]=[PAD][PAD], Where [PAD] is the ABCD parameter matrix of the front key 110 and the back key 120, and [Dem] is the ABCD parameter matrix when the front key 110 and the back key 120 are directly connected. Since the front-stage key 110 and the subsequent-stage key 120 of the present embodiment have the same electrical length and characteristic impedance, the ABCD parameter matrix of the previous-stage key 110 and the subsequent-stage key 120 is the same, so as long as the two test keys 110, 120 are directly connected The ABCD parameter matrix [Dem] of the ABCD parameter matrix [Dem] can be obtained by the root operation, and the ABCD parameter matrix [PAD] of the previous key 110 and the subsequent key 120 can be obtained. It can be known from the formula (1): [ PAD ]=
Figure 110142087-A0305-02-0007-3

另外,請參照第2圖,當加入一待測物102於前級鍵110與後級鍵120之間時,測試模組130量測加入待測物102於該前級鍵110與後級鍵120之間的受測結構的S參數,之後將S參數轉換為ABCD參數,並根據反矩陣得到一去嵌入的待測物102的ABCD參數。計算公式(2)如下:[DUT]=[PAD][Golden][PAD],其中[Golden]為去嵌化的待測物102的ABCD參數矩陣,而[DUT]為前級鍵110與後級鍵120與待測物102直通連接時的 ABCD參數矩陣。由公式(2)可得知[Golden]=[PAD]-1[DUT][PAD]-1,其中[PAD]-1為前級鍵110與後級鍵120的ABCD參數矩陣的反矩陣,即[PAD]-1=

Figure 110142087-A0305-02-0008-4
In addition, please refer to FIG. 2, when adding an object under test 102 between the front key 110 and the back key 120, the test module 130 measures the addition of the object under test 102 between the front key 110 and the back key. 120 between the S parameters of the tested structure, and then convert the S parameters into ABCD parameters, and obtain a de-embedded ABCD parameter of the test object 102 according to the inverse matrix. The calculation formula (2) is as follows: [DUT]=[PAD][Golden][PAD], where [Golden] is the ABCD parameter matrix of the de-embedded object under test 102, and [DUT] is the front-level key 110 and the rear key The ABCD parameter matrix when the level key 120 is directly connected to the object under test 102 . It can be known from the formula (2) that [Golden]=[PAD] -1 [DUT][PAD] -1 , wherein [PAD] -1 is the inverse matrix of the ABCD parameter matrix of the previous key 110 and the subsequent key 120, That is, [ PAD ] -1 =
Figure 110142087-A0305-02-0008-4

在本實施例中,高頻元件測試裝置100僅需一組去嵌入之測試鍵,即可將由於量測而額外增加之佈局及走線的寄生效應去除,可加速去嵌入的檢測速度,並減少下針誤差以提升精準度。 In this embodiment, the high-frequency component testing device 100 only needs a set of test keys for de-embedding, which can remove the additional layout and wiring parasitic effects due to measurement, speed up the detection speed of de-embedding, and Reduce stitch error to improve accuracy.

請參照第1至3圖,其中第3圖繪示依照本發明一實施例之高頻元件測試方法的流程圖。首先,在步驟S30中,提供測試鍵105,其包括對稱排列的前級鍵110及後級鍵120,前級鍵110與後級鍵120具有前後一致的電氣長度及特性阻抗。在步驟S32中,量測前級鍵110與後級鍵120直通連接的S參數及加入一待測物102於前級鍵110與後級鍵120之間的結構的S參數。在步驟S34中,以頻域計算並將S參數轉換成ABCD參數矩陣,再以開根運算得到前級鍵110與後級鍵120的ABCD參數矩陣。在步驟S36中,根據前級鍵110與後級鍵120的ABCD參數矩陣的反矩陣計算一去嵌入的待測物102的ABCD參數。 Please refer to FIGS. 1 to 3 , wherein FIG. 3 shows a flow chart of a method for testing high-frequency components according to an embodiment of the present invention. First, in step S30 , a test key 105 is provided, which includes a symmetrically arranged front key 110 and a rear key 120 , and the front key 110 and the rear key 120 have the same electrical length and characteristic impedance. In step S32 , the S parameters of the direct connection between the front key 110 and the back key 120 and the S parameters of the structure in which a test object 102 is added between the front key 110 and the back key 120 are measured. In step S34, the S parameters are calculated and converted into an ABCD parameter matrix in the frequency domain, and then the ABCD parameter matrix of the previous key 110 and the subsequent key 120 is obtained by root-opening operation. In step S36 , a de-embedded ABCD parameter of the object under test 102 is calculated according to the inverse matrix of the ABCD parameter matrix of the previous key 110 and the subsequent key 120 .

請參照第4A至4D圖,其分別繪示依照本發明一實施例之高頻元件測試裝置100的S參數特性驗證的示意圖。在第4A圖中,S(1,1)參數為輸入反射係數,也就是輸入回波損耗。在第4B圖中,S(1,2)參數為反向傳輸係數,也就是隔離。在第4C 圖中,S(2,1)參數為正向傳輸係數,也就是增益。在第4D圖中,S(2,2)參數為輸出反射係數,也就是輸出回波損耗。在本實施例中以模擬驗證方式來進行S參數可行性及特性驗證,經比對圖中的模擬的模型曲線、DUT模型曲線及去嵌化的曲線的數據可發現,使用本實施例之去嵌入程序可以得到與待測物102的本徵傳輸參數非常接近的結果。模擬驗證至100GHz小信號曲線擬合(curve fitting)誤差小於10%。在另一實施例中,若採傳輸鍵測試鍵驗證至67GHz小信號相位的特性阻抗Z0及傳輸線長度βL誤差可小於8%。 Please refer to FIGS. 4A to 4D , which are respectively schematic diagrams illustrating the S-parameter characteristic verification of the high-frequency component testing device 100 according to an embodiment of the present invention. In Figure 4A, the S(1,1) parameter is the input reflection coefficient, that is, the input return loss. In Figure 4B, the S(1,2) parameter is the reverse transmission coefficient, that is, isolation. at 4C In the figure, the S(2,1) parameter is the forward transmission coefficient, that is, the gain. In Figure 4D, the S(2,2) parameter is the output reflection coefficient, that is, the output return loss. In this embodiment, the feasibility and characteristics of S parameters are verified by means of simulation verification. After comparing the data of the simulated model curve, DUT model curve and de-embedded curve in the figure, it can be found that using the de-embedding curve of this embodiment The embedding program can obtain a result very close to the intrinsic transmission parameter of the object under test 102 . Simulation verification to 100GHz small signal curve fitting (curve fitting) error is less than 10%. In another embodiment, if the transmission key test key is used to verify that the error of the characteristic impedance Z0 and the transmission line length βL to the 67 GHz small signal phase can be less than 8%.

本發明上述實施例的高頻元件測試裝置及其測試方法,僅需一種測試鍵做為校正模塊,此測試鍵具有前後一致的電氣長度及特性阻抗的前級鍵與後級鍵,特性阻抗例如為50歐姆與探針的阻抗一致,避免因校正誤差而導致待測物的量測失準。相對於傳統高頻元件量測及校正方式以SOLT、TRL為主,本實施例可減少校正步驟,並能去除S參數測試在高頻工作狀態下帶來的寄生效應,從而得到準確的S參數。 The high-frequency component testing device and testing method thereof in the above-mentioned embodiments of the present invention only need a test key as a calibration module, and the test key has a front-stage key and a back-stage key with consistent electrical length and characteristic impedance, and the characteristic impedance is, for example, It is 50 ohms consistent with the impedance of the probe to avoid measurement inaccuracy of the object to be measured due to calibration errors. Compared with the traditional high-frequency component measurement and calibration methods based on SOLT and TRL, this embodiment can reduce the calibration steps and remove the parasitic effects of S-parameter testing under high-frequency working conditions, thereby obtaining accurate S-parameters .

綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

100:高頻元件測試裝置 100: High-frequency component testing device

105:測試鍵 105: Test key

110:前級鍵 110: front key

120:後級鍵 120: Back stage key

112:第一傳輸線 112: The first transmission line

122:第二傳輸線 122: Second transmission line

130:測試模組 130: Test module

G:接地 G: ground

S:信號線 S: signal line

Claims (10)

一種高頻元件測試裝置,包括:測試鍵,包括對稱排列的一前級鍵及一後級鍵,該前級鍵與該後級鍵具有一致的電氣長度及特性阻抗;以及一測試模組,用以量測該前級鍵與該後級鍵直通連接的S參數及加入一待測物於該前級鍵與該後級鍵之間的結構的S參數,該測試模組以頻域計算並將該S參數轉換成ABCD參數矩陣,再以矩陣開根運算及反矩陣運算得到一去嵌入的該待測物的ABCD參數。 A high-frequency component testing device, comprising: a test key, including a front key and a back key symmetrically arranged, the front key and the back key have the same electrical length and characteristic impedance; and a test module, It is used to measure the S parameters of the direct connection between the previous key and the subsequent key and the S parameter of the structure of adding a test object between the previous key and the subsequent key. The test module is calculated in the frequency domain The S parameter is converted into an ABCD parameter matrix, and then a de-embedded ABCD parameter of the object to be measured is obtained by matrix root operation and inverse matrix operation. 如請求項1所述之測試裝置,其中該前級鍵包括一第一傳輸線,該後級鍵包括一第二傳輸線,該第一傳輸線與該第二傳輸線具有相同的特性阻抗。 The test device as claimed in claim 1, wherein the preceding key comprises a first transmission line, the subsequent key comprises a second transmission line, and the first transmission line and the second transmission line have the same characteristic impedance. 如請求項2所述之測試裝置,其中該待測物連接於該第一傳輸線及該第二傳輸線之間,該待測物該與第一傳輸線及該第二傳輸線之間分別形成一去嵌入平面。 The test device as described in claim 2, wherein the object under test is connected between the first transmission line and the second transmission line, and a de-embedding is formed between the object under test and the first transmission line and the second transmission line respectively flat. 如請求項3所述之測試裝置,其中[PAD]為該前級鍵與該後級鍵的ABCD參數矩陣,[Dem]為該前級鍵與該後級鍵直通連接時的ABCD參數矩陣,[Dem]=[PAD][PAD],該前級鍵與該後級鍵的ABCD參數矩陣
Figure 110142087-A0305-02-0011-5
The test device as described in claim item 3, wherein [PAD] is the ABCD parameter matrix of the preceding key and the subsequent key, and [Dem] is the ABCD parameter matrix when the preceding key is directly connected to the subsequent key, [Dem]=[PAD][PAD], the ABCD parameter matrix of the previous key and the subsequent key
Figure 110142087-A0305-02-0011-5
.
如請求項4所述之測試裝置,其中[Golden]為去嵌化的該待測物的ABCD參數矩陣,而[DUT]為該二測試鍵與該待測物直通連接時的ABCD參數矩陣,[DUT]=[PAD][Golden][PAD],根據該前級鍵與該後級鍵的ABCD參數矩陣的反矩陣 [PAD]-1計算去嵌化的該待測物的ABCD參數矩陣[Golden]=[PAD]-1[DUT][PAD]-1The test device as described in claim 4, wherein [Golden] is the ABCD parameter matrix of the de-embedded object under test, and [DUT] is the ABCD parameter matrix when the two test keys are directly connected to the object under test, [DUT]=[PAD][Golden][PAD], calculate the de-embedded ABCD parameter matrix of the DUT according to the inverse matrix [PAD] -1 of the ABCD parameter matrix of the previous key and the subsequent key [ Golden]=[PAD] -1 [DUT][PAD] -1 . 一種高頻元件測試方法,包括:提供測試鍵,該測試鍵包括對稱排列的一前級鍵及一後級鍵,該前級鍵與該後級鍵具有前後一致的電氣長度及特性阻抗;量測該前級鍵與該後級鍵直通連接的S參數及加入一待測物於該前級鍵與該後級鍵之間的結構的S參數;以頻域計算並將該S參數轉換成ABCD參數矩陣,再以開根運算得到該前級鍵與該後級鍵的ABCD參數矩陣;以及根據該前級鍵與該後級鍵的ABCD參數矩陣的反矩陣計算一去嵌入的該待測物的ABCD參數。 A method for testing high-frequency components, comprising: providing a test key, the test key including a front-stage key and a rear-stage key symmetrically arranged, the front-stage key and the rear-stage key having the same electrical length and characteristic impedance; measuring Measure the S parameter of the direct connection between the previous key and the subsequent key and add the S parameter of the structure between the preceding key and the subsequent key; calculate in the frequency domain and convert the S parameter into ABCD parameter matrix, obtain the ABCD parameter matrix of this front-level key and this back-level key with root operation again; The ABCD parameters of the substance. 如請求項6所述之測試方法,其中該前級鍵包括一第一傳輸線,該後級鍵包括一第二傳輸線,該第一傳輸線與該第二傳輸線具有相同的特性阻抗。 The testing method according to claim 6, wherein the previous key includes a first transmission line, the subsequent key includes a second transmission line, and the first transmission line and the second transmission line have the same characteristic impedance. 如請求項7所述之測試方法,其中該待測物連接於該第一傳輸線及該第二傳輸線之間,該待測物該與第一傳輸線及該第二傳輸線之間分別形成一去嵌入平面。 The test method as described in claim 7, wherein the object under test is connected between the first transmission line and the second transmission line, and a de-embedding is formed between the object under test and the first transmission line and the second transmission line respectively flat. 如請求項6所述之測試方法,其中[PAD]為該前級鍵與該後級鍵的ABCD參數矩陣,[Dem]為該前級鍵與該後級鍵直通連接時的ABCD參數矩陣,[Dem]=[PAD][PAD],該前級鍵與該後級鍵的ABCD參數矩陣
Figure 110142087-A0305-02-0012-6
The test method as described in claim item 6, wherein [PAD] is the ABCD parameter matrix of the previous key and the subsequent key, and [Dem] is the ABCD parameter matrix when the previous key is directly connected to the subsequent key, [Dem]=[PAD][PAD], the ABCD parameter matrix of the previous key and the subsequent key
Figure 110142087-A0305-02-0012-6
.
如請求項9所述之測試方法,其中[Golden]為去嵌化的該待測物的ABCD參數矩陣,而[DUT]為該前級鍵與該後級鍵與該待測物直通連接時的ABCD參數矩陣,[DUT]=[PAD][Golden][PAD],根據該前級鍵與該後級鍵的ABCD參數矩陣的反矩陣[PAD]-1計算去嵌化的該待測物的ABCD參數矩陣[Golden]=[PAD]-1[DUT][PAD]-1The test method as described in claim item 9, wherein [Golden] is the ABCD parameter matrix of the de-embedded object under test, and [DUT] is when the front key and the subsequent key are directly connected to the object under test The ABCD parameter matrix of [DUT]=[PAD][Golden][PAD], according to the inverse matrix [PAD] -1 of the ABCD parameter matrix of the previous key and the subsequent key to calculate the de-embedded test object The ABCD parameter matrix of [Golden]=[PAD] -1 [DUT][PAD] -1 .
TW110142087A 2021-04-26 2021-11-11 High-frequency component test device and method thereof TWI805069B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202111457916.6A CN115248364A (en) 2021-04-26 2021-12-02 High-frequency element testing device and testing method thereof
US17/559,371 US20220341978A1 (en) 2021-04-26 2021-12-22 High-frequency component test device and method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US202163179597P 2021-04-26 2021-04-26
US63/179,597 2021-04-26

Publications (2)

Publication Number Publication Date
TW202242430A TW202242430A (en) 2022-11-01
TWI805069B true TWI805069B (en) 2023-06-11

Family

ID=85793259

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110142087A TWI805069B (en) 2021-04-26 2021-11-11 High-frequency component test device and method thereof

Country Status (1)

Country Link
TW (1) TWI805069B (en)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060052962A1 (en) * 2002-12-02 2006-03-09 Silverbrook Research Pty Ltd. Integrated circuit having clock trim circuitry
US20100315115A1 (en) * 2009-06-05 2010-12-16 Yue-Shiun Lee Method of characterizing a semiconductor device and semiconductor device
US20110267087A1 (en) * 2010-04-28 2011-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for wafer level classification of light emitting device
CN107330184A (en) * 2017-06-29 2017-11-07 南通大学 The emulation test method and storage medium and equipment of bonding line in electric component
CN108627696A (en) * 2018-01-08 2018-10-09 深圳市鼎阳科技有限公司 A kind of measuring device and its measurement method of vector network
CN109804256A (en) * 2016-10-17 2019-05-24 韩国标准科学研究院 Electromagnetic resistivity measuring device and electromagnetic resistivity bearing calibration
CN110703054A (en) * 2019-10-29 2020-01-17 山东省科学院自动化研究所 Sample dielectric property testing device and method based on terahertz free space method
CN111581903A (en) * 2020-04-02 2020-08-25 中国电力科学研究院有限公司 Distribution cable impedance spectrum determination method and device based on improved infinitesimal equivalent model
CN111929558A (en) * 2020-09-28 2020-11-13 浙江铖昌科技有限公司 Self-calibration-based de-embedding method, system, storage medium and terminal
CN112305480A (en) * 2019-07-31 2021-02-02 是德科技股份有限公司 Calibrating impedance measurement device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060052962A1 (en) * 2002-12-02 2006-03-09 Silverbrook Research Pty Ltd. Integrated circuit having clock trim circuitry
US20100315115A1 (en) * 2009-06-05 2010-12-16 Yue-Shiun Lee Method of characterizing a semiconductor device and semiconductor device
US20110267087A1 (en) * 2010-04-28 2011-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for wafer level classification of light emitting device
CN109804256A (en) * 2016-10-17 2019-05-24 韩国标准科学研究院 Electromagnetic resistivity measuring device and electromagnetic resistivity bearing calibration
CN107330184A (en) * 2017-06-29 2017-11-07 南通大学 The emulation test method and storage medium and equipment of bonding line in electric component
CN108627696A (en) * 2018-01-08 2018-10-09 深圳市鼎阳科技有限公司 A kind of measuring device and its measurement method of vector network
CN112305480A (en) * 2019-07-31 2021-02-02 是德科技股份有限公司 Calibrating impedance measurement device
CN110703054A (en) * 2019-10-29 2020-01-17 山东省科学院自动化研究所 Sample dielectric property testing device and method based on terahertz free space method
CN111581903A (en) * 2020-04-02 2020-08-25 中国电力科学研究院有限公司 Distribution cable impedance spectrum determination method and device based on improved infinitesimal equivalent model
CN111929558A (en) * 2020-09-28 2020-11-13 浙江铖昌科技有限公司 Self-calibration-based de-embedding method, system, storage medium and terminal

Also Published As

Publication number Publication date
TW202242430A (en) 2022-11-01

Similar Documents

Publication Publication Date Title
CN104502878B (en) Microwave GaAs substrate is in piece S parameter microstrip line TRL calibrating devices
US7157918B2 (en) Method and system for calibrating a measurement device path and for measuring a device under test in the calibrated measurement device path
US6960920B2 (en) Method for correcting measurement error and electronic component characteristic measurement apparatus
US7865319B1 (en) Fixture de-embedding method and system for removing test fixture characteristics when calibrating measurement systems
US8798953B2 (en) Calibration method for radio frequency scattering parameter measurement applying three calibrators and measurement structure thereof
CN106405462B (en) Piece scattering parameter trace to the source and uncertainty evaluation method
US20070073499A1 (en) Method and apparatus for determining one or more s-parameters associated with a device under test (DUT)
TW201300799A (en) Method of measuring scattering parameters of device under test
US8290736B2 (en) Calibration standards and methods of their fabrication and use
US8860431B2 (en) Application of open and/or short structures to bisect de-embedding
CN107345986B (en) Impedance testing method in de-embedding mode
Chen et al. Analytical and numerical sensitivity analyses of fixtures de-embedding
US7643957B2 (en) Bisect de-embedding for network analyzer measurement
US8552742B2 (en) Calibration method for radio frequency scattering parameter measurements
WO2016065531A1 (en) Test structure and method for judging de-embedding accuracy of radio-frequency device using introduction device
US20050091015A1 (en) Method and apparatus for modeling a uniform transmission line
TWI463147B (en) Calibration method of radio frequency scattering parameters with two correctors
TWI805069B (en) High-frequency component test device and method thereof
CN115248364A (en) High-frequency element testing device and testing method thereof
TWI463146B (en) Radiofrequency Scattering Parameter Measurement and Correction Method
KR101680473B1 (en) The method of high-frequency S-parameter measurement for planar components
Mubarak et al. Residual error analysis of a calibrated vector network analyzer
WO2008021907A2 (en) Calibrated s-parameter measurements of probes
Kim et al. Extraction of the frequency-dependent characteristic impedance of transmission lines using TDR measurements
TWI426289B (en) Radio frequency scattering parameter correction method with three correctors