TWI804290B - Power supply voltage detector, power supply voltage detection apparatus, system and medium - Google Patents

Abstract

The application provides an apparatus, a system, a detector and a method. The apparatus includes: a power supply voltage detector, including: N buffers, an input terminal of a first buffer being connected to a clock signal, output terminals of other buffers being connected to the input terminal of an adjacent buffer; N latch chains, each of which includes M latches, a clock input terminal of each latch being connected to a clock signal, a D terminal of a first latch of each latch chain being connected to the output terminal of a corresponding buffer, Q terminals of other latches being connected to the D terminal of an adjacent latch, M and N being positive integers, the D terminal of each latch being connected to an area where a power supply voltage is to be detected; and a voltage regulation module connected to the Q terminal of each latch.

Description

Supply voltage detector, supply voltage detection device, system and medium

The present invention relates to the field of integrated circuits, and in particular to a supply voltage detector, a supply voltage detection device, a system and a computer-readable medium.

For the integrated circuit, its operation requires an external voltage source to supply power through the voltage pin, and the external voltage source is connected to different latch circuits through the internal power network of the integrated circuit. For integrated circuits with a technology of 55nm and below, hundreds of millions of latch circuits are often integrated. When a large number of latch circuits in one area of the integrated circuit are turned over at the same time or the operating frequency is increased, that is, the load in this area Increase, the supply voltage in this area may drop, lower than expected. In addition, when an integrated circuit is disturbed by power noise, its power supply voltage will also fluctuate.

Voltage droop is a term used to refer to the drop in voltage from a desired voltage level when a power supply drives a load. In integrated circuits, when the load is suddenly and very rapidly increased, the output voltage may drop. For example, a transient load condition may occur that causes the voltage to drop hang down. If the voltage sags too much, it will cause circuit failure.

Therefore, it is necessary to detect the power supply voltage inside the integrated circuit in real time, and send an early warning signal in time when the voltage is lower than expected, reminding the voltage regulation module to adjust the voltage. Of course, there is also a need to regulate the voltage when the voltage is higher than expected.

According to one or more embodiments of the present disclosure, there is provided a supply voltage detection device connected to an integrated circuit power grid, comprising: a supply voltage detector including a buffer string including N buffers, wherein the first buffer The input terminal of the buffer is connected to the clock signal, the output terminal of the first buffer is connected to the input terminal of the second buffer, the output terminal of the nth buffer is connected to the input terminal of the n+1th buffer, N and n are positive integers, n is greater than 1 and less than N; N latch chains, each latch chain includes M latches, and the clock input terminal of each latch is connected to the clock signal, each The data input terminal of the first latch of the latch chain is connected to the output terminal of a buffer corresponding to the N buffers, and the data output terminal of the first latch is connected to the second latch The data input terminal of the mth latch is connected to the data input terminal of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, the power supply of each latch The input terminal VDD is connected to the area in the integrated circuit power network where the supply voltage is to be sensed, the ground terminal of each latch is connected to ground; and the voltage regulation module is connected to each latch of each latch chain The data output terminal of the latch is configured to detect the data output of each latch to determine the magnitude of the supply voltage in the area where the supply voltage is to be detected in the integrated circuit power network.

According to one or more embodiments of the present disclosure, there is provided a supply voltage detection system, comprising: a plurality of supply voltage detection devices according to the embodiments of the present disclosure connected to multiple regions of an integrated circuit power network.

According to one or more embodiments of the present disclosure, there is provided a supply voltage detector, including a buffer string, including N buffers, wherein the input end of the first buffer is connected to the clock signal, and the input end of the first buffer The output terminal is connected to the input terminal of the second buffer, the output terminal of the nth buffer is connected to the input terminal of the n+1th buffer, N and n are positive integers, n is greater than 1 and less than N; N latches A chain of latches, each chain of latches includes M latches, the clock input of each latch is connected to the clock signal, and the data input of the first latch of each chain of latches Connect to the output end of a buffer corresponding to the N buffers, the data output end of the first latch is connected to the data input end of the second latch, and the data output end of the mth latch is connected to To the data input terminal of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, and the power input terminal VDD of each latch is connected to the power supply network of the integrated circuit to detect the power supply voltage area, the ground terminal of each latch is connected to ground.

According to one or more embodiments of the present disclosure, there is provided a power supply voltage detection method, including: providing a power supply voltage detector, including a buffer string, including N buffers, wherein the input end of the first buffer is connected to the clock Signal, the output of the first buffer is connected to the input of the second buffer, the output of the nth buffer is connected to the input of the n+1th buffer, N and n are positive integers, and n is greater than 1 and less than N; N latch chains, each latch chain includes M latches, the clock pulse input of each latch is connected to the clock signal, the first latch of each latch chain latch The data input terminal of the latch is connected to the output terminal of a buffer corresponding to the N buffers, the data output terminal of the first latch is connected to the data input terminal of the second latch, and the mth latch The data output terminal of the latch is connected to the data input terminal of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, and the power input terminal VDD of each latch is connected to the power supply network of the integrated circuit In the region where the supply voltage is to be sensed in the circuit, the ground terminal of each latch is connected to the ground; and the data output of each latch is detected to determine the power supply voltage of the region where the power supply voltage is to be sensed in the integrated circuit power network size.

According to one or more embodiments of the present disclosure, there is provided a computer-readable medium on which a computer program is stored, wherein the program implements the power supply voltage detection method of the present disclosure when executed by a processor.

Compared with the prior art, the advantages of the technical solution of the present application include but are not limited to: 1. Compared with the use of digital-to-analog conversion circuits, resistors and capacitors, etc., this structure uses a pure digital structure, which can be realized by using the devices in the standard cell library , can be synthesized directly, and is very friendly to the integrated circuit design process; 2. This structure has a high response frequency, and can output a voltage detection result every clock cycle; 3. This structure has high detection accuracy, At a working frequency of 1.5GHz, a voltage change detection accuracy of about 6mV can be achieved; 4. This structure can adapt to different working frequencies without using additional delay adjustment circuits; The design of the original integrated circuit has very little influence; 6. All latch circuits in this structure and other nearby latch circuits are connected to the same power supply network, without special access to the ideal power supply, which is easy to install after the integrated circuit terminal integration.

H1: Processor

H2: storage medium

H3: data bus

H4: I/O bus bar

11: Intellectual property core

12: Intellectual property core

13: Customized circuit

21: Supply voltage detector

22:Voltage regulation module

23: Power network

100: integrated circuit chip

101: Power supply voltage detection device

102: Power supply voltage detection device

103: Power supply voltage detection device

104: Power supply voltage detection device

105: Power supply voltage detection device

106: Power supply voltage detection device

107: Power supply voltage detection device

200: power supply voltage detection device

201: buffer string

202: N latch chains

500: Power supply voltage detection method

501, 502, 503: steps

5021, 5022: steps

5021', 5022', 5023', 5024': steps

50221', 50222', 50223', 50224': steps

1010: instruction

1020: computer-readable storage medium

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only the present invention. For some disclosed embodiments, those skilled in the art can also obtain other drawings based on these drawings without any creative work.

FIG. 1 shows a block diagram of a supply voltage detection system according to an embodiment of the present disclosure.

Fig. 2 shows a block diagram of a power supply voltage detection device according to an embodiment of the present disclosure.

FIG. 3 shows a schematic diagram of the structure of a supply voltage detector according to an embodiment of the present disclosure.

FIG. 4 shows a timing diagram of a clock signal and an input signal at a data input terminal of each latch in a latch chain according to an embodiment of the disclosure.

Fig. 5 shows a flowchart of a method for detecting a power supply voltage according to an embodiment of the present disclosure.

FIG. 6A shows an embodiment of the step of detecting the data output of each latch to determine the magnitude of the supply voltage in the area where the supply voltage is to be detected in the integrated circuit power network according to an embodiment of the present disclosure.

FIG. 6B shows detecting the data output of each latch to determine the supply voltage of the area in the integrated circuit power network to detect the supply voltage according to an embodiment of the present disclosure. Another example of pressing the size step.

FIG. 7 shows, according to an embodiment of the present disclosure, according to the logic value strings of the plurality of latch chains and the time length of the high potential of the clock signal, the respective latches in the plurality of latch chains are obtained. A flow chart of specific steps in the steps of the delay range.

Fig. 8 shows a flowchart of a power supply voltage detection method according to another embodiment of the present disclosure.

Figure 9 shows a block diagram of an exemplary computer system suitable for implementing embodiments of the present disclosure.

FIG. 10 shows a schematic diagram of a non-transitory computer readable storage medium according to an embodiment of the disclosure.

FIG. 11A and FIG. 11B respectively show the representations of the value ranges of x and y obtained by the range constraints of the four latch chains and the range constraint of the first latch chain on the two-dimensional coordinate axes.

Reference will now be made in detail to specific embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. While the disclosure will be described in conjunction with specific embodiments, it will be understood that it is not intended to limit the disclosure to the described embodiments. On the contrary, it is intended to cover alterations, modifications, and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims. It should be noted that the method steps described here can all be realized by any functional block or functional arrangement, and any functional block or functional arrangement can be realized as a physical entity or a logical entity, or a combination of both.

FIG. 1 shows a block diagram of a supply voltage detection system according to an embodiment of the present disclosure. The supply voltage detection system comprises supply voltage detection devices 101 , 102 , .

The supply voltage detection devices 101, 102, . . . , X connected to multiple areas can be distributed in different areas of the power network inside the integrated circuit chip 100, and can detect voltage fluctuations in each area in real time. These areas may include intellectual property cores (IP cores) 11, 12 and different areas in the customized circuit 13, etc. Generally speaking, if the IP core is relatively large, the area that is often used is more likely to be disturbed by power noise, and a power supply voltage detection device can be connected to this area. Alternatively, the areas where the power supply voltage detection devices are distributed can be obtained through prior simulation. Through the simulation, it is known which areas have higher workloads and may have larger voltage drops, and then the power supply voltage detection devices are connected to these areas.

FIG. 2 shows a block diagram of a power supply voltage detection device 200 according to an embodiment of the present disclosure.

The power supply voltage detection device 200 is connected to the integrated circuit power network 23 and includes: a power supply voltage detector 21 and a voltage regulation module 22 .

The supply voltage detector 21 includes a buffer string 201, including N buffers, wherein the input end of the first buffer is connected to the clock signal, and the output end of the first buffer is connected to the input end of the second buffer. , the output end of the nth buffer is connected to the input end of the n+1th buffer, N, n are positive integers, n is greater than 1 and less than N; N latch chains 202, each latch chain includes M latches, the clock input of each latch is connected to the clock signal, and the first latch of each latch chain The data input terminal is connected to the output terminal of a buffer corresponding to the N buffers, the data output terminal of the first latch is connected to the data input terminal of the second latch, and the data input terminal of the mth latch The output terminal is connected to the data input terminal of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, and the power input terminal VDD of each latch is connected to the integrated circuit power supply network 23 To detect the area of the supply voltage, the ground terminal of each latch is connected to ground.

The voltage regulation module 22 is connected to the data output terminal of each latch of each latch chain, and is configured to detect the data output of each latch to determine the power supply voltage to be detected in the integrated circuit power network 23 The size of the supply voltage of the area.

The structure of the power supply voltage detector 21 mainly uses a digital circuit device such as a latch to realize indirect measurement of the power supply voltage of the integrated circuit. A latch is a potential-sensitive storage unit circuit. When the latch is enabled by the trigger potential, the output will change with the input. When the enabling signal ends, the latch will store the enabling signal , until the next enable. The time delay from the data input terminal (D terminal) to the data output terminal (Q terminal) of the latch is also affected by the supply voltage.

FIG. 3 shows a schematic diagram of the structure of the supply voltage detector 21 according to an embodiment of the present disclosure.

As shown in FIG. 3 , the supply voltage detector 21 includes a buffer string 201 including N buffers. The supply voltage detector 21 also includes N latch chains 202 .

Among the N buffers, the input terminal of the first buffer is connected to the clock signal. The output of the first buffer is connected to the input of the second buffer. The output of the first buffer is also connected to the first latch in the first latch chain The data input terminal (D terminal) of the device. Here, the first buffer before the data input of the first latch can delay the clock signal by a delay time of the buffer, and then input it to the data input of the first latch as a data Input signal, this is to stagger the rising edge of the data input signal of the first latch and the clock enable signal, so as to avoid metastability due to insufficient setup time.

The output of the second buffer is connected to the input of the third buffer, and so on, the output of the nth buffer is connected to the input of the n+1th buffer, N and n are positive integers, n is greater than 1 and less than N. The output terminal of the Nth buffer is connected to the data input terminal (D terminal) of the first latch in the Nth latch chain.

In the N latch chains 202, each latch chain includes M latches, the clock input end (CLK end) of each latch is connected to the clock signal, and each latch chain The data input terminal (D terminal) of the first latch is connected to the output terminal of a buffer corresponding to the N buffers, and the data output terminal (Q terminal) of the first latch is connected to the second latch The data input terminal (D terminal) of the latch, the data output terminal (Q terminal) of the mth latch is connected to the data input terminal (D terminal) of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, the power input terminal VDD of each latch is connected to the area where the power supply voltage is to be detected in the integrated circuit power network 23 , and the ground terminal (GND) of each latch is connected to ground.

That is, in a chain of latches, the clock input terminals of all latches are connected to the clock signal, and the same clock signal is connected to the first latch through a buffer (here, The data input of the first latch is the one closest to the buffer), the data output of the first latch and the data of the second latch The data input terminal of the second latch is connected to the data input terminal of the third latch, and so on, the data output terminal of the m-1th latch is connected to the mth latch The data input end of the latch is connected, the data output end of the mth latch is connected to the data input end of the m+1th latch... . The data output terminal of each latch is connected with the voltage regulation module.

In one embodiment, N is the rounded up result of dividing the latency of a single latch by the latency of a single buffer. The value of N is to consider how many buffers the clock signal can pass through within the delay of a latch. In one embodiment, M is greater than or equal to 1 times the period of the clock signal divided by the delay of a single latch. In a more preferred embodiment, M is greater than or equal to 1.5 times the period of the clock signal divided by the delay of a single latch. The larger the value of M, the specific range of the transmission delay of the input signal in the latch chain can be seen. Assuming that the time delay of a latch at normal voltage (or rated voltage) is about 100ps, and that of a buffer at normal voltage (or rated voltage) is about 30ps, then N=4 and M=10.

Note that the RSTB reset terminal of each latch can receive a reset signal to reset the latch. The QN end of each latch outputs a signal opposite to the signal output by the data output end Q, which can be suspended.

Observation found that the level of voltage will affect the delay of the latch. In the case of lower than normal voltage, the delay of the latch will become longer, which may cause it to fail to work. At higher than normal voltages, the latch has a short delay and high power consumption. So consider using a latch chain in which the clock signal can propagate within one clock cycle The number of latches is used to detect the magnitude of the voltage, whether the voltage has dropped or increased compared to the normal voltage (or a certain predetermined voltage).

In one embodiment, the voltage regulating module obtains a logical value according to the comparison between the data output of each latch and a reference potential to obtain a logical value string of each latch chain.

In one embodiment, if the data output of the latch is higher than the reference potential, the logical value is a first value, and if the data output of the latch is lower than the reference potential, the logical value is a second value.

FIG. 4 shows a timing diagram of a clock signal and an input signal at a data input terminal of each latch in a latch chain according to an embodiment of the disclosure.

If so, these latches are enabled high. When the clock signal (clk) is at a high potential, the clock signal can be transmitted from the data input end of the latch, and then pass through the data input end of the first, second...pth latch until the clock The pulse signal becomes low potential. At this time, the value stored and output by the first p latches is high potential, that is, higher than or equal to the reference potential, which is logic '1' (the first value is 1), and then (m-p) The value stored and output by each latch is a low potential, ie lower than the reference potential, which is logic '0' (the second value is 0). That is, the output potentials of the data output terminals of the first p latches are higher than or equal to the reference potential, and the output potentials of the data output terminals of the next (m-p) latches are lower than the reference potential. The logical value string of the latch chain is a string of p 1s and (m-p) 0s.

When the supply voltage of the latch chain fluctuates, the delay of the latch will also fluctuate. When the voltage is lower than the normal voltage, the delay of the latch will become longer. At higher than normal voltages, the latency of the latch becomes shorter. Therefore, for the same clock signal, the number p of latches storing logic '1' after one measurement will also vary. For example, when the voltage is 1.05V and higher than 1V, the delay of the latch becomes shorter, and the more latches the clock signal can propagate in one clock cycle, p is 8; and when the voltage is 0.9V , When it is lower than 1V, the delay of the latch becomes longer, and the fewer latches the clock signal can propagate in one clock cycle, p is 4. Therefore, in the present application, the quantity of the first value in the logical value string composed of the output values of each latch in a latch chain, that is, the change of p can indirectly reflect the change of the supply voltage.

In one embodiment, the voltage regulation module determines the power supply network of the integrated circuit according to the relationship between the logical value strings of the N latch chains and the value of the logical value strings of the N latch chains and the magnitude of the supply voltage. The magnitude of the power supply voltage in the area where the power supply voltage is to be detected on the road. In one embodiment, the relationship between the values of the logical value strings of the N latch chains and the magnitude of the power supply voltage is obtained through experimental measurement.

That is to say, since it is known that when the supply voltage of the latch chain fluctuates, the delay of the latches will also fluctuate accordingly, which will lead to a logic composed of the output values of each latch in a latch chain The number of the first value in the numerical string, that is, the change of p, so it is possible to measure the relationship between the value of p in each of the N latch chains and the voltage through a series of experiments . For example, by inputting low voltage, 0.9V, 0.95V, etc. into the latch chains respectively, the value of p in each of the N latch chains under different low voltages can be obtained respectively. The same goes for high voltage. A mapping table between the magnitude of the voltage and the value of p in each of the N latch chains can be obtained. In this way, the logical value strings of N latch chains, and the relationship between the values of the logical value strings of the N latch chains and the magnitude of the power supply voltage (for example, to realize the generated mapping table), determine the power supply voltage in the area where the power supply voltage is to be detected in the integrated circuit power network, or The magnitude of the voltage droop is obtained directly.

Alternatively, in another embodiment, the voltage regulation module obtains the respective latches in the plurality of latch chains according to the logic value strings of the plurality of latch chains and the time length of the high potential of the clock signal The delay range of the latch; according to the delay range of each latch in multiple latch chains, the actual delay range of a single latch is obtained; according to the actual delay range of a single latch and the size of the supply voltage To determine the magnitude of the power supply voltage in the area where the power supply voltage is to be detected in the integrated circuit power supply network.

Firstly, according to the logic value strings of the multiple latch chains and the time length of the high potential of the clock signal, the delay ranges of the respective latches in the multiple latch chains can be obtained in the following manner.

In the first embodiment, the voltage regulation module is configured to obtain each of the plurality of latch chains according to the logic value strings of the plurality of latch chains and the time length of the high potential of the clock signal through the following steps: The delay range of the latch: determine the number of the first value in the logical value string in a predetermined chain of latches; determine the buffer that exists between a predetermined chain of latches and the input clock signal The number of; determine the time length of the high potential of the clock signal is greater than the sum of the product of the number of buffers and the time delay of a single buffer and the product of the number of first values and the time delay of a single latch, and less than the sum of the The sum of the product of the number of buffers before the latch chain and the delay of a single buffer and the product of the delay of a single latch after adding 1 to the number of the first value; calculate the actual time of a single latch extended range.

Specifically, due to the relatively high delay of a single latch, if only a single latch chain is used for monitoring, the voltage detection accuracy will be relatively low, that is, the value of p can only be changed when the voltage changes greatly. . In order to improve monitoring accuracy, this application uses N latch chains, all latches are enabled with the same clock signal, so all latches have the same test time, that is, one clock cycle .

In addition, this clock signal is input to the data input terminals of the latches of the first latch chain through a buffer. This buffer is mainly used to avoid metastable states due to failure to meet the settling time of the latches. ; After that, it is input to the data input end of each latch of the second latch chain through the second buffer, and the data of each latch of the third latch chain is input through the third buffer The input end...is input to the data input end of each latch of the Nth latch chain through the Nth buffer. In this way, the input signal of each latch chain is sequentially delayed by one buffer delay.

Since the voltage level will bring the delay of the latch and the delay of the buffer, the following demonstrates the relationship between the time length of the high potential of the clock signal and the delay of the latch and the buffer , and the principle that adopting N latch chains can bring higher detection accuracy.

Assuming that the power supply voltage of a certain value (such as 0.95V) is known, it is known that correspondingly, the delay of a latch is 100ps, and the delay of a buffer is 30ps, taking N=4, M= 10. After the clock signal enables the four latch chains once in one clock cycle, the logic values of the data stored in the four latch chains are 1111110000, 1111110000, 1111100000, 1111100000 respectively. then in a In the clock cycle, the actual transmission delay of the input signal (that is, the time length of the high potential of the clock signal) should meet the following conditions: For the first chain of latches, the actual propagation delay of the input signal (i.e., the length of time the clock signal is high) is greater than the number of buffers times the delay of a single buffer multiplied by the first value and the delay of a single latch (ie >6*100+1*30=630ps), and less than the product of the number of buffers before the latch chain and the delay of a single buffer and the first The sum of the product of the number of values plus 1 and the delay of a single latch; calculate the transmission delay of the input signal (ie <7*100+1*30=730ps), that is, between 630ps-730ps, for The second latch chain, the transmission delay of the input signal (that is, the time length of the high potential of the clock signal) (ie >6*100+2*30=660ps and <7*100+2*30=760ps ) between 660ps-760ps, for the third latch chain, the transfer delay of the input signal (that is, the time length of the high potential of the clock signal) (ie>5*100+3*30=590ps and < 6*100+3*30=690ps) between 590ps-690ps, for the fourth latch chain, the transmission delay of the input signal (ie, the time length of the high potential of the clock signal) (ie>5* 100+4*30=620ps and <6*100+4*30=720ps) between 620ps-720ps, because these four latches are connected to the same input signal, so the actual transmission time of the input signal can be judged The delay (that is, the time length of the high potential of the clock signal) is constrained by 4 ranges calculated for the 4 latch chains, that is, it is finally constrained between 660ps-690ps.

Therefore, the actual propagation delay (i.e., clock signal The time length of the high potential of the signal) accuracy (can be obtained, for example, between 660ps-690ps).

Of course, the above examples are just to illustrate the relationship between the delay of a single latch, the delay of a single buffer and the actual transmission delay of the input signal (ie, the time length of the high potential of the clock signal). However, the purpose of this application is to obtain the time delay of a single latch, so as to obtain the magnitude of the power supply voltage. Therefore, when the magnitude of the power supply voltage is unknown, and the time delay of a single latch and the time delay of the buffer are also unknown in the case of this power supply voltage, since the time length of the high potential of the input clock signal is known, The time delay range of a single latch can also be derived and obtained through the same formula and relationship as the above example.

Specifically, in actual test use, this application uses a fixed input signal (clock signal), that is, the time length of the high potential of the known input clock signal, by determining the length of the transmission path of the fixed input signal ( Corresponding to the time length of the high potential of the input clock signal), to determine the delay range of a single latch.

For example, assuming that the high-potential enable signal length of the clock signal (that is, the time length of the high potential) is 500ps (for example, a clock signal with a duty cycle of 1000ps and a duty cycle of 50%), the latch is still under normal voltage. The relationship between the delay and the delay of the buffer is taken as N=4, M=10, assuming that the delay of a single buffer under the current supply voltage is x, and the delay of a single latch is y (at this time, x, y Since the power supply voltage is not necessarily a normal voltage, it is uncertain), after the clock signal is enabled once (for a duration of high potential), the data stored in the four latch chains are 1111110000, 1111110000, 1111100000 , 1111100000.

According to the relationship obtained from the above example, it can be judged that for the first latch chain, x+5y<500ps<x+6y; for the second latch chain, 2x+5y<500ps<2x+6y; for For the third latch chain, 3x+4y<500ps<3x+5y; for the fourth latch chain, 4x+4y<500ps<4x+5y.

According to the range constraints of the above four latch chains, after transformation:

Where ^ is the logical AND function. Then transform to get:

can be obtained:

Wherein, the value ranges of x and y are represented on the two-dimensional coordinate axes as shown in FIG. 11A : obtained, the time delay y range of a single latch is 75ps<y<100ps.

In contrast, the constraints x+5y<500ps<x+6y and x>0 for the first latch chain yield only:

The value ranges of x and y are represented on the two-dimensional coordinate axes as shown in FIG. 11B : only the range of time delay y of a single latch on the first latch chain can be determined as 0ps<y<100ps.

Therefore, using multiple latch chains for testing can significantly improve the test obtained The precision of the time delay of a single latch.

The time delay of the latch will vary under different supply voltages. In one embodiment, the relationship between the actual delay range of a single latch and the power supply voltage can be obtained through experimental measurement. For example, by testing the output results of N latch chains under different supply voltages, the actual delay range of a single latch can be calculated, so that the tester can create a look-up data table to compare the actual delay range of a single latch. The extension range is mapped to the corresponding supply voltage. In actual use, the actual delay range of a single latch is calculated according to the output results of the N latch chains, and the current power supply voltage is deduced inversely according to the reference table, and the voltage adjustment unit is made to perform corresponding adjust.

In one embodiment, the voltage regulation module is configured to increase the supply voltage to compensate for voltage droop when the determined supply voltage is lower than a predetermined voltage, or increase the supply voltage when the determined supply voltage is higher than a predetermined voltage according to the magnitude of the determined supply voltage. Reduce the supply voltage to compensate for the voltage rise. That is to say, in this embodiment, the voltage regulation module can not only detect whether there is a voltage sag, but also increase the voltage of the region to compensate for the voltage sag according to the determined magnitude of the voltage sag. Of course, the voltage regulation module can also reduce the voltage to maintain the voltage at the target voltage according to the inferred power supply voltage being higher than the target voltage.

Note that the RSTB reset terminal of each latch can receive a reset signal to reset the latch.

In one embodiment, the N latch chains in the supply voltage detector are enabled at the rising edge of the clock signal, and output data at the falling edge of the clock signal. losing After the data is out, each latch is reset by resetting the signal. Then, it is enabled at the rising edge of the next clock signal, and the data is output and reset at the falling edge of the clock signal, and so on. In this structure, the test is performed when the clock pulse is at a high potential, and the test result is output when the clock pulse is at a low potential, and all latches are reset to wait for the next test.

If in order to improve the response speed, two sets of latch chains can be used to measure during the high potential and low potential of the clock respectively, and then output the test results during the low potential and high potential of the clock to achieve output in each clock cycle Two test results. This enables the detection of voltage droop pulses or voltage rise pulses of very short duration. That is, in an alternative embodiment, the supply voltage detector further includes another N latch chains having the same structure as the N latch chains and another N buffers, and the rising edge of the clock signal N latches can be chained, and data can be output on the falling edge of the clock signal. Then, after outputting the data, the latches of the N latch chains are reset through a reset signal. And the other N latch chains are enabled at the falling edge of the clock signal, and data are output at the rising edge of the clock signal. Then, reset the latches of the other N latch chains by resetting the signal after outputting the data.

Compared with the prior art, the advantages of the technical solution of the present application include but are not limited to: 1. Compared with the use of digital-to-analog conversion circuits, resistors and capacitors, etc., this structure uses a pure digital structure, which can be realized by using the devices in the standard cell library , can be synthesized directly, and is very friendly to the integrated circuit design process; 2. This structure has a high response frequency, and can output a voltage detection result every clock cycle; 3. This structure has high detection accuracy, At 1.5GHz operating frequency, about 6mV of Voltage change detection accuracy; 4. This structure can adapt to different operating frequencies without using additional delay adjustment circuits; 5. This structure only requires a very small area overhead, which has little impact on the original integrated circuit design; 6. This structure All the latch circuits in the circuit and other nearby latch circuits are connected to the same power supply network, no special connection to the ideal power supply is required, and it is easy to integrate at the back end of the integrated circuit.

FIG. 5 shows a flowchart of a method 500 for detecting a power supply voltage according to an embodiment of the present disclosure. The method 500 includes: step 501, providing a power supply voltage detector, including a buffer string, including N buffers, wherein the input end of the first buffer is connected to the clock signal, and the output end of the first buffer is connected to The input end of the second buffer, the output end of the nth buffer is connected to the input end of the n+1th buffer, N, n are positive integers, n is greater than 1 and less than N; N latch chains, Each latch chain includes M latches, the clock input of each latch is connected to the clock signal, and the data input of the first latch of each latch chain is connected to N The output end of a corresponding buffer in the buffer, the data output end of the first latch is connected to the data input end of the second latch, and the data output end of the mth latch is connected to the m+th The data input terminals of one latch, M and m are positive integers, m is greater than 1 and less than M, and the power input terminal VDD of each latch is connected to the area where the power supply voltage is to be detected in the power supply network of the integrated circuit. The ground terminal of each latch is connected to the ground; and step 502, detecting the data output of each latch to determine the magnitude of the supply voltage in the area where the supply voltage is to be detected in the integrated circuit power network.

Here, the first buffer before the data input end of the first latch can delay the clock signal by a delay time of the buffer, and then input it to the first The data input terminal of the first latch is used as the data input signal, which is to stagger the rising edge of the data input signal of the first latch and the clock enable signal, so as to avoid metastability due to insufficient setup time.

Note that the RSTB reset terminal of each latch can receive a reset signal to reset the latch. The QN terminal of each latch is floating.

In this way, the magnitude of the power supply voltage in the region where the power supply voltage is to be detected in the integrated circuit power network can be determined by detecting the data output of each latch. Compared with the use of digital-to-analog conversion circuits, resistors and capacitors, etc., this structure uses a pure digital structure, which can be realized by using the devices in the standard cell library, and can be directly synthesized. It is very friendly to the design process of integrated circuits. With a high response frequency, a voltage detection result can be output every clock cycle; this structure has high detection accuracy, and can achieve a voltage change detection accuracy of about 6mV at a working frequency of 1.5GHz; this structure can adapt to different There is no need to use an additional delay adjustment circuit; this structure only requires a very small area cost, and has little impact on the original integrated circuit design. All latch circuits in this structure and other nearby latch circuits are connected to the same power supply network, without special connection to an ideal power supply, and are easy to integrate at the back end of the integrated circuit.

In one embodiment, the relationship between the actual delay range of a single latch and the magnitude of the power supply voltage is obtained through experimental measurement, or the relationship between the values of the logic value strings of the N latch chains and the magnitude of the power supply voltage is obtained through experiments measured.

In one embodiment, N is the rounded up result of dividing the latency of a single latch by the latency of a single buffer.

In one embodiment, M is greater than or equal to the period of the clock signal divided by a single The result of the delay of a latch is more than 1 times.

In one embodiment, M is greater than or equal to 1.5 times the period of the clock signal divided by the delay of a single latch.

Assuming that the power supply voltage of a certain value is known, it is known that correspondingly, the time delay of a latch is 100 ps, and the time delay of a buffer is 30 ps, N=4, M=10.

FIG. 6A shows an embodiment of the step of detecting the data output of each latch to determine the magnitude 502 of the power supply voltage in the region where the power supply voltage is to be detected in the IC power network according to an embodiment of the present disclosure.

In this embodiment, the step of detecting the data output of each latch to determine the magnitude 502 of the power supply voltage in the area where the power supply voltage is to be detected in the integrated circuit power network includes: Step 5021, according to the output of each latch Comparing the data output with the reference potential to obtain a logical value to obtain a logical value string of each latch chain; step 5022, according to the logical value string of the N latch chains and the logical value string of the N latch chains The relationship between the value and the magnitude of the power supply voltage determines the magnitude of the power supply voltage in the area where the power supply voltage is to be detected in the integrated circuit power network.

In one embodiment, if the data output of the latch is higher than the reference potential, the logical value is a first value, and if the data output of the latch is lower than the reference potential, the logical value is a second value. For example, the data output of the latch is higher than or equal to the reference potential, which is a logic '1' (the first value is 1), and the data output of the latch is lower than the reference potential, which is a logic '0' (the second value is 0).

After the clock signal enables the chain of 4 latches once in a clock cycle, the 4 The logical values of the data stored in the latch chains are 1111110000, 1111110000, 1111100000, 1111100000 respectively. If the relationship between the value of the logical value string of the N latch chains and the magnitude of the supply voltage is obtained through experimental measurement, for example, the logical values of the data stored in the four latch chains have been obtained through experimental measurement in advance. 1111110000, 1111110000, 1111100000, 1111100000, the power supply voltage is 0.95V.

In this way, the integrated circuit power supply can be determined directly according to the relationship between the logical value strings 1111110000, 1111110000, 1111100000, 1111100000 of the N latch chains and the value of the logical value strings of the N latch chains and the power supply voltage The magnitude of the power supply voltage in the area where the power supply voltage is to be detected in the network is 0.95V. The program is convenient and quick.

FIG. 6B shows another embodiment of the step 502 of detecting the data output of each latch to determine the magnitude of the supply voltage in the area where the supply voltage is to be detected in the IC power network according to an embodiment of the present disclosure.

In this embodiment, the step of detecting the data output of each latch to determine the magnitude 502 of the power supply voltage in the area where the power supply voltage is to be detected in the integrated circuit power network includes: step 5021', according to each latch Comparing the data output of the data output with the reference potential to obtain a logic value to obtain a logic value string of each latch chain; step 5022', according to the logic value string of multiple latch chains and the time length of the high potential of the clock signal , to obtain the delay range of each latch in multiple latch chains; Step 5023', according to the delay range of each latch in multiple latch chains, obtain the actual delay range of a single latch; Step 5024', according to a single latch The relationship between the actual delay range of the device and the size of the power supply voltage determines the size of the power supply voltage in the area where the power supply voltage is to be detected in the integrated circuit power network.

FIG. 7 shows, according to an embodiment of the present disclosure, according to the logic value strings of the plurality of latch chains and the time length of the high potential of the clock signal, the respective latches in the plurality of latch chains are obtained. A flow chart of the specific steps of the steps in the delay range 5022'.

The step 5022' of obtaining the delay ranges of the respective latches in the plurality of latch chains according to the logic value strings of the plurality of latch chains and the time length of the high potential of the clock signal includes: step 50221', Determine the number of first values in the logical value string in a predetermined chain of latches; step 50222', determine the number of buffers existing between a predetermined chain of latches and the input clock signal; step 50223 ', determine that the time length of the high potential of the clock signal is greater than the sum of the product of the number of buffers and the time delay of a single buffer and the product of the number of first values and the time delay of a single latch, and is less than the sum of the product of the number of buffers and the time delay of a single latch The sum of the product of the number of buffers before the locker chain and the time delay of a single buffer and the product of the time delay of a single latch after the number of the first value is added to 1; step 50224', calculate and obtain a single latch the actual delay range.

For example, suppose the length of the high potential enabling signal (ie, the time length of the high potential) of the clock signal is 500 ps. N=4, M=10, assuming that the time delay of a single buffer under the current supply voltage is x, and the time delay of a single latch is y. After the clock signal is enabled once (for a duration of high potential), the data stored in the four latch chains are 1111110000, 1111110000, 1111100000, 1111100000 respectively.

Then according to the relationship obtained in the above example, it can be judged that for the first latch For the latch chain, x+5y<500ps<x+6y; for the second latch chain, 2x+5y<500ps<2x+6y; for the third latch chain, 3x+4y<500ps<3x+ 5y; for the fourth latch chain, 4x+4y<500ps<4x+5y.

The range of time delay y obtained for a single latch is 75ps<y<100ps.

If the relationship between the actual delay range of a single latch and the power supply voltage is obtained through experimental measurement, for example, when the actual delay range of a single latch is 75ps<y<100ps, the power supply voltage is 0.95V, then According to the relationship between the actual time delay range of a single latch and the power supply voltage, the power supply voltage of the area to detect the power supply voltage in the integrated circuit power network can be determined to be 0.95V. This method is convenient and quick.

FIG. 8 shows a flowchart of a power supply voltage detection method 500 according to another embodiment of the present disclosure.

In this embodiment, in addition to steps 501 and 502, the power supply voltage detection method 500 may further include: step 503, according to the magnitude of the determined power supply voltage, when the determined power supply voltage is lower than a predetermined voltage, the power supply voltage is increased to compensate the voltage Drooping, or reducing the supply voltage to compensate for the voltage rise when the determined supply voltage is higher than a predetermined voltage.

In this way, not only the magnitude of the power supply voltage can be detected, but also voltage regulation can be performed according to the magnitude relationship between the power supply voltage and the predetermined voltage to stabilize the power supply voltage at the predetermined voltage. Of course, this solution is not limited thereto, and other voltage adjustments may be performed after the magnitude of the power supply voltage is detected, or other processing may be performed using the magnitude of the power supply voltage, which will not be detailed here.

In one embodiment, the chain of N latches in the supply voltage detector is enabled on the rising edge of the clock signal, and outputs data and resets on the falling edge of the clock signal. In this way, within one clock cycle, detection and output can be performed once.

Or, in another embodiment, the power supply voltage detector further includes another N latch chains and another N buffers having the same structure as the N latch chains, and the rising edge of the clock signal corresponds to Enable N latch chains, and output data and reset on the falling edge of the clock signal, and enable another N latch chains on the falling edge of the clock signal, and output data and reset on the rising edge of the clock signal Certainly. In this way, two sets of latch chains are used to measure during the high potential and low potential of the clock respectively, and then output the test results during the low potential and high potential of the clock, so as to output two test results in each clock cycle, The response speed can be improved, and the detection of voltage sag pulses or voltage rising pulses with a short duration can also be realized.

In short, the advantages of the technical solution of the present application compared with the prior art include but are not limited to: 1. Compared with the use of digital-to-analog conversion circuits, resistors and capacitors, etc., this structure uses a pure digital structure, using the devices in the standard cell library, namely Realizable, can be synthesized directly, and is very friendly to the integrated circuit design process; 2. This structure has a high response frequency, and can output a voltage detection result every clock cycle; 3. This structure has a high detection Accuracy, at a working frequency of 1.5GHz, a voltage change detection accuracy of about 6mV can be achieved; 4. This structure can adapt to different operating frequencies without using additional delay adjustment circuits; 5. This structure only requires a very small area overhead , has little impact on the design of the original integrated circuit; 6. All latch circuits in this structure and other nearby latch circuits are connected to the same power supply network, and there is no need to connect to the ideal circuit source, easy to integrate in the back end of the integrated circuit.

Figure 9 shows a block diagram of an exemplary computer system suitable for implementing embodiments of the present disclosure.

The computer system may include a processor (H1); a memory (H2) coupled to the processor (H1) and storing therein computer-executable instructions for performing various methods of embodiments of the present disclosure when executed by the processor A step of.

The processor ( H1 ) may include but not limited to, for example, one or more processors or microprocessors and the like.

The memory (H2) may include, but is not limited to, for example, random access memory (RAM), read only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, computer storage media (such as hard disk, floppy disk, solid state drive, removable disk, CD-ROM, DVD-ROM, Blu-ray, etc.).

In addition, the computer system may also include a data bus (H3), an input/output (I/O) bus (H4), a display (H5) and an input/output device (H6) (for example, a keyboard, a slider mouse, speakers, etc.) etc.

The processor (H1) can communicate with external devices (H5, H6, etc.) via a wired or wireless network (not shown) through the I/O bus (H4).

The memory (H2) can also store at least one computer-executable instruction for executing various functions and/or method steps in the embodiments described in the present technology when executed by the processor (H1).

In one embodiment, the at least one computer-executable instruction can also be compiled or constitute a power supply voltage detection software product, wherein the one or more When the computer-executable instructions are executed by the processor, various functions and/or method steps in the embodiments described in the present technology are executed.

FIG. 10 shows a schematic diagram of a non-transitory computer readable storage medium according to an embodiment of the disclosure.

As shown in FIG. 10 , instructions are stored on a computer-readable storage medium 1020 , such as computer-readable instructions 1010 . When the computer-readable instructions 1010 are executed by the processor, the power supply voltage detecting method described with reference to the above figures can be executed. Computer readable storage media include, but are not limited to, volatile memory and/or nonvolatile memory, for example. The volatile memory may include random access memory (RAM) and/or cache memory (cache), etc., for example. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, and the like. For example, the computer-readable storage medium 1020 can be connected to a computing device such as a computer, and then, when the computing device executes the computer-readable instructions 1010 stored on the computer-readable storage medium 1020, the power supply voltage as described above can be performed. Detection method.

Of course, the above specific embodiments are only examples and not limiting, and those skilled in the art can combine and combine some steps and devices from the above separately described embodiments according to the concept of the present disclosure to realize the effect of the present disclosure. Embodiments formed by combinations and combinations are also included in the present disclosure, and such combinations and combinations are not described here one by one.

Note that the advantages, advantages, effects, etc. mentioned in the present disclosure are only examples rather than limitations, and it cannot be considered that these advantages, advantages, effects, etc. must be possessed by each embodiment of the present disclosure. In addition, the specific details disclosed above are for illustrative purposes only. For purposes of convenience and understanding, rather than limitation, the above details do not limit the present disclosure to be practiced using the above specific details.

According to one or more embodiments of the present disclosure, there is provided a supply voltage detection device connected to an integrated circuit power grid, comprising: a supply voltage detector including a buffer string including N buffers, wherein the first buffer The input terminal of the buffer is connected to the clock signal, the output terminal of the first buffer is connected to the input terminal of the second buffer, the output terminal of the nth buffer is connected to the input terminal of the n+1th buffer, N and n are positive integers, n is greater than 1 and less than N; N latch chains, each latch chain includes M latches, and the clock input terminal of each latch is connected to the clock signal, each The data input terminal of the first latch of the latch chain is connected to the output terminal of a buffer corresponding to the N buffers, and the data output terminal of the first latch is connected to the second latch The data input terminal of the mth latch is connected to the data input terminal of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, the power supply of each latch The input terminal VDD is connected to the area in the integrated circuit power network where the supply voltage is to be sensed, the ground terminal of each latch is connected to ground; and the voltage regulation module is connected to each latch of each latch chain The data output terminal of the latch is configured to detect the data output of each latch to determine the magnitude of the supply voltage in the area where the supply voltage is to be detected in the integrated circuit power network.

In one embodiment, the voltage regulation module is configured to: obtain a logical value according to a comparison between the data output of each latch and a reference potential to obtain a logical value string of each latch chain; The relationship between the logical value string of the chain and the value of the logical value string of the N latch chains and the size of the supply voltage determines the integrated body The magnitude of the power supply voltage in the area where the power supply voltage is to be detected in the circuit power supply network; or the voltage regulation module is configured to: obtain a logic value according to the comparison between the data output of each latch and the reference potential to obtain each latch The logic value string of the chain; according to the logic value string of the multiple latch chains and the time length of the high potential of the clock signal, the delay range of each latch in the multiple latch chains is obtained; according to the multiple According to the delay range of each latch in the latch chain, the actual delay range of a single latch is obtained; according to the relationship between the actual delay range of a single latch and the power supply voltage, the power supply network of the integrated circuit is determined The magnitude of the power supply voltage in the area where the power supply voltage is to be detected on the road.

In one embodiment, if the data output of the latch is higher than the reference potential, the logic value is a first value, and if the data output of the latch is lower than the reference potential, the logic value is a second value, and the voltage regulation module It is configured to obtain the delay ranges of the respective latches in the plurality of latch chains according to the logic value strings of the plurality of latch chains and the time length of the high potential of the clock signal through the following steps: determine the predetermined The number of the first value in the logical value string in a chain of latches; the number of buffers that exist between a predetermined chain of latches and the input clock signal; the number of high potentials of the clock signal The time length is greater than the sum of the product of the number of buffers and the time delay of a single buffer and the product of the number of the first value and the time delay of a single latch, and is less than the number of buffers before the chain of latches and The sum of the product of the time delay of a single buffer and the product of the time delay of a single latch after adding 1 to the number of the first value; the actual time delay range of a single latch is obtained by calculation.

In one embodiment, the voltage regulation module is configured to: according to the determined The magnitude of the supply voltage. When the determined supply voltage is lower than the predetermined voltage, the supply voltage is increased to compensate for voltage droop, or when the determined supply voltage is higher than the predetermined voltage, the supply voltage is decreased to compensate for voltage rise.

In one embodiment, the relationship between the actual delay range of a single latch and the magnitude of the power supply voltage is obtained through experimental measurement, or the relationship between the values of the logic value strings of the N latch chains and the magnitude of the power supply voltage is obtained through experiments measured.

In one embodiment, N is the rounded up result of dividing the latency of a single latch by the latency of a single buffer.

In one embodiment, M is greater than or equal to 1 times the period of the clock signal divided by the delay of a single latch.

In one embodiment, M is greater than or equal to 1.5 times the period of the clock signal divided by the delay of a single latch.

In one embodiment, the N latch chains in the supply voltage detector are enabled at the rising edge of the clock signal, and output data and reset at the falling edge of the clock signal; or the supply voltage detector further includes The N latch chains have another N latch chains and another N buffers with the same structure, and the N latch chains are enabled on the rising edge of the clock signal and output on the falling edge of the clock signal The data is reset, and the other N latch chains are enabled on the falling edge of the clock signal, and the data is output and reset on the rising edge of the clock signal.

According to one or more embodiments of the present disclosure, there is provided a supply voltage detection system, comprising: a plurality of supply voltage detection devices according to the embodiments of the present disclosure connected to multiple regions of an integrated circuit power network.

According to one or more embodiments of the present disclosure, there is provided a supply voltage detector, including a buffer string, including N buffers, wherein the input end of the first buffer is connected to the clock signal, and the input end of the first buffer The output terminal is connected to the input terminal of the second buffer, the output terminal of the nth buffer is connected to the input terminal of the n+1th buffer, N and n are positive integers, n is greater than 1 and less than N; N latches A chain of latches, each chain of latches includes M latches, the clock input of each latch is connected to the clock signal, and the data input of the first latch of each chain of latches Connect to the output end of a buffer corresponding to the N buffers, the data output end of the first latch is connected to the data input end of the second latch, and the data output end of the mth latch is connected to To the data input terminal of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, and the power input terminal VDD of each latch is connected to the power supply network of the integrated circuit to detect the power supply voltage area, the ground terminal of each latch is connected to ground.

According to one or more embodiments of the present disclosure, there is provided a power supply voltage detection method, including: providing a power supply voltage detector, including a buffer string, including N buffers, wherein the input end of the first buffer is connected to the clock Signal, the output of the first buffer is connected to the input of the second buffer, the output of the nth buffer is connected to the input of the n+1th buffer, N and n are positive integers, and n is greater than 1 and less than N; N latch chains, each latch chain includes M latches, the clock pulse input of each latch is connected to the clock signal, the first latch of each latch chain The data input end of the first latch is connected to the output end of a buffer corresponding to the N buffers, the data output end of the first latch is connected to the data input end of the second latch, and the mth The data output terminal of the latch is connected to the data input of the m+1th latch Input terminals, M and m are positive integers, m is greater than 1 and less than M, the power input terminal VDD of each latch is connected to the area where the power supply voltage is to be detected in the integrated circuit power network, and the ground terminal of each latch connected to ground; and sensing the data output of each latch to determine the magnitude of the supply voltage in the area of the integrated circuit power network where the supply voltage is to be sensed.

In one embodiment, detecting the data output of each latch to determine the magnitude of the supply voltage in the region where the supply voltage is to be detected in the power supply network of the integrated circuit includes: according to the relationship between the data output of each latch and the reference potential Compare the logical values obtained to obtain the logical value strings of each latch chain; according to the relationship between the logical value strings of N latch chains and the value of the logical value strings of N latch chains and the magnitude of the supply voltage , to determine the size of the supply voltage in the area where the supply voltage is to be detected in the integrated circuit power supply network.

Or, in another embodiment, detecting the data output of each latch to determine the magnitude of the power supply voltage in the area where the power supply voltage is to be detected in the integrated circuit power network includes: according to the data output of each latch and The comparison of the reference potential obtains the logical value to obtain the logical value string of each latch chain; according to the logical value string of multiple latch chains and the time length of the high potential of the clock signal, multiple latch chains are obtained The delay range of each latch in the chain; according to the delay range of each latch in multiple latch chains, the actual delay range of a single latch is obtained; according to the actual delay range of a single latch The relationship with the size of the power supply voltage determines the size of the power supply voltage in the area where the power supply voltage is to be detected in the integrated circuit power network.

In one embodiment, if the data output of the latch is higher than the reference potential High, the logic value is the first value, if the data output of the latch is lower than the reference potential, the logic value is the second value, the voltage regulation module is configured to follow the logic of multiple latch chains through the following steps Numerical strings, and the time length of the high potential of the clock signal, to obtain the delay range of each latch in multiple latch chains: determine the first value in the logical numerical string in a predetermined latch chain the number of buffers; determine the number of buffers that exist between a predetermined latch chain and the input clock signal; determine that the time length of the high potential of the clock signal is greater than the number of buffers and the delay of a single buffer The sum of the product and the product of the number of first values and the delay of a single latch is less than the product of the number of buffers before the latch chain and the delay of a single buffer and the number of first values plus 1 Afterwards, the sum of the products with the delay of a single latch; the actual delay range of a single latch is calculated.

In one embodiment, the method further includes: according to the magnitude of the determined power supply voltage, increasing the power supply voltage to compensate for voltage droop when the determined power supply voltage is lower than a predetermined voltage, or decreasing the power supply voltage when the determined power supply voltage is higher than a predetermined voltage supply voltage to compensate for voltage rise.

In one embodiment, the relationship between the actual delay range of a single latch and the magnitude of the power supply voltage is obtained through experimental measurement, or the relationship between the values of the logic value strings of the N latch chains and the magnitude of the power supply voltage is obtained through experiments measured.

In one embodiment, N is the rounded up result of dividing the latency of a single latch by the latency of a single buffer.

In one embodiment, M is greater than or equal to 1 times the period of the clock signal divided by the delay of a single latch.

In one embodiment, M is greater than or equal to 1.5 times the period of the clock signal divided by the delay of a single latch.

In one embodiment, the N latch chains in the supply voltage detector are enabled at the rising edge of the clock signal, and output data and reset at the falling edge of the clock signal; or the supply voltage detector further includes The N latch chains have another N latch chains and another N buffers with the same structure, and the N latch chains are enabled on the rising edge of the clock signal and output on the falling edge of the clock signal The data is reset, and the other N latch chains are enabled on the falling edge of the clock signal, and the data is output and reset on the rising edge of the clock signal.

According to one or more embodiments of the present disclosure, there is provided a computer-readable medium on which a computer program is stored, wherein the program implements the power supply voltage detection method of the present disclosure when executed by a processor.

The block diagrams of devices, devices, devices, and systems involved in the present disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, devices, devices, systems may be connected, arranged, configured in any manner. Words such as "including", "comprising", "having" and the like are open-ended words meaning "including but not limited to" and may be used interchangeably therewith. As used herein, the words "or" and "and" refer to the word "and/or" and are used interchangeably therewith, unless the context clearly dictates otherwise. As used herein, the word "such as" refers to and can be used interchangeably with the phrase "such as but not limited to".

The flow chart of the steps in the present disclosure and the description of the above methods are only illustrative examples and is not intended to require or imply that the steps of the various embodiments must be performed in the order presented. As will be appreciated by those skilled in the art, the order of the steps in the above embodiments may be performed in any order. Words such as "thereafter," "then," "next," etc. are not intended to limit the order of the steps; these words are simply used to guide the reader through the description of the methods. In addition, any reference to an element in the singular, eg, using the articles "a," "an," or "the," is not to be construed as limiting that element to the singular.

In addition, the steps and devices in the various embodiments herein are not limited to implementation in a certain embodiment, in fact, some steps and some devices related to the various embodiments herein can be combined according to the concepts of the present disclosure to New embodiments are contemplated and are within the scope of this disclosure.

Each operation of the method described above may be performed by any suitable means capable of performing the corresponding function. The means may include various hardware and/or software components and/or modules, including but not limited to hardware circuits, application specific integrated circuits (ASICs) or processors.

General purpose processors, digital signal processors (DSPs), ASICs, field programmable gate arrays (FPGAs) or other programmable logic devices (PLDs), discrete gates designed to perform the functions described herein may be utilized. Each of the illustrated logic blocks, modules, and circuits are implemented or described as being implemented or described as transistor logic, discrete hardware components, or any combination thereof. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices such as A combination of DSP and microprocessor, multiple microprocessors, microprocessors cooperating with DSP cores, or any other such configuration.

The steps of the method or algorithm described in connection with the present disclosure may be directly embedded in hardware, in a software module executed by a processor, or in a combination of the two. Software modules can exist in any form of tangible storage media. Some examples of storage media that may be used include random access memory (RAM), read only memory (ROM), flash memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD- ROM, etc. A storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. A software module may be a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media.

The methods disclosed herein include acts for implementing the described methods. The methods and/or acts may be interchanged with one another without departing from the scope of the claimed claims. In other words, unless a specific order of actions is specified, the order and/or use of specific actions may be modified without departing from the scope of what is claimed.

The above functions can be realized by hardware, software, firmware or any combination thereof. If implemented in software, the functions may be stored as instructions on a tangible computer-readable medium. A storage media may be any available tangible media that can be accessed by a computer. By way of example and not limitation, such computer readable media may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage, magnetic disk storage, or other magnetic memory devices or devices that may be used to carry or store instructions or data in the form of structures expected code and any other tangible medium that can be accessed by a computer. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital video disc (DVD), floppy disc, and blu-ray disc, where discs usually reproduce data magnetically and Disks use lasers to optically reproduce data.

Therefore, the computer program product can perform the operations given herein. For example, such a computer program product may be a computer-readable tangible medium having instructions tangibly stored (and/or encoded) thereon that are executable by a processor to perform the operations described herein. A computer program product may include packaging materials.

Software or instructions may also be transmitted via a transmission medium. For example, software may be transmitted from a website, server, or other remote source using a transmission medium such as coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, radio, or microwave.

In addition, modules and/or other appropriate means for performing the methods and techniques described herein may be downloaded and/or otherwise obtained by user terminals and/or base stations as appropriate. For example, such a device can be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, the various methods described herein may be provided via storage means (e.g., RAM, ROM, physical storage media such as CD or floppy disks), so that user terminals and/or base stations may be Various methods are obtained when providing storage parts. In addition, any other suitable technique for providing the methods and techniques described herein to a device may be utilized.

Other examples and implementations are within the scope and spirit of the disclosure and appended claims. For example, due to the nature of software, the functions described above can be used A software implementation executed by a processor, hardware, firmware, hardwiring, or any combination of these. Features implementing functions may also be physically located at various locations, including being distributed so that portions of functions are implemented at different physical locations. Also, as used herein, including in claims, the use of "or" in a listing of items beginning with "at least one" indicates separate listings such that, for example, "at least one of A, B, or C The enumeration of " means A or B or C, or AB or AC or BC, or ABC (ie A and B and C). Furthermore, the word "exemplary" does not mean that the described examples are preferred or better than other examples.

Various changes, substitutions and alterations to the techniques described herein may be made without departing from the teachings of the techniques as defined by the appended claims. Furthermore, the claimant scope of the present disclosure is not limited to specific aspects of the process, machine, manufacture, composition of matter, means, methods and acts described above. Any process, machine, manufacture, composition of matter, means, method or act, currently existing or later developed, which performs substantially the same function or achieves substantially the same result as the corresponding aspect described herein may be utilized. Accordingly, the appended claims include within their scope such process, machine, manufacture, composition of matter, means, method or acts.

The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the disclosed embodiments to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and subcombinations thereof.

21: Supply voltage detector

22:Voltage regulation module

23: Power network

200: power supply voltage detection device

201: buffer string

202: N latch chains

Claims (13)

A power supply voltage detection device connected to an integrated circuit power network, comprising: a buffer string including N buffers, wherein the input end of the first buffer is connected to a clock signal, and the first buffer's The output terminal is connected to the input terminal of the second buffer, the output terminal of the nth buffer is connected to the input terminal of the n+1th buffer, N and n are positive integers, n is greater than 1 and less than N; N latches A chain of latches, each chain of latches includes M latches, the clock input of each latch is connected to the clock signal, the data of the first latch of each chain of latches The input end is connected to the output end of a corresponding buffer in the N buffers, the data output end of the first latch is connected to the data input end of the second latch, and the mth latch The data output terminal of the device is connected to the data input terminal of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, and the power input terminal of each latch is connected to the integrated circuit power supply the region of the network where the supply voltage is to be sensed, the ground terminal of each latch connected to ground; and the voltage regulation module, connected to the data output terminal of each latch of each latch chain, configured as The data output of each latch is detected to determine the magnitude of the power supply voltage in the region where the power supply voltage is to be detected in the integrated circuit power network. The power supply voltage detection device according to claim 1, wherein the voltage regulation module is configured to: obtain a logic value according to a comparison between the data output of each latch and a reference potential to obtain the logic of each latch chain value string; According to the logical value strings of the N latch chains and the relationship between the value of the logical value strings of the N latch chains and the power supply voltage, determine the power supply network of the integrated circuit. The magnitude of the power supply voltage in the region where the power supply voltage is to be detected; or the voltage regulation module is configured to: obtain a logical value according to a comparison between the data output of each latch and the reference potential to obtain each latch chain a logical value string; according to the logical value strings of the multiple latch chains and the time length of the high potential of the clock signal, the delay ranges of the respective latches in the multiple latch chains are obtained; According to the delay range of each latch in the multiple latch chains, the actual delay range of a single latch is obtained; according to the actual delay range of the single latch and the size of the power supply voltage Determine the magnitude of the supply voltage in the area where the supply voltage is to be detected in the integrated circuit power supply network. The power supply voltage detection device according to claim 2, wherein if the data output of the latch is higher than the reference potential, the logic value is a first value, and if the data output of the latch is higher than the reference potential If the reference potential is low, the logical value is a second value, and the voltage regulation module is configured to perform the following steps according to the logical value strings of the plurality of latch chains and the high value of the clock signal The time length of the potential is obtained to obtain the delay range of each latch in the plurality of latch chains: determining the number of first values in the logical value string in a predetermined one latch chain; determining the number of buffers existing between the predetermined one latch chain and the input clock signal; determining the The time length of the high potential of the clock signal is greater than the sum of the product of the number of buffers and the time delay of a single buffer and the product of the number of first values and the time delay of a single latch, And less than the sum of the product of the number of buffers before the chain of latches and the time delay of the single buffer and the product of the number of the first value plus 1 and the time delay of the single latch ; Calculate the actual delay range of the single latch. The power supply voltage detection device according to claim 2, wherein the voltage regulation module is configured to: according to the magnitude of the determined power supply voltage, when the determined power supply voltage is lower than a predetermined voltage, increase the power supply voltage to Compensating for voltage droop, or reducing the supply voltage to compensate for voltage rise when the determined supply voltage is higher than a predetermined voltage. The power supply voltage detection device according to claim 2, wherein the relationship between the actual delay range of the single latch and the magnitude of the power supply voltage is obtained through experimental measurement, or the logic value of the N latch chains The relationship between the value of the string and the magnitude of the supply voltage is obtained through experimental measurement. The power supply voltage detecting device as claimed in claim 1, wherein N is the rounded-up result of dividing the time delay of a single latch by the time delay of a single buffer. The power supply voltage detection device according to claim 1, wherein M is greater than or equal to one time of the period of the clock signal divided by the time delay of a single latch. The power supply voltage detecting device according to claim 1, wherein M is greater than or equal to 1.5 times the result of dividing the period of the clock signal by the time delay of a single latch. The supply voltage detection device according to claim 1, wherein the N latch chains in the supply voltage detector are enabled at the rising edge of the clock signal, and are enabled at the falling edge of the clock signal and reset along the output data; or the supply voltage detector also includes another N latch chains and another N buffers having the same structure as the N latch chains, and the clock signal The rising edge of the clock signal enables the N latch chains, outputs data and resets on the falling edge of the clock signal, and enables the other N latch chains on the falling edge of the clock signal , and output data and reset at the rising edge of the clock signal. A power supply voltage detection system, comprising: a plurality of power supply voltage detection devices according to Claim 1 connected to multiple areas of an integrated circuit power network. A supply voltage detector, comprising: a buffer string including N buffers, wherein the input end of the first buffer is connected to a clock signal, and the output end of the first buffer is connected to a second buffer The input end of the nth buffer is connected to the input end of the n+1th buffer, N and n are positive integers, n is greater than 1 and less than N; N latch chains, each latch The chain consists of M latches, each of which The clock input terminal of the latch is connected to the clock signal, the data input terminal of the first latch of each latch chain is connected to the output terminal of a corresponding buffer in the N buffers, and the The data output terminal of the first latch is connected to the data input terminal of the second latch, the data output terminal of the mth latch is connected to the data input terminal of the m+1th latch, M, m is a positive integer, m is greater than 1 and less than M, the power input terminal of each latch is connected to the area where the power supply voltage is to be detected in the integrated circuit power network, and the ground terminal of each latch is connected to the ground. A power supply voltage detection method, comprising: providing a power supply voltage detector, including: a buffer string including N buffers, wherein the input end of the first buffer is connected to a clock signal, and the output of the first buffer The terminal is connected to the input terminal of the second buffer, the output terminal of the nth buffer is connected to the input terminal of the n+1th buffer, N and n are positive integers, n is greater than 1 and less than N; N latches Each latch chain includes M latches, the clock input of each latch is connected to the clock signal, and the data input of the first latch of each latch chain terminal is connected to the output terminal of a corresponding buffer in the N buffers, the data output terminal of the first latch is connected to the data input terminal of the second latch, and the mth latch The data output end of each latch is connected to the data input end of the m+1th latch, M and m are positive integers, m is greater than 1 and less than M, and the power input end of each latch is connected to the integrated circuit power supply network In the area where the power supply voltage is to be detected in the road, the ground terminal of each latch is connected to the ground; and the data output of each latch is detected to determine the power supply network of the integrated circuit The magnitude of the power supply voltage in the region where the power supply voltage is to be detected. A computer-readable medium, on which a computer program is stored, wherein, when the program is executed by a processor, the power supply voltage detection method as described in claim 12 is implemented.

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