TWI803272B - Semiconductor circuit and semiconductor device for determining status of a fuse element - Google Patents

Abstract

A semiconductor circuit and semiconductor device for determining status of a fuse element are provided. The semiconductor circuit includes a configurable reference resistor unit with a first terminal receiving a first power signal and a second terminal electrically coupled to the fuse element. The semiconductor circuit also includes a latch circuit for reading a first status signal of a first node between the configurable reference resistor unit and the fuse element. The configurable reference resistor unit includes a first resistor, a first transistor connected in parallel with the first resistor, and a first configurable unit connected to a gate of the first transistor. The first configurable unit is configured to generate a first configurable signal to be provided to the gate of the first transistor.

Description

Semiconductor circuit and semiconductor element for determining the state of a fuse element

This application claims priority to US Patent Application Nos. 17/568,052 and 17/568,100 (ie, with a priority date of "January 4, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor circuit and semiconductor device for determining the state of a fuse element. More particularly, it relates to a semiconductor circuit having a one-time programmable element and a configurable reference resistor for determining the state of a fuse element in a memory element.

Fuses and electronic fuses are commonly used in multiple memory devices to convert a redundant memory cell into a normal memory cell. A test circuit is used to determine the state of the fuse (ie, whether the fuse is blown), so that the corresponding memory cell can be identified as a normal memory cell or a redundant memory cell. With the development of technology, the size of many memory elements is reduced, and due to process variation, the resistance of the fuse may sometimes fail to meet a desired value. As a result, the state of the fuse may not be correctly discerned.

In the current implementation, the problem of not meeting the desired fuse resistance value can be solved by modifying a reference resistor in the memory devices. However, modifying a reference resistor in the memory devices will cause the entire manufacturing process to be restarted, and the entire manufacturing process restart requires additional photomasks, which inevitably increases time and cost requirements.

The above "prior art" description only provides background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" is It should not be part of this case.

An embodiment of the present disclosure provides a semiconductor device for determining the state of a fuse element of a memory device. The semiconductor circuit includes a configurable reference resistor unit having a first terminal and a second terminal, the first terminal receives a first power signal, and the second terminal is configured to be electrically coupled to the fuse element. In addition, the semiconductor circuit also includes a first latch circuit configured to read a first state signal of a first node located between the configurable reference resistor unit and the fuse between components. The configurable reference resistor unit includes a first resistor; a first transistor connected in parallel with the first resistor; and a first configurable unit connected to a gate of the first transistor pole. The first configurable unit is configured to generate a first configurable signal to be provided to the gate of the first transistor.

Another embodiment of the present disclosure provides a semiconductor device for determining the state of a fuse element of a memory device. The semiconductor element includes a configurable reference resistor unit having a first terminal and a second terminal, the first terminal receives a first power signal, and the second terminal is configured to be electrically connected to the fuse element coupling. The configurable reference resistor unit includes a first resistor; a first transistor connected in series with the first resistor; and a first configurable unit connected to a gate of the first transistor pole. The first configurable unit is configured to generate a first configurable signal to be provided to the gate of the first transistor.

Another embodiment of the present disclosure provides a method of determining the state of a fuse element of a memory device. The method includes providing the memory element with a first terminal and a second terminal; and applying a first power signal to the first terminal of the memory element. The memory element includes a configurable reference resistor unit electrically coupled to the fuse element. The method also includes obtaining an evaluation signal at the second terminal of the memory device in response to the first power signal; and identifying the evaluation signal to determine whether the memory device is redundant. The configurable reference resistor unit includes a first resistor; a first transistor connected in parallel with the first resistor; and a first configurable unit connected to a gate of the first transistor pole. The first configurable unit is configured to generate a first configurable signal to turn on the first transistor.

The configurable resistor unit is represented as a variable resistance. The variable resistor can be adjusted according to the resistance change of the fuse element caused by the process changes. According to the actual resistance value of the corresponding fuse element, the resistance value of the configurable reference resistor can be modified after the element is manufactured. Therefore, the flexibility of the present disclosure is increased. In addition, the configurable reference resistor unit is adjusted by programming the OTP device (such as an antifuse), which reduces the impact on adjacent areas during programming. The component with the flexibility resistor eliminates the need to add an additional photomask for the reference resistor, reducing production time.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Certainly, these embodiments are only for illustration, and are not intended to limit the scope of the present disclosure. For example, where a first component is formed on a second component, it may include embodiments where the first and second components are in direct contact, or may include an additional component formed between the first and second components, An embodiment such that the first and second parts do not come into direct contact. In addition, embodiments of the present disclosure may repeat reference numerals and/or letters in many instances. These repetitions are for the purpose of simplicity and clarity and, unless otherwise indicated in the context, do not in themselves imply a specific relationship between the various embodiments and/or configurations discussed.

It should be understood that when forming a component on, connected to, and/or coupled to another component, it may include implementations where these components are formed in direct contact. Examples, and may also include embodiments in which additional components are formed between these components such that the components do not come into direct contact.

It will be understood that although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not constrained by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the presently advanced concepts.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. Presence, but not excluding the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

It should be understood that in describing the present disclosure, use of the term "about" varies the quantities of ingredients, compositions, or reactants of the present disclosure, meaning, for example, by typical measurements used to prepare concentrates or solutions and liquid handling Quantitative changes that may occur due to procedures. Furthermore, inadvertent errors in measurement procedures, differences in the manufacture, source or purity of ingredients used to make a composition or perform a method, etc. may cause variation. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. Still, in another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

FIG. 1 is a schematic structural diagram illustrating a system 10 for testing a plurality of semiconductor devices according to some embodiments of the present disclosure.

According to FIG. 1 , a system 10 is configured to monitor a semiconductor device 11 . In one embodiment, system 10 is configured to test semiconductor device 11 . The semiconductor device can be a memory, a memory device, a memory die or a memory chip. In some embodiments, the semiconductor device 11 may include one or more memory cells. The semiconductor element 11 may be tested after manufacture and then shipped.

In some embodiments, system 10 may constitute a testing device. System 10 may include hardware and software components that provide a testing environment suitable for selection and function. In some embodiments, the system 10 may include a signal generator 12 , a monitor 13 and a coupler 14 .

The signal generator 12 is configured to generate a test signal. In some embodiments, the signal generator 12 can provide a power signal. It should be understood that other electronic signals may also be provided to the semiconductor device 11, such as multiple data signals and multiple power signals.

The monitor 13 is configured to determine a state of the semiconductor element 11 . Monitor 13 may be configured to determine a state of one of semiconductor elements 11 . A plurality of response signals can be identified by the monitor 13 to determine whether an element (such as a memory cell) of the semiconductor element 11 is a normal element or a redundant element.

The coupler 14 is configured to couple the signal generator 12 to the semiconductor device 11 . In some embodiments, the coupler 14 can be coupled to the semiconductor device 11 through one or more probes 15 . The probes 15 can be a probe head or a part of a probe package (not shown). The probes 15 can be electrically coupled to a plurality of test conductive contacts (a plurality of bonding pads) and/or a plurality of bonding pads disposed on the semiconductor device 11 . The test conductive pads and/or bonding pads provide multiple electrical connections to an interconnection structure (eg, wiring) of the semiconductor device 11 . For example, some probes may be coupled to the pads associated with a power supply terminal (eg, VDD) and a ground terminal (eg, VSS) of the semiconductor device 11 . Other probes may be coupled to the pads associated with input/output (I/O) terminals (eg, data signals) of the semiconductor device 11 . As such, the system 10 is operable to apply a plurality of electronic signals to the semiconductor device 11 and obtain other responsive signals from the semiconductor device 11 during testing.

FIG. 2 is a structural schematic diagram illustrating a semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 can be a memory, a memory device, a memory die or a memory chip. The semiconductor device 100 can be a memory, a memory device, a memory die or a part of a memory chip. For example, the memory can be a dynamic random access memory (DRAM). In some embodiments, the DRAM may be a double data rate fourth generation (DDR4) DRAM. In some embodiments, the memory includes one or more memory cells (or memory bits, memory blocks). In some embodiments, the memory cell includes a fuse element.

The semiconductor device 100 may include a fuse element 101 , an evaluation unit 110 and a state setting unit 120 . In some embodiments, the evaluation unit 110 may include a configurable reference resistor unit 105 , switching circuits TD and TE, and a latch circuit 130 . In some embodiments, the fuse element 101 and the switching circuits TD, TE can be used as a part of the evaluation unit 110 . In some embodiments, the state setting unit 120 may include a fuse element 101 , a conductive contact 122 and two switching circuits TB and TC.

Referring to FIG. 2, the configurable reference resistor unit 105 has a terminal 105-1 configured to receive a power signal VDD. The configurable reference resistor unit 105 has a terminal 105 - 2 configured to be electrically coupled to the fuse element 101 . In some embodiments, switching circuit TB may be connected to fuse element 101 . The switching circuit TD is connectable to a configurable reference resistor unit 105 . In some embodiments, switching circuit TD may be connected to switching circuit TB. In some embodiments, the fuse element 101 can be coupled to ground via the switching circuits TB and TC. The switching circuit TA may be connected to the fuse element 101 . The switching circuit TA may be connected to ground.

In some embodiments, the latch circuit 130 is coupled to the configurable reference resistor unit 105 . In some embodiments, the latch circuit 130 may be coupled to the fuse element 101 via the switching circuits TB, TD, TE. In some embodiments, the switching circuit TE is connected to a configurable reference resistor unit 105 . The switching circuit TE may be connected to the latch circuit 130 . In some embodiments, switching circuit TE may be connected to switching circuit TD. An evaluation/output signal is available at a conductive terminal VE of the latch circuit 130 .

Referring to FIG. 2 , the conductive contact 122 can be connected to the fuse element 101 . The conductive contact point 122 can be a test pad, a probe pad, a conductive pad, a conductive terminal or other suitable components. In some embodiments, the conductive contact 122 is configured to receive a state setting signal VB. In some embodiments, switching circuit TB may be connected to fuse element 101 . Switching circuit TC is connectable to switching circuit TB. The switching circuit TC may be connected to ground.

In some embodiments, the switch circuits TA, TB, TC, TD, TE may be switches, transistors or other switchable circuits.

FIG. 2A is a schematic structural diagram illustrating a semiconductor device 100 according to some embodiments of the present disclosure. Please refer to FIG. 2A , the switching circuits TB and TC are configured to conduct, thereby establishing a conductive path 111A in response to the state setting signal VB. In some embodiments, the conductive path 111A may pass through the fuse element 101 to ground in response to the state setting signal VB. In some embodiments, when the state setting signal VB is applied to the conductive terminal 122 , the conductive path 111A passes through the fuse element 101 , the switching circuits TB and TC, and reaches the ground. In addition, the switching circuits TA, TD, TE can be configured to be turned off so that the conductive path 111A can pass through the fuse element 101 .

In some embodiments, the state setting signal VB can be a voltage signal or a current signal. In some embodiments, the state setting signal VB may be a voltage signal having a voltage exceeding the normal operating voltage of the semiconductor device 100 . For example, the state setting signal VB can have a voltage ranging from 4V to 6V. In one embodiment, the state setting signal VB may have a voltage ranging from 5V to 6V. When the state setting signal VB is applied, a state of the fuse element 101 can be changed. Before the state setting operation, the fuse element 101 may have a relatively high resistance. After the state setting operation, the fuse element 101 may have a relatively low resistance. In this disclosure, a fuse element may be represented as an "unblown" fuse element before a state setting operation, and a fuse element may be represented as a "blown" fuse after a state setting operation. wire element.

A blown fuse element 101 has a resistance lower than that of an unblown fuse element 101 . In some embodiments, the fuse element 101 can be an antifuse. For example, the antifuse can be an electronic fuse. In some embodiments, the antifuse includes a polysilicon electronic fuse or other types of antifuse.

In one embodiment, the resistance of the unblown fuse element 101 may range from 1.5 MΩ to 20 MΩ. In another embodiment, the resistance of the unblown fuse element 101 may range from 5MΩ to 20MΩ. In some embodiments, the resistance of the unblown fuse element 101 may exceed 20 MΩ. After the state set operation, the resistance of the blown fuse element 101 may be approximately 2 kΩ to 800 kΩ. In one embodiment, the resistance of the blown fuse element 101 may be approximately 2 kΩ to 20 kΩ. In another embodiment, the resistance of the blown fuse element 101 may exceed 100 kΩ. In some embodiments, the resistance of the blown fuse element 101 may be approximately 100 kΩ to 800 kΩ.

FIG. 2B is a schematic structural diagram illustrating a semiconductor device 100 according to some embodiments of the present disclosure. Please refer to FIG. 2B , the switching circuits TA, TB, TD are configured to conduct, thereby establishing a conductive path 111B. In some embodiments, the conductive path 111B may pass through the configurable reference resistor unit 105 and the fuse element 101 to ground in response to the power signal VDD. In some embodiments, switching circuit TC is configured to be turned off so as to establish conductive path 111B. In some embodiments, when the power signal VDD is applied to the terminal 105-1 of the configurable reference resistor unit 105, the conductive path 111B passes through the configurable reference resistor unit 105, the switching circuits TD and TB, the fuse The wire element 101 and the switching circuit TA, and then to the ground. In some embodiments, the power signal VDD can be a normal operating voltage. For example, the power signal VDD may have a voltage of about 1.2V.

In some embodiments, a signal X can be generated at a node W between the configurable reference resistor unit 105 and the fuse element 101 in response to the power supply signal VDD. Referring to FIG. 2B , the signal X generated at the node W can be transmitted to the latch circuit 130 through the switching circuits TD and TE.

In some embodiments, the latch circuit 130 is configured to read the signal X generated at node W between the configurable reference resistor unit 105 and the fuse element 101 . Node W is located between the configurable reference resistor unit 105 and the fuse element 101 , with or without other elements coupled therebetween. For example, node W may be located between switching circuits TB and TD. In one embodiment, the node W may be located between the switching circuit TD and the configurable reference resistor unit 105 . In another embodiment, the node W may be located between the switching circuit TB and the fuse element 101 . In some embodiments, the signal X may include a voltage signal or a current signal.

In some embodiments, the switching circuit TE is configured to be turned on so as to transmit the signal X to the latch circuit 130 . During an evaluation period, when the switching circuits TA, TB, TD, TE are configured to conduct, thereby establishing the conduction path 111B, the signal X can be obtained at the node W and transmitted to the latch circuit 130 . In some embodiments, the latch circuit 130 can read the signal X. In some embodiments, the latch circuit 130 can convert the signal X into a signal Y. For example, the conversion of signal X operated by the latch circuit 130 may include inverting one signal into another. In one embodiment, the conversion of the signal X operated by the latch circuit 130 may include phase shifting. In another embodiment, the conversion of the signal X operated by the latch circuit 130 may include amplification.

In some embodiments, the latch circuit 130 can convert the analog signal X into a logic signal Y. The latch circuit 130 can compare the signal X with a threshold, and output a signal Y according to the comparison result between the signal X and the threshold. For example, when the signal X exceeds the threshold, the latch circuit 130 can output a logic low signal Y. On the contrary, when the signal X is lower than the threshold value, the latch circuit 130 can output a logic high signal Y. In some embodiments, the signal Y has a logic value relative to the signal X. For example, when the signal X is logic "0", then the signal Y will be logic "1". Conversely, when the signal X is logic "1", the signal Y will be logic "0". In some embodiments, the latch circuit 130 can store the signal Y.

Please refer to FIG. 2B , the latch circuit 130 may include two inverters 131 and 132 . In some embodiments, the latch circuit 130 may include more than two inverters. In some embodiments, the latch circuit 130 may be other types of latch circuits. The inverter 131 has an input terminal IN_1 and an output terminal OUT_1. The inverter 132 has an input terminal IN_2 and an output terminal OUT_2. In some embodiments, the input terminal IN_1 of the inverter 131 may be coupled to the configurable reference resistor unit 105 via the switching circuit TE. The input terminal IN_1 of the inverter 131 can be coupled to the fuse element 101 via the switching circuits TB, TD, TE. The output terminal OUT_1 of the inverter 131 may be coupled to the conduction terminal VE. In some embodiments, the input terminal IN_1 of the inverter 131 may be connected to the output terminal OUT_2 of the inverter 132 . The output terminal OUT_1 of the inverter 131 may be connected to the input terminal IN_2 of the inverter 132 . That is, the input terminal IN_2 of the inverter 132 can be coupled to the conduction terminal VE. The output terminal OUT_2 of the inverter 132 may be coupled to the configurable reference resistor unit 105 . The output terminal OUT_2 of the inverter 132 may be coupled to the fuse element 101 .

In order to evaluate the state of the fuse element 101 (eg, whether the fuse element 101 is blown), the signal X (or the signal Y) is monitored. The signal X is compared with a predetermined signal or a threshold. According to the comparison of the signal X with the predetermined signal, the logic signal Y can be output at the conductive terminal VE. When the signal X exceeds the predetermined signal, it indicates that the fuse element 101 is not blown. When the signal X does not exceed the predetermined signal, it indicates that the fuse element 101 has been blown.

In some embodiments, if the signal X exceeds a predetermined signal, the latch circuit 130 can output a logic low signal Y. That is, the logic low signal Y indicates that the fuse element 101 is not blown. When the signal X is lower than the predetermined signal, the latch circuit 10 can output a logic high signal Y. In other words, the logic high signal Y indicates that the fuse element 101 has been blown.

Signal Y is available at conductive terminal VE so that the state of fuse element 101 can be determined. The state of the fuse element 101 can be used to determine whether the semiconductor element is a redundant element or a normal element.

FIG. 2C is a schematic diagram of an equivalent circuit, illustrating an equivalent circuit 100C of a part of the semiconductor device 100 when establishing the conductive path 111B according to some embodiments of the present disclosure. The equivalent circuit 100C is configured such that the switching circuits TA, TB, and TD are turned on, and the switching circuit TC is turned off. In other words, the equivalent circuit 100C shows a simplified circuit, and the conductive path 111B passes through the simplified circuit.

The equivalent circuit 100C has two resistors RR and RF. In some embodiments, resistor RR may be the resistance of the configurable reference resistor unit 105 . Resistor RF may be the resistance of fuse element 101 . In some embodiments, resistor RR may be in series with resistor RF. A node E is located between resistor RR and resistor RF. That is, the node W in FIG. 2C corresponds to the node in FIG. 2B. In some embodiments, the resistor RR is configured to receive a power signal VDD. For example, the power signal VDD can be a voltage of 1.2V. In some embodiments, resistor RF is connected to resistor RR and ground.

[式1] Please refer to FIG. 2C , the signal X can be a voltage signal obtained at the node W. Therefore, the signal X can be calculated according to Equation 1.

[Formula 1]

In Equation 1, X represents the voltage of the signal X; RR represents the resistance of the configurable reference resistor unit 105; RF represents the resistance of the fuse element 101; and VDD represents the power signal.

In order to accurately assess the state of fuse element 101, resistance RR may be dropped below resistance RF of an unblown fuse element. In addition, the resistance RR may exceed the resistance RF of the blown fuse element. In some embodiments, resistance RR may be between the resistance of an unblown fuse element and the resistance of a blown fuse element.

In one embodiment, the resistance of the unblown fuse element 101 may range from 1.5 MΩ to 20 MΩ. In some embodiments, the resistance of the unblown fuse element 101 may exceed 5 MΩ. In another embodiment, the resistance of the unblown fuse element 101 may range from 5MΩ to 20MΩ. In some embodiments, the resistance of the unblown fuse element 101 may exceed 20 MΩ. After the state set operation, the resistance of the blown fuse element 101 may be approximately 2 kΩ to 800 kΩ. In some embodiments, the resistance of the blown fuse element 101 may be less than 400 kΩ. In one embodiment, the resistance of the blown fuse element 101 may be approximately 2 kΩ to 20 kΩ. In another embodiment, the resistance of the blown fuse element 101 may exceed 100 kΩ. In some embodiments, the resistance of the blown fuse element 101 may be approximately 100 kΩ to 800 kΩ.

In some embodiments, the resistance of resistor RR may be variable depending on the resistance of resistor RF. In some embodiments, the configurable reference resistor unit 105 has a variable resistance RR. For example, the resistance of resistor RR may be adjusted to exceed the resistance of resistor RF of a blown fuse element. Resistor RR is adjusted to drop below resistor RF of the unblown fuse element.

When the resistor RR is adjusted to be between the resistance of the unblown fuse element and the resistance of the blown fuse element, the state of the fuse element 101 can be accurately determined.

In some embodiments, the predetermined signal has a voltage lower than the power signal VDD. In some embodiments, the predetermined signal has a voltage that is a fractional multiple of the power signal VDD. For example, if the predetermined signal has a voltage which is half of the power signal VDD, such as 1.2V, then the predetermined signal may have a voltage of 0.6V. That is, when the result of formula 1 exceeds 0.6V, the signal X at the node W will be regarded as a logic high, indicating that the fuse element 101 is not blown, and when it is less than 0.6V, the signal X at the node W The signal X will be regarded as a logic low, indicating that the fuse element 101 has been blown.

When the resistance of the configurable reference resistor unit 105 is variable, the flexibility of the semiconductor device is increased. Resistor RR can be adjusted according to resistor RF fabricated next. Thus, inaccurate determination of the state of the fuse element 101 resulting from unstable resistance of the fuse element caused by process variations may be avoided. Production time is reduced since manufacturing does not need to be restarted to adjust resistor RR. Therefore, the present disclosure provides a more flexible semiconductor device/circuit that reduces production time.

FIG. 3 is a block diagram illustrating a configurable reference resistor unit 105A of some embodiments of the present disclosure. The reference resistor unit 105A can be an embodiment of the reference resistor unit 105 as shown in FIG. 2 , FIG. 2A and FIG. 2B . As shown in FIG. 3 , the configurable reference resistor unit 105A may include a resistor R1 , a transistor T1 and a configurable unit 300 . The configurable unit 300 is configured to generate a configurable signal N, which is then provided to the transistor T1. In some embodiments, the configurable signal 300 may include a one-time programmable (OTP) element AS1, a resistor R1a, three transistors T2, T3, T4, a latch circuit 330, and a programming circuit 310. The programming circuit 310 is configured to program the OTP element AS1. That is, the programming circuit 310 can be configured to change a state of the OTP element AS1. In some embodiments, the programming circuit 310 includes an OTP element AS1 , transistors T5 and T6 , and a conductive contact 322 . In some embodiments, the latch circuit 330 may include two inverters 331 and 332 .

In some embodiments, the resistor R1 is configured to receive the power signal VDD. Resistor R1 may be connected to transistor T1. In some embodiments, transistor T1 may be connected in parallel with resistor R1. In some embodiments, transistor T1 has a gate connected to configurable cell 300 . In some embodiments, the gate of the transistor T1 can be configured to receive the configurable signal N generated by the configurable unit 300 . In response to a configurable signal N, transistor T1 can be turned on or off.

The resistance of the resistor R1 can be in kΩ level. In some embodiments, resistor R1 may have a resistance of 100kΩ, 200kΩ, 300kΩ, 400kΩ, 500kΩ, 800kΩ, 1MΩ, 1.5MΩ, 2MΩ, 3MΩ, 4MΩ, 5MΩ, 6MΩ, 7MΩ, 8MΩ, or even greater. The resistance of the resistor R1 can be configured according to design requirements. When the transistor T1 is turned off, the resistance of the configurable reference resistor unit 105A is the same as that of the resistor R1. When the transistor T1 is turned on, the resistance of the configurable reference resistor unit 105A is approximately 0Ω.

As shown in FIG. 3 , the configurable unit 300 includes an OTP element AS1 , a resistor R1 a , three transistors T2 , T3 , T4 , a latch circuit 330 and a programming circuit 310 . OTP element AS1 may be configured to be connected to reference resistor R1a, eg, via transistor T3. In some embodiments, reference resistor R1a may be connected in series with OTP element AS1.

The OTP element AS1 can be configured to receive the power signal VDD through the transistor T2. The transistor T2 has a gate configured to receive a control signal P1. In some embodiments, transistor T3 is coupled between OTP element AS1 and reference resistor R1a. The transistor T3 has a gate configured to receive the control signal P1. In some embodiments, the OTP element AS1 can be an antifuse. For example, the antifuse can be an electronic fuse. In some embodiments, the antifuse includes a polysilicon electronic fuse, a dielectric antifuse, a gate oxide antifuse, or other types of antifuse. In some embodiments, the OTP element AS1 (eg, an antifuse) may represent an "unblown" fuse prior to the programming operation, and the OTP element AS1 (eg, the antifuse) may represent an "unblown" fuse after the programming operation. Denoted as a "blown" fuse. In some embodiments, the current capable of blowing the antifuse is generally low compared to the current of a normal fuse element. Then, the blocking distance of the antifuse may be relatively short. Therefore, the use of antifuse can reduce the component footprint.

In some embodiments, the resistance of the unprogrammed OTP element AS1 may exceed 5 MΩ. In another embodiment, the resistance of the unprogrammed OTP device AS1 may range from 5MΩ to 20MΩ. In some embodiments, the resistance of the unprogrammed OTP element AS1 may exceed 20 MΩ. After the programming operation, the resistance of the programmed OTP device AS1 may be lower than 300 kΩ. In one embodiment, the resistance of the programmed OTP device AS1 may be approximately 2 kΩ to 300 kΩ. In another embodiment, the resistance of the programmed OTP device AS1 may be approximately 2 kΩ to 20 kΩ. In some embodiments, the resistance of the programmed OTP device AS1 may be approximately 100 kΩ to 300 kΩ.

In response to the control signal P1, the transistors T2 and T3 are turned on to generate a signal M at a node G between the OTP element AS1 and the reference resistor R1a. In some embodiments, the transistors T2 and T3 can be configured to conduct to establish a conductive path (not shown) in response to the power signal VDD, and the conductive path goes to ground through the OTP element AS1 and the reference resistor R1a. In some embodiments, when the power signal VDD is applied to the OTP element AS1, the conduction path passes through the transistor T2, the OTP element AS1, the transistor T3, the reference resistor R1a, and then to ground. In some embodiments, the power signal VDD can be a normal operating voltage. For example, the power signal VDD may have a voltage of about 1.2V.

In some embodiments, the signal M can be generated at a node G between the OTP element AS1 and the reference resistor R1a in response to the power signal VDD. Referring to FIG. 3 , the signal M generated at the node G can be transmitted to the latch circuit 330 through the transistor T4 .

In some embodiments, the latch circuit 330 is configured to read the signal M generated at the node G, which is between the OTP element AS1 and the reference resistor R1a. The node G is located between the OTP element AS1 and the reference resistor R1a, with or without other elements coupled therebetween. For example, node G can be located between transistors T3 and T4. In one embodiment, the node G may be located between the transistor T3 and the OTP device AS1. In some embodiments, the signal M may include a voltage signal or a current signal.

The transistor T4 is coupled between the reference resistor R1a and the latch circuit 330 . The transistor T4 has a gate configured to receive the control signal P1. In some embodiments, the transistor T4 can be turned on to transmit the signal M to the latch circuit 330 . When the transistors T2 , T3 , T4 are turned on to establish a conduction path through the OTP element AS1 and the reference resistor R1 a , the signal M can be obtained at the node G and transmitted to the latch circuit 330 . In some embodiments, the latch circuit 330 can read the signal M. In some embodiments, the latch circuit 330 can convert the signal M into a configurable signal N. For example, the conversion of signal M operated by latch circuit 330 may include inverting one signal into the other. In one embodiment, the transition of the signal M operated by the latch circuit 330 may include a phase shift. In another embodiment, the conversion of the signal M operated by the latch circuit 330 may include amplification.

In some embodiments, the latch circuit 330 can convert the analog signal M into a logic signal N. The latch circuit 330 can compare the signal M with a threshold value, and output a configurable signal N accordingly. For example, when the signal M exceeds the threshold, the latch circuit 330 can output a logic low signal N. On the contrary, when the signal M is lower than the threshold value, the latch circuit 330 can output a logic high signal N. In some embodiments, the configurable signal N has a logical value relative to the signal M. For example, when the signal M is logic "0", the configurable signal N will be logic "1". Conversely, when the signal M is logic "1", the configurable signal N will be logic "0". In some embodiments, the latch circuit 330 can store a configurable signal N.

Please refer to FIG. 3 , the latch circuit 330 may include two inverters 331 and 332 . In some embodiments, the latch circuit 330 may include more than two inverters. In some embodiments, the latch circuit 330 may be other types of latch circuits. The inverter 331 has an input terminal IN_1 and an output terminal OUT_1. The inverter 332 has an input terminal IN_2 and an output terminal OUT_2. In some embodiments, the input terminal IN_1 of the inverter 331 may be coupled to the reference resistor R1a via the switching circuit T4. The input terminal IN_1 of the inverter 331 can be coupled to the OTP element AS1 via the switching circuits T3 and T4. The output terminal OUT_1 of the inverter 331 can be coupled to a gate of the transistor T1. In some embodiments, the input terminal IN_1 of the inverter 331 may be connected to the output terminal OUT_2 of the inverter 332 . The output terminal OUT_1 of the inverter 331 may be connected to the input terminal IN_2 of the inverter 332 . That is, the input terminal IN_2 of the inverter 332 can be coupled to the gate of the transistor T1. The output terminal OUT_2 of the inverter 332 may be coupled to the reference resistor R1a. The output terminal OUT_2 of the inverter 332 may be coupled to the OTP element AS1.

The configurable signal N (or signal M) is associated with the state of the OTP element AS1 (eg whether the OTP element AS1 is programmed or not). A configurable signal N (or signal M) can be sent to the gate of transistor T1 to turn transistor T1 on or off. The signal M is compared with a predetermined signal or a threshold. According to the comparison between the signal M and the predetermined signal, the logic signal N can be output to the gate of the transistor T1. When the OTP element AS1 is programmed, the signal M can exceed a predetermined signal, so that the transistor T1 can be turned off. When the OTP device AS1 is not programmed, the signal M can be lower than a predetermined signal so as to turn on the transistor T1.

In some embodiments, if the signal M exceeds a predetermined signal, the latch circuit 330 can output a logic low signal N. That is, the logic low signal N generated by the programmed OTP element AS1 can turn off the transistor T1. When the signal M is lower than the predetermined signal, the latch circuit 330 can output a logic high signal N. In other words, the logic high signal N caused by the unprogrammed OTP device AS1 can turn on the transistor T1.

Transistor T1 can be turned on or off in response to a configurable signal N received at the gate of transistor T1 . The state of the OTP element AS1 can be used to generate a configurable signal N (or signal N).

Please refer to FIG. 3 , the programming circuit 310 means programming the OTP device AS1. In other words, the state of the OTP element AS1 can be changed through the programming circuit 310 . In some embodiments, the OTP element AS1 can be coupled to the conductive contact 322 to receive a state setting signal VB. The state setting signal VB in FIG. 3 may be similar to the state setting signal VB in FIG. 2 . In some embodiments, the state setting signal VB may have a voltage level capable of programming (fusing) the OTP device AS1. For example, the state setting signal VB may have a voltage level ranging from 4V to 6V. In another embodiment, the state setting signal VB may have a voltage level ranging from 5 to 6V. In some embodiments, the transistor T5 may be coupled between the conductive contact 322 and the OTP element AS1. The transistor T5 has a gate configured to receive a control signal P2. In some embodiments, transistor T6 may be coupled between OTP element AS1 and ground. The transistor T6 has a gate configured to receive the control signal P2.

FIG. 3A is a block diagram illustrating a programming circuit 310a of some embodiments of the present disclosure. The programming circuit 310a in FIG. 3A is similar to the programming circuit 310 in FIG. Provide state setting signal VB. In some embodiments, the power supply can be a voltage supply. In some embodiments, the power supply can be a current supply.

In some embodiments, in response to the control signal P2, the transistors T5 and T6 can be turned on so that the state setting signal VB can be applied to the OTP device AS1. Since the state setting signal VB is applied to the OTP element AS1, a state of the OTP element AS1 can be changed. In some embodiments, the OTP device AS1 can be programmed by the state setting signal VB.

Referring to FIG. 3, the number of resistors included in the configurable reference resistor unit 105A can be increased. The flexibility of the variable resistor is increased when more resistors are included in the configurable reference resistor unit 105A. In some embodiments, the number of configurable cells in configurable reference resistor cell 105A may be increased. In some embodiments, the number of configurable cells may correspond to the number of such resistors.

3B is a schematic diagram of an equivalent circuit illustrating an equivalent circuit 105A' of a portion of the reference resistor unit 105A that can be configured in some implementations of the present disclosure when establishing a conductive path through the OTP element A1 and the reference resistor R1a. The equivalent circuit 105A' is configured to turn on the switching circuits T2, T3, T4 and turn off the switching circuits T5, T6. In other words, equivalent circuit 105A' represents a simplified circuit that generates signal M at node G.

The equivalent circuit 105A' includes an OTP element AS1 and a reference resistor R1a. The resistance of the OTP element AS1 can vary depending on its state. In some embodiments, OTP element AS1 may be connected in series with reference resistor R1a in some embodiments. Node G is between OTP element AS1 and reference resistor R1a. That is, node G in FIG. 3B corresponds to node G in FIG. 3 . In some embodiments, the OTP device AS1 is configured to receive a power signal VDD. For example, the power signal VDD may have a voltage of 1.2V. In some embodiments, reference resistor R1a is connected to OTP element AS1 and ground.

[式2] Please refer to FIG. 3B , the signal M can be a voltage signal obtained at the node G. Referring to FIG. Therefore, the signal M can be calculated according to Equation 2.

[Formula 2]

In Equation 2, M represents the voltage of the signal M, R1a represents the resistance of the reference voltage R1a, R _AS1 represents the resistance of the OTP element AS1, and VDD represents the power signal.

In some embodiments, a result of the comparison between the signal M and a predetermined signal (threshold) may turn on the transistor T1. In one embodiment, the predetermined signal may be a predetermined signal of the latch circuit 330 . In another embodiment, the predetermined signal may be a predetermined signal of the transistor T1. The predetermined signal (threshold) may have a voltage which is lower than the voltage of the power signal VDD. In some embodiments, the predetermined signal has a voltage that is a fractional multiple of the power signal VDD. For example, if the predetermined signal has a voltage which is half of the power signal VDD, such as 1.2V, then the predetermined signal may have a voltage of 0.6V. That is, when the result of Equation 2 exceeds 0.6V, the signal M at the node G can be regarded as logic high, so that the transistor T1 can be turned off. On the contrary, when it is less than 0.6V, the signal M at the node G is logic low so as to turn on the transistor T1.

In response to the configurable signal N generated by the configurable unit 300, the transistor T1 is turned on so that the resistance of the configurable reference resistor unit 105A' is variable. Therefore, the flexibility of the semiconductor element can be increased. The total resistance of the configurable reference resistor unit 105A' can be adjusted after manufacture. Manufacturing time can be reduced since manufacturing does not have to be restarted. Accordingly, the present disclosure provides a more flexible semiconductor device/circuit that reduces manufacturing time.

FIG. 4 is a block diagram illustrating a configurable reference resistor unit 405 of some embodiments of the present disclosure. The configurable reference resistor unit 405 in FIG. 4 is similar to the configurable reference resistor unit 105A in FIG. 3, different from FIG. 4, and for better flexibility, the configurable reference resistor The resistor unit 405 includes more resistors as well as OTP components.

As shown in FIG. 4, the configurable reference resistor unit 405 may include resistors R1, R2, R3, R4, OTP elements AS1, AS2, AS3, AS4, reference resistors R1a, R2a, R3a, R4a, transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, T21, T22, T23, T24, Latch Circuits 431 , 432 , 433 , 434 and a conductive contact 422 .

In some embodiments, the resistor R1 is configured to receive the power signal VDD. Resistor R1 may be connected to transistor T1. For example, resistor R1 can be connected in parallel with transistor T1. Resistor R1 may be connected to resistor R2. In some embodiments, resistor R1 may be connected in series with resistor R2. Transistor T1 may be coupled to resistor R2. In some embodiments, transistor T1 may be connected in series with transistor T2.

Resistor R2 may be connected to transistor T2. For example, resistor R2 can be connected in parallel with transistor T2. Resistor R2 may be connected to resistor R3. In some embodiments, resistor R2 may be connected in series with resistor R3. Transistor T2 may be coupled to resistor R3. In some embodiments, resistor R2 may be connected in series with resistor R3. Transistor T2 may be coupled to resistor R3. In some embodiments, transistor T2 may be connected in series with transistor T3.

Resistor R3 may be connected to transistor T3. For example, resistor R3 can be connected in parallel with transistor T3. Resistor R3 may be connected to resistor R4. In some embodiments, resistor R3 may be in series with resistor R4. Transistor T3 may be coupled to resistor R4. In some embodiments, transistor T3 may be connected in series with transistor T4.

Resistor R4 may be connected to transistor T4. For example, resistor R4 can be connected in parallel with transistor T4. In some embodiments, resistor R4 may be connected to node W. Transistor T4 may be connected to node W.

Resistors R1, R2, R3, R4 may have the same resistance. In some embodiments, resistors R1, R2, R3, R4 may have different resistances. For example, the resistance of resistor R1 may exceed the resistance of resistor R2. The resistance of resistor R1 may drop below the resistance of resistor R2. In some embodiments, the resistance of resistors R1, R2, R3, R4 can each be 100kΩ, 200kΩ, 300kΩ, 400kΩ, 500kΩ, 800kΩ, 1MΩ, 1.5MΩ, 2MΩ, 3MΩ, 4MΩ, 5MΩ, 6MΩ, 7MΩ, 8MΩ or greater. Resistors R1, R2, R3, R4 can be selected according to design requirements.

Please refer to FIG. 4, the configurable reference resistor unit 405 includes four configurable units (similar to the configurable unit 300 in FIG. 3), which correspond to transistors T1, T2, T3, T4, the gate of each transistor T1, T2, T3, T4 can receive a corresponding configurable signal, and the corresponding configurable signal is provided by the corresponding configurable unit (in the figure 4 not marked) produced.

The configurable reference resistor unit 405 may include an OTP element AS1 configured to receive a power signal VDD. OTP element AS1 may be connected to reference resistor R1a. For example, reference resistor R1a may be connected in series with OTP element AS. The OTP element AS1 can be configured to receive the power signal VDD through the transistor T5. The transistor T5 has a gate configured to receive a control signal P0. In some embodiments, transistor T6 is coupled between OTP element AS1 and reference resistor R1a. The transistor T6 has a gate configured to receive the control signal P0.

As shown in FIG. 4, the latch circuit 431 is coupled to the OTP element AS1. The latch circuit 431 can be coupled to the OTP element AS1 via the transistor T13. That is, the transistor T13 can be coupled between the OTP element AS1 and the latch circuit 431 . The transistor T13 has a gate configured to receive the control signal P0. In some embodiments, the transistor T13 is configured to be turned on so as to transmit the signal obtained between the OTP element AS1 and the reference resistor R1 a to the latch circuit 431 .

In some embodiments, the latch circuit 431 can output a configurable signal to the gate of the transistor T1 according to the signal obtained between the OTP element AS1 and the reference resistor R1a. In other words, the configurable signal is associated with the state of the OTP element AS1. The OTP element AS1 is similar to the OTP element AS1 in FIG. 3 and thus a detailed description thereof is omitted. Transistor T1 can be turned on or off in response to a configurable signal generated by the latch circuit 431 .

The configurable reference resistor unit 405 may include an OTP element AS2 configured to receive a power supply signal VDD. OTP element AS2 may be connected to reference resistor R2a. For example, reference resistor R2a may be connected in series with OTP element AS2. The OTP element AS2 can be configured to receive the power signal VDD through the transistor T7. The transistor T7 has a gate configured to receive a control signal P0. In some embodiments, transistor T8 is coupled between OTP element AS2 and reference resistor R2a. The transistor T8 has a gate configured to receive the control signal P0.

As shown in FIG. 4, the latch circuit 432 is coupled to the OTP element AS2. The latch circuit 432 can be coupled to the OTP element AS2 via the transistor T14. That is, the transistor T14 can be connected between the OTP element AS2 and the latch circuit 432 . The transistor T14 has a gate configured to receive the control signal P0. In some embodiments, the transistor T14 is configured to be turned on so as to transmit the signal obtained between the OTP element AS2 and the reference resistor R2 a to the latch circuit 432 .

In some embodiments, the latch circuit 432 can output a configurable signal to the gate of the transistor T2 according to the signal obtained between the OTP element AS2 and the reference resistor R2a. In other words, the configurable signal is associated with the state of the OTP element AS2. The OTP element AS2 is similar to the OTP element AS1 in FIG. 3, so a detailed description thereof is omitted. Transistor T2 can be turned on or off in response to a configurable signal generated by the latch circuit 432 .

The configurable reference resistor unit 405 may include an OTP element AS3 configured to receive a power supply signal VDD. OTP element AS3 may be connected to reference resistor R3a. For example, reference resistor R3a may be connected in series with OTP element AS3. The OTP element AS3 can be configured to receive the power signal VDD through the transistor T9. The transistor T9 has a gate configured to receive a control signal P0. In some embodiments, the transistor T10 is coupled between the OTP element AS3 and the reference resistor R3a. The transistor T10 has a gate configured to receive the control signal P0.

As shown in FIG. 4, the latch circuit 433 is coupled to the OTP element AS3. The latch circuit 433 can be coupled to the OTP element AS3 via the transistor T15. That is, the transistor T15 can be connected between the OTP element AS3 and the latch circuit 433 . The transistor T15 has a gate configured to receive the control signal P0. In some embodiments, the transistor T15 is configured to be turned on so as to transmit the signal obtained between the OTP element AS3 and the reference resistor R3 a to the latch circuit 433 .

In some embodiments, the latch circuit 433 can output a configurable signal to the gate of the transistor T3 according to the signal obtained between the OTP element AS3 and the reference resistor R3a. In other words, the configurable signal is associated with the state of the OTP element AS3. The OTP element AS3 is similar to the OTP element AS1 in FIG. 3, so a detailed description thereof is omitted. Transistor T3 can be turned on or off in response to a configurable signal generated by the latch circuit 433 .

The configurable reference resistor unit 405 may include an OTP element AS4 configured to receive a power supply signal VDD. OTP element AS4 may be connected to reference resistor R4a. For example, reference resistor R4a may be connected in series with OTP element AS4. The OTP element AS4 can be configured to receive the power signal VDD through the transistor T11. The transistor T11 has a gate configured to receive a control signal P0. In some embodiments, transistor T12 is coupled between OTP element AS4 and reference resistor R4a. The transistor T12 has a gate configured to receive the control signal P0.

As shown in FIG. 4, the latch circuit 434 is coupled to the OTP element AS4. The latch circuit 434 can be coupled to the OTP element AS4 via the transistor T16. That is, the transistor T16 can be connected between the OTP element AS4 and the latch circuit 434 . The transistor T16 has a gate configured to receive the control signal P0. In some embodiments, the transistor T16 is configured to be turned on to transmit the signal obtained between the OTP element AS4 and the reference resistor R4 a to the latch circuit 434 .

In some embodiments, the latch circuit 434 can output a configurable signal to the gate of the transistor T4 according to the signal obtained between the OTP element AS4 and the reference resistor R4a. In other words, the configurable signal is associated with the state of the OTP element AS4. The OTP element AS4 is similar to the OTP element AS1 in FIG. 3, so a detailed description thereof is omitted. Transistor T4 can be turned on or off in response to a configurable signal generated by latch circuit 434 .

In some embodiments, the latch circuits 431 , 432 , 433 , 434 are similar to the latch circuit 330 in FIG. 3 , and thus a detailed description thereof is omitted.

In some embodiments, in response to the control signal P0, the transistors T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16 are configured to conduct, thereby generating the signal X at the node W . In some embodiments, a resistance of one of the configurable reference resistor units 405 is associated with OTP elements AS1 , AS2 , AS3 , AS4 . By programming one or more OTP elements AS1, AS2, AS3, AS4, the total resistance of the configurable reference resistor unit 405 can be adjusted.

Please refer to FIG. 4 , the OTP element AS1 can be coupled to the conductive contact point 422 and has received a state setting signal VB. The state setting signal VB in FIG. 4 may be the same as the state setting signal VB in FIG. 3 . In some embodiments, the transistor T17 may be coupled between the conductive contact 422 and the OTP element AS1. The transistor T17 has a gate configured to receive a control signal P1. In some embodiments, transistor T18 may be coupled between OTP element AS1 and ground. The transistor T18 has a gate configured to receive the control signal P1. In response to the control signal P1, the transistors T17 and T18 are turned on so that the state setting signal VB can be applied to the OTP element AS1. Since the state setting signal VB is applied to the OTP element AS1, a state of the OTP element AS1 can be changed. In other words, the OTP element AS1 can be programmed under the state setting signal VB.

In some embodiments, the OTP element AS2 can be coupled to the conductive contact 422 to receive a state setting signal VB. The state setting signal VB in FIG. 4 may be the same as the state setting signal VB in FIG. 3 . In some embodiments, the transistor T19 may be coupled between the conductive contact 422 and the OTP element AS2. The transistor T19 has a gate configured to receive a control signal P2. In some embodiments, transistor T20 may be coupled between OTP element AS2 and ground. The transistor T20 has a gate configured to receive the control signal P2. In response to the control signal P2, the transistors T19 and T20 are configured to be turned on so that the state setting signal VB can be applied to the OTP element AS2. Since the state setting signal VB is applied to the OTP element AS2, a state of the OTP element AS2 can be changed. In other words, the OTP element AS2 can be programmed under the state setting signal VB.

In some embodiments, the OTP element AS3 can be coupled to the conductive contact 422 to receive a state setting signal VB. The state setting signal VB in FIG. 4 may be the same as the state setting signal VB in FIG. 3 . In some embodiments, the transistor T21 may be coupled between the conductive contact 422 and the OTP element AS3. The transistor T21 has a gate configured to receive a control signal P3. In some embodiments, transistor T22 may be coupled between OTP element AS3 and ground. The transistor T22 has a gate configured to receive the control signal P3. In response to the control signal P3, the transistors T21 and T22 are configured to be turned on so that the state setting signal VB can be applied to the OTP element AS3. Since the state setting signal VB is applied to the OTP element AS3, a state of the OTP element AS3 can be changed. In other words, the OTP element AS3 can be programmed under the state setting signal.

In some embodiments, the OTP element AS4 can be coupled to the conductive contact 422 to receive a state setting signal VB. The state setting signal VB in FIG. 4 may be the same as the state setting signal VB in FIG. 3 . In some embodiments, the transistor T23 may be coupled between the conductive contact 422 and the OTP element AS4. The transistor T23 has a gate configured to receive a control signal P4. In some embodiments, transistor T24 may be coupled between OTP element AS4 and ground. The transistor T24 has a gate configured to receive the control signal P4. In response to the control signal P4, the transistors T23 and T24 are configured to be turned on so that the state setting signal VB can be applied to the OTP element AS4. Since the state setting signal VB is applied to the OTP element AS4, a state of the OTP element AS4 can be changed. In other words, the OTP element AS4 can be programmed under the state setting signal.

The resistance of the configurable reference resistor unit 405 can be adjusted by programming one or more OTP elements AS1 , AS2 , AS3 , AS4 as needed. In some embodiments, configurable reference resistor unit 405 includes sixteen configurations, each of which provides a different total resistance. Details of the configurations of the configurable reference resistor unit 405 are provided in Table 1 below. In Table 1, rows AS1 , AS2 , AS3 , and AS4 list the states of the corresponding OTP devices, where "0" represents an unprogrammed state, and "1" represents a programmed state. The total resistance row displays the total resistance of the configurable reference resistor unit 405 in each configuration. Table 1 configuration AS1 AS2 AS3 AS4 total resistance 1 0 0 0 0 0 2 1 0 0 0 R1 3 0 1 0 0 R2 4 0 0 1 0 R3 5 0 0 0 1 R4 6 1 1 0 0 R1+R2 7 1 0 1 0 R1+R3 8 1 0 0 1 R1+R4 9 0 1 1 0 R2+R3 10 0 1 0 1 R2+R4 11 0 0 1 1 R3+R4 12 1 1 1 0 R1+R2+R3 13 1 1 0 1 R1+R2+R4 14 1 0 1 1 R1+R3+R4 15 0 1 1 1 R2+R3+R4 16 1 1 1 1 R1+R2+R3+R4

In some embodiments, resistor R1 can be 100 kΩ; resistor R2 can be 200 kΩ; resistor R3 can be 400 kΩ; and resistor R4 can be 800 kΩ. Accordingly, the total resistance may be variable, ranging from 0 to 1500 kΩ. Again, the total resistance for each configuration in this example is provided in Table 1A below. Table 1A configuration AS1 AS2 AS3 AS4 Total resistance (kΩ) 1 0 0 0 0 0 2 1 0 0 0 100 3 0 1 0 0 200 4 0 0 1 0 400 5 0 0 0 1 800 6 1 1 0 0 300 7 1 0 1 0 500 8 1 0 0 1 900 9 0 1 1 0 600 10 0 1 0 1 1000 11 0 0 1 1 1200 12 1 1 1 0 700 13 1 1 0 1 1100 14 1 0 1 1 1300 15 0 1 1 1 1400 16 1 1 1 1 1500

As shown in FIG. 4, the OTP elements AS1, AS2, AS3, and AS4 are not programmed. FIG. 4 may represent configuration 1 listed in Table 1 and Table 1A. That is, the total resistance of the configurable reference resistor unit 405 may be 0Ω.

FIG. 4A is an exemplary architectural diagram illustrating an exemplary configuration of a configurable reference resistor unit 405a according to some embodiments of the present disclosure. The configurable reference resistor unit 405a in FIG. 4A is similar to the configurable reference resistor unit 405 in FIG. OTP element AS1.

FIG. 4A shows configuration 2 listed in Table 1 and Table 1A when the OTP element AS1 is programmed. That is, in this embodiment, the total resistance of the configurable reference resistor unit 405a is the same as the resistance of the resistor R1. According to the embodiment shown in Table 1A, the total resistance of the configurable reference resistor unit 405a may be 100 kΩ.

FIG. 4B is an exemplary architectural diagram illustrating an exemplary configuration of a configurable reference resistor unit 405b according to some embodiments of the present disclosure. The configurable reference resistor unit 405b in FIG. 4B is similar to the configurable reference resistor unit 405 in FIG. OTP components AS1 and AS2.

When OTP elements AS1 and AS2 are programmed, FIG. 4B shows configuration 6 listed in Table 1 and Table 1A. That is, in this embodiment, the total resistance of the configurable reference resistor unit 405b is the same as the sum of the resistors R1 and R2. According to the embodiment shown in Table 1A, the total resistance of the configurable reference resistor unit 405b may be 300 kΩ.

FIG. 4C is an exemplary architectural diagram illustrating an exemplary configuration of a configurable reference resistor unit 405c according to some embodiments of the present disclosure. Configurable reference resistor unit 405c in FIG. 4C is similar to configurable reference resistor unit 405 in FIG. The OTP components AS1, AS2, AS3, AS4. In other words, all OTP elements are programmed in the configurable reference resistor unit 405c.

When the OTP elements AS1, AS2, AS3, AS4 are programmed, FIG. 4C shows the configuration 16 listed in Table 1 and Table 1A. That is, in this embodiment, the total resistance of the configurable reference resistor unit 405c is the same as the sum of the resistors R1, R2, R3, R4. According to the embodiment shown in Table 1A, the total resistance of the configurable reference resistor unit 405c may be 1500 kΩ.

FIG. 5 is a block diagram illustrating a configurable reference resistor unit 105B of some embodiments of the present disclosure. In some embodiments, the elements shown in Figure 5 are similar to Figure 3 but have a different configuration. Accordingly, the detailed descriptions of those elements in the paragraphs associated with FIG. 3 are applicable to those elements in FIG. 5, such as OTP element AS1.

As shown in FIG. 5 , the configurable reference resistor unit 105B may include a resistor R1 , a transistor T1 and a configurable unit 500 . The configurable cell 500 is configured to generate a configurable signal N to be provided to the transistor T1. In some embodiments, the configurable unit 500 may include the OTP element AS1 , a resistor R1 a , four transistors T2 , T3 , T4 , T5 , a latch circuit 530 and a conductive contact 522 . In some embodiments, the latch circuit 530 may include two inverters.

In some embodiments, the resistor R1 is configured to receive the power signal VDD. Transistor T1 is connected to resistor R1. For example, transistor T1 can be connected in series with resistor R1. In some embodiments, the transistor T1 is configured to receive the power signal VDD. Transistor T1 has a gate connected to configurable cell 500 . In some embodiments, the gate of transistor T1 can be configured to receive the configurable signal N generated by the configurable cell 500 . In response to a configurable signal N, the transistor T1 can be turned on or off.

In some embodiments, the resistances of the resistors R1 and R2 may be in the kΩ range. In some embodiments, the resistance of resistors R1 and R2 can each be 100kΩ, 200kΩ, 300kΩ, 400kΩ, 500kΩ, 800kΩ, 1MΩ, 1.5MΩ, 2MΩ, 3MΩ, 4MΩ, 5MΩ, 6MΩ, 7MΩ, 8MΩ, or more big. The resistance of the resistor R1 can be determined according to needs. When the transistor T1 is turned on, the resistance of the configurable reference resistor unit 105B is the same as that of the resistor R1. When the transistor T1 is turned off, the resistance of the configurable reference resistor unit 105B is approximately ∞Ω.

As shown in FIG. 5 , the configurable unit 500 includes an OTP element AS1 , a resistor R1 a , four transistors T2 , T3 , T4 , T5 and a latch circuit 530 . The OTP component AS1 can be configured to receive the power signal VDD. OTP element AS1 may be connected to reference resistor R1a. In some embodiments, reference resistor R1a may be connected in series with OTP element AS1. The OTP element AS1 can be configured to receive the power signal VDD through the transistor T2. The transistor T2 has a gate configured to receive a control signal P1. In some embodiments, transistor T3 is coupled between OTP element AS1 and reference resistor R1a. The transistor T3 has a gate configured to receive the control signal P1.

In response to the control signal P1, the transistors T2 and T3 are turned on to generate a signal M at the node G between the OTP element AS1 and the reference resistor R1a. In some embodiments, the transistors T2 and T3 can be turned on to establish a conduction circuit (not shown) in response to the power signal VDD, and the conduction path passes through the OTP element AS1 and the reference resistor R1a to ground.

In some embodiments, the signal M is generated at the node G between the OTP element AS1 and the reference resistor R1a in response to the power signal VDD. Please refer to FIG. 5 , the signal M generated at the node G can be transmitted to the latch circuit 530 through the transistor T4 .

In some embodiments, the latch circuit 530 is configured to read the signal M generated at the node G, which is between the OTP element AS1 and the reference resistor R1a. The node G is located between the OTP element AS1 and the reference resistor R1a with or without other elements coupled therebetween. For example, node G can be located between transistors T3 and T4. In one embodiment, the node G may be located between the transistor T3 and the OTP device AS1.

The transistor T4 is coupled between the reference resistor R1a and the latch circuit 530 . The transistor T4 has a gate configured to receive the control signal P1. In some embodiments, the transistor T4 is configured to be turned on, thereby transmitting the signal M to the latch circuit 530 . When transistors T2 , T3 , T4 are configured to conduct, thereby establishing a conduction path through OTP element AS1 and reference resistor R1 a , signal M is obtained at node G and transmitted to latch circuit 530 . In some embodiments, the latch circuit 530 can convert the signal M into a configurable signal N. In some embodiments, the latch circuit 530 is similar to the latch circuit 330 in FIG. 3 , and thus a detailed description thereof is omitted.

The configurable signal N (or signal M) is associated with the state of the OTP element AS1 (eg OTP element AS1 is programmed). The configurable signal N (or signal M) can be output to the gate of the transistor T1 to turn on or off the transistor T1.

Please refer to FIG. 5 , the OTP element AS1 can be coupled to the conductive contact point 522 to receive a state setting signal VB. The state setting signal VB in FIG. 5 may be similar to the state setting signal VB in FIG. 2 . In some embodiments, the state setting signal VB may have a voltage capable of programming (fusing) the OTP device AS1. In some embodiments, transistor T5 may be coupled between OTP element AS1 and ground. The transistor T5 has a gate configured to receive a control signal P2.

In some embodiments, in response to the control signal P2, the transistor T5 is configured to be turned on so that the state setting signal VB can be applied to the OTP element AS1. Since the state setting signal VB is applied to the OTP element AS1, a state of the OTP element AS1 can be changed. In some embodiments, the OTP device AS1 can be programmed by the state setting signal VB.

Similarly, the number of the resistors included in the configurable reference resistor unit 105B may be greater. The flexibility of the variable resistor is improved when more resistors are included in the configurable reference resistor unit 105B. In some embodiments, the number of configurable units in configurable reference resistor unit 105B may be greater. In some embodiments, the number of configurable cells may correspond to the number of resistors.

FIG. 6 is a block diagram illustrating a configurable reference resistor unit 605 of some embodiments of the present disclosure. The configurable reference resistor unit 605 in FIG. 6 is similar to the configurable reference resistor unit 105B in FIG. Cell 605 includes more resistors as well as OTP elements.

As shown in FIG. 6, the configurable reference resistor unit 605 may include resistors R1, R2, R3, R4, OTP elements AS1, AS2, AS3, AS4, reference resistors R1a, R2a, R3a, R4a, transistor T1 , T2, T3, T, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, T19, T20, latch circuits 631, 632, 633, 634 and Conductive contacts 621 , 622 , 623 , 624 .

In some embodiments, the resistor R1 is configured to receive the power signal VDD. Resistor R1 may be connected to transistor T1. For example, resistor R1 can be connected in series with transistor T1. In some embodiments, the transistor T1 is configured to receive the power signal VDD. Resistor R1 may be connected to resistor R2. In some embodiments, resistor R1 may be connected in parallel with resistor R2. In some embodiments, resistor R1 may be connected to node W.

In some embodiments, the resistor R2 is configured to receive the power signal VDD. Resistor R2 may be connected to transistor T2. For example, resistor R2 can be connected in series with transistor T2. In some embodiments, the transistor T2 is configured to receive the power signal VDD. Resistor R2 may be connected to resistor R3. In some embodiments, resistor R2 may be connected in parallel with resistor R3. In some embodiments, resistor R2 may be connected to node W.

In some embodiments, the resistor R3 is configured to receive the power signal VDD. Resistor R3 may be connected to transistor T3. For example, resistor R3 can be connected in series with transistor T3. In some embodiments, the transistor T3 is configured to receive the power signal VDD. Resistor R3 may be connected to resistor R4. In some embodiments, resistor R3 may be connected in parallel with resistor R4. In some embodiments, resistor R3 may be connected to node W.

In some embodiments, the resistor R4 is configured to receive the power signal VDD. Resistor R4 may be connected to transistor T4. For example, resistor R4 can be connected in series with transistor T4. In some embodiments, resistor R4 may be connected to node W. Resistors R1 , R2 , R3 , R4 may be connected to node W in some embodiments. In other words, resistors R1, R2, R3, R4 may be connected in parallel.

Resistors R1, R2, R3, R4 may have the same resistance. In some embodiments, resistors R1, R2, R3, R4 may have different resistances. For example, the resistance of resistor R1 may exceed that of resistor R2. The resistance of resistor R1 may drop below resistor R2. In some embodiments, the resistance of resistors R1, R2, R3, R4 can each be 100kΩ, 200kΩ, 300kΩ, 400kΩ, 500kΩ, 800kΩ, 1MΩ, 1.5MΩ, 2MΩ, 3MΩ, 4MΩ, 5MΩ, 6MΩ, 7MΩ, 8MΩ or greater. Resistors R1, R2, R3, R4 can be selected according to needs.

Please refer to FIG. 6, the configurable reference resistor unit 605 includes four configurable units (similar to the configurable unit 500 in FIG. 5), which correspond to transistors T1, T2, T3, T4. The gate of each transistor T1 , T2 , T3 , T4 can receive a corresponding configurable signal generated by a corresponding configurable unit (not shown in FIG. 6 ).

Configurable reference resistor unit 605 may include OTP element AS1 configured to receive power signal VDD. OTP element AS1 may be connected to reference resistor R1a. For example, reference resistor R1a may be connected in series with OTP element AS1. The OTP element AS1 can be configured to receive the power signal VDD through the transistor T5. The transistor T5 has a gate configured to receive a control signal P0. In some embodiments, transistor T6 is coupled between OTP element AS1 and reference resistor R1a. The transistor T6 has a gate configured to receive the control signal P0.

As shown in FIG. 6, the latch circuit 631 is coupled to the OTP element AS1. The latch circuit 631 can be coupled to the OTP element AS1 via the transistor T7. That is, the transistor T7 can be connected between the OTP element AS1 and the latch circuit 631 . The transistor T7 has a gate configured to receive the control signal P0. In some embodiments, the transistor T7 is configured to be turned on so as to transmit the signal obtained between the OTP element AS1 and the reference resistor R1 a to the latch circuit 631 .

In some embodiments, the latch circuit 631 can output a configurable signal to the gate of the transistor T1 according to the signal obtained between the OTP element AS1 and the reference resistor R1a. In other words, the configurable signal is associated with the state of the OTP element AS1. The OTP element AS1 is similar to the OTP element AS1 in FIG. 3 and thus a detailed description thereof is omitted. Transistor T1 is turned on in response to a configurable signal generated by latch circuit 631 .

Configurable reference resistor unit 605 may include OTP element AS2 configured to receive power signal VDD. OTP element AS2 may be connected to reference resistor R2a. For example, reference resistor R2a may be connected in series with OTP element AS2. The OTP element AS2 can be configured to receive the power signal VDD through the transistor T8. The transistor T8 has a gate configured to receive a control signal P0. In some embodiments, transistor T9 is coupled between OTP element AS2 and reference resistor R2a. The transistor T9 has a gate configured to receive the control signal P0.

As shown in FIG. 6, the latch circuit 632 is coupled to the OTP element AS2. The latch circuit 632 can be coupled to the OTP element AS2 via the transistor T10. That is, the transistor T10 can be connected between the OTP element AS2 and the latch circuit 632 . The transistor T10 has a gate configured to receive the control signal P0. In some embodiments, the transistor T10 is configured to be turned on, thereby transmitting the signal obtained between the OTP element AS2 and the reference resistor R2 a to the latch circuit 632 .

In some embodiments, the latch circuit 632 can output to the gate of the transistor T2 according to the signal obtained between the OTP element AS2 and the reference resistor R2a. In other words, the configurable signal is associated with the state of the OTP element AS2. The OTP element AS2 is similar to the OTP element AS2 in FIG. 3 and thus a detailed description thereof is omitted. Transistor T2 is turned on in response to a configurable signal generated by latch circuit 632 .

Configurable reference resistor unit 605 may include OTP element AS3 configured to receive power signal VDD. OTP element AS3 may be connected to reference resistor R3a. For example, reference resistor R3a may be connected in series with OTP element AS3. The OTP element AS3 can be configured to receive the power signal VDD through the transistor T11. The transistor T11 has a gate configured to receive a control signal P0. In some embodiments, transistor T12 is coupled between OTP element AS3 and reference resistor R3a. The transistor T12 has a gate configured to receive the control signal P0.

As shown in FIG. 6, the latch circuit 633 is coupled to the OTP element AS3. The latch circuit 633 can be coupled to the OTP element AS3 via the transistor T13. That is, the transistor T13 can be connected between the OTP element AS3 and the latch circuit 633 . The transistor T13 has a gate configured to receive the control signal P0. In some embodiments, the transistor T13 is configured to be turned on so as to transmit the signal obtained between the OTP element AS3 and the reference resistor R3 a to the latch circuit 633 .

In some embodiments, the latch circuit 633 can output to the gate of the transistor T3 according to the signal obtained between the OTP element AS3 and the reference resistor R3a. In other words, the configurable signal is associated with the state of the OTP element AS3. The OTP element AS3 is similar to the OTP element AS3 in FIG. 3 and thus a detailed description thereof is omitted. Transistor T3 is turned on in response to a configurable signal generated by latch circuit 633 .

Configurable reference resistor unit 605 may include OTP element AS4 configured to receive power signal VDD. OTP element AS4 may be connected to reference resistor R4a. For example, reference resistor R4a may be connected in series with OTP element AS4. The OTP element AS4 can be configured to receive the power signal VDD through the transistor T14. The transistor T14 has a gate configured to receive a control signal P0. In some embodiments, transistor T15 is coupled between OTP element AS4 and reference resistor R4a. The transistor T15 has a gate configured to receive the control signal P0.

As shown in FIG. 6, the latch circuit 634 is coupled to the OTP element AS4. The latch circuit 634 can be coupled to the OTP element AS4 via the transistor T16. That is, the transistor T16 can be connected between the OTP element AS4 and the latch circuit 634 . The transistor T16 has a gate configured to receive the control signal P0. In some embodiments, the transistor T16 is configured to be turned on to transmit the signal obtained between the OTP element AS4 and the reference resistor R4 a to the latch circuit 634 .

In some embodiments, the latch circuit 634 can output to the gate of the transistor T4 according to the signal obtained between the OTP element AS4 and the reference resistor R4a. In other words, the configurable signal is associated with the state of the OTP element AS4. The OTP element AS4 is similar to the OTP element AS4 in FIG. 3, so a detailed description thereof is omitted. Transistor T4 is turned on in response to a configurable signal generated by latch circuit 634 .

In some embodiments, the OTP elements AS1 , AS2 , AS3 , AS4 are similar to the OTP element AS1 in FIG. 5 , and thus their detailed descriptions are omitted.

In some embodiments, the transistors T5 , T6 , T7 , T8 , T9 , T10 , T11 , T12 , T13 , T14 , T15 , T16 are turned on to generate the signal X at the node W in response to the control signal P0 . In some embodiments, the configurable reference resistor unit 605 is associated with a state of the OTP elements AS1, AS2, AS3, AS4. By programming one or more OTP elements AS1, AS2, AS3, AS4, the total resistance of the configurable reference resistor unit 605 can be adjusted.

Please refer to FIG. 6 , the OTP element AS1 can be coupled to the conductive contact 621 to receive a state setting signal VB. The state setting signal VB in FIG. 6 may be the same as the state setting signal VB in FIG. 5 . In some embodiments, the transistor T17 may be coupled between the OTP element AS1 and ground. The transistor T17 has a gate configured to receive a control signal P1. In response to the control signal P1, the transistor T17 is configured to be turned on so that the state setting signal VB can be applied to the OTP element AS1. Since the state setting signal VB is applied to the OTP element AS1, a state of the OTP element AS1 can be changed. In other words, the OTP device AS1 can be programmed through the state setting signal VB.

In some embodiments, the OTP element AS2 can be coupled to the conductive contact 622 to receive a state setting signal VB. The state setting signal VB in FIG. 6 may be the same as the state setting signal VB in FIG. 5 . In some embodiments, transistor T18 may be coupled between OTP element AS2 and ground. The transistor T18 has a gate configured to receive a control signal P2. In response to the control signal P2, the transistor T18 is configured to be turned on so that the state setting signal VB can be applied to the OTP element AS2. Since the state setting signal VB is applied to the OTP element AS2, a state of the OTP element AS2 can be changed. In other words, the OTP element AS2 can be programmed under the state setting signal VB.

In some embodiments, the OTP element AS3 can be coupled to the conductive contact 623 to receive a state setting signal VB. The state setting signal VB in FIG. 6 may be the same as the state setting signal VB in FIG. 5 . In some embodiments, transistor T19 may be coupled between OTP element AS3 and ground. The transistor T19 has a gate configured to receive a control signal P3. In response to the control signal P3, the transistor T19 is configured to be turned on so that the state setting signal VB can be applied to the OTP element AS3. Since the state setting signal VB is applied to the OTP element AS3, a state of the OTP element AS3 can be changed. In other words, the OTP element AS3 can be programmed under the state setting signal VB.

In some embodiments, the OTP element AS4 can be coupled to the conductive contact 624 to receive a state setting signal VB. The state setting signal VB in FIG. 6 may be the same as the state setting signal VB in FIG. 5 . In some embodiments, transistor T20 may be coupled between OTP element AS4 and ground. The transistor T20 has a gate configured to receive a control signal P4. In response to the control signal P4, the transistor T20 is configured to be turned on so that the state setting signal VB can be applied to the OTP element AS4. Since the state setting signal VB is applied to the OTP element AS4, a state of the OTP element AS4 can be changed. In other words, the OTP element AS4 can be programmed under the state setting signal VB.

The resistance of the configurable reference resistor unit 605 can be adjusted by one or more OTP elements AS1 , AS2 , AS3 , AS4 as needed. In some embodiments, configurable reference resistor unit 605 includes fifteen different configurations, each of which provides a different total resistance. The detailed configuration of the configurable reference resistor unit 605 is provided in Table 2 below. Rows AS1 , AS2 , AS3 , and AS4 show the states of the corresponding OTP components, where "0" represents an unprogrammed state, and "1" represents a programmed state. The total resistance row shows the total resistance of the configurable reference resistor unit 605 in each configuration. Table 2 configuration AS1 AS2 AS3 AS4 total resistance 1 0 0 0 0 1/(1/R1+1/R2+1/R3+1/R4) 2 1 0 0 0 1/(1/R2+1/R3+1/R4) 3 0 1 0 0 1/(1/R1+1/R3+1/R4) 4 0 0 1 0 1/(1/R1+1/R2+1/R4) 5 0 0 0 1 1/(1/R1+1/R2+1/R3) 6 1 1 0 0 1/(1/R3+1/R4) 7 1 0 1 0 1/(1/R2+1/R4) 8 1 0 0 1 1/(1/R2+1/R3) 9 0 1 1 0 1/(1/R1+1/R4) 10 0 1 0 1 1/(1/R1+1/R3) 11 0 0 1 1 1/(1/R1+1/R2) 12 1 1 1 0 R4 13 1 1 0 1 R3 14 1 0 1 1 R2 15 0 1 1 1 R1 16 1 1 1 1 ∞

In some embodiments, resistor R1 may be 1 MΩ, resistor R2 may be 2 MΩ, resistor R3 may be 4 MΩ, and resistor R4 may be 8 MΩ. Accordingly, the total resistance may be variable, ranging from 0.375 to 8 MΩ. Since configuration 16 has a total resistance of an infinite value, it generally cannot be applied in normal conditions. Accordingly, the total resistance may be variable, ranging from 0.533 to 8 MΩ. Again, the total resistance for each configuration in this example is provided in Table 2A below. Table 2A configuration AS1 AS2 AS3 AS4 Total resistance (MΩ) 1 0 0 0 0 0.533 2 1 0 0 0 1.143 3 0 1 0 0 0.727 4 0 0 1 0 0.615 5 0 0 0 1 0.571 6 1 1 0 0 2.667 7 1 0 1 0 1.6 8 1 0 0 1 1.333 9 0 1 1 0 0.889 10 0 1 0 1 0.8 11 0 0 1 1 0.667 12 1 1 1 0 8 13 1 1 0 1 4 14 1 0 1 1 2 15 0 1 1 1 1 16 1 1 1 1 ∞

As shown in FIG. 6 , the OTP components AS1 , AS2 , AS3 , and AS4 are not blown. Figure 6 shows configuration 1 listed in Table 2 and Table 2A. That is, the configurable reference resistor unit 605 can be regarded as a parallel equivalent resistance of the resistors R1 , R2 , R3 , R4 . According to the embodiment of Table 2A, the total resistance of the configurable reference resistor unit 605 may be approximately 0.533 MΩ.

FIG. 6A is an exemplary architectural diagram illustrating a configurable reference resistor unit 605a according to some embodiments of the present disclosure. The configurable reference resistor unit 605a in FIG. 6A is similar to the configurable reference resistor unit 605 in FIG. OTP element AS1.

When the OTP element AS1 is programmed, FIG. 6A shows configuration 1 listed in Table 2 and Table 2A. That is, in this embodiment, the total resistance of the configurable reference resistor unit 605a can be regarded as the parallel resistance of the resistors R2, R3, R4. According to the embodiment of Table 2A, the total resistance of the configurable reference resistor unit 605a may be 1.143 MΩ.

FIG. 7 is a flowchart illustrating a method 700 for determining the state of a fuse element according to some embodiments of the present disclosure. For example, method 700 may be utilized to determine a state of fuse element 101 of FIG. 2 . The method 700 for determining the state of a fuse element 101 in a memory element may include steps 701 , 702 , 703 , 704 , 705 , 706 . In some embodiments, the method 700 may be performed by a system as shown in FIG. 1 .

For better understanding, the method 700 may be described with reference to the semiconductor device (memory device) 100 shown in FIG. 2 . In step 701 , a memory element can be provided, and the memory element includes an input terminal and an output terminal. In some embodiments, the memory device may include one or more cells or memory bits.

In step 702, a power signal VDD may be applied to the input terminal of the memory device. In some embodiments, the memory device may include a configurable reference resistor unit 105 and a fuse element 101 . The configurable reference resistor unit 105 is electrically coupled to the fuse element 101 .

In step 703 , a signal X may be generated at a node W between the configurable reference resistor unit 105 and the fuse element 101 in response to the power signal. In some embodiments, the resistance of the configurable reference resistor unit 105 may exceed the resistance of the fuse element 101 . In another embodiment, the configurable reference resistor unit 105 may have a lower resistance than the fuse element 101 .

In step 704 , the signal X can be converted into a signal Y by a latch circuit 130 . In some embodiments, the latch circuit 130 is electrically coupled to the node W. In some embodiments, the process of converting the signal may include inverting or phase shifting the signal. In other words, signal X can be inverted into signal Y. Signal X can be phase shifted to become signal Y. In some embodiments, the signal X can be compared with a predetermined signal. Accordingly, a signal Y may be generated in response to the comparison result. In some embodiments, the step of comparing can be performed by the latch circuit. In some embodiments, the comparing step can be performed by an external system coupled to the memory device.

In some embodiments, according to the comparison between the signal X and the predetermined signal, the logic signal Y can be output at the output terminal of the memory device. When the signal X exceeds the predetermined signal, it indicates that the fuse element is not blown. On the contrary, when the signal X does not exceed the predetermined signal, it indicates that the fuse element 101 has been blown.

In some embodiments, since the signal X exceeds the predetermined signal, the latch circuit 130 can output a logic high signal Y. On the contrary, when the signal X is lower than the predetermined signal, the latch circuit 130 can output a logic low signal Y.

In step 705, an evaluation signal Y is available at the output terminal of the memory element.

In step 706, signal Y is judged to determine whether the memory device is redundant. In some embodiments, the state of the fuse element 101 can be used to determine whether the semiconductor element is a redundant element or a normal element. In some embodiments, the step of identifying signal Y may be performed by a system external to the memory device. In some embodiments, when identified as a logic high signal Y, it indicates that the fuse element 101 is blown, and a logic low signal Y indicates that the fuse element 101 is not blown.

When the signal is recognized, the state of the fuse element can be determined. Accordingly, the memory status (normal or redundant) can be determined. Memory problems can be easily resolved due to improved state discrimination.

An embodiment of the present disclosure provides a semiconductor device for determining the state of a fuse element of a memory device. The semiconductor circuit includes a configurable reference resistor unit having a first terminal and a second terminal, the first terminal receives a first power signal, and the second terminal is configured to be electrically coupled to the fuse element. In addition, the semiconductor circuit also includes a first latch circuit configured to read a first state signal of a first node located between the configurable reference resistor unit and the fuse between components. The configurable reference resistor unit includes a first resistor; a first transistor connected in parallel with the first resistor; and a first configurable unit connected to a gate of the first transistor pole. The first configurable unit is configured to generate a first configurable signal to be provided to the gate of the first transistor.

Another embodiment of the present disclosure provides a semiconductor device for determining the state of a fuse element of a memory device. The semiconductor element includes a configurable reference resistor unit having a first terminal and a second terminal, the first terminal receives a first power signal, and the second terminal is configured to be electrically connected to the fuse element coupling. The configurable reference resistor unit includes a first resistor; a first transistor connected in series with the first resistor; and a first configurable unit connected to a gate of the first transistor pole. The first configurable unit is configured to generate a first configurable signal to be provided to the gate of the first transistor.

Another embodiment of the present disclosure provides a method of determining the state of a fuse element of a memory device. The method includes providing the memory element with a first terminal and a second terminal; and applying a first power signal to the first terminal of the memory element. The memory element includes a configurable reference resistor unit electrically coupled to the fuse element. The method also includes obtaining an evaluation signal at the second terminal of the memory device in response to the first power signal; and identifying the evaluation signal to determine whether the memory device is redundant. The configurable reference resistor unit includes a first resistor; a first transistor connected in parallel with the first resistor; and a first configurable unit connected to a gate of the first transistor pole. The first configurable unit is configured to generate a first configurable signal to turn on the first transistor.

The configurable resistor unit is represented as a variable resistance. The variable resistor can be adjusted according to the resistance change of the fuse element caused by the process changes. According to the actual resistance value of the corresponding fuse element, the resistance value of the configurable reference resistor can be modified after the element is manufactured. Therefore, the flexibility of the present disclosure is increased. In addition, the configurable reference resistor unit is adjusted by programming the OTP device (such as an antifuse), which reduces the impact on adjacent areas during programming. The component with the flexibility resistor eliminates the need to add an additional photomask for the reference resistor, reducing production time.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such process, machinery, manufacture, material composition, means, method, or steps are included in the patent scope of this application.

10: System 11: Semiconductor components 12: Signal generator 13: Monitor 14: Coupler 15: Probe 100: Semiconductor components 100C: Equivalent circuit 101: Fuse element 105: Configurable reference resistor unit 105A: Configurable reference resistor unit 105A': Equivalent circuit 105B: Configurable reference resistor unit 105-1: Terminal 105-2: Terminal 110: Evaluation Units 111A: Conductive path 111B: Conductive path 120: State setting unit 122: Conductive contact point 130: Latch circuit 131: Inverter 132: Inverter 300: Configurable unit 310: Stylized circuits 310a: Stylized circuits 322: Conductive contact point 330: Latch circuit 331: Inverter 332: Inverter 405: Configurable reference resistor unit 405a: Configurable reference resistor unit 405b: Configurable reference resistor unit 405c: Configurable reference resistor unit 422: Conductive contact point 431: Latch circuit 432: Latch circuit 433: Latch circuit 434: Latch circuit 500: Configurable units 522: Conductive contact point 530: Latch circuit 605: Configurable reference resistor unit 605a: Configurable reference resistor unit 621: Conductive contact point 622: Conductive contact point 623: Conductive contact point 624: Conductive contact point 631: Latch circuit 632: Latch circuit 633: Latch circuit 634: Latch circuit 700: method 701: Step 702: Step 703: Step 704: Step 705: Step 706: Step AS1: Single Programmable Components AS2: Single Programmable Components AS3: Single Programmable Components AS4: Single Programmable Components G: node IN_1: Input terminal IN_2: Input terminal M: signal N: configurable signal OUT_1: output terminal OUT_2: output terminal P0: Control signal P1: Control signal P2: Control signal P3: Control signal P4: Control signal R1: Resistor R1a: Reference resistor R2: Resistor R2a: Reference resistor R3: Resistor R3a: Reference resistor R4: Resistor R4a: Reference resistor RF: Resistor RR: Resistor T1: Transistor T2: Transistor T3: Transistor T4: Transistor T5: Transistor T6: Transistor T7: Transistor T8: Transistor T9: Transistor T10: Transistor T11: Transistor T12: Transistor T13: Transistor T14: Transistor T15: Transistor T16: Transistor T17: Transistor T18: Transistor T19: Transistor T20: Transistor T21: Transistor T22: Transistor T23: Transistor T24: Transistor TA: switching circuit TB: switch circuit TC: switching circuit TD: switching circuit TE: switching circuit VB: Status setting signal VDD: power signal VE: conductive terminal VSS: ground terminal W: node X: signal Y: signal

The disclosure content of the present application can be understood more fully when the drawings are considered together with the embodiments and the patent scope of the application. The same reference numerals in the drawings refer to the same components. FIG. 1 is a structural diagram illustrating a system for testing a plurality of semiconductor devices according to some embodiments of the present disclosure. FIG. 2 is a schematic structural diagram illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 2A is a schematic structural diagram illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 2B is a schematic structural diagram illustrating a semiconductor device according to some embodiments of the present disclosure. FIG. 2C is a schematic diagram of an equivalent circuit illustrating a portion of the semiconductor device shown in FIG. 2B in some embodiments of the present disclosure. FIG. 3 is a block diagram illustrating a configurable reference resistor unit of some embodiments of the present disclosure. FIG. 3A is a block diagram illustrating the state setting circuit shown in FIG. 3 according to some embodiments of the present disclosure. 3B is a schematic diagram of an equivalent circuit illustrating a portion of the configurable reference resistor unit shown in FIG. 3 in some implementations of the present disclosure. FIG. 4 is a block diagram illustrating a configurable reference resistor unit of some embodiments of the present disclosure. FIG. 4A is an exemplary architectural diagram illustrating a configurable reference resistor unit according to some embodiments of the present disclosure. FIG. 4B is an exemplary architectural diagram illustrating a configurable reference resistor unit according to some embodiments of the present disclosure. FIG. 4C is an exemplary architectural diagram illustrating a configurable reference resistor unit according to some embodiments of the present disclosure. FIG. 5 is a block diagram illustrating a configurable reference resistor unit of some embodiments of the present disclosure. FIG. 6 is a block diagram illustrating a configurable reference resistor unit of some embodiments of the present disclosure. FIG. 6A is an exemplary architectural diagram illustrating a configurable reference resistor unit of some embodiments of the present disclosure. FIG. 7 is a flowchart illustrating a method for determining a state of a fuse element according to some embodiments of the present disclosure.

100: Semiconductor components

101: Fuse element

105: Configurable reference resistor unit

105-1: Terminal

105-2: Terminal

110: Evaluation Units

120: State setting unit

122: Conductive contact point

130: Latch circuit

TA: switching circuit

TB: switch circuit

TC: switching circuit

TD: switching circuit

TE: switching circuit

VB: Status setting signal

VDD: power signal

VE: conductive terminal

Claims (20)

A semiconductor circuit for determining the state of a fuse element of a memory element, the semiconductor circuit comprising: A configurable reference resistor unit has a first terminal and a second terminal, the first terminal receives a first power signal, the second terminal is configured to be electrically coupled to the fuse element; and a first latch circuit configured to read a first state signal of a first node between the configurable reference resistor unit and the fuse element; Wherein the configurable reference resistor unit includes: a first resistor; a first transistor connected in parallel with the first resistor; and a first configurable unit connected to a gate of the first transistor, wherein the first configurable unit is configured to generate a first configurable signal to be provided to the first The gate of the transistor. The semiconductor circuit according to claim 1, wherein the first configurable unit further comprises: a one-time programmable device configured to receive a second power signal; a reference resistor in series with the one-time programmable element; and a second latch circuit configured to read a first mode signal at a second node between the one time programmable element and the reference resistor, wherein the first Two latch circuits are configured to convert the first mode signal into the first configurable signal, and then provide to the gate of the first transistor. The semiconductor circuit as claimed in claim 2, wherein the one-time programmable device includes an antifuse. The semiconductor circuit as claimed in claim 2, wherein a resistance value of the configurable reference resistor unit is associated with a state of the one-time programmable element. The semiconductor circuit according to claim 2, wherein the first configurable unit further comprises: a second transistor coupled to the one-time programmable device and having a gate configured to receive a first control signal; and A third transistor, coupled between the one-time programmable element and the reference resistor, has a gate configured to receive the first control signal. The semiconductor circuit as claimed in item 5, wherein in response to the second power signal applied to the one-time programmable device, the second transistor and the third transistor are configured to be turned on (tuned on), and then in The first mode signal is generated at the second node, and the second node is located between the one-time programmable device and the reference resistor. The semiconductor circuit according to claim 5, wherein the first configurable unit further comprises: a fourth transistor coupled between the one-time programmable element and the second latch circuit; Wherein the fourth transistor is configured to transmit the first mode signal to the second latch circuit. The semiconductor circuit according to claim 5, wherein the first configurable unit further comprises: A fifth transistor is coupled between a second conductive contact point and the single programmable element, and has a gate configured to receive a second control signal, wherein the fifth transistor the crystal is configured to receive a third power signal from the second conductive contact; and a sixth transistor coupled between the one-time programmable element and the ground, and having a gate configured to receive the second control signal; The one-time programmable element is programmed in response to the fifth transistor and the sixth transistor turned on by the second control signal. The semiconductor circuit according to claim 1, further comprising: a first switching circuit configured to electrically connect the configurable reference resistor unit and the fuse element; and A second switching circuit configured to electrically couple the fuse element to the ground. The semiconductor circuit of claim 9, wherein in response to the first power signal applied to the first terminal of the configurable reference resistor unit, the first switching circuit and the second switching circuit are configured to establish A first conductive path passes through the configurable reference resistor unit and the fuse element to the ground. The semiconductor circuit according to claim 1, further comprising: a first conductive contact coupled to the fuse element and configured to receive a fourth power signal; and a third switching circuit coupled between the first node and the ground; Wherein the first switching circuit, the second switching circuit and the third switching circuit are configured to establish a second conductive path, and the second conductive path passes through the fuse element to the ground. The semiconductor circuit according to claim 1, further comprising: a fourth switching circuit coupled between the configurable reference resistor unit and the first latch circuit; Wherein the fourth switching circuit is configured to transmit the first state signal to the first latch circuit, wherein the first latch circuit is configured to convert the first state signal into an evaluation signal. A semiconductor element for determining the state of a fuse element of a memory element, the semiconductor element comprising: A configurable reference resistor unit has a first terminal and a second terminal, the first terminal receives a first power signal, and the second terminal is configured to be electrically coupled with the fuse element; Wherein the configurable reference resistor unit includes: a first resistor; a first transistor connected in series with the first resistor; and A first configurable unit connected to a gate of the first transistor, wherein the first configurable unit is configured to generate a first configurable signal, which is then provided to the first transistor the gate of the crystal. The semiconductor device as claimed in claim 13, wherein the first configurable unit comprises: a one-time programmable device configured to receive a second power signal; a reference resistor in series with the one-time programmable element; and a latch circuit configured to read a first mode signal at a second node between the one time programmable element and the reference resistor, wherein the latch Circuitry is configured to convert the first mode signal into the first configurable signal, and the first configurable signal is transmitted to the gate of the first transistor. The semiconductor device as claimed in claim 14, wherein the one-time programmable device includes an antifuse. The semiconductor device as claimed in claim 14, wherein a resistance value of the configurable reference resistor unit is associated with a state of the one-time programmable device. The semiconductor device as claimed in claim 14, wherein the first configurable unit further comprises: a second transistor coupled to the one-time programmable device and having a gate configured to receive a first control signal; and A third transistor, coupled between the one-time programmable element and the reference resistor, has a gate configured to receive the first control signal. The semiconductor device as claimed in claim 17, wherein in response to the second power signal applied to the one-time programmable device, the second transistor and the third transistor are configured to conduct, thereby at the second node The first mode signal is generated at , and the second node is located between the one-time programmable element and the reference resistor. The semiconductor device as claimed in claim 17, wherein the first configurable unit further comprises: a fourth transistor coupled between the one-time programmable element and the latch circuit; Wherein the fourth transistor is configured to transmit the first mode signal to the latch circuit. The semiconductor device as claimed in claim 17, wherein the first configurable unit further comprises: a fifth transistor coupled between the one-time programmable element and the ground, and having a gate configured to receive a second control signal; wherein in response to the fifth transistor turned on by the second control signal, a third power signal from a second conductive via contact is applied to the one-time programmable element, so that the one-time programmable element stylized components.

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