KR101017775B1 - Parallel anti fuse - Google Patents

Abstract

The present invention discloses a parallel connected antifuse.

The parallel-connected antifuse of the present invention connects the series-connected sub-antifuses and the capacitors in parallel and forms a current path of the break-down sub-antifuses so that the total resistance after programming is much smaller than with a single fuse. This allows the circuit to operate normally even if a soft breakdown occurs.

Description

Parallel anti fuse

The present invention relates to an anti-fuse of MOS type (Metal-Oxide-Semiconductor) type, and more particularly, by connecting MOS type anti-fuses in parallel to reduce the resistance value of the anti-fuse, even when a soft breakdown occurs. It's a parallel-connected anti-fuse that allows the circuit to operate normally.

A semiconductor device, in particular a memory device, is treated as a defective product because it fails to function as a memory if any one of many unit cells is defective at the time of manufacture. However, even though only a few cells in the memory have failed, discarding the entire device as defective is inefficient in terms of productivity. Therefore, by replacing a defective cell using a redundancy cell previously manufactured in the memory device, the yield is improved and the cost is reduced in a manner that restores the entire device.

A repair operation using a redundancy cell is typically made in advance of a redundancy low and a redundancy column for each cell array, so that a defective memory cell in which a defective memory cell exists is present. Or by replacing columns with redundancy rows or redundancy columns. For example, if a defective memory cell is found through a test after wafer processing is completed, a program operation for converting a corresponding address into an address of a redundancy cell is performed in an internal circuit. Therefore, when an address signal corresponding to a bad line is input in actual use of the semiconductor memory device, the spare line is accessed instead of accessing the bad line.

A typical repair operation uses a fuse. The method of using a fuse is a method of installing a fuse in an internal circuit for repairing and then blowing the fuse existing in a line connected to a row or a column in which a defective cell exists by blowing an over current, and burning the fuse with a laser beam. The method refers to a method of connecting junctions to each other with a laser beam and programming with an EPROM to replace rows or columns in which defective cells exist with redundancy rows or redundancy columns. Among them, the method of disconnecting a fuse with a laser beam is widely used because it is simple, reliable, and less likely to be programmed incorrectly. A fuse using a polysilicon wire or a metal wire is used. However, the method of repairing a semiconductor device using a fuse has a limitation that cannot be applied when it is found that a defective cell exists in a state where the package is completed because the repair is performed in a wafer state. Therefore, the antifuse method was developed to overcome the limitation of the fuse method.

Antifuse can be programmed for fault relief simply at the package level. In general, antifuse devices have opposite electrical characteristics as fuse devices. That is, the antifuse generally has a high resistance (for example, 100 MΩ) when not programmed as a resistive fuse device, and a low resistance (for example, 100 KΩ or less) after the program operation. Antifuse devices typically have a dielectric such as silicon dioxide (SiO2), silicon nitride, tantalum oxide or silicon dioxide-silicon nitride-silicon dioxide (ONO) sandwiched between two conductors. It is composed of very thin dielectric materials such as composites. The program operation of the antifuse is programmed in such a way as to break down the dielectric between both conductors by applying a constant voltage (program voltage) (eg 10V) through the terminals of the antifuse for a sufficient time. Therefore, when the antifuse is programmed, the conductors at both ends of the antifuse are shorted so that the resistance becomes a small value.

As described above, antifuse is easy to program and has a large resistance difference before and after the program. Therefore, antifuse is widely used in semiconductor devices such as FPGAs, programmable read only memory (PROM), and programmable array logic (PAL).

Among these antifuses, an MOS type antifuse generally includes one MOS capacitor connected to a source / drain of an NMOS transistor as shown in FIG. 1. The MOS type antifuse breaks down the gate oxide by applying a program voltage to the gate during programming.

By the way, when using a single MOS cap as an antifuse as in the prior art, it is difficult to obtain uniform breakdown characteristics. That is, breakdown of the oxide film occurs at a weak point of the oxide film, and there is a problem in that the resistance value is different for each fuse after the breakdown because the distribution and the range of the weak parts are different for each fuse.

In addition, when a soft breakdown other than a hard breakdown occurs, an error may occur because the resistance value after the breakdown is large and the program is not normally performed.

The present invention is to improve the configuration of the anti-fuse to more stably reduce the resistance value of the anti-fuse after the breakdown and to allow the circuit to operate normally even when a soft breakdown occurs.

The parallel-connected antifuse of the present invention includes a switching unit that forms a current between the fuse sets according to a plurality of fuse sets and flag signals in which a sub antifuse and a capacitor are connected in series between both ends of a program voltage. do.

In the parallel-connected antifuse of the present invention, the sub-antifuse is composed of a metal-oxide-semiconductor (MOS) capacitor, and has a smaller capacitance than the capacitor.

In the parallel connection anti-fuse of the present invention, the switching unit may be configured by MOS transistors that are turned on / off according to the flag signal to selectively connect neighboring fuse sets and connect the connected fuse sets to a ground terminal. The MOS transistors may be turned on or off according to the flag signal to selectively connect each of the fuse sets to a ground terminal. This switching unit is turned on when the sub antifuses all break down to form a current path of the fuse sets.

The present invention can reduce the overall resistance much more than a single fuse by forming a plurality of fuses connected in parallel rather than forming a single fuse, and allows the repair operation to be performed normally even if a soft breakdown occurs.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a circuit diagram illustrating a configuration of a parallel connection antifuse according to an embodiment of the present invention.

The parallel connection antifuse of the present invention includes a plurality of fuse sets 10 to 30 and a switching unit 40.

The fuse sets 10 to 30 are connected in parallel between both ends of the fuse to which the program voltages hvdd and hvss are applied, and each of the fuse sets 10 to 30 connects the sub antifuse Ca1 to Ca3 and the capacitors Cb1 to Cb3 connected in series. Include. At this time, the sub-antifuse Ca1 ~ Ca3 is composed of MOS (Metal-Oxide-Semiconductor) type capacitor, like the conventional single antifuse, the capacitors Cb1 ~ Cb3 has a much larger capacitance than the serially connected sub-antifuse Ca1 ~ Ca3 Have

The switching unit 40 forms a current path between the fuse sets 10 to 30 according to the flag signal antifuse-flag. That is, when all of the sub antifuse Ca1 to Ca3 of the fuse sets 10 to 30 are all broken down, the switching unit 40 connects the sub antifuses Ca1 to Ca3 that are turned on and broken down according to the flag signal antifuse-flag. Let's do it. The switching unit 40 is a NMOS transistor N1 connected between a sub-antifuse Ca1 and a capacitor Cb1 and a common node of a sub-antifuse Ca2 and a capacitor Cb2, a common node and a sub-antifuse of a sub-antifuse Ca2 and a capacitor Cb2. NMOS transistor N2 connected between Ca3 and common node of capacitor Cb3, subantifuse NMOS transistor N3 connected between common node and ground power supply of Ca3 and capacitor Cb3, and flag signal antifuse-flag by inverting NMOS transistors T1 and T2 And an inverter IV applied to the gate of T3.

The flag signal antifuse-flag has a high level potential while the sub antifuses Ca1 to Ca3 connected in parallel break down, and a ground level potential after all of the sub antifuses Ca1 to Ca3 break down.

FIG. 3 is a circuit diagram illustrating a resistance component after all of the sub antifuses are broken down in the parallel-connected antifuse of FIG. 2.

The resistors R1 to R3 represent resistance values when a current flows through the gate oxide film after the breakdown in the sub-antifuse Ca1 to Ca3, respectively. The resistors R4 to R6 are NMOS transistors T1 to T3 due to the flag signal antifuse-flag, respectively. Indicates the channel resistance value when turned on.

The operation of the parallel connection antifuse of the present invention will be described with reference to FIGS. 2 and 3 as follows.

In order to program the parallel-connected antifuse of the present invention, program voltages hvdd and hvss are first applied to both ends of the fuse. At this time, the NMOS transistors T1 to T3 are turned off because the flag signal antifuse-flag maintains a high level potential.

When the program voltages hvdd (eg, 3.3V) and hvss (eg, -4V) are applied to both ends of the parallel-connected antifuse, most of the applied program voltages are applied to the subantifuse Ca1 to Ca3 and thus the subantifuse Ca1 to The gate oxide film of Ca 3 is stressed. In other words, the voltage across the capacitor is inversely proportional to the capacitance. In the present invention, the capacitors Cb1 to Cb3 have a much larger capacitance than the sub-antifuse Ca1 to Ca3 in each of the fuse sets 10 to 30. Most of them are applied to sub-antifuse Ca1 to Ca3 with small capacitance.

The gate oxide films of sub antifuse Ca1 to Ca3 are sequentially broken down by such a program voltage. In this case, since each of the sub antifuses Ca1 to Ca3 has different breakdown characteristics, breakdown starts first from the subantifuse where the oxide film is the weakest among them. However, if any one of the sub antifuses, for example Ca1, breaks down first, no current flows through the sub antifuse R1 that has been broken down because of the capacitor Cb1 in series with it. Therefore, little voltage drop across the fuse occurs while the parallel connection antifuse is programmed.

If the program voltage is continuously applied, the breakdown starts sequentially from the weak oxide film, and eventually all of the sub antifuse Ca1 to Ca3 connected in parallel breaks down.

When all of the sub antifuse Ca1 to Ca3 break down, the potential of one end of the parallel connection antifuse to which the negative power supply hvss is applied is converted to the ground potential vss. Then, the flag signal antifuse-flag is converted to the low level to turn on the NMOS transistors T1 to T3.

When the NMOS transistors T1 to T3 are turned on, a current path via R1 to R6 is formed as shown in FIG. That is, a current path is formed through the resistors R1 to R3 and the channel resistances R4 to R6 of the NMOS transistors T1 to T3 by the break down oxide film. At this time, since the channel resistances R4 to R6 are very small, the total resistance of the parallel-connected antifuse has a structure in which the resistors R1 to R3 are substantially connected in parallel by the oxide film which is broken down, and the resistance thereof is a single antifuse conventionally. It becomes much smaller than the resistance value at the time of breakdown.

Accordingly, the parallel-connected antifuse of the present invention makes it easier to determine whether or not the program by making the resistance difference before and after the program larger than that of the conventional single antifuse.

In addition, even if a soft breakdown occurs in one or more subantifuses among the subantifuses Ca1 to Ca3, if a hard breakdown occurs in one or more other subantifuses, all of the sub antifuses connected in parallel may be soft breakdown. Very unlikely), and their parallel connection allows the total resistance to be much smaller than if a hard breakdown occurred in a single antifuse, ensuring the normal operation of the circuit.

In the above-described embodiment, only three fuse sets are connected in parallel. However, the number of fuse sets connected in parallel may be increased as necessary.

FIG. 4 is a view illustrating resistance changes in various situations for the parallel connection antifuse of the structure shown in FIG. 2.

That is, FIG. 4 illustrates a case in which the number of sub antifuses connected in parallel is increased, when all of the sub antifuses connected in parallel are hard braked down, when one sub antifuse is soft breakdown, and two sub antifuses are connected. It shows the change in resistance value when the anti-fuse is soft-breaked down.

4, it can be seen that as the number of parallel connected resistors increases, the total resistance value of the programmed parallel connected antifuse decreases.

In addition, when a single antifuse is used, the difference in resistance value between the hard fuse down and the soft break down is large. However, in the state in which a plurality of anti fuses are connected in parallel as in the present invention, Even if some of the soft breakdowns occur, the total resistance value is smaller than the resistance value when a single antifuse is hard breakdown.

FIG. 5 is a circuit diagram illustrating a configuration of a parallel connected antifuse according to another embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a resistance component after all of the sub antifuses are broken down in the parallel connected antifuse of FIG. 5.

For convenience of description, the reference numerals of FIGS. 2 and 3 are used as they are in FIGS. 5 and 6.

In the present exemplary embodiment, the NMOS transistors N1 and N2 of the switching unit 40 connect the breakdown sub-antifuses R1 and R2 with the ground power supply without connecting the neighboring fuse sets 10 to 30. Forming a current path is different from the configuration of FIG.

In this case, each of the fuse sets 10 to 30 has a structure in which the resistance of the break down sub antifuse and the channel resistance are connected in series after all the sub antifuses have been broken down, and the total resistance of the parallel connection antifuse is such a fuse set. 10 to 30 resistors are connected in parallel.

Preferred embodiments of the present invention described above are intended for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, and such modifications may be made by the following patents. It should be regarded as belonging to the claims.

1 shows a MOS capacitor conventionally used as a single antifuse.

Figure 2 is a circuit diagram showing the configuration of a parallel connection anti-fuse in accordance with an embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating a resistance component after all of the sub antifuses are broken down in the parallel-connected antifuse of FIG. 2. FIG.

FIG. 4 is a view illustrating resistance changes in various situations for a parallel connection antifuse of the structure shown in FIG. 2.

5 is a circuit diagram showing the configuration of the parallel connection anti-fuse according to another embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a resistance component after all of the sub antifuses are broken down in the parallel-connected antifuse of FIG. 5. FIG.

Claims (7)

A plurality of fuse sets in which a sub antifuse and a capacitor are connected in series between both ends of a program voltage; And It includes a switching unit for connecting in parallel to the sub anti-fuse programmed by the program voltage on / off according to the flag signal, And said plurality of fusesets are programmed identically. The method of claim 1, wherein the sub antifuse Parallel-connected antifuse, characterized in that it is a metal-oxide-semiconductor (MOS) capacitor. The method of claim 1, wherein the sub antifuse And a capacitance smaller than that of the capacitor. The method of claim 1, wherein the switching unit And MOS transistors that are turned on or off in response to the flag signal to selectively connect the adjacent fuse sets and connect the connected fuse sets to a ground terminal. The method of claim 4, wherein the switching unit Parallel connection anti-fuse, characterized in that for connecting one end of the sub-antifuse breakdown from the fuse set. The method of claim 1, wherein the switching unit And MOS transistors turned on / off according to the flag signal to selectively connect each of the fuse sets with a ground terminal. The method of claim 6, wherein the switching unit And connecting one end of the sub antifuse broken down from the fuse set to a ground terminal.

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