TWI803206B - Semiconductor device structure and semiconductor circuit having fuse elements - Google Patents

Abstract

A semiconductor device structure and semiconductor circuit are provided. The semiconductor device structure includes a first gate structure, a second gate structure, and a first active region. The first gate structure extends along a first direction and is electrically connected to a first transistor. The second gate structure extends along the first direction and is electrically connected to a second transistor. The first active region extends along a second direction different from the first direction and across the first gate structure and the second gate structure. The first gate structure and the first active region collaboratively form a first fuse element. The second gate structure and the first active region collaboratively form a second fuse element.

Description

Semiconductor element structure and semiconductor circuit with fuse element

This application claims priority to U.S. Patent Application Nos. 17/542,705 and 17/545,471 (i.e., with priority dates of "December 6, 2021" and "December 8, 2021"), the content of which is It is incorporated herein by reference in its entirety.

The present disclosure relates to a semiconductor device structure and a semiconductor circuit, in particular to a semiconductor device structure and a semiconductor circuit with a fuse element.

Fuses and e-fuses are commonly used in memory devices to convert redundant memory cells into normal memory cells. The test circuit is used to determine the state of the fuse (that is, whether the fuse is blown), so that the corresponding memory cell can be determined as a normal memory cell or a redundant memory cell. With the development of technology, the size of the memory cell of the semiconductor device structure is continuously reduced. Since the size of each component in the semiconductor device structure cannot be reduced without limit, it is very important to find other ways to reduce the size of the semiconductor device structure.

The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.

An embodiment of the disclosure provides a semiconductor device structure. The semiconductor element structure includes a first gate structure, a second gate structure and a first active region. The first gate structure extends along a first direction and is electrically connected with a first transistor. The second gate structure extends along the first direction and is electrically connected with a second transistor. The first active region extends along a second direction different from the first direction, and spans the first gate structure and the second gate structure. The first gate structure and the first active region jointly form a first fuse element. The second gate structure and the first active region jointly form a second fuse element.

Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor element structure includes a plurality of fuse elements, a reference resistance unit, a first switch circuit and a latch circuit. The reference resistance unit is configured to receive a first power signal and is electrically coupled with the plurality of fuse elements. The first switch circuit is configured to electrically connect the reference resistance unit and the plurality of fuse elements. The latch circuit is configured to read an evaluation signal of a first node located between the reference resistance unit and one of the plurality of fuse elements.

Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a plurality of fuse elements, a reference resistance unit, a first conductive terminal, a first switch circuit and a second switch circuit. Each of the plurality of fuse elements has a first terminal and a second terminal. The reference resistance unit is configured to receive a first power signal and is electrically coupled to the first terminal of each of the plurality of fuse elements. The first conductive terminal is configured to receive a second power signal and is electrically coupled to the second terminal of each of the plurality of fuse elements. The first switch circuit is configured to electrically couple the second terminal of each of the plurality of fuse elements with ground. The second switch circuit is coupled between the reference resistor unit and ground. In response to the first power signal being applied to the reference resistance unit, the first switch circuit is configured to establish a first conduction path through the reference resistance unit and one of the plurality of fuse elements to land. In response to the second power signal being applied to the first conductive terminal, the second switch circuit is configured to establish a second conductive path through one of the plurality of fuses to ground.

The reference resistance unit exhibits variable resistance. The variable resistor can be adjusted according to the different resistance of the fuse element caused by the process variation. Depending on the actual resistance of the corresponding fuse element, the resistance of the reference resistor can be changed after fabrication. Thus, the present disclosure provides an element with improved flexibility. Since the component has a reference resistor unit, no additional photomask is required to modify the reference resistor. In addition, production time is reduced because the entire manufacturing process does not need to be restarted.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

Embodiments, or examples, of the present disclosure illustrated in the drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are considered to be within the ordinary skill of the art to which this disclosure pertains. Reference signs may be repeated throughout the embodiments, but this does not necessarily mean that features of one embodiment are applicable to another embodiment, even if they share the same reference signs.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the original element can be directly connected or coupled to the other element or to other intervening elements.

It will be understood that although the terms first, second, third etc. may be used to describe various elements, elements, regions, layers or sections. can be used to describe various elements, components, regions, layers or sections, but these elements, components, regions, layers or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include plural forms unless the context specifically dictates otherwise. It should be further understood that when the words "comprise" and "comprising" are used in this specification, they point out the existence of said features, integers, steps, operations, elements or elements, but do not exclude the existence or addition of one or more other features, An integer, step, operation, element, component, or group thereof.

It should be noted that "about" the amount of an ingredient, component, or reactant employed to modify the present disclosure refers to variations in numerical quantities that may occur, for example, by typical measurements and liquid handler. In addition, inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of ingredients used in making compositions or performing methods may produce variations. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

FIG. 1 is a schematic diagram illustrating a test system 10 for semiconductor device structures according to some embodiments of the present disclosure.

According to FIG. 1 , a test system 10 is configured to monitor a semiconductor component structure 11 . In some embodiments, the test system 10 is configured to test the semiconductor device structure 11 . The semiconductor device structure 11 may include a memory, a memory device, a memory die or a memory chip. In some embodiments, the semiconductor device structure 11 may include one or a plurality of memory cells. The semiconductor device structure 11 can be tested after being manufactured, and then shipped.

In some embodiments, the testing system 10 may constitute a testing device. Test system 10 may include hardware and software components to provide a suitable operating and functional environment for testing. In some embodiments, the test system 10 may include a signal generator 12 , a monitor 13 and a coupler 14 .

The signal generator 12 is configured to generate a test signal. In some embodiments, the signal generator 12 can provide a power signal. It should be understood that other power signals, such as data signals and power signals, can also be provided to the semiconductor device structure 11 .

The monitor 13 is configured to determine the status of the semiconductor device structure 11 . Monitor 13 may be configured to determine the status of components of semiconductor device structure 11 . The response signal can be recognized by the monitor 13 to determine whether a component (eg, a memory cell) of the semiconductor device structure 11 is a normal device or a redundant device.

The coupler 14 is configured to couple the signal generator 12 to the semiconductor device structure 11 . In some embodiments, the coupler 14 may be coupled to the semiconductor device structure 11 through one or a plurality of probes 15 . The probe 15 may be part of a probe head or a probe package (not shown). The probe 15 can be electrically coupled to a test conductive terminal (pad) and/or bonding pad disposed on the semiconductor device structure 11 . The test conductive terminals (pads) and/or bonding pads provide an electrical connection with an interconnection structure (eg, wiring) of the semiconductor device structure 11 . For example, some probes may be coupled to pads associated with a power terminal (eg, VDD) and a ground terminal (eg, VSS) of the semiconductor device structure 11 . Other probes may be coupled to pads associated with an input and output (I/O) terminal (eg, data signal) of the semiconductor device structure 11 . Therefore, the test system 10 can apply electrical signals to the semiconductor device structure 11 and obtain response signals from the semiconductor device structure 11 during the test.

FIG. 2 is a schematic diagram illustrating a schematic diagram of a semiconductor device structure 100a according to some embodiments of the present disclosure. The semiconductor device structure 100a may include a memory, memory device, memory die, memory chip or other components. The semiconductor device structure 100a may be a part of a memory, a memory device, a memory die or a memory chip. For example, the memory may be a dynamic random access memory (DRAM). In some embodiments, the DRAM may be a fourth generation double data rate synchronous (DDR4) DRAM. In some embodiments, the memory includes one or more memory cells (or memory bits, memory blocks). In some embodiments, the memory cell includes a fuse element.

The semiconductor element structure 100 a may include a fuse element 101 , an evaluation unit 110 , and a state setting unit 120 . In some embodiments, the evaluation unit 110 may include a reference resistor unit 105 , switch circuits TD and TE, and a latch circuit 130 . In some embodiments, the fuse element 101 and the switch circuits TA and TB may be part of the evaluation unit 110 . In some embodiments, the state setting unit 120 may include a fuse element 101 , a conductive terminal 122 and two switch circuits TB and TC.

Referring to FIG. 2, the reference resistor unit 105 has a terminal 105-1 configured to receive a power signal VDD. The reference resistor unit 105 has a terminal 105 - 2 configured to be electrically coupled with the fuse element 101 . In some embodiments, the switch circuit TB can be electrically connected to the fuse element 101 . The switch circuit TD can be electrically connected with the reference resistor unit 105 . In some embodiments, the switch circuit TD can be electrically connected with the switch circuit TB. In some embodiments, the switch circuit TD may be electrically connected between the switch circuit TB and the reference resistor unit 105 . In some embodiments, fuse element 101 may be coupled to ground through switching circuits TB and TC. The switch circuit TA can be electrically connected with the fuse element 101 . The switch circuit TA can be electrically connected to ground.

In some embodiments, the latch circuit 130 is electrically coupled to the reference resistor unit 105 . The latch circuit 130 can be electrically coupled to the fuse element 101 through the switch circuits TB, TD and TE. In some embodiments, the switch circuit TE is electrically connected to the reference resistor unit 105 . The switch circuit TE can be electrically connected with the latch circuit 130 . In some embodiments, the switch circuit TE may be electrically connected to the switch circuit TD. An evaluation or an output signal is available at the conductive terminal VE of the latch circuit 130 .

Referring to FIG. 2 , the conductive terminal 122 can be electrically connected to the fuse element 101 . The conductive terminal 122 can be a test pad, a probe pad, a conductive pad, a conductive terminal, or other suitable components. In some embodiments, the conductive terminal 122 is configured to receive the state setting signal VB. In some embodiments, the switch circuit TB can be electrically connected to the fuse element 101 . The switch circuit TC can be electrically connected with the switch circuit TB. The switch circuit TB can be electrically connected between the switch circuit TC and the fuse element 101 . The switch circuit TC can be electrically connected to the ground.

In some embodiments, each switch circuit TA, TB, TC, TD and TE may be a switch, transistor or other switchable circuit.

FIG. 2A is a schematic diagram illustrating a semiconductor device structure 100a according to some embodiments of the present disclosure. In some embodiments, the switching circuits TB and TC are configured to be turned on in response to the state setting signal VB to establish the conductive path 111A. In some embodiments, the conductive path 111A may pass through the fuse element 101 to ground in response to the state setting signal VB. In some embodiments, when the state setting signal VB is applied to the conductive terminal 122 , the conductive path 111A sequentially passes through the fuse element 101 , the switching circuits TB and TC, and is grounded. In addition, the switch circuits TA, TD and TE can be configured to be turned off, thus allowing the conductive path 111A to pass through the fuse element 101 .

In some embodiments, the state setting signal VB can be a voltage signal or a current signal. In some embodiments, the state setting signal VB may be a voltage signal having a voltage exceeding a normal operating voltage of the semiconductor device structure 100a. In some embodiments, the state setting signal VB may have a voltage in the range of 4-6V. In one embodiment, the state setting signal VB may have a voltage in the range of 5-6V. When the state setting signal VB is applied, the state of the fuse element 101 can be changed. For example, state set signal VB can be configured to burn out a layer (not shown) of fuse element 101 . After the layer of the fuse element 101 is burned, the physical properties of the layer of the fuse element 101, such as corrosion resistance, density, or other characteristics, may be changed. Before a state setting operation, the fuse element 101 may have a relatively high resistance. After this state setting operation, the fuse element 101 may have a relatively low resistance. In this disclosure, the fuse element before the state setting operation may be referred to as an "unblown" fuse element, and the fuse element after the state setting operation may be referred to as a "blown" fuse element. "The fuse element.

A blown fuse element 101 has a lower resistance than an unblown fuse element 101 . In some embodiments, the fuse element 101 may be an anti-fuse. For example, the antifuse can be an e-fuse. In some embodiments, the antifuse includes a polysilicon e-fuse or other types of antifuse.

In one embodiment, the resistance of the unblown fuse element 101 may be in the range of 1.5M to 20MΩ. In another embodiment, the resistance of the unblown fuse element 101 may be in the range of 5M to 20MΩ. In some embodiments, the resistance of unblown fuse element 101 may exceed 20 MΩ. After this state setting operation, the resistance of the blown fuse element 101 may be in the range of about 2k to 800kΩ. In one embodiment, the blown fuse element 101 may have a resistance of approximately 2k to 20kΩ. In another embodiment, the resistance of blown fuse element 101 may exceed 100 kΩ. In some embodiments, the resistance of the fuse element 101 may be approximately 100k to 800kΩ.

FIG. 2B is a schematic diagram illustrating a semiconductor device structure 100a according to some embodiments of the present disclosure. In some embodiments, switch circuits TA, TB, and TD are configured to be turned on to establish conductive path 111B. In some embodiments, the conductive path 111B can pass through the reference resistor unit 105 and the fuse element 101 to ground in response to the power signal VDD. In some embodiments, switching circuit TC is configured to be closed in order to establish conductive path 111B. In some embodiments, when the power signal VDD is applied to the terminal 105-1 of the reference resistor unit 105, the conduction path 111B sequentially passes through the reference resistor unit 105, the switch circuits TD and TB, the fuse element 101 and the switch circuit TA to ground . In some embodiments, the power signal VDD may be a normal operating voltage. In some embodiments, the power provided by the power signal VDD may be smaller than that of the state setting signal VB. For example, the voltage of the power signal VDD may be about 1.2V.

In some embodiments, the signal X is generated at the node W between the reference resistor 105 and the fuse element 101 in response to the power signal VDD. Referring to FIG. 2B, the signal X generated at the node W may be transmitted to the latch circuit 130 through the switch circuits TD and TE.

In some embodiments, the latch circuit 130 is configured to read the signal X generated at the node W between the reference resistor 105 and the fuse element 101 . Node W is between reference resistor 105 and fuse element 101, with or without other coupled elements in between. For example, node W may be between switching circuits TB and TD. In one embodiment, the node W may be between the switch circuit TD and the reference resistor unit 105 . In another embodiment, node W may be between switch circuit TB and fuse element 101 . In some embodiments, the signal X may include a voltage signal or a current signal.

In some embodiments, the switch circuit TE is configured to be turned on to transmit the signal X to the latch circuit 130 . During an evaluation, when the switch circuits TA, TB, TD and TE are configured to be turned on to establish the conduction path 111B, the signal X may be obtained at the node W and transmitted to the latch circuit 130 . In some embodiments, the latch circuit 130 can read the signal X. In some embodiments, the latch circuit 130 can convert the signal X into the signal Y. For example, a conversion of the signal X operated by the latch circuit 130 may include converting or inverting one signal into another signal. In one embodiment, the transition of the signal X operated by the latch circuit 130 may include a phase shift. In another embodiment, the conversion of the signal X operated by the latch circuit 130 may include an amplification.

In some embodiments, the latch circuit 130 can convert the analog signal X into a logic signal Y. The latch circuit 130 can compare the signal X with a threshold, and output the signal Y according to a comparison result between the signal X and the threshold. For example, when the signal X exceeds the threshold, the latch circuit 130 can output a logic low signal Y. On the contrary, when the signal X is lower than the threshold, the latch circuit 130 can output a logic high signal Y. In some embodiments, the signal Y has a logic value opposite to that of the signal X. For example, when signal X is logic "0", signal Y will be logic "1". Conversely, when signal X is logic "1", signal Y will be logic "0". In some embodiments, the latch circuit 130 can store the signal Y.

Referring to FIG. 2B , the latch circuit 130 may include two inverters 131 and 132 . In some embodiments, the latch circuit 130 may include more than two inverters. In some embodiments, latch circuit 130 may be another type of latch circuit. The inverter 131 has an input terminal IN_1 and an output terminal OUT_1. The inverter 132 has an input terminal IN_2 and an output terminal OUT_2. In some embodiments, the input terminal IN_1 of the inverter 131 may be coupled to the reference resistance unit 105 through the switch circuit TE. The input terminal IN_1 of the inverter 131 may be coupled to the fuse element 101 through the switch circuits TB, TD and TE. The output terminal OUT_1 of the inverter 131 may be coupled to the conduction terminal VE. In some embodiments, the input terminal IN_1 of the inverter 131 may be connected to the output terminal OUT_2 of the inverter 132 . The output terminal OUT_1 of the inverter 131 may be connected to the input terminal IN_2 of the inverter 132 . That is, the input terminal IN_2 of the inverter 132 may be coupled with the conductive terminal VE. The output terminal OUT_2 of the inverter 132 may be coupled to the reference resistance unit 105 . The output terminal OUT_2 of the inverter 132 may be coupled to the fuse element 101 .

In order to evaluate the state of the fuse element 101 (ie, whether the fuse element 101 is blown), the signal X (or signal Y) is monitored. The signal X depends on the resistance of the fuse element 101 . The signal X is compared with a predetermined signal or a threshold. According to a comparison result between the signal X and the predetermined signal, the logic signal Y can be output on the conductive terminal VE. When the signal X exceeds the predetermined signal, it means that the fuse element 101 is not blown. When the signal X fails to exceed the predetermined signal, it means that the fuse element 101 is blown.

In some embodiments, if the signal X exceeds the predetermined signal, the latch circuit 130 can output a logic low signal Y. That is, the logic low signal Y indicates that the fuse element 101 is not blown. When the signal X is lower than the predetermined signal, the latch circuit 130 can output a logic high signal Y, in other words, the logic high signal Y indicates that the fuse element 101 is blown.

The signal Y can be obtained at the conductive terminal VE so that the state of the fuse element 101 can be determined. The status of the fuse element 101 can be used to determine whether the semiconductor device structure is a redundant device or a normal device.

FIG. 2C is a schematic diagram illustrating an equivalent circuit 20 of a part of the semiconductor device structure 100a when the conductive path 111B is established according to some embodiments of the present disclosure. The equivalent circuit 20 is configured when the switch circuits TA, TB, and TD are turned on, and is configured when the switch circuit TC is turned off. In other words, the equivalent circuit 20 represents a simplified circuit through which the conductive path 111B passes.

The equivalent circuit 20 includes two resistors RR and RF. In some embodiments, the resistance RR may be the resistance of the reference resistance unit 105 . Resistor RF may be the resistance of fuse element 101 . In some embodiments, resistor RR may be connected in series with resistor RF. There is a node W between the resistor RR and the resistor RF. That is, the node W in FIG. 2C corresponds to the node in FIG. 2B. In some embodiments, the resistor RR is configured to receive the power signal VDD. For example, the power signal VDD may be at a voltage of 1.2V. In some embodiments, resistor RF is connected to resistor RR and ground.

[公式1] Referring to FIG. 2C , the signal X can be a voltage signal obtained at the node W, therefore, the signal X can be calculated according to Equation 1. Referring to FIG.

[Formula 1]

In Formula 1, X represents the voltage of the signal X; RR represents the resistance of the reference resistor unit 105; RF represents the resistance of the fuse element 101; VDD represents the power signal.

In order to accurately assess the state of the fuse element 101, the resistance RR may be lower than the resistance RF of the unblown fuse element. Furthermore, the resistance RR may exceed the resistance RF of the blown fuse element. In some embodiments, resistance RR may be between the resistance of the unblown fuse element and the resistance of the blown fuse element.

In one embodiment, the resistance of the unblown fuse element 101 may be in the range of 1.5M to 20MΩ. In another embodiment, the resistance of the unblown fuse element 101 may be in the range of 5M to 20MΩ. In some embodiments, the resistance of unblown fuse element 101 may exceed 20 MΩ. After this state setting operation, the resistance of the blown fuse element 101 may be 2k to 800kΩ. In one embodiment, the resistance of the blown fuse element 101 may be 2k to 20kΩ. In another embodiment, the resistance of the fuse element 101 may exceed 100 kΩ. In some embodiments, the resistance of the blown fuse element 101 may be 100k to 800kΩ.

In some embodiments, the voltage of the predetermined signal is lower than the voltage of the power signal VDD. In some embodiments, the predetermined signal has a voltage that is multiplied by the power signal VDD in fractional form. For example, if the voltage of the predetermined signal is half of the power signal VDD, such as 1.2V, then the voltage of the predetermined signal can be 0.6V. That is to say, when the result of formula 1 exceeds 0.6V, the signal X at the node W will be determined as a logic high, indicating that the fuse element 101 is not blown, and when it is less than 0.6V, the signal X at the node W will be judged as a logic low, indicating that the fuse element 101 is blown.

FIG. 3 is a schematic diagram illustrating a semiconductor device structure 100b according to some embodiments of the present disclosure. The semiconductor device structure 100 b is similar to the semiconductor device structure 100 a shown in FIG. 1 , the difference is that the semiconductor device structure 100 b may include a fuse structure 140 .

In some embodiments, the fuse structure 140 may include a plurality of fuse elements. In some embodiments, the fuse elements of the fuse structure 140 may form an n×n array. For example, the fuse structure 140 may include fuse elements 1411 , 1412 , 1413 , . . . and 141X forming a first row. The fuse structure 140 may include fuse elements 1421 , 1422 , 1423 , . . . and 142X forming a second column, and X may be a positive integer of 1 to n. The fuse structure 140 may include fuse elements 1431 , 1432 , 1433 , . . . and 143X forming a third column. The fuse structure 140 may include fuse elements 14X1 , 14X2 , 14X3 , . . . and 14XX forming an X-th column. Also, the fuse elements 1411, 1421, 1431, . . . and 14X1 form a first column. Fuse elements 1412, 1422, 1432, . . . and 14X2 form a second row. Fuse elements 1413, 1423, 1433, . . . and 14X3 form a third row. Fuse elements 141X, 142X, 143X, . . . and 14XX form the Xth row.

In some embodiments, the semiconductor device structure 100b may include a plurality of transistors, such as transistors TF1, TF2, TF3 and TFX. Transistors TF1-TFX can be configured to turn on or off the columns of fuse structures 140 . For example, transistors TF1-TFX may be electrically connected to fuse elements 1411-141X, 1421-142X, 1431-143X and 14X1-14XX respectively. Transistors, such as TF1-TFX, can be electrically connected between the conductive terminal 122 and the fuse structure 140 .

In some embodiments, the semiconductor device structure 100b may include a plurality of transistors, such as transistors TG1 , TG2 , TG3 and TGX. Transistors TG1 -TGX can be configured to turn on or off the row of fuse structures 140 . For example, transistors TG1-TGX may be electrically connected to fuse elements 1411-14X1, 1412-14X2, 1413-14X3 and 141X-14XX respectively. The transistors TG1 - TGX can be electrically connected between the switch circuit TD and the fuse structure 140 .

In some embodiments, the fuse structure 140 shares a switch circuit TA. In some embodiments, the fuse structure 140 shares a switch circuit TC. In some embodiments, the fuse structure 140 shares a switch circuit TD. In some embodiments, the fuse structure 140 shares a reference resistor unit 105 . In some embodiments, the fuse structures 140 share one latch circuit 130 . Compared with the semiconductor device structure 100a shown in FIG. 2, in which one switch circuit TA, TC or TD is electrically coupled with only one fuse element 101, the semiconductor device structure 100b may have a relatively smaller size.

FIG. 3A is a schematic diagram illustrating a semiconductor device structure 100b according to some embodiments of the present disclosure.

In some embodiments, one of the transistors (eg, transistors TF1, TF2, TF3, or TFX), one of the fuse elements 1411-14XX, one of the transistors (eg, transistors TG1, TG2, TG3, or TGX) And the switching circuit TC is configured to be turned on in response to the state setting signal VB to establish the conductive path 150A. In some embodiments, the conductive path 150A may pass through one of the fuse elements 1411-14XX to ground in response to the state setting signal VB. For example, when transistors TF2 and TG3 are turned on, conductive path 150A will sequentially pass through transistor TF2, fuse element 1423, transistor TG3, and switching circuit TC to ground. Additionally, switching circuits TA, TD, and TE may be configured to close, thus allowing conductive path 150A to pass through one of fuse elements 1411-14XX.

In some embodiments, the state setting signal VB can be a voltage signal or a current signal. In some embodiments, the state setting signal VB may be a voltage signal having a voltage exceeding a normal operating voltage of the semiconductor device structure 100b. In some embodiments, the state setting signal VB may have a voltage in the range of 4-7V, such as 4V, 4.5V, 5V, 5.5V, 6V, 6.5V or 7V. When the state setting signal VB is applied, the state of one of the fuse elements 1411-14XX can be changed. For example, the state setting signal VB can be configured to burn a gate dielectric layer (not shown) of one of the fuse elements 1411-14XX. Prior to this state setting operation, fuse elements 1411-14XX may have a relatively high resistance. After this state setting operation, the transistor through which the conductive path 150A passes (eg, transistor 1423 ) may have a relatively low resistance compared to other transistors (eg, transistor 1411 ).

FIG. 3B is a schematic diagram illustrating a semiconductor device structure 100b according to some embodiments of the present disclosure.

In some embodiments, one of the transistors (eg, transistors TF1, TF2, TF3, or TFX), one of the fuse elements 1411-141X, one of the transistors (eg, transistors TG1, TG2, TG3, or TGX) And switch circuits TA and TD are configured to turn on to establish conductive path 150B. In some embodiments, the conductive path 150B may pass through one of the reference resistor unit 105 and the fuse elements 1411 - 141X to ground in response to the power signal VDD. In some embodiments, the conductive path 150B sequentially passes through the reference resistance unit 105, the switch circuit TD, one of the transistors (for example, transistors TG1, TG2, TG3 or TGX), one of the fuse elements 1411-141X, the transistor ( For example, one of the transistors TF1, TF2, TF3 or TFX) and the switching circuit TA to ground. For example, when transistors TF2 and TG2 are turned on, the conductive path 150B will sequentially pass through switch circuit TD, transistor TG2, fuse element 1422, transistor TF2 and switch circuit TA to ground. In some embodiments, switching circuit TC is configured to close in order to establish conductive path 150B.

In some embodiments, the power signal VDD may be a normal operating voltage. In some embodiments, the power provided by the power signal VDD may be smaller than that of the state setting signal VB. For example, the power signal VDD may have a voltage in the range of 1-1.5V, such as 1V, 1.1V, 1.2V, 1.3V, 1.4V or 1.5V.

In some embodiments, the signal X is generated at the node W between the reference resistor unit 105 and one of the fuse elements 1411-14XX in response to the power signal VDD. Referring to FIG. 3B , the signal X generated at the node W may be transmitted to the latch circuit 130 through the switch circuits TD and TE.

In some embodiments, the latch circuit 130 is configured to read the signal X generated at the node W between the reference resistor unit 105 and one of the fuse elements 1411-14XX. Node W is between reference resistor unit 105 and one of fuse elements 1411-14XX, with or without other element coupling therebetween. For example, node W may be between one of the transistors (eg, transistor TG1 , TG2 , TG3 or TGX) and the switch circuit TD. In one embodiment, the node W may be between the switch circuit TD and the reference resistor unit 105 . In some embodiments, the signal X may include a voltage signal or a current signal.

In some embodiments, the switch circuit TE is configured to be turned on to transmit the signal X to the latch circuit 130 . During an evaluation, when switch circuits TA, TD and TE and transistors TGX and TFX are configured to turn on to establish conduction path 150B, signal X may be obtained at node W and transmitted to latch circuit 130 .

To assess the state of one of the fuse elements 1411-14XX (ie, whether one of the fuse elements 1411-14XX is blown), signal X (or signal Y) is monitored. The signal X depends on the resistance of one of the fuse elements 1411-14XX. The signal X is compared with a predetermined signal or a threshold. According to a comparison result of the signal X and the predetermined signal, a logic signal Y can be output on the conductive terminal VE. When the signal X exceeds the predetermined signal, it means that one of the fuse elements 1411-14XX is not blown. When the signal X fails to exceed the predetermined signal, it means that one of the fuse elements 1411-14XX is blown.

In some embodiments, if the signal X exceeds the predetermined signal, the latch circuit 130 can output a logic low signal Y. That is, the logic low signal Y indicates that one of the fuse elements 1411-14XX is not blown. When the signal X is lower than the predetermined signal, the latch circuit 130 may output a logic high signal Y, in other words, the logic high signal Y indicates that one of the fuse elements 1411-14XX is blown.

The signal Y can be obtained at the conductive terminal VE, so that the state of one of the fuse elements 1411-14XX can be determined. The state of one of the fuse elements 1411-14XX can be used to determine whether the semiconductor device structure is a redundant element or a normal element.

For example, when the conductive path 150A is established as shown in FIG. 3A, the fuse element 1423 is blown. In this case, the signal X generated at the node W between the reference resistor unit 105 and the fuse element 1423 will not exceed the predetermined signal. As a result, the latch circuit 130 will output a logic high signal Y.

FIG. 4 is a schematic diagram illustrating the layout of the fuse structure 140 of the semiconductor device structure 100b in FIG. 3 according to some embodiments of the present disclosure.

In some embodiments, the semiconductor device structure 100b may include a plurality of gate structures (eg, gate structures PO1 , PO2 , PO3 , . . . and POX) extending along a direction D1 (eg, X direction). In some embodiments, the semiconductor device structure 100b may include a plurality of active regions (eg, active regions OD1 , OD2 , OD3 , . . . and ODX) extending along a direction D2 (eg, Y direction). Each of the active regions OD1, OD2, OD3 and ODX may span gate structures PO1-POX. One of the gate structures PO1-POX and one of the active regions OD1-ODX may jointly form or define a fuse element. For example, the gate structure PO1 may overlap with the active region OD1 , and thus, the overlapping region of the gate structure PO1 and the active region OD1 may define the fuse element 1411 .

In some embodiments, each gate structure PO1-POX can serve as a first terminal of one of the fuse elements 1411-14XX. In some embodiments, each of the gate structures PO1-POX may be electrically connected to a corresponding one of the transistors TF1-TFX. In some embodiments, each active area OD1-ODX can serve as a second terminal of one of the fuse elements 1411-14XX. In some embodiments, each active region OD1 - ODX may be electrically connected to one of the corresponding transistors TG1 - TGX respectively. For example, the gate structure PO1 can be used as a first terminal of the fuse element 1412, and is electrically connected to the transistor TF1. The active area OD2 can be used as a second terminal of the fuse element 1412, and is electrically connected with the transistor TG2.

FIG. 5A is a cross-sectional view illustrating a semiconductor device structure 100b taken along line AA' in FIG. 4 according to some embodiments of the present disclosure.

As shown in FIG. 5A , the semiconductor device structure 100 b may include a substrate 202 , a doped region 204 , a gate dielectric layer 206 , a gate electrode 208 , and spacers 210 .

The substrate 202 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, and the like. Substrate 202 may include an elementary semiconductor, including silicon or germanium in single crystal form, polycrystalline form, or amorphous (amorphous) form; a compound semiconductor material, including silicon carbide, gallium arsenide, gallium phosphide, phosphide At least one of indium, indium arsenide and indium antimonide. An alloy semiconductor material comprising at least one of SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloyed semiconductor material substrate may be a SiGe alloy having a graded Ge feature, wherein the composition of Si and Ge changes from a ratio at one location of the graded SiGe feature to another location. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 202 may have a multilayer structure, or the substrate 202 may include a multilayer compound semiconductor structure.

A doped region 204 may be disposed within the substrate 202 . In some embodiments, the doped region 204 may be a semiconductor material doped with a dopant. The dopant may include p-type and/or n-type dopant. In some embodiments, the p-type dopant may include boron (B), other Group III elements, or any combination thereof. In some embodiments, the n-type dopant may include arsenic (As), phosphorus (P), other Group V elements, or any combination thereof. In some embodiments, doped regions 204 may define active regions OD1-ODX.

The gate dielectric layer 206 can be disposed on the substrate 202 and cover the doped region 204 . The gate dielectric layer 206 may have a single layer or a multilayer structure. In some embodiments, the gate dielectric layer 206 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof. In some embodiments, the gate dielectric layer 206 is a multi-layer structure including an interface layer and a high-k (dielectric constant greater than 4) dielectric layer. The interface layer may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, or combinations thereof. The high-k dielectric layer may include a high-k dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the high-k dielectric material can also be selected from metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides , metal aluminates, and combinations thereof.

The gate electrode 208 is disposed on the gate dielectric layer 206 . The gate electrode 208 may comprise polysilicon, silicon germanium and at least one metal material, including Mo, Cu, W, Ti, Ta, TiN, TaN, NiSi, CoSi and other elements and compounds, or other suitable conductive materials known in the art . In some embodiments, the gate electrode 208 includes a work function metal layer, providing a metal gate having an n-type metal work function or a p-type metal work function. P-type metal work function materials include, for example, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or other suitable materials. N-type metal work function materials include hafnium zirconium, titanium, tantalum, aluminum, metal carbides (eg, hafnium carbides, zirconium carbides, titanium carbides, and aluminum carbides), aluminides, or other suitable materials. The gate dielectric layer 206 and the gate electrode 208 can collectively define the gate structures PO1-POX.

The spacers 210 may be disposed on the substrate 202 and on two opposite sides of the gate 208 . The spacer 210 may include a dielectric material such as oxide, nitride, oxynitride and other dielectric materials. In some embodiments, the spacer 210 may include a multi-layer structure, such as an oxide-nitride-oxide structure. Each of the gate structures PO1 -POX may be separated from each other by spacers 210 and other dielectric structures (not shown) filled between the spacers 210 .

As shown in FIG. 5A , the transistor TG2 has a first terminal electrically connected to the active area OD2 and a second terminal electrically connected to the switch circuit TD. Each of the transistors TF1-TFX has a first terminal electrically connected to the corresponding gate structure PO1-POX and a second terminal electrically connected to the switching circuit TA.

As shown in FIG. 5A , each fuse element (eg, fuse element 1412 - 14X2 ) can be composed of a Z-direction along the active region (eg, active region OD2 ), gate dielectric layer 206 , and gate electrode 208 . Overlaps are defined.

Although not shown in FIG. 5A, it is contemplated that some conductive lines or conductive vias (not shown) are electrically connected between the gate electrode 208 and the transistors TF1-TFX. Likewise, some conductive lines or vias (not shown) can be electrically connected between the doped region 204 and the transistors TG1 - TGX.

FIG. 5B is a cross-sectional view illustrating the semiconductor device structure 100b taken along line BB' in FIG. 4 according to some embodiments of the present disclosure.

As shown in FIG. 5B , the semiconductor device structure 100 b may include isolation features 212 that separate the plurality of active regions OD1 - ODX from each other. In some embodiments, the isolation feature 212 may be a shallow trench isolation (STI) embedded in the substrate 202 . Isolation feature 212 may include a dielectric material such as oxide, nitride, oxynitride, and other dielectric materials.

As shown in FIG. 5B , the gate structure PO2, including the gate dielectric layer 206 and the gate electrode 208, may be disposed on a plurality of active regions OD1-ODX. The transistor TF2 has a first terminal electrically connected to the gate structure PO2 and a second terminal electrically connected to the switch circuit TA. Each of the transistors TG1-TGX has a first terminal electrically connected to the corresponding active area OD1-ODX and a second terminal electrically connected to the switch circuit TD.

FIG. 6 is a schematic diagram illustrating the layout of a terminal of a semiconductor device structure according to some embodiments of the present disclosure.

In some embodiments, the gate structure PO may have an opening 181 exposing a portion of the active region OD from a top view. In some embodiments, the active region OD may have a raised portion 182 partially within the opening 181 . The gate structure PO and the protruding portion 182 of the active area OD together form or define the fuse element 141 . In some embodiments, at least one conductive terminal 160 may be electrically connected to the gate structure PO. In some embodiments, at least one conductive terminal 170 may be electrically connected to the active area OD. The gate structure PO includes a connection region 160C in which at least one conductive terminal 160 is disposed. The active area OD includes a connection area 170C in which at least one conductive terminal 170 is disposed. In some embodiments, the conductive terminal 160 may be electrically connected to a transistor (eg, transistors TF1-TFX). In some embodiments, the conductive terminal 170 may be electrically connected to a transistor (eg, transistors TG1 -TGX). Conductive terminations 160 and/or 170 may include a conductive pad or other suitable structure.

Referring to FIG. 6 , the area occupied by the connection area 160C is much larger than the area of the fuse element 141 , and the area occupied by the connection area 170C is much larger than the area of the fuse element 141 .

FIG. 7 is a schematic diagram illustrating the layout of a semiconductor device structure 100c according to some embodiments of the present disclosure.

As shown in FIG. 7 , each of the gate structures PO1 -POX can be electrically connected to a corresponding conductive terminal (eg, conductive terminal 161 , 162 , . . . , or 16X). In some embodiments, the conductive terminals 161 - 16X may be alternately disposed on two opposite sides of the active regions OD1 - ODX along the direction D1 . For example, the conductive terminals 161 and 162 are disposed on two opposite sides of the active region OD1 along the direction D1.

Each active area OD1-ODX can be electrically connected to a corresponding conductive terminal (eg, conductive terminal 171, 172, . . . , or 17X). In some embodiments, the conductive terminals 171 - 17X may be alternately arranged on two opposite sides of the gate structures PO1 -POX along the direction D2. For example, the conductive terminals 171 and 172 are disposed on two opposite sides of the gate structure PO1 along the direction D2.

In some embodiments, two adjacent connection regions 160C on which the conductive terminals 161 and 162 are disposed are disposed on two opposite sides of the active regions OD1-ODX along the direction D1. For example, two adjacent connection regions 160C where the conductive terminals 161 and 162 are located are disposed on two opposite sides of the active region OD1 along the direction D1.

In some embodiments, two adjacent connection regions 170C on which the conductive terminals 171 and 172 are disposed are disposed on two opposite sides of the gate structures PO1 -POX along the direction D2 . For example, two adjacent connection regions 170C where the conductive terminals 171 and 172 are located are disposed on two opposite sides of the gate structure PO1 along the direction D2.

As mentioned above, the connection area 160C or the connection area 170C occupies significantly more area than the area of the fuse element 141 . Therefore, the arrangement shown in FIG. 7 can effectively utilize the area of the semiconductor element structure 100c, and thus can reduce the size of the semiconductor element structure 100c.

An embodiment of the disclosure provides a semiconductor device structure. The semiconductor element structure includes a first gate structure, a second gate structure and a first active region. The first gate structure extends along a first direction and is electrically connected with a first transistor. The second gate structure extends along the first direction and is electrically connected with a second transistor. The first active region extends along a second direction different from the first direction, and spans the first gate structure and the second gate structure. The first gate structure and the first active region jointly form a first fuse element. The second gate structure and the first active region jointly form a second fuse element.

Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor element structure includes a plurality of fuse elements, a reference resistance unit, a first switch circuit and a latch circuit. The reference resistance unit is configured to receive a first power signal and is electrically coupled with the plurality of fuse elements. The first switch circuit is configured to electrically connect the reference resistance unit and the plurality of fuse elements. The latch circuit is configured to read an evaluation signal of a first node located between the reference resistance unit and one of the plurality of fuse elements.

Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a plurality of fuse elements, a reference resistance unit, a first conductive terminal, a first switch circuit and a second switch circuit. Each of the plurality of fuse elements has a first terminal and a second terminal. The reference resistance unit is configured to receive a first power signal and is electrically coupled to the first terminal of each of the plurality of fuse elements. The first conductive terminal is configured to receive a second power signal and is electrically coupled to the second terminal of each of the plurality of fuse elements. The first switch circuit is configured to electrically couple the second terminal of each of the plurality of fuse elements with ground. The second switch circuit is coupled between the reference resistor unit and ground. In response to the first power signal being applied to the reference resistance unit, the first switch circuit is configured to establish a first conduction path through the reference resistance unit and one of the plurality of fuse elements to land. In response to the second power signal being applied to the first conductive terminal, the second switch circuit is configured to establish a second conductive path through one of the plurality of fuses to ground.

Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made hereto without departing from the spirit and scope of the present disclosure as defined by the patent claims disclosed. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the disclosure is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that they can use existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machinery, manufacture, material composition, means, methods, or steps are included in the scope of the patent disclosure of this disclosure.

10: Test system

11:Semiconductor element structure

12: Signal generator

13: Monitor

14: Coupler

15: Probe

20: Equivalent circuit

100a: Semiconductor device structure

100b: Semiconductor device structure

100c: Semiconductor Component Structure

101: Fuse element

105: Reference resistance unit

105-1: Terminal

105-2: Terminal

110: Evaluation Units

111A: Conductive path

111B: Conductive path

120: State setting unit

122: Conductive terminal

130: Latch circuit

131: Inverter

132: Inverter

140: Fuse structure

141: Fuse element

150A: Conductive path

150B: Conductive path

160: Conductive terminal

160C: Connection area

161~16X: Conductive terminal

170: Conductive terminal

170C: Connection area

171~17X: Conductive terminal

181: opening

182: protruding part

202: base

204: doping area

206: gate dielectric layer

208: gate electrode

210: Gap

212: Isolation feature

1411~141X: fuse element

1421~142X: fuse element

1431~143X: fuse element

14X1~14XX: fuse element

A-A': line

B-B': line

D1: Direction

D2: Direction

IN_1: input terminal

IN_2: input terminal

OD: active area

OD1~ODX: active area

OUT_1: output terminal

OUT_2: output terminal

PO: gate structure

PO1~POX: gate structure

RF: Resistance

RR: resistance

TA: switch circuit

TB: switch circuit

TC: switching circuit

TD: switch circuit

TE: switch circuit

TF1: Transistor

TF2: Transistor

TF3: Transistor

TFX: Transistor

TG1: Transistor

TG2: Transistor

TG3: Transistor

TGX: Transistor

VB: Status setting signal

VDD: power signal

VE: conductive terminal

W: node

X: signal

Y: signal

Z: Direction

The disclosure content of the present application can be understood more comprehensively when referring to the embodiments and the patent scope of the application for combined consideration of the drawings, and the same reference numerals in the drawings refer to the same components. FIG. 1 is a schematic diagram illustrating a test system for semiconductor device structures according to some embodiments of the present disclosure. FIG. 2 is a schematic diagram illustrating the semiconductor device structure of some embodiments of the present disclosure. FIG. 2A is a schematic diagram illustrating the semiconductor device structure of some embodiments of the present disclosure. FIG. 2B is a schematic diagram illustrating the semiconductor device structure of some embodiments of the present disclosure. FIG. 2C is a circuit diagram illustrating an equivalent circuit of a part of the semiconductor device structure in FIG. 2B according to some embodiments of the present disclosure. FIG. 3 is a schematic diagram illustrating the semiconductor device structure of some embodiments of the present disclosure. FIG. 3A is a schematic diagram illustrating the semiconductor device structure of some embodiments of the present disclosure. FIG. 3B is a schematic diagram illustrating the semiconductor device structure of some embodiments of the present disclosure. FIG. 4 is a schematic diagram illustrating the layout of the fuse element of the semiconductor device structure in FIG. 3 according to some embodiments of the present disclosure. 5A is a cross-sectional view illustrating the structure of a semiconductor device taken along line AA' in FIG. 4 according to some embodiments of the present disclosure. 5B is a cross-sectional view illustrating the structure of a semiconductor device taken along line BB' in FIG. 4 according to some embodiments of the present disclosure. FIG. 6 is a schematic diagram illustrating the layout of a terminal of a semiconductor device structure according to some embodiments of the present disclosure. FIG. 7 is a schematic diagram illustrating the layout of a semiconductor device structure according to some embodiments of the present disclosure.

100b: Semiconductor device structure

105: Reference resistance unit

122: Conductive terminal

130: Latch circuit

131: Inverter

132: Inverter

140: Fuse structure

1411~141X: fuse element

1421~142X: fuse element

1431~143X: fuse element

14X1~14XX: fuse element

IN_1: input terminal

IN_2: input terminal

OUT_1: output terminal

OUT_2: output terminal

TA: switch circuit

TC: switching circuit

TD: switch circuit

TE: switch circuit

TF1: Transistor

TF2: Transistor

TF3: Transistor

TFX: Transistor

TG1: Transistor

TG2: Transistor

TG3: Transistor

TGX: Transistor

VB: Status setting signal

VDD: power signal

VE: conductive terminal

W: node

Y: signal

Claims (27)

A semiconductor device structure, comprising: a first gate structure extending along a first direction and electrically connected to a first transistor; a second gate structure extending along the first direction and electrically connected to a second transistor The crystal is electrically connected; and a first active region extends along a second direction different from the first direction and spans the first gate structure and the second gate structure; wherein the first gate structure and the second gate structure The first active area jointly forms a first fuse element, the second gate structure and the first active area jointly form a second fuse element; a second active area extends along the second direction and spans the The first gate structure and the second gate structure; wherein the first active region is electrically connected to a third transistor, the second active region is electrically connected to a fourth transistor, and the first gate structure A third fuse element is jointly formed with the second active area, a fourth fuse element is jointly formed by the second gate structure and the second active area; a reference resistance unit has a first terminal and a second terminal, the first terminal is configured to receive a first power signal, and the second terminal is configured to be electrically coupled with the third transistor and the fourth transistor. The semiconductor device structure according to claim 1, further comprising: a first switch circuit configured to electrically connect the reference resistance unit with the third transistor and the fourth transistor. The semiconductor device structure as claimed in Claim 2, further comprising: a latch circuit configured to read an evaluation signal of a first node, wherein the first node is located between the reference resistance unit and the first fuse element , between one of the second fuse element, the third fuse element and the fourth fuse element. The semiconductor device structure according to claim 3, further comprising: a second switch circuit configured to electrically couple the first transistor and the second transistor to ground. The semiconductor device structure as claimed in claim 4, wherein in response to the first power supply signal being applied to the first terminal of the reference resistance unit, the first switch circuit and the second switch circuit are configured to establish a first conduction path, the first conductive path passes through the reference resistor unit and one of the first fuse element, the second fuse element, the third fuse element and the fourth fuse element to ground. The semiconductor device structure as claimed in claim 3, further comprising: a first conductive terminal coupled to one of the first transistor and the second transistor and configured to receive a second power signal; and a first three switch circuits coupled between the first node and ground; wherein the second switch circuit and the third switch circuit are configured to establish a second conductive path through the first fuse element, One of the second fuse element, the third fuse element and the fourth fuse element is connected to ground. The semiconductor device structure as claimed in claim 6, wherein a voltage of the second power signal is in the range of 5-6V. The semiconductor device structure as claimed in claim 6, further comprising: a second conductive terminal coupled to one of the first transistor and the second transistor, wherein the first conductive terminal and the second conductive terminal are arranged on opposite sides of the first active zone. The semiconductor device structure as claimed in claim 3, further comprising: a fourth switch circuit coupled between the reference resistance unit and the latch circuit. The semiconductor device structure of claim 1, wherein the first active region and the second active region are separated by an isolation feature. The semiconductor device structure as claimed in claim 1, wherein a voltage of the first power signal is in the range of 1-1.5V. The semiconductor device structure according to claim 1, further comprising: a third conductive terminal electrically connected to the first active region; and a fourth conductive terminal electrically connected to the second active region, wherein the first active region The three conductive terminals and the fourth conductive terminal are disposed on opposite sides of the first gate structure. A semiconductor circuit, comprising: a plurality of fuse elements; A reference resistance unit configured to receive a first power signal and electrically coupled to the plurality of fuse elements; a first switch circuit configured to electrically connect the reference resistance unit and the plurality of fuse elements ; and a latch circuit configured to read an evaluation signal at a first node located between the reference resistance unit and one of the plurality of fuse elements. The semiconductor circuit according to claim 13, wherein the plurality of fuse elements share the first switch circuit. The semiconductor circuit according to claim 13, further comprising: a second switch circuit configured to electrically couple the plurality of fuse elements to ground. The semiconductor circuit as claimed in claim 15, wherein in response to the first power signal being applied to a first terminal of the reference resistance unit, the first switch circuit and the second switch circuit are configured to establish a first conduction path, the first conductive path passes through the reference resistor unit and one of the plurality of fuse elements to ground. The semiconductor circuit of claim 13, further comprising: a first conductive terminal coupled to one of the plurality of fuse elements and configured to receive a second power signal; and a third switch circuit coupled to the between the first node and ground; wherein the third switch circuit is configured to establish a second conductive path, the second conductive path path through one of the plurality of fuse elements to ground. The semiconductor circuit according to claim 13, further comprising: a plurality of gate structures extending along a first direction; and a plurality of active regions extending along a second direction different from the first direction, wherein the plurality of The gate structure and the plurality of active regions define the plurality of fuse elements. A semiconductor device structure, comprising: a plurality of fuse elements, wherein each of the plurality of fuses has a first terminal and a second terminal; a reference resistance unit configured to receive a first power signal, and electrically coupled to the first terminal of each of the plurality of fuse elements; a first conductive terminal configured to receive a second power signal and connected to each of the plurality of fuse elements The second terminal is electrically connected; a first switch circuit configured to electrically couple the second terminal of each of the plurality of fuse elements to ground; and a second switch circuit coupled to the reference Between the resistance unit and the ground; wherein in response to the first power signal being applied to the reference resistance unit, the first switch circuit is configured to establish a first conductive path through the reference resistance unit and the first conductive path one of the plurality of fuse elements to ground, and in response to the second power signal being applied to the first conductive terminal, the second switching circuit is configured to establish a second conductive path through the plurality of One of the fuse elements to ground. The semiconductor device structure as claimed in claim 19, wherein the plurality of fuse elements share the first switch circuit. The semiconductor device structure as claimed in claim 19, wherein the plurality of fuse elements share the second switch circuit. The semiconductor device structure as claimed in claim 19, further comprising: a plurality of gate structures extending along a first direction; and a plurality of active regions extending along a second direction different from the first direction; wherein the plurality Each of the active regions serves as a corresponding first terminal of the plurality of fuse elements, and each of the plurality of gate structures serves as a corresponding second terminal of the plurality of fuse elements. The semiconductor element structure as claimed in claim 22, further comprising: a plurality of first transistors electrically connected between the plurality of active regions and the reference resistance unit; and a plurality of second transistors electrically connected connected between the plurality of gate structures and the first conductive terminal. The semiconductor element structure as claimed in claim 19, further comprising: a third switch unit configured to electrically connect the reference resistance unit and the plurality of fuses A wire element, wherein the third switch circuit and the first switch unit are configured to establish the first conductive path. The semiconductor device structure as claimed in claim 24, wherein the plurality of fuse elements share the third switch unit. The semiconductor device structure according to claim 24, further comprising: a latch circuit configured to read an evaluation signal of a first node located between the reference resistance unit and the plurality of fuse elements between one. The semiconductor device structure as claimed in claim 19, wherein the second power signal is greater than the first power signal.

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