TWI802800B - 用以致能工作負載之靜態映射的亂序管線化執行之方法及設備 - Google Patents

用以致能工作負載之靜態映射的亂序管線化執行之方法及設備 Download PDF

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TWI802800B
TWI802800B TW109120637A TW109120637A TWI802800B TW I802800 B TWI802800 B TW I802800B TW 109120637 A TW109120637 A TW 109120637A TW 109120637 A TW109120637 A TW 109120637A TW I802800 B TWI802800 B TW I802800B
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buffer
workload
scheduler
quota
credit
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TW109120637A
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TW202109285A (zh
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麥可 貝赫爾
羅尼 羅斯納
莫旭 馬歐
羅南 加拜
吉吉 華特
歐倫 亞剛
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美商英特爾公司
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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Human Computer Interaction (AREA)
  • General Health & Medical Sciences (AREA)
  • Computing Systems (AREA)
  • Molecular Biology (AREA)
  • Evolutionary Computation (AREA)
  • Mathematical Physics (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • Artificial Intelligence (AREA)
  • Neurology (AREA)
  • Advance Control (AREA)
TW109120637A 2019-08-15 2020-06-18 用以致能工作負載之靜態映射的亂序管線化執行之方法及設備 TWI802800B (zh)

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US16/542,012 2019-08-15
US16/542,012 US11231963B2 (en) 2019-08-15 2019-08-15 Methods and apparatus to enable out-of-order pipelined execution of static mapping of a workload

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TWI802800B true TWI802800B (zh) 2023-05-21

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JP (1) JP7400169B2 (cg-RX-API-DMAC10.html)
KR (1) KR102684511B1 (cg-RX-API-DMAC10.html)
CN (2) CN112395010A (cg-RX-API-DMAC10.html)
DE (1) DE102020119519A1 (cg-RX-API-DMAC10.html)
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10901657B2 (en) * 2018-11-29 2021-01-26 International Business Machines Corporation Dynamic write credit buffer management of non-volatile dual inline memory module
US11231963B2 (en) 2019-08-15 2022-01-25 Intel Corporation Methods and apparatus to enable out-of-order pipelined execution of static mapping of a workload
US11599780B2 (en) * 2020-03-02 2023-03-07 Apple Inc. Asynchronous task execution for neural processor circuit
US11875247B1 (en) * 2020-06-18 2024-01-16 Amazon Technologies, Inc. Input batching with serial dynamic memory access
US11704058B2 (en) * 2020-07-28 2023-07-18 Samsung Electronics Co., Ltd. Systems and methods for resource-based scheduling of commands
CN112003846B (zh) * 2020-08-13 2023-02-03 广州市百果园信息技术有限公司 一种信用阈值的训练、ip地址的检测方法及相关装置
US12223174B2 (en) * 2020-10-26 2025-02-11 Google Llc Modulating credit allocations in memory subsystems
US11620159B2 (en) 2021-04-23 2023-04-04 Samsung Electronics Co., Ltd. Systems and methods for I/O command scheduling based on multiple resource parameters
US12001701B2 (en) * 2022-01-26 2024-06-04 Western Digital Technologies, Inc. Storage biasing for solid state drive accelerators

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120239833A1 (en) * 2011-03-14 2012-09-20 Kabushiki Kaisha Toshiba Buffer management device, buffer management method, and storage device
US20160140071A1 (en) * 2014-11-13 2016-05-19 Cavium, Inc. Arbitrated Access To Resources Among Multiple Devices
US20190050261A1 (en) * 2018-03-29 2019-02-14 Intel Corporation Arbitration across shared memory pools of disaggregated memory devices
TW201923558A (zh) * 2017-10-20 2019-06-16 英商葛夫科有限公司 主機處理器之同步化

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5418953A (en) * 1993-04-12 1995-05-23 Loral/Rohm Mil-Spec Corp. Method for automated deployment of a software program onto a multi-processor architecture
JP3892829B2 (ja) * 2003-06-27 2007-03-14 株式会社東芝 情報処理システムおよびメモリ管理方法
US9395990B2 (en) * 2013-06-28 2016-07-19 Intel Corporation Mode dependent partial width load to wider register processors, methods, and systems
BR112017001975B1 (pt) * 2014-07-30 2023-02-28 Movidius Limited Imageamento computacional de baixa potência
US11153223B2 (en) * 2016-04-07 2021-10-19 International Business Machines Corporation Specifying a disaggregated compute system
US10289752B2 (en) * 2016-12-12 2019-05-14 Intel Corporation Accelerator for gather-update-scatter operations including a content-addressable memory (CAM) and CAM controller
GB2569275B (en) * 2017-10-20 2020-06-03 Graphcore Ltd Time deterministic exchange
US11669372B2 (en) * 2018-12-13 2023-06-06 Intel Corporation Flexible allocation of compute resources
US11231963B2 (en) 2019-08-15 2022-01-25 Intel Corporation Methods and apparatus to enable out-of-order pipelined execution of static mapping of a workload

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120239833A1 (en) * 2011-03-14 2012-09-20 Kabushiki Kaisha Toshiba Buffer management device, buffer management method, and storage device
US20160140071A1 (en) * 2014-11-13 2016-05-19 Cavium, Inc. Arbitrated Access To Resources Among Multiple Devices
TW201923558A (zh) * 2017-10-20 2019-06-16 英商葛夫科有限公司 主機處理器之同步化
US20190050261A1 (en) * 2018-03-29 2019-02-14 Intel Corporation Arbitration across shared memory pools of disaggregated memory devices

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KR20210021263A (ko) 2021-02-25
CN114895965A (zh) 2022-08-12
US11847497B2 (en) 2023-12-19
US20220197703A1 (en) 2022-06-23
DE102020119519A1 (de) 2021-02-18
TW202109285A (zh) 2021-03-01
US20190370073A1 (en) 2019-12-05
CN112395010A (zh) 2021-02-23
KR102684511B1 (ko) 2024-07-15
US11231963B2 (en) 2022-01-25
CN114895965B (zh) 2025-09-09
JP7400169B2 (ja) 2023-12-19
JP2021034020A (ja) 2021-03-01

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