TWI800560B - 多處理器系統、資料管理方法以及非暫態電腦可讀取儲存媒體 - Google Patents
多處理器系統、資料管理方法以及非暫態電腦可讀取儲存媒體 Download PDFInfo
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- TWI800560B TWI800560B TW107141267A TW107141267A TWI800560B TW I800560 B TWI800560 B TW I800560B TW 107141267 A TW107141267 A TW 107141267A TW 107141267 A TW107141267 A TW 107141267A TW I800560 B TWI800560 B TW I800560B
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- Taiwan
- Prior art keywords
- storage medium
- readable storage
- transitory computer
- data management
- management method
- Prior art date
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/0292—User address space allocation, e.g. contiguous or non contiguous base addressing using tables or multilevel address translation means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F2015/761—Indexing scheme relating to architectures of general purpose stored programme computers
- G06F2015/765—Cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/40—Specific encoding of data in memory or cache
- G06F2212/401—Compressed data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/62—Details of cache specific to multiprocessor cache arrangements
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201762588717P | 2017-11-20 | 2017-11-20 | |
US62/588,717 | 2017-11-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201937372A TW201937372A (zh) | 2019-09-16 |
TWI800560B true TWI800560B (zh) | 2023-05-01 |
Family
ID=64402025
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107141267A TWI800560B (zh) | 2017-11-20 | 2018-11-20 | 多處理器系統、資料管理方法以及非暫態電腦可讀取儲存媒體 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10866891B2 (zh) |
EP (1) | EP3486784B1 (zh) |
KR (1) | KR102157354B1 (zh) |
CN (1) | CN109815165A (zh) |
TW (1) | TWI800560B (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10831669B2 (en) * | 2018-12-03 | 2020-11-10 | International Business Machines Corporation | Systems, methods and computer program products using multi-tag storage for efficient data compression in caches |
US12066944B2 (en) * | 2019-12-20 | 2024-08-20 | Advanced Micro Devices, Inc. | Zero value memory compression |
CN111143244B (zh) * | 2019-12-30 | 2022-11-15 | 海光信息技术股份有限公司 | 计算机设备的内存访问方法和计算机设备 |
US11262938B2 (en) * | 2020-05-05 | 2022-03-01 | Silicon Motion, Inc. | Method and apparatus for performing access management of a memory device with aid of dedicated bit information |
CN112953853A (zh) * | 2021-02-05 | 2021-06-11 | 井芯微电子技术(天津)有限公司 | 共享缓存系统及方法、电子设备及存储介质 |
US11573899B1 (en) | 2021-10-21 | 2023-02-07 | International Business Machines Corporation | Transparent interleaving of compressed cache lines |
GB2614073B (en) * | 2021-12-21 | 2024-06-05 | Advanced Risc Mach Ltd | Cache systems |
GB2614069A (en) * | 2021-12-21 | 2023-06-28 | Advanced Risc Mach Ltd | Cache systems |
GB2614071B (en) * | 2021-12-21 | 2024-07-17 | Advanced Risc Mach Ltd | Cache systems |
US20230359556A1 (en) * | 2022-05-03 | 2023-11-09 | Advanced Micro Devices, Inc. | Performing Operations for Handling Data using Processor in Memory Circuitry in a High Bandwidth Memory |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130332652A1 (en) * | 2012-06-11 | 2013-12-12 | Hitachi, Ltd. | Computer system and method for controlling computer system |
TW201423402A (zh) * | 2012-12-12 | 2014-06-16 | Paneve Llc | 通用目的數位資料處理器、系統及方法 |
CN104620231A (zh) * | 2012-08-17 | 2015-05-13 | 华为技术有限公司 | 有序和无序网络的缓存相干握手协议 |
US20150347297A1 (en) * | 2014-05-29 | 2015-12-03 | Green Cache AB | Systems and methods for implementing a tag-less shared cache and a larger backing cache |
US20150372910A1 (en) * | 2014-06-20 | 2015-12-24 | Niara, Inc. | System, Apparatus and Method for Managing Redundancy Elimination in Packet Storage During Observation of Data Movement |
US20160170878A1 (en) * | 2014-12-16 | 2016-06-16 | Sanjeev N. Trika | Apparatus, system and method for caching compressed data |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7243191B2 (en) | 2004-08-31 | 2007-07-10 | Intel Corporation | Compressing data in a cache memory |
US8217813B2 (en) | 2010-04-29 | 2012-07-10 | Advanced Micro Devices, Inc. | System and method for low-latency data compression/decompression |
KR101956031B1 (ko) | 2012-10-15 | 2019-03-11 | 삼성전자 주식회사 | 데이터 압축 장치 및 방법, 데이터 압축 장치를 포함하는 메모리 시스템 |
EP3371707B1 (en) | 2015-11-04 | 2021-10-27 | Samsung Electronics Co., Ltd. | Systems and methods for implementing coherent memory in a multiprocessor system |
US20170255561A1 (en) | 2016-03-07 | 2017-09-07 | Intel Corporation | Technologies for increasing associativity of a direct-mapped cache using compression |
-
2018
- 2018-11-16 KR KR1020180141960A patent/KR102157354B1/ko active IP Right Grant
- 2018-11-19 CN CN201811374894.5A patent/CN109815165A/zh active Pending
- 2018-11-20 TW TW107141267A patent/TWI800560B/zh active
- 2018-11-20 US US16/195,942 patent/US10866891B2/en active Active
- 2018-11-20 EP EP18207155.5A patent/EP3486784B1/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130332652A1 (en) * | 2012-06-11 | 2013-12-12 | Hitachi, Ltd. | Computer system and method for controlling computer system |
CN104620231A (zh) * | 2012-08-17 | 2015-05-13 | 华为技术有限公司 | 有序和无序网络的缓存相干握手协议 |
TW201423402A (zh) * | 2012-12-12 | 2014-06-16 | Paneve Llc | 通用目的數位資料處理器、系統及方法 |
US20150347297A1 (en) * | 2014-05-29 | 2015-12-03 | Green Cache AB | Systems and methods for implementing a tag-less shared cache and a larger backing cache |
US20150372910A1 (en) * | 2014-06-20 | 2015-12-24 | Niara, Inc. | System, Apparatus and Method for Managing Redundancy Elimination in Packet Storage During Observation of Data Movement |
US20160170878A1 (en) * | 2014-12-16 | 2016-06-16 | Sanjeev N. Trika | Apparatus, system and method for caching compressed data |
Also Published As
Publication number | Publication date |
---|---|
EP3486784A1 (en) | 2019-05-22 |
US10866891B2 (en) | 2020-12-15 |
KR102157354B1 (ko) | 2020-09-17 |
US20190155731A1 (en) | 2019-05-23 |
KR20190058318A (ko) | 2019-05-29 |
TW201937372A (zh) | 2019-09-16 |
CN109815165A (zh) | 2019-05-28 |
EP3486784B1 (en) | 2020-11-18 |
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