TWI799220B - Method for preparing semiconductor structure having air gap - Google Patents

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a bit line on a substrate, forming a first dielectric layer over the substrate and surrounding a lower portion of the bit line, forming a second dielectric layer over the bit line and the first dielectric layer, forming a contact over the second dielectric layer, wherein a height of the contact above the substrate is greater than a height of the first dielectric layer above the substrate, removing the first dielectric layer and the second dielectric layer, and forming a third dielectric layer conformally over the bit line, the substrate and the contact, thereby forming an air gap between the contact and the bit line.

Description

Fabrication method of semiconductor structure with air gap

This application claims priority to US Patent Application Nos. 17/573,774 and 17/573,960 (ie, the priority date is "January 12, 2022"), the contents of which are incorporated herein by reference in their entirety.

The disclosure relates to a semiconductor structure and a method for preparing the semiconductor structure. In particular, it relates to a semiconductor structure with an air gap and a method for preparing the semiconductor structure.

Due to the simplicity of the structure of dynamic random access memory (DRAM), a DRAM can provide more memory per chip area than other types of memory such as static random access memory (SRAM) soma. DRAM is composed of multiple DRAM cells. Each DRAM cell has a capacitor for storing information and a transistor coupled to the capacitor to control when the capacitor is charged or discharged. During a read operation, the word line (WL) is asserted, thereby turning on the transistor. Turning on the transistor allows a sense amplifier to read a voltage across the capacitor via the bit line (BL). During a write operation, when WL is contacted, the data to be written is provided to BL.

In order to meet the demand for larger memory storage capacity, the size of DRAM memory cells is continuously reduced; thus, the packaging density of these DRAMs is greatly increased. However, capacitive coupling resulting in increased parasitic capacitance has become an increasingly important issue due to the shrinking size of DRAM memory cells. As a result of the parasitic capacitance, the speed of DRAM memory cells is undesirably reduced, and overall device performance is negatively affected.

The above "prior art" description only provides background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" is It should not be part of this case.

An embodiment of the present disclosure provides a method for fabricating a semiconductor structure. The manufacturing method includes forming a first bit line and a second bit line on a substrate; forming a patterned layer between the first bit line and the second bit line, wherein the patterned layer covering the substrate and surrounding a lower portion of the first bit line and a lower portion of the second bit line; forming a conformal layer on the patterned layer; forming a contact on the conformal layer and on the second bit line between a bit line and the second bit line, wherein a vertical distance between a top of the contact and the base is greater than a vertical distance between a top of the patterned layer and the base; removing the patterned layer and the conformal layer; and forming an air gap between the contact and the first bit line, or between the contact and the second bit line, wherein the air gap sealed by a dielectric layer.

In some embodiments, the manufacturing method further includes forming a sacrificial layer on the first bit line, on the second bit line and on the substrate; and removing the sacrificial layer around the first bit line an upper portion and a portion of an upper portion of the second bit line, thereby forming the patterned layer.

In some embodiments, a height of the patterned layer is substantially greater than a height of a metal layer of the first bit line or a height of a metal layer of the second bit line measured from the substrate.

In some embodiments, the conformal layer covers a top of the patterned layer, an upper portion of the first bit line, and an upper portion of the second bit line.

In some embodiments, the fabrication method further includes removing a portion of the patterned layer and a portion of the conformal layer prior to forming the contact, thereby exposing the substrate.

In some embodiments, the manufacturing method further includes depositing a layer of contact material on the conformal layer, the first bit line, and the second bit line; and removing a portion of the layer of contact material, thereby The contact point is formed, wherein a height of the contact point is substantially greater than a height of the patterned layer.

In some embodiments, a first horizontal distance between a top of the contact point and the first bit line is substantially smaller than a second distance between a lower portion of the contact point and the first bit line. Horizontal distance.

In some embodiments, the first horizontal distance is defined by a thickness of the conformal layer.

In some embodiments, the second horizontal distance is defined by a thickness of the patterned layer and a thickness of the conformal layer.

In some embodiments, forming the air gap includes depositing the dielectric layer between the contact and the first bit line, or between the contact and the second bit line; and filling A space between the first bit line and a top of the contact, or a space between the second bit line and the top of the contact.

In some embodiments, a thickness of the dielectric layer is approximately greater than or equal to half of a thickness of the conformal layer.

In some embodiments, a width of the air gap is substantially equal to a thickness of the patterned layer.

Another embodiment of the disclosure provides a method for fabricating a semiconductor structure. The manufacturing method includes forming a bit line on a base; forming a first dielectric layer on the base and surrounding a lower part of the bit line; forming a second dielectric layer on the base and the first On the dielectric layer; forming a contact point on the second dielectric layer, wherein a vertical distance between a top of the contact point and the base is greater than that between a top of the first dielectric layer and the base a vertical distance between; remove the first dielectric layer and the second dielectric layer; and conformally form a third dielectric layer on the bit line, the substrate and the contact, thereby forming An air gap is between the contact and the bit line.

In some embodiments, forming the first dielectric layer includes forming a first conformal layer on the substrate and the bit line; forming a mask layer on the first conformal layer; removing the mask layer and a portion of the first conformal layer, thereby exposing an upper portion of the bit line; and removing a remaining portion of the mask layer.

In some embodiments, the height of the first dielectric layer is defined by the mask layer.

In some embodiments, the fabrication technique of the second dielectric layer includes a conformal deposition.

In some embodiments, a thickness of the first dielectric layer is between 1 and 5 nm.

In some embodiments, a thickness of the second dielectric layer is between 5 and 12 nm.

In some embodiments, the fabrication method further includes, before forming the contact, etching the first dielectric layer and the second dielectric layer, thereby forming a gap substructure to surround the bit line; and exposing the base.

In some embodiments, the gap substructure tapers toward a top of the bitline.

In some embodiments, at least one of the first dielectric layer, the second dielectric layer and the third dielectric layer is fabricated by atomic layer deposition.

Another embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first bit line disposed on a substrate; a contact point adjacent to the first bit line disposed on the substrate, wherein an upper portion of the contact point is connected to the first bit line a first distance between the lines is less than a second distance between the lower portion of the contact point and the first bit line; a dielectric layer conformally disposed on the first bit line, the substrate and on the contact; and a first air gap sealed by the dielectric layer and bounded by the first bit line, the substrate and the contact.

In some embodiments, the first bit line includes a metal layer, and a vertical distance between a top of the contact and the base is greater than a vertical distance between a top of the metal layer and the base. distance.

In some embodiments, the vertical distance between the top of the contact point and the base is greater than the vertical distance between the top of the metal layer and the base (about 5 to 45 nm).

In some embodiments, the first bit line includes a metal layer, and a vertical distance between a top of the first air gap and the base is greater than or equal to a distance between a top of the metal layer and the base a vertical distance between.

In some embodiments, a vertical distance between the top of the first air gap and the top of the metal layer is between 0 and 10 nm.

In some embodiments, a vertical distance between a top of the first bitline and the base is greater than a vertical distance between a top of the contact and the base (about 90 to 130 nm).

In some embodiments, the contact point above the base tapers toward the base.

In some embodiments, the contact point is configured in a T shape.

In some embodiments, a thickness of the dielectric layer ranges from 3 to 6 nm.

In some embodiments, the dielectric layer fills a space between the top of the contact and the first bit line.

In some embodiments, the difference between the first distance and the second distance is approximately equal to a width of the first air gap.

In some embodiments, the semiconductor structure further includes a second bit line disposed on the substrate, wherein the contact point is disposed between the first bit line and the second bit line, and the dielectric a layer conformally disposed on the second bitline; and a second air gap sealed by the dielectric layer and bounded by the second bitline, the substrate, and the contact.

In some embodiments, a vertical distance between a top of the second air gap and the base is substantially greater than a vertical distance between a top of a metal layer of the second bit line and the base.

In some embodiments, a third distance between the bottom of the contact point and the second bit line is substantially less than a fourth distance between the lower portion of the contact point and the second bit line .

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Certainly, these embodiments are only for illustration, and are not intended to limit the scope of the present disclosure. For example, where a first component is formed on a second component, it may include embodiments where the first and second components are in direct contact, or may include an additional component formed between the first and second components, An embodiment such that the first and second parts do not come into direct contact. In addition, embodiments of the present disclosure may repeat reference numerals and/or letters in many instances. These repetitions are for the purpose of simplicity and clarity and, unless otherwise indicated in the context, do not in themselves imply a specific relationship between the various embodiments and/or configurations discussed.

It will be understood that although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not constrained by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the presently advanced concepts.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. Presence, but not excluding the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

FIG. 1 is a schematic cross-sectional view illustrating a semiconductor structure 1 according to some embodiments of the present disclosure. In some embodiments, the semiconductor structure 1 includes a substrate 11, a first bit line 13, a second bit line 14, a contact 16, a dielectric layer 17, air gaps AG1, AG2 and a landing pad 20. The first bit line 13 is disposed on the substrate 11 adjacent to the second bit line 14 . In some embodiments, the substrate 11 includes various components and/or one or more electronic devices. In some embodiments, the substrate 11 is a semiconductor substrate. In some embodiments, the semiconductor substrate 11 includes a transistor in an active region. In some embodiments, the first bit line 13 and the second bit line 14 are disposed on the substrate 11 in the active area. In some embodiments, the first bit line 13 or the second bit line 14 is electrically connected to the transistor.

In some embodiments, the substrate 11 includes a silicon portion 111 and an isolation portion 112 , and the isolation portion 112 is disposed on the silicon portion 111 . In some embodiments, the isolation portion 112 provides electrical isolation between the silicon portion 111 and the first bit line 13 and/or between the silicon portion 111 and the second bit line 14 . In some embodiments, an upper surface of the silicon portion 111 is not flat. In some embodiments, the isolation portion 112 provides a flat surface for subsequent processing. In some embodiments, the formation of the first bitline 13 and the second bitline 14 is performed on the planar surface of the isolation portion 112 . In some embodiments, the isolation portion 112 includes silicon nitride.

In some embodiments, the first bit line 13 includes a nitride layer 131 , a metal layer 132 and a mask layer 133 sequentially stacked on the substrate 11 . In some embodiments, the nitride layer 131 includes a metal nitride (eg, titanium nitride). In some embodiments, the nitride layer 131 acts as an adhesion layer. In some embodiments, metal layer 132 includes tungsten. In some embodiments, the mask layer 133 includes silicon nitride. In some embodiments, the second bit line 14 includes a nitride layer 141 , a metal layer 142 and a mask layer 143 to be stacked on the substrate 11 . In some embodiments, the second bit line 14 is similar to the first bit line 13, and its description will not be repeated.

In some embodiments, the semiconductor structure 1 further includes a gap sublayer 15 disposed on the substrate 11 , the first bit line 13 and the second bit line 14 . In some embodiments, as shown in FIG. 1 , the gap sublayer 15 covers a top and sidewalls of the first bitline 13 and/or covers a top and sidewalls of the second bitline 14 . In some embodiments, the top of the first bitline 13 is exposed through the gap sublayer 15 , and/or the top of the second bitline 14 is exposed through the gap sublayer 15 (not shown). In some embodiments, the interstitial sublayer 15 includes silicon nitride.

In some embodiments, contact points 16 are disposed on and in substrate 11 . In some embodiments, the contact point 16 passes through the isolation portion 112 and is electrically connected to the silicon portion 111 . In some embodiments, the contact point 16 is disposed at an edge of the active area of the substrate 11 from a top view. In some embodiments, the contact point 16 tapers toward the base 11 . In some embodiments, the contact point 16 is configured in a T shape. In some embodiments, a vertical distance between a top of the contact point 16 and the substrate 11 is greater than a vertical distance between the top of the metal layer 132 of the first bit line 13 and the substrate 11 . In some embodiments, the vertical distance between the top of the contact point 16 and the top of the metal layer 132 of the first bit line 13 is between 5 and 45 nm. In some embodiments, the vertical distance between the top of the contact point 16 and the substrate 11 is greater than the vertical distance between a top of the metal layer 142 of the second bit line 14 and the substrate 11 . In some embodiments, the vertical distance between the top of the contact point 16 and the top of the metal layer 142 of the second bit line 14 is between 5 and 45 nm. In some embodiments, a vertical distance between the top of the first bit line 13 and the substrate 11 is greater than a vertical distance between the top of the contact point 16 and the substrate 11 . In some embodiments, the vertical distance between the top of the first bitline 13 and the substrate 11 is greater than the vertical distance between the top of the contact 16 and the substrate 11 (about 90 to 130 nm). In some embodiments, a vertical distance between a top of the second bit line 14 and the base 11 is similar to the vertical distance between the first bit line 13 and the base 11, and between the second bit line 14 and the base 11 The height comparison between the contact points 16 is not repeated here.

For ease of description, the contact point 16 is divided into four parts from top to bottom: a top 161 , an upper part 162 , a lower part 163 and a bottom 164 . Top 161 is connected to upper part 162 , while upper part 162 is connected to lower part 163 , and lower part 163 is connected to bottom 164 . In some embodiments, the top portion 161 , the upper portion 162 and the lower portion 163 are disposed on the base 11 . In some embodiments, the bottom 164 is disposed in the base 11 . In some embodiments, top 161 is wider than lower portion 163 . In some embodiments, a width W161 of the top portion 161 is greater than a width W163 of the lower portion 163 . In some embodiments, upper portion 162 tapers in a width from top 161 to lower portion 163 . In some embodiments, the width W161 of the upper portion 161 remains constant from the contact point 16 to the upper portion 162 . In some embodiments, the width W163 of the lower portion 163 remains constant from the upper portion 162 to the bottom 164 . In some embodiments, the bottom 164 tapers toward a bottom of the contact point 16 inside the base 11 . In some embodiments, the configuration of the contact points 16 is closer to a perfect T-shape. In some embodiments, contact point 16 does not have upper portion 162 and lower portion 163 is directly connected to top portion 161 (not shown). In some embodiments, contact 16 includes polysilicon. In some embodiments, contact 16 includes doped polysilicon.

In some embodiments, a horizontal distance between the top portion 161 and the first bit line 13 is smaller than a horizontal distance between the lower portion 163 and the first bit line 13 . Similarly, in some embodiments, a horizontal distance between the top 161 of the contact point 16 and the second bit line 14 is smaller than a horizontal distance between the lower portion 163 of the contact point 16 and the second bit line 14 . In some embodiments, a horizontal distance between the upper part 162 and the first bit line 13 gradually increases from a connection point of the upper part 162 and the top part 161 toward a connection point of the upper part 162 and the lower part 163 . Similarly, in some embodiments, a horizontal distance between the upper portion 162 and the second bit line 14 gradually increases from the connection point of the upper portion 162 and the top portion 161 toward the connection point of the upper portion 162 and the lower portion 163 .

In some embodiments, the dielectric layer 17 is conformally disposed on each sidewall of the first bit line 13 , the second bit line 14 , the substrate 11 , and the contact 16 . In some embodiments, a first portion of the dielectric layer 17 surrounding the top 161 of the contact 16 is a fourth portion of the physical contact dielectric layer 17 surrounding the first bit line 13 . In some embodiments, a third portion of the dielectric layer 17 surrounding the lower portion 163 of the contact 16 is separated from the fourth portion of the dielectric layer 17 surrounding the first bit line 13 . In some embodiments, a second portion of the dielectric layer 17 surrounding the upper portion 162 of the contact point 16 may have an apex that contacts the fourth portion of the dielectric layer 17 . In some embodiments, a distance between the second portion and the fourth portion increases at positions of decreasing vertical distance from the base 11 .

In some embodiments, there may be no boundary or interface between the first portion and the fourth portion of the dielectric layer 17 . In some embodiments, the dielectric layer 17 is a nitride layer. In some embodiments, the dielectric layer 17 includes silicon nitride. In some embodiments, a thickness of the dielectric layer 17 is between 3 and 6 nm.

In some embodiments, the first portion of the dielectric layer 17 surrounding the top 161 of the contact 16 is a fifth portion of the physical contact dielectric layer 17 surrounding the second bit line 14 . In some embodiments, a distance between the second portion of the dielectric layer 17 surrounding the upper portion 162 of the contact 16 and the fifth portion of the dielectric layer 17 surrounding the second bit line 14 then decreases from the base. where the vertical distance increases. In some embodiments, the connection point between the first portion of the dielectric layer 17 and the second portion (or an apex of the second portion) may contact the fifth portion of the dielectric layer 17 . In some embodiments, the third portion of the dielectric layer 17 surrounding the lower portion 163 of the contact 16 is separated from the fifth portion of the dielectric layer 17 surrounding the second bit line 14 . In some embodiments, there may be no boundary or interface between the first portion and the fifth portion of dielectric layer 17 .

The air gap AG1 is sealed by the dielectric layer 17 . In some embodiments, the air gap AG1 is defined by the contact point 16 , the first bit line 13 and the substrate 11 . More particularly, in some embodiments, the air gap AG1 is defined by the upper portion 162 , the lower portion 163 , the substrate 11 , and the sidewalls of the first bit line 13 . In some embodiments, the air gap AG1 is mostly disposed between the lower portion 163 of the contact point 16 and the first bit line 13 . In some embodiments, a top of the air gap AG1 and a top of the metal layer 132 are at the same plane. In some embodiments, the air gap AG1 is substantially higher than the metal layer 132 of the first bit line 13 as measured from the substrate 11 . In other words, in some embodiments, a vertical distance between the top of the air gap AG1 and the base 11 is greater than or equal to a vertical distance between the top of the metal layer 132 of the first bit line 13 and the base 11 . In some embodiments, a vertical distance between the top of the metal layer 132 and the top of the air gap AG1 is between 0 and 10 nm.

The air gap AG2 is sealed by the dielectric layer 17 . In some embodiments, the air gap AG2 is defined by the contact point 16 , the second bit line 14 and the substrate 11 . More particularly, in some embodiments, the air gap AG2 is defined by the upper portion 162 , the lower portion 163 , the substrate 11 , and the sidewalls of the second bit line 14 . In some embodiments, the air gap AG2 is mostly disposed between the lower portion 163 of the contact point 16 and the second bit line 14 . In some embodiments, a top of the air gap AG2 is at the same plane as a top of the metal layer 142 . In some embodiments, a vertical distance between the top of the air gap AG2 and the substrate 11 is substantially greater than a vertical distance between the top of the metal layer 142 of the second bit line 14 and the substrate 11 . In other words, in some embodiments, a vertical distance between the top of the air gap AG2 and the substrate 11 is equal to or greater than a vertical distance between the top of the metal layer 142 of the second bit line 14 and the substrate 11 . In some embodiments, a vertical distance between the top of the metal layer 142 and the top of the air gap AG2 is between 0 and 10 nm.

In some embodiments, the semiconductor structure 1 further includes a contact layer 18 disposed on the contact point 16 . In some embodiments, the contact layer 18 is a cobalt layer. In some embodiments, contact layer 18 includes silicon cobalt. In some embodiments, the contact layer 18 is surrounded by the dielectric layer 17 . In some embodiments, contact layer 18 completely overlaps contact point 16 . In some embodiments, the contact layer 18 serves to adjust a resistance of the contact point 16 .

In some embodiments, the semiconductor structure 1 includes a plurality of contact points 16 and a corresponding plurality of landing pads 20 . In some embodiments, the semiconductor structure 1 includes a plurality of adhesive layers 19 corresponding to a plurality of landing pads 20 . In some embodiments, in order to avoid the peeling of the landing pads 20, the adhesive layers 19 are used to raise the distance between the landing pad 20 and the first bit line 13 and between the landing pad 20 and the second bit line 14. sticky purpose. For ease of description, only the landing pad 20 electrically connected to the contact point 16 as shown in FIG. 1 and the adhesive layer 19 disposed between the contact point 16 and the landing pad 20 are discussed in detail.

In some embodiments, the adhesive layer 19 is continuously disposed on the contact point 16 and an adjacent bit line (eg, the second bit line 14 in the embodiment shown in FIG. 1 ). In some embodiments, adhesive layer 19 contacts contact layer 18 , a top of the first portion of dielectric layer 17 and a portion of the fifth portion of dielectric layer 17 . In some embodiments, the adhesive layer 19 contacts a portion of the dielectric layer 17 on the second bit line 14 . In some embodiments, the adhesive layer 19 also contacts a portion of the dielectric layer 17 on the sidewall of the second bit line 17 .

In some embodiments, the landing pad 20 is disposed on the adhesive layer 19 . In some embodiments, landing pad 20 completely overlaps adhesive layer 19 . In some embodiments, in the cross-sectional view of FIG. 1 , the landing pad 19 covers an entire upper surface of the contact point 16 and at least a portion of an upper surface of one of the second bit lines 14 .

FIG. 2 is a schematic flow diagram illustrating a method M1 for fabricating a semiconductor structure 2 according to some embodiments of the present disclosure, and the semiconductor structure 2 is similar to the semiconductor structure 1 shown in FIG. 1 . The manufacturing method M1 includes: (S11) forming a first bit line and a second bit line on a substrate; (S12) forming a patterned layer between the first bit line and the second bit line (S13) forming a conformal layer on the patterned layer; (S14) forming a contact point on the conformal layer and between the first bit line and the second bit line; (S15) removing the patterned layer and the conformal layer; and (S16) forming an air gap between the contact and the first bit line, or between the contact and the second bit line. In some embodiments, the semiconductor structure 1 is manufactured according to the manufacturing method M1.

In order to further illustrate the concepts of the present disclosure, various examples are provided below. For purposes of clarity and simplicity, element numbers having the same or similar function are repeated in different embodiments. However, such usage is not intended to limit the disclosure to particular embodiments or particular elements. In addition, as long as the used parameters or conditions do not conflict, conditions or parameters described in different embodiments may be combined or improved to have a combination of different embodiments.

Please refer to FIG. 3 , according to some embodiments of the present disclosure and the step S11 of the manufacturing method M1 , the first bit line 13 and the second bit line 14 are formed on the substrate 11 . In some embodiments, the first bit line 13 and the second bit line 14 are disposed adjacently. In some embodiments, the first bit line 13 is a multi-layer structure. In some embodiments, the first bit line 13 includes a nitride layer 131 , a metal layer 132 and a mask layer 133 sequentially stacked on the substrate 11 . In some embodiments, the second bitline 14 is formed simultaneously with the first bitline 13 . In some embodiments, the second bit line 14 is similar to the first bit line 13 and includes a nitride layer 141 , a metal layer 142 and a mask layer 143 stacked on the substrate 11 .

A height of the metal layer 132 and a height of the metal layer 142 are adjustable and can be changed according to different generations of different devices. In some embodiments, the height of the metal layer 132 may be between 15% and 20% of the height of one of the first bit lines 13 . Similarly, in this embodiment, the height of the metal layer 142 is between 15% and 20% of the height of one of the second bit lines 14 . However, the present disclosure is not limited thereto. The detailed configuration of the stacked materials of the first bit line 13 and the second bit line 14 is not limited herein, and can be adjusted according to different applications.

In some embodiments, step S11 includes: (S111) performing a first blanket deposition (blanket deposition) to form a blanket nitride layer on the substrate 11; (S112) performing a second blanket deposition to forming a blanket metal layer on the blanket nitride layer; (S113) performing a third blanket deposition to form a blanket mask layer on the blanket metal layer; and (S114) patterning the blanket The nitride layer, the blanket metal layer and the blanket mask layer are coated to form a plurality of bit lines. It should be understood that the first bit line 13 and the second bit line 14 are examples of the plurality of bit lines. The semiconductor structures of the present invention may include more than two bit lines.

In some embodiments, the preparation method M1 further includes receiving the substrate 11 . In some embodiments, the substrate 11 undergoes multiple steps before the first bitline 13 and the second bitline 14 are formed. In some embodiments, the substrate 11 includes an isolation portion 112 formed on a silicon portion 111 . In some embodiments, the fabrication technique of the isolation portion 112 includes depositing a nitride layer. In some embodiments, the isolation portion 112 provides electrical isolation between the bit lines and the silicon portion 111 . In some embodiments, the silicon portion 111 includes a non-uniform surface from a previous process, and the isolation portion 111 contacts the non-uniform surface of the silicon portion 111 and provides a flat surface for subsequent steps of the manufacturing method M1. For simple description, the isolation part 112 is not shown in FIGS. 4 to 21 .

Please refer to FIG. 4 , according to some embodiments of the present disclosure, the manufacturing method M1 further includes forming a gap sublayer 15 . In some embodiments, the gap sublayer 15 is formed on the substrate 11 , the first bitline 13 and the second bitline 14 . In some embodiments, the gap sublayer 15 conforms to a contour of the first bitline 13 , the second bitline 14 and the substrate 11 . In some embodiments, the fabrication technique of the interstitial sublayer 15 includes depositing a nitride layer. In some embodiments, a thickness of the gap sublayer 15 is between 1 and 3 nm. In some embodiments, the fabrication technique of the interstitial sub-layer 15 includes an atomic layer deposition (ALD).

Referring to FIG. 5 to FIG. 8 , according to some embodiments of the present disclosure and step S12 of the manufacturing method M1 , a patterned layer O1 ′ is formed between the first bit line 13 and the second bit line 14 . The patterned layer O1 ′ covers the substrate 11 and surrounds a lower portion of the first bit line 13 and a lower portion of the second bit line 14 . In some embodiments, step S12 includes multiple steps as shown in FIG. 5 to FIG. 8 . In some embodiments, step S12 includes: (S121) forming a first sacrificial layer O1 on the substrate 11, the first bit line 13 and the second bit line 14; (S122) forming a photoresist PR1 on the substrate 11 to cover the first sacrificial layer O1; (S123) removing a part of the photoresist PR1 and a part of the first sacrificial layer O1, thereby exposing an upper part of the first bit line 13 and an upper part of the second bit line 14 and (S124) removing a remaining portion of the photoresist PR1.

Referring to FIG. 5 , according to some embodiments of the present disclosure and the step S121 of the step S12 of the manufacturing method M1 , the first sacrificial layer O1 is conformally formed on the substrate 11 . In some embodiments, the fabrication technique of the first sacrificial layer O1 includes a conformal deposition. In some embodiments, the fabrication technique of the first sacrificial layer O1 includes atomic layer deposition (ALD). In some embodiments, the first sacrificial layer O1 conformally covers the substrate 11 , the first bit line 13 and the second bit line 14 . In some embodiments, the first sacrificial layer O1 has a profile that conforms to the gap sublayer 15 . In some embodiments, the first sacrificial layer O1 is a dielectric layer. In some embodiments, the first sacrificial layer O1 is an oxide layer. In some embodiments, the first sacrificial layer O1 includes silicon oxide. In some embodiments, a thickness of the first sacrificial layer O1 is greater than or equal to a thickness of the gap sublayer 15 . In some embodiments, the thickness of the first sacrificial layer O1 is between 1 nm and 5 nm.

Please refer to FIG. 6 , according to some embodiments of the present disclosure and the step S122 of the step S12 of the manufacturing method M1 , a photoresist PR1 is formed on the substrate 11 and covers the first sacrificial layer O1 . The photoresist PR1 is used to define a height of the patterned layer O1 ′, and the patterned layer O1 ′ is formed in a subsequent process. In some embodiments, the photoresist PR1 can be another type of mask layer or protective layer.

Please refer to FIG. 7 to FIG. 8 , according to some embodiments of the present disclosure and steps S123 to S124 of step S12 of the manufacturing method M1, a part of the photoresist PR1 and a part of the first sacrificial layer O1 are removed, each of which is surrounding the first sacrificial layer. An upper portion 13T of the bit line 13 and an upper portion 14T of the second bit line 14 thereby form the patterned layer O1 ′. The patterned layer O1' is formed from the first sacrificial layer O1, that is, the portion of the first sacrificial layer O12 remaining after step S123. The upper portion 13T of the first bit line 13 and the upper portion 14T of the second bit line 14 are exposed through the patterned layer O1 ′, while the lower portion 13B of the first bit line 13 and the lower portion 14B of the second bit line 14 Surrounded by the patterned layer O1'. In some embodiments, a first boundary between the upper portion 13T and the lower portion 13B of the first bit line 13 is defined by the patterned layer O1′; similarly, between the upper portion 14T and the lower portion of the second bit line 14 A second boundary between 14B is also defined by the patterned layer O1'. In some embodiments, the first boundary is at or on a top of the metal layer 132 . In some embodiments, the second boundary is at or on a top of the metal layer 142 .

A height HO1' of the patterned layer O1' measured from the substrate 11 is defined by the photoresist PR1. As shown in FIG. 7 , after step S123 , the photoresist PR1 has a height HPR1 measured from the substrate 11 , and the height HO1 ′ is substantially equal to the height HPR1 . In some embodiments, the height HO1' of the patterned layer O1' is designed to be equal to or greater than a height H132 of the metal layer 132 and/or a height H142 of the metal layer 142, wherein the height H132 and the height H142 are measured from the base 11 . In some embodiments, a thickness of the patterned layer O1' (which is substantially equal to the thickness of the first sacrificial layer O1) is used to define a width of the air gap AG1 and a width of the air gap AG2, the air gap AG1 and the air gap AG2 is formed in a subsequent process. In some embodiments, during steps S123 and S124 , the consumable gap sublayer 15 covers portions of the tops of the first bit lines 13 and the second bit lines 14 . In some embodiments, portions of the gap sublayer 15 covering the tops of the first bitline 13 and the second bitline 14 are thinner (not shown). In some embodiments, after step S123 and/or step S124 of step S12 , a top portion of the mask layer 133 of the first bit line 13 is exposed through the gap sublayer 15 . In some embodiments, after step S123 and/or step S124 of step S12 , a top portion of the mask layer 143 of the second bit line 14 is exposed through the gap sublayer 15 .

Please refer to FIG. 9 , according to some embodiments of the present disclosure and step S13 of the manufacturing method M1 , a conformal layer O2 is formed on the substrate 11 . The conformal layer O2 in other embodiments may be represented as a second sacrificial layer. In some embodiments, the fabrication technique for the conformal layer O2 includes a blanket deposition. In some embodiments, the fabrication technique of the conformal layer O2 includes an atomic layer deposition (ALD). In some embodiments, the conformal layer O2 covers the patterned layer O1 ′, the upper portion 13T of the first bit line 13 and the upper portion 14T of the second bit line 14 . In some embodiments, the conformal layer O2 is a dielectric layer. In some embodiments, the conformal layer O2 is an oxide layer. In some embodiments, the conformal layer O2 includes the same material as the patterned layer O1'. In some embodiments, a thickness of the conformal layer O2 is greater than that of the patterned layer O1 ′. In some embodiments, the thickness of the conformal layer O2 is between 5 and 12 nm. In some embodiments, the thickness of the conformal layer O2 is designed to be twice the thickness of the dielectric layer 17, and the dielectric layer 17 is formed in a subsequent process. In some embodiments, the conformal layer O2 contacts the mask layer 133 of the first bit line 13 or the mask layer 143 of the second bit line 14 (not shown).

Please refer to FIG. 10 , according to some embodiments of the present disclosure, after step S13 , the manufacturing method M1 may further include exposing the substrate 11 between the first bit line 13 and the second bit line 14 . In some embodiments, each lateral portion of conformal layer O2, a lateral portion of patterned layer O1′ between first bitline 13 and second bitline 14, and gap sublayer 15 are removed. A lateral portion between the first bit line 13 and the second bit line 14 . In some embodiments, the lateral portions of conformal layer O2 disposed on substrate 11, on top of first bitline 13, and on top of second bitline 14 are removed, thereby forming an etch Conformal layer O21. In some embodiments, the lateral portion of the patterned layer O1 ′ on the substrate 11 exposed by etching the conformal layer O21 is removed, thereby forming an etched patterned layer O11 . In some embodiments, the conformal layer O21 together with the patterned layer O11 may define a gap substructure that tapers from the substrate 11 toward the top of the first bit line 13 and/or the top of the second bit line 14. thin. In some embodiments, the lateral portion of the spacer sublayer 15 on the substrate 11 exposed through the conformal layer O21 and the patterned layer O11 is removed, thereby forming an etched spacer sublayer 151 . In some embodiments, the interstitial substructure further includes an interstitial sublayer 151 . In some embodiments, a portion of the substrate 11 exposed through the conformal layer O21 , the patterned layer O11 and the gap sublayer 151 is removed to form a recess RC in the substrate 11 . In some embodiments, during the step of exposing the substrate 11, the top of the first bitline 13 and the top of the second bitline 14 may be protected by a hard mask (not shown), leaving the interstitial sublayer 15 covers the top of the first bit line 13 and those parts of the top of the second bit line 14 . Therefore, in some embodiments, the patterned mask 151 also covers the top of the first bit line 13 and the top of the second bit line 14 . In some embodiments, during the step of exposing substrate 11 , depleting spacer sublayer 15 covers portions of the top of first bitline 13 and the top of second bitline 14 , and after the step of exposing substrate 11 , exposing the top of the first bit line 13 and the top of the second bit line 14 .

In some embodiments, both the conformal layer O21 and the patterned layer O11 include oxide, and the fabrication technique includes a single etching process. In some embodiments, the gap sublayer 151 includes nitride, and its fabrication technique includes another etching process. In some embodiments, an etchant with low oxide-to-nitride selectivity is used to simultaneously remove the conformal layer O2, the patterned layer O1', and the spacer sublayer 15 in a single etch process. In some embodiments, removal of the portion of substrate 11 is performed by another etching process. In other words, in some embodiments, the formation of the recess RC is performed after the gap sublayer 151 is formed by a different etching process.

Referring to FIG. 11 to FIG. 12 , according to some embodiments of the present disclosure and step S14 of the manufacturing method, the contact point 16 is formed on the conformal layer O21 and between the first bit line 13 and the second bit line 14 . For electrical connection to the substrate 11, a contact 16 is formed in the recess RC.

In some embodiments, the step S14 of the manufacturing method M1 includes: forming a contact point material layer 16' to fill the recess RC and cover the first bit line 13 and the second bit line 14; and removing the contact point material layer 16' to form contact point 16. In some embodiments, the contact material layer 16' includes doped polysilicon. In some embodiments, an etch-back process is performed to remove the portion of the contact material layer 16'.

As shown in FIG. 12 , a contact 16 is formed in the recess RC and between the first bit line 13 and the second bit line 14 . In some embodiments, a height H16 of the contact point 16 on the substrate 11 is greater than a height HO1' of the patterned layer O1' on the substrate 11 (or the patterned layer O11, because a height of the patterned layer O11 is equal to the height HO1 ', for ease of description, the height HO1' also represents the height of the patterned layer O11). In some embodiments, the height H16 of the contact point 16 is greater than the height HO1′ (about 5 to 35 nm), and in some embodiments, the height H16 of the contact point 16 is smaller than a height of the first bit line 13 H13 and/or a height H14 of the second bit line 14 . In some embodiments, the height H16 of the contact point 16 is smaller than the height H13 of the first bit line 13 (between about 90 and 130 nm). In some embodiments, the height H13 of the first bit line 13 is substantially equal to the height H14 of the second bit line 14 .

A contour of the contact point 16 is defined by the conformal layer O21 and the patterned layer O11. Thus, the contact point 16 tapers towards the base 11 . The contact point 16 includes a top portion 161 , an upper portion 162 , a lower portion 163 and a bottom portion 164 . A width W161 of the top 161 is defined by the conformal layer O21 surrounding the upper portion 13T of the first bitline 13 and the upper portion 14T of the second bitline 14 . A width W163 of the lower portion 163 is defined by the conformal layer O21 and the patterned layer O11 surrounding the lower portion 13B of the first bitline 13 and the lower portion 14B of the second bitline 14 . Therefore, the width W161 of the top portion 161 is greater than the width W163 of the lower portion 163 . The top 161 and the lower part 163 are connected by the upper part 162 . A width W162 of the upper portion 162 gradually decreases from a width W161 to a width W163 at positions where the vertical distance from the base 11 decreases. It should be understood that width W 162 is depicted at a middle of upper portion 162 in FIG. 12 for illustrative purposes only. The bottom 164 of the contact point 16 is connected to the lower part 163 and is disposed in the base 11 , while the top 161 , the upper part 162 and the lower part 163 are all disposed on the base 11 .

Referring to FIG. 13 , according to some embodiments of the present disclosure and step S15 of the manufacturing method M1 , the patterned layer O11 and the conformal layer O21 are removed. In some embodiments, a wet etch process is performed to remove the patterned layer O11 and/or the conformal layer O21. In some embodiments, the patterned layer O11 and the conformal layer O21 are simultaneously removed by an etching process.

A distance D31 between the top 161 of the contact 16 and the first bit line 13 is smaller than a distance D33 between the bottom 163 of the contact 16 and the first bit line 13 . A distance D41 between the top 161 of the contact 16 and the second bit line 14 is smaller than a distance D43 between the bottom 163 of the contact 16 and the second bit line 14 . As shown in FIG. 12 , the distance D31 and the distance D41 are both defined by the conformal layer O21 , so the distance D31 and the distance D41 are approximately equal, and each is approximately equal to the thickness of the conformal layer O21 . Similarly, as shown in FIG. 12 , the distance D33 and the distance D43 are both defined by the conformal layer O21 and the patterned layer O11 , so the distance D33 and the distance D43 are approximately equal. Each of the distance D33 and the distance D43 is approximately equal to a total thickness equal to the sum of one of the thickness of the conformal layer O21 and the thickness of the patterned layer O11 . A distance D32 between the upper portion 162 and the first bit line 13 gradually increases at positions where the vertical distance from the substrate 11 decreases. Distance D32 increases from distance D31 to distance D33. A distance D42 between the upper portion 162 and the second bit line 14 gradually increases at positions where the vertical distance from the substrate 11 decreases. Distance D42 increases from distance D41 to distance D43.

In some embodiments, when the height HO1' of the patterned layer O11 is equal to the height H132 of the metal layer 132, a connection point between the upper part 162 and the lower part 163 is above the substrate 11 and the metal layer of the first bit line 13 The top of 132 is roughly on the same plane. In some embodiments, when the height HO1 ′ is greater than the height H132 , the connection point between the upper portion 162 and the lower portion 163 is higher (eg, a vertical distance from the substrate 11 is greater than) the metal layer 132 of the first bit line 13 . Similarly, in some embodiments, when the height HO1' of the patterned layer O11 is equal to the height H142 of the metal layer 142, the connection point between the upper part 162 and the lower part 163 is above the substrate 11 and the metal of the second bit line 14 The top of layer 142 is generally on the same plane. In some embodiments, when the height HO1 ′ is greater than the height H142 , the connection point between the upper portion 162 and the lower portion 163 is higher than (eg, a vertical distance from the substrate 11 is greater than) the metal layer 142 of the second bit line 14 .

Please refer to FIG. 14 , according to some embodiments of the present disclosure and step S16 of the manufacturing method M1, the air gap AG1 is formed between the contact point 16 and the first bit line 13, and the air gap AG2 is formed between the contact point 16 and the second bit line. between bit lines 14. In step S16 , a dielectric layer 17 is conformally formed on the first bit line 13 , the second bit line 14 and the contact 16 . In some embodiments, the dielectric layer 17 includes silicon nitride. The dielectric layer 17 seals the space between the upper portion 161 and the first bit line 13 , and the space between the upper portion 161 and the second bit line 14 . Thereby, the air gap AG1 and the air gap AG2 are respectively formed between the contact point 16 and the first bit line 13 and between the contact point 16 and the second bit line 14 . In some embodiments, dielectric layer 17 fills the space between upper portion 161 and first bit line 13 , and thereby defines air gap AG1 . In some embodiments, dielectric layer 17 fills the space between upper portion 161 and second bit line 14, and thereby defines air gap AG2.

In order to seal the air gaps AG1 and AG2 , a thickness of the dielectric layer 17 is designed to be at least half of the thickness of the conformal layer O2 . In a preferred embodiment, the thickness of the dielectric layer 17 is approximately half of the thickness of the conformal layer O2. A width W1 of the air gap AG1 and a thickness W2 of the air gap AG2 are defined by the thickness of the patterned layer O1 ′. In some embodiments, the width W1 of the air gap AG1 is approximately equal to the thickness of the patterned layer O1 ′. In some embodiments, the thickness W2 of the air gap AG2 is substantially equal to the thickness of the patterned layer O1 ′. In other words, the difference between the distance D31 and the distance D33 is approximately equal to the width W1 of the air gap AG1 ; and the difference between the distance D41 and the distance D43 is approximately equal to the width W2 of the air gap AG2 . A height H1 of the air gap AG1 and a height H2 of the air gap AG2 are defined by the height HO1 ′ of the patterned layer O1 ′. In some embodiments, the height H1 of the air gap AG1 is substantially equal to or greater than the height HO1 ′ of the patterned layer O1 ′. In some embodiments, the height H1 of the air gap AG1 is substantially greater than the height H132 of the metal layer 132 of the first bit line 13 . In some embodiments, the difference between the height H1 and the height H132 is substantially greater than or equal to a thickness of the conformal layer O2. In some embodiments, the difference between height H2 and height H142 is substantially greater than or equal to the height of upper portion 162 of contact point 16 (which is a vertical distance between top 161 and lower portion 163 ). In some embodiments, the height H2 of the air gap AG2 is substantially equal to or greater than the height HO1 ′ of the patterned layer O1 ′. In some embodiments, the height H2 of the air gap AG2 is substantially greater than the height H142 of the metal layer 142 of the second bit line 14 . In some embodiments, the difference between the height H2 and the height H142 is approximately equal to a thickness of the conformal layer O2. In some embodiments, the difference between height H2 and height H142 is approximately equal to the height of upper portion 162 of contact point 16 (which is a vertical distance between top 161 and lower portion 163 ). In some embodiments, dielectric layer 17 surrounds the portion of upper portion 161 and dielectric layer 17 surrounds the portion of first bit line 13 , with no boundary between the two locations. Similarly, in some embodiments, dielectric layer 17 surrounds the portion of upper portion 161 and dielectric layer 17 surrounds the portion of second bit line 14 , with no boundary between the two locations.

Please refer to FIG. 15 , according to some embodiments of the present disclosure, the manufacturing method M1 further includes: exposing the contact point 16 . In some embodiments, a portion of dielectric layer 17 over contact 16 is removed. In some embodiments, the portion of dielectric layer 17 is physically connected to contact 16 prior to removal. In some embodiments, a dry etch process is performed to remove the portion of the dielectric layer 17 . In some embodiments, a hard mask (not shown) is formed on the first bit line 13 and the second bit line 14 to define the portion where the dielectric layer 17 is removed. In some embodiments, the portions of dielectric layer 17 on top of first bit line 13 and on top of second bit line 14 are also removed during the dry etch process. In some embodiments, the remainder of the dielectric layer 17 after the dry etch process has rounded corners (or a spacer profile) due to the nature of the etch process.

Please refer to FIG. 16, according to some embodiments of the present disclosure, the manufacturing method M1 further includes: forming a contact layer 18 on the contact point 16; forming an adhesive layer 19' on the contact point 16, the first bit line 13 and the second on bit line 14. In some embodiments, contact layer 18 includes metallic elements. In some embodiments, contact layer 18 includes silicon cobalt. In some embodiments, contact layer 18 is formed only on contact points 16 . In some embodiments, the contact layer 18 is surrounded by a portion of the dielectric layer 17 extending on the upper portion 161 of the contact point 16 . In some embodiments, contact layer 18 may be used to adjust the resistance of contact point 16 . In some embodiments, the adhesive layer 19' is used to provide between a plurality of landing pads (formed in a subsequent process) and a plurality of bit lines (such as the first bit line 13 and the second bit line 14). stickiness between them. In some embodiments, the adhesion layer 19' includes a metal nitride. In some embodiments, the adhesion layer 19' includes at least one titanium nitride.

Please refer to FIG. 17 to FIG. 18 , according to some embodiments of the present disclosure, the manufacturing method M1 further includes: forming a landing pad 20 on the contact point 16 . In this way, a semiconductor structure 2 as shown in FIG. 18 is formed.

In some embodiments, forming the landing pad 20 includes: forming a pad layer 20 ′ on the adhesive layer 19 ′; and removing a portion of the pad layer 20 ′. In some embodiments, the pad layer 20' fabrication technique includes a blanket deposition. In some embodiments, the portion of the bonding pad layer 20 ′ is removed by an etching process, and one or more landing pads 20 are formed. In some embodiments, a contour of the landing pads 20 is defined by a pattern formed on the pad layer 20'. In some embodiments, a portion of the adhesive layer 19' is removed along with the portion of the pad layer 20' by the same etching process. In some embodiments, the plurality of adhesive layers 19 and the plurality of landing pads 20 are formed simultaneously. For ease of description, only the adhesive layer 19 and the landing pad 20 disposed on the contact point 16 and electrically connected to the contact point 16 are described in the following description. In some embodiments, the landing pad 20 conforms to the contact 16 and an adjacent bit line (eg, the second bit line 14 of the semiconductor structure 2 ). In some embodiments, adhesive layer 19 is conformally disposed between landing pad 20 and contact point 16 , and between landing pad 20 and second bitline 14 . In some embodiments, as shown in the semiconductor structure 1 of FIG. 1 , the landing pad 20 has rounded corners due to the etching process.

FIG. 19 is a schematic cross-sectional view illustrating a semiconductor structure 3 according to some embodiments of the present disclosure. As mentioned above, in some embodiments, the portions of gap sublayer 15 on top of first bitline 13 and on top of second bitline 14 are consumed during execution of fabrication method M1 . The semiconductor structure 3 is manufactured according to the fabrication method M1 and has a structure similar to that of the semiconductor structure 1 , but the tops of the first bit line 13 and the second bit line 14 are exposed through the gap sublayer 151 .

20 to 21 are schematic cross-sectional views illustrating various intermediate stages in the fabrication of the semiconductor structure 4 according to some embodiments of the present disclosure.

As mentioned above, in some embodiments, the substrate 11 includes a plurality of depressions disposed on the upper surface of the silicon portion 111 . Please refer to FIG. 20 , in some embodiments, the substrate 11 further includes a bit line contact 113 and an isolation portion 114 . In some embodiments, a recess surrounding the bit line contact 113 is formed after step S11. In some embodiments, the recess is formed simultaneously with the first bit line 13 and the second bit line 14 during step S114 . In some embodiments, the bit line contact 113 provides an electrical connection to a transistor in the substrate 11 . In some embodiments, after step S11 , the isolation portion 114 is formed and the recess is filled. In some embodiments, the semiconductor structure 4 includes a third bit line 12 disposed between the first bit line 13 and the second bit line 14 . In some embodiments, the semiconductor structure 4 is manufactured according to the manufacturing method M1, and the third bit line 12 is formed simultaneously with the first bit line 13 and the second bit line 14 in step S11. In some embodiments, the third bitline 12 is aligned with the bitline contact 113 . Then, steps S12 to S16 of the manufacturing method M1 are performed on the intermediate structure of FIG. 20 to form the semiconductor structure 5 as shown in FIG. 21 , and repeated descriptions thereof are omitted herein. In some embodiments, two contact points 16 are disposed at two edges at both ends of the active area from a top view. In some embodiments, the bit line contact 113 is disposed at a central area or at a center of the active area from a top view. It should be understood that the isolation portion 112 may also be included in the substrate 11 of the semiconductor structure 4 , but it is not shown in FIG. 20 and FIG. 21 for ease of description. In some embodiments, third bitline 12 contacts bitline contact 113 without isolation 112 therebetween. In some embodiments, a material of the isolation part 112 and a material of the isolation part 114 may be the same.

An embodiment of the present disclosure provides a method for fabricating a semiconductor structure. The manufacturing method includes forming a first bit line and a second bit line on a substrate; forming a patterned layer between the first bit line and the second bit line, wherein the patterned layer covering the substrate and surrounding a lower portion of the first bit line and a lower portion of the second bit line; forming a conformal layer on the patterned layer; forming a contact on the conformal layer and on the second bit line between a bit line and the second bit line, wherein a vertical distance between a top of the contact and the base is greater than a vertical distance between a top of the patterned layer and the base; removing the patterned layer and the conformal layer; and forming an air gap between the contact and the first bit line, or between the contact and the second bit line, wherein the air gap sealed by a dielectric layer.

Another embodiment of the disclosure provides a method for fabricating a semiconductor structure. The manufacturing method includes forming a bit line on a base; forming a first dielectric layer on the base and surrounding a lower part of the bit line; forming a second dielectric layer on the base and the first On the dielectric layer; forming a contact point on the second dielectric layer, wherein a vertical distance between a top of the contact point and the base is greater than that between a top of the first dielectric layer and the base a vertical distance between; remove the first dielectric layer and the second dielectric layer; and conformally form a third dielectric layer on the bit line, the substrate and the contact, thereby forming An air gap is between the contact and the bit line.

Another embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first bit line disposed on a substrate; a contact point adjacent to the first bit line disposed on the substrate, wherein an upper portion of the contact point is connected to the first bit line a first distance between the lines is less than a second distance between the lower portion of the contact point and the first bit line; a dielectric layer conformally disposed on the first bit line, the substrate and on the contact; and a first air gap sealed by the dielectric layer and bounded by the first bit line, the substrate and the contact.

In conclusion, the present application discloses a semiconductor structure and a method for preparing the semiconductor structure. The fabrication method includes forming two sacrificial layers to define an air gap between a contact and a bit line. The nitride-oxide-nitride sandwich structure is replaced by two sacrificial layers, and since the nitride is refilled during the nitride sealing process, the size reduction of the air gap is avoided. The width and height of the air gap can be better controlled.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such process, machinery, manufacture, material composition, means, method, or steps are included in the patent scope of this application.

1: Semiconductor structure 2: Semiconductor structure 3: Semiconductor structure 4: Semiconductor structure 5: Semiconductor structure 11: Base 12: The third bit line 13: The first bit line 13B: lower part 13T: upper part 14: Second bit line 14B: lower part 14T: upper part 15:Interstitial sublayer 16: Touchpoints 16': contact point material layer 17: Dielectric layer 18: Contact layer 19: Adhesive layer 19': Adhesive layer 20: Landing Pad 20': pad layer 111: Silicon department 112: Isolation Department 113: bit line contact point 114: Isolation Department 131: Nitride layer 132: metal layer 133: mask layer 141: Nitride layer 142: metal layer 143: mask layer 151: Etching the gap sublayer 161: top 162: upper part 163: lower part 164: bottom AG1: air gap AG2: air gap D31: Distance D32: Distance D33: Distance D41: Distance D42: Distance D43: Distance H1: height H13: Height H132: Height H14: height H142: Height H16: height H2: height HO1': Height HPR1: height M1: Preparation method O1: first sacrificial layer O1': patterned layer O11: Etching the patterned layer O2: conformal layer O21: Etching the conformal layer PR1: photoresist RC: concave S11: step S12: step S13: step S14: step S15: step S16: step W1: width W161: Width W162: Width W163: Width W2: width

The disclosure content of the present application can be understood more fully when the drawings are considered together with the embodiments and the patent scope of the application. The same reference numerals in the drawings refer to the same components. FIG. 1 is a schematic cross-sectional view illustrating a semiconductor structure of some embodiments of the present disclosure. FIG. 2 is a schematic flow diagram illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure. 3 to 18 are schematic cross-sectional views illustrating intermediate stages in the fabrication of semiconductor structures according to some embodiments of the present disclosure. FIG. 19 is a schematic cross-sectional view illustrating a semiconductor structure of some embodiments of the present disclosure. 20 to 21 are schematic cross-sectional views illustrating intermediate stages in the fabrication of semiconductor structures according to some embodiments of the present disclosure.

1: Semiconductor structure

11: Base

13: The first bit line

14: Second bit line

15:Interstitial sublayer

16: Touchpoints

17: Dielectric layer

18: Contact layer

19: Adhesive layer

20: Landing Pad

111: Silicon department

112: Isolation Department

131: Nitride layer

132: metal layer

133: mask layer

141: Nitride layer

142: metal layer

143: mask layer

161: top

162: upper part

163: lower part

164: bottom

AG1: air gap

AG2: air gap

W161: Width

W163: Width

Claims (21)

A method for preparing a semiconductor structure, comprising: forming a first bit line and a second bit line on a substrate; forming a patterned layer between the first bit line and the second bit line, wherein the patterned layer covers the substrate and surrounds a lower portion of the first bit line and a lower portion of the second bit line; forming a conformal layer on the patterned layer; forming a contact point on the conformal layer on and between the first bit line and the second bit line, wherein a vertical distance between a top of the contact point and the base is greater than between a top of the patterned layer and the base removing the patterned layer and the conformal layer; and forming an air gap between the contact and the first bit line, or between the contact and the second bit line , where the air gap is sealed by a dielectric layer. The method for preparing a semiconductor structure as claimed in claim 1, further comprising: forming a sacrificial layer on the first bit line, on the second bit line and on the substrate; and removing the sacrificial layer around the first bit line An upper portion of one of the bit lines and a portion of an upper portion of the second bit line, thereby forming the patterned layer. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the vertical distance between the top of the patterned layer and the substrate is substantially greater than a top of a metal layer of the first bit line A vertical distance between the bottom and the substrate or a vertical distance between a top of a metal layer of the second bit line and the substrate. The method of manufacturing a semiconductor device as claimed in claim 15, wherein the conformal layer covers a top of the patterned layer, an upper portion of the first bit line, and an upper portion of the second bit line. The method of manufacturing a semiconductor device according to claim 1, further comprising removing a part of the patterned layer and a part of the conformal layer before forming the contact point, thereby exposing the substrate. The method for manufacturing a semiconductor device as claimed in claim 1, further comprising: depositing a contact point material layer on the conformal layer, the first bit line and the second bit line; and removing the contact point material layer part of the , thereby forming the contact point. The method of manufacturing a semiconductor device as claimed in claim 1, wherein a first horizontal distance between a top of the contact point and the first bit line is substantially smaller than that between a lower part of the contact point and the first bit line A second horizontal distance between element lines. The method of manufacturing a semiconductor device as claimed in claim 7, wherein the first horizontal distance is defined by a thickness of the conformal layer. The method of manufacturing a semiconductor device as claimed in claim 7, wherein the second horizontal distance is defined by a thickness of the patterned layer and a thickness of the conformal layer. The method for manufacturing a semiconductor device as claimed in item 1, wherein the formation of the air gap comprises: depositing the dielectric layer between the contact point and the first bit line, or between the contact point and the second bit line between bit lines; and filling a space between the first bit line and a top of the contact, or a space between the second bit line and the top of the contact . The method of manufacturing a semiconductor device as claimed in claim 10, wherein a thickness of the dielectric layer is approximately greater than or equal to half of a thickness of the conformal layer. The method for manufacturing a semiconductor device as claimed in claim 11, wherein a width of the air gap is approximately equal to a thickness of the patterned layer. A method for manufacturing a semiconductor element, comprising: forming a bit line on a base; forming a first dielectric layer on the base and surrounding a lower part of the bit line; forming a second dielectric layer on the base On the substrate and the first dielectric layer; forming a contact point on the second dielectric layer, wherein a vertical distance between a top of the contact point and the substrate is greater than a a vertical distance between the top and the base; removing the first dielectric layer and the second dielectric layer; and conformally forming a third dielectric layer on the bit line, the base, and the contact above, thereby forming an air gap between the contact and the bit line. The method for manufacturing a semiconductor device as claimed in claim 13, wherein the forming of the first dielectric layer comprises: forming a first conformal layer on the base and the bit line; forming a mask layer on the first conformal layer layer; removing a portion of the mask layer and a portion of the first conformal layer, thereby exposing an upper portion of the bit line; and removing the mask layer. The method of manufacturing a semiconductor device as claimed in claim 14, wherein the vertical distance between the top of the first dielectric layer and the base is defined by the mask layer. The method for fabricating a semiconductor device as claimed in claim 13, wherein the fabrication technique of the second dielectric layer includes a conformal deposition. The method for manufacturing a semiconductor device as claimed in claim 13, wherein a thickness of the first dielectric layer is between 1 and 5 nanometers. The method of manufacturing a semiconductor device as claimed in claim 13, wherein a thickness of the second dielectric layer is between 5 and 12 nanometers. The method for manufacturing a semiconductor device as claimed in claim 13, further comprising: before forming the contact point, etching the first dielectric layer and the second dielectric layer, thereby forming a gap substructure to surround the bit line; and exposing the substrate. The method of manufacturing a semiconductor device as claimed in claim 19, wherein the gap substructure tapers toward a top of the bit line. The method of manufacturing a semiconductor device as claimed in claim 13, wherein at least one of the first dielectric layer, the second dielectric layer, and the third dielectric layer is fabricated by atomic layer deposition.

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