TWI794086B - Method for preparing a semiconductor structure having air gap - Google Patents

Abstract

The present disclosure provides a method for prepaing a semiconductor structure having an air gap. The method includes: forming a bit line over a substrate; forming a first spacer layer over and conformal to the bit line; forming a sacrificial layer over and conformal to the first spacer layer; forming a second spacer layer over and conformal to the sacrificial layer; forming a mask layer covering a lower portion of the second spacer layer; removing an upper portion of the second spacer layer; removing the sacrificial layer; and forming a third spacer layer over the first spacer layer and the second spacer layer, thereby forming a first air gap surrounded by the lower portion of the second spacer layer.

Description

Fabrication method of semiconductor structure with air gap

This application claims priority to US Patent Application Nos. 17/582,179 and 17/582,726 (ie, the priority date is "January 24, 2022"), the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a method for preparing a semiconductor structure, in particular to a method for preparing a semiconductor structure with an air gap.

Due to the simple structure of dynamic random access memory (DRAM), DRAM can provide more memory cells per chip area than other types of memory such as static random access memory (SRAM) . DRAM is composed of multiple DRAM cells. Each DRAM cell includes a capacitor for storing information and a transistor coupled to the capacitor to control when the capacitor is charged or discharged. During a read operation, the word line (WL) is asserted, thus turning on the transistor. Turning on the transistor allows the sense amplifier to read the voltage on the capacitor through the bit line (BL). During a write operation, when WL is activated, the data to be written is provided to BL.

In order to meet the demand for greater storage capacity, the size of DRAM memory cells continues to shrink; therefore, the packaging density of DRAM has also increased significantly. However, since DRAM memory cells Capacitive coupling resulting in increased parasitic capacitance has become an increasingly important issue as size shrinks. Due to the increased parasitic capacitance, the speed of the DRAM memory cell is unduly slowed down and overall device performance is adversely affected.

The above "prior art" description is only to provide background technology, and does not acknowledge that the above "prior art" description discloses the subject of this disclosure, and does not constitute the prior art of this disclosure, and any description of the above "prior art" shall not form part of this case.

One aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes: a base; a bit line structure disposed on the base; a first dielectric layer surrounding the bit line structure; a second dielectric layer surrounding the first dielectric a lower portion of the layer, wherein the second dielectric layer is separated from the first dielectric layer by the first air gap; and a third dielectric layer surrounding an upper portion of the first dielectric layer And seal the first air gap.

In some embodiments, the semiconductor structure further includes a fourth dielectric layer disposed between the second dielectric layer and the third dielectric layer.

In some embodiments, the fourth dielectric layer is disposed between the first air gap and the first dielectric layer.

In some embodiments, the semiconductor structure further includes a contact disposed on the substrate adjacent to the bit line structure.

In some embodiments, the distance between the top of the first air gap and the base is greater than the distance between the top of the contact surface and the base.

In some embodiments, the semiconductor structure further includes a landing pad disposed on the contact and the bit line structure.

In some embodiments, the landing pad covers the top of the bitline structure.

In some embodiments, the semiconductor structure further includes a fifth dielectric layer disposed on a portion of the landing pad, wherein the fifth dielectric layer penetrates into the landing pad and is in contact with the first dielectric layer. layer or the third dielectric layer.

In some embodiments, the semiconductor structure further includes a fifth dielectric layer disposed on a portion of the landing pad, wherein the fifth dielectric layer seals a hole of the landing pad and communicates with the first dielectric layer. The dielectric layer or the third dielectric layer is separated.

In some embodiments, the semiconductor structure further includes a second air gap surrounding an upper portion of the first dielectric layer and disposed between the first dielectric layer and the third dielectric layer.

In some embodiments, the second air gap is separate from the first air gap.

In some embodiments, the second air gap extends from the top of the first dielectric layer to the first air gap.

In some embodiments, the first air gap is elongated perpendicular to the base, and the second air gap is tapered toward the first air gap.

Another aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes: a first bit line and a second gap substructure. The first bit line is configured on a substrate. The second gap substructure surrounds the first bit line and includes a first dielectric layer and a first air gap sealed by the first dielectric layer. The first air gap surrounds a lower portion of the first bit line.

In some embodiments, the distance between the top of the first air gap and the base is greater than the distance between the top of a metal layer of the first bit line and the base.

In some embodiments, the semiconductor structure further includes a contact surrounding the first gap substructure, wherein the distance between the top of the first air gap and the substrate is greater than or equal to the The distance between the top of the contact and the base.

In some embodiments, the semiconductor structure further includes a landing pad disposed on the contact and in contact with a portion of the first interstitial substructure.

In some embodiments, the top of the first air gap is surrounded by the landing pad.

In some embodiments, the semiconductor structure further includes a second bit line disposed on the substrate and adjacent to the first bit line; and a second gap substructure surrounding the second bit line, And it includes a second dielectric layer and a second air gap sealed by the second dielectric layer.

In some embodiments, the semiconductor structure further includes a contact disposed between the first bit line and the second bit line, wherein the distance between the top of the second air gap and the substrate is greater than the distance between the top of the second air gap and the substrate. The distance between the top of the contact and the base.

In some embodiments, the first gap substructure further includes a third air gap disposed in the first dielectric layer and above the first air gap.

In some embodiments, the third air gap is separate from the first air gap.

In some embodiments, the size of the third air gap is smaller than the size of the first air gap.

In some embodiments, the first gap substructure further includes a native dielectric layer disposed in the first dielectric layer and located between the first air gap and the third air gap.

Another aspect of the present disclosure provides a method for fabricating a semiconductor structure. The preparation method includes: forming a bit line on a substrate; forming a first gap sublayer on the bit line and conforming to it; forming a sacrificial layer on the first gap sublayer and conforming to it ; forming a second gap sublayer on the sacrificial layer and conforming thereto; forming a mask layer covering a lower portion of the second gap sublayer; removing an upper portion of the second gap sublayer; removing the sacrificial layer; and in the A third gap sublayer is formed over a gap sublayer and the second gap sublayer, thereby forming a first air gap surrounded by the lower portion of the second gap sublayer.

In some embodiments, the first interstitial sublayer, the first air gap, the second interstitial sublayer, and the third interstitial sublayer are collectively defined as an interstitial substructure, and the interstitial substructure tapers from the substrate .

In some embodiments, the thickness of the gap substructure on the first air gap is substantially equal to the total thickness of the first gap sublayer and the third gap sublayer.

In some embodiments, the thickness of the gap substructure located at the lower portion of the second gap sublayer is substantially equal to the thickness of the first gap sublayer, the sacrificial layer, the second gap sublayer, and the first gap sublayer. Total thickness.

In some embodiments, the boundary between the lower portion of the second interstitial sublayer and the upper portion of the second interstitial sublayer is defined by the mask layer.

In some embodiments, the height of the first air gap is defined by the mask layer.

In some embodiments, a wet etch is performed to remove the sacrificial layer disposed between the first gap sublayer and the lower portion of the second gap sublayer.

In some embodiments, the method further includes conformally forming a native dielectric on the lower portions of the first interstitial sublayer and the second interstitial sublayer after the upper portion of the second interstitial sublayer is removed. stratum.

In some embodiments, the manufacturing method further includes removing a portion of the first gap sublayer and a portion of the third gap sublayer above the first air gap; A dielectric layer is formed on the gap sublayer, thereby forming a second air gap.

In some embodiments, a directional dry etch is performed to remove the portion of the first interstitial sublayer and the portion of the third interstitial sublayer.

In some embodiments, the fabrication method further includes exposing the substrate through the first gap sublayer, the second gap sublayer, and the third gap sublayer; and forming a contact to surround the first air gap, Wherein the distance between the top of the first air gap and the base is greater than the distance between the top of the contact and the base.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

1: Semiconductor structure

2: Semiconductor structure

3: Semiconductor structure

4: Semiconductor structure

5: Semiconductor structure

6: Semiconductor structure

11: Base

13: The first bit line

13B: lower part

13T: upper part

14: Second bit line

14B: lower part

14T: upper part

15: First gap sublayer

15B: lower part

15T: upper part

15': First gap sublayer

16: Dielectric layer

16': dielectric layer

17: Second gap sublayer

17B: lower part

17T: upper part

17': Second gap sublayer

18: Dielectric layer

18a: dielectric layer

18b: dielectric layer

19: The third interstitial sublayer

19': Third gap sublayer

20: Contact material layer

20': Contact

22: Landing layer

22': Landing Pad

23: Dielectric layer

131: Nitride layer

132: metal layer

133: mask layer

141: Nitride layer

142: metal layer

143: mask layer

153: The first part of the layer

154: The second part of the layer

163: The first partial layer

164:Second part layer

173: The first partial layer

174: The second part of the layer

193: The first partial layer

193B: lower part

193T: the upper part

194: The second part of the layer

194B: lower part

194T: the upper part

AG1: air gap

AG2: air gap

AG3: air gap

AG4: air gap

D1: distance

D2: distance

H1: distance (height)

H132: Height

H142: Height

H17B: Height

H2: distance (height)

H20': Height

HPR1': height

M1: Preparation method

OP1: first opening

OP2: second opening

PR1: photoresist

PR1': photoresist

RC: Groove

S11: Operation

S12: Operation

S13: Operation

S14: Operation

S15: Operation

S16: Operation

S17: Operation

S18: Operation

SA1: sacrificial layer

X: direction

Y: Direction

The disclosure content of the present application can be understood more comprehensively when referring to the embodiments and the patent scope of the application for combined consideration of the drawings, and the same reference numerals in the drawings refer to the same components.

FIG. 1 is a cross-sectional view illustrating a semiconductor structure of some embodiments of the present disclosure.

FIG. 2 is a flowchart illustrating a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

3-20 are cross-sectional views illustrating intermediate stages in the formation of semiconductor structures according to some embodiments of the present disclosure.

21-23 are cross-sectional views illustrating intermediate stages in the formation of semiconductor structures according to some embodiments of the present disclosure.

24-25 are cross-sectional views illustrating intermediate stages in the formation of semiconductor structures according to some embodiments of the present disclosure.

26 to 28 are cross-sectional views illustrating shapes of semiconductor structures according to some embodiments of the present disclosure. into an intermediate stage.

29-32 are cross-sectional views illustrating intermediate stages in the formation of semiconductor structures according to some embodiments of the present disclosure.

FIG. 33 is a flowchart illustrating a method of fabricating a semiconductor structure according to some embodiments of the present disclosure.

Embodiments, or examples, of the present disclosure illustrated in the drawings will now be described in specific language. It should be understood that no limitation of the scope of the present disclosure is intended herein. Any changes or modifications to the described embodiments, and any further applications of the principles described herein, are considered to be within the ordinary skill of the art to which this disclosure pertains. Reference symbols may be repeated throughout the embodiments, but this is not intended to apply to features of one embodiment over another, even if they share the same reference symbols.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the inventive concept.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the concept of the present invention. As used herein, the singular forms "a", "an" and "the" also include plural forms unless the context clearly dictates otherwise. It should be understood that when the words "comprise" and "comprising" are used in this specification, they indicate the presence of the stated features, integers, steps, operations, elements or components, but do not exclude the presence or addition of one or more other features. , integer, step, operation, element, part, or group thereof.

FIG. 1 is a cross-sectional view illustrating a semiconductor structure 1 of some embodiments of the present disclosure. In some embodiments, the semiconductor structure 1 includes: a substrate 11, a first bit line 13, a second bit line 14, a first gap sublayer 15', a dielectric layer 16', and a second gap sublayer 17' , a third gap sublayer 19', a contact 20', a dielectric layer 23, air gaps AG1 and AG2, and a landing pad 22'. The first bit line 13 and the second bit line 14 are adjacently disposed on the substrate 11 . In some embodiments, substrate 11 includes various components and/or one or more electronic components. In some embodiments, substrate 11 is a semiconductor substrate. In some embodiments, substrate 11 includes transistors in the active region. In some embodiments, the first bit line 13 and the second bit line 14 are disposed on the substrate 11 in the active area. In some embodiments, the first bit line 13 or the second bit line 14 is electrically connected to the transistor.

In some embodiments, the first bit line 13 includes a nitride layer 131 , a metal layer 132 and a mask layer 133 sequentially stacked on the substrate 11 . In some embodiments, the nitride layer 131 includes a metal nitride (eg, titanium nitride and/or tantalum nitride). In some embodiments, metal layer 132 includes tungsten. In some embodiments, the mask layer 133 includes silicon nitride. In some embodiments, the second bit line 14 includes a nitride layer 141 , a metal layer 142 and a mask layer 143 sequentially stacked on the substrate 11 . In some embodiments, the second bit line 14 is similar to the first bit line 13, and the description will not be repeated.

In some embodiments, first gap sublayer 15', second gap sublayer 17', and third gap sublayer 19' exhaustively represent one or more gaps on substrate 11 surrounding one or more bitlines substructure. In some embodiments, the first partial layer 153 of the first gap sublayer 15', the first partial layer 163 of the dielectric layer 16', the air gap AG1, the first partial layer 173 of the second gap sublayer 17' and the third The first partial layer 193 of the gap sublayer 19 ′ may be collectively defined as a first gap substructure surrounding the first bit line 13 . In some embodiments, the second partial layer 154 of the first gap sublayer 15', the second partial layer 164 of the dielectric layer 16', the air gap AG2, and the second partial layer 17' of the second gap sublayer 17' The second sub-layer 194 of the second sub-layer 174 and the third gap sub-layer 19 ′ may collectively define a second gap sub-structure surrounding the second bit line 14 . In some embodiments, the second gap substructure further includes an air gap AG3. In some embodiments, the second gap substructure further includes an air gap AG4.

In some embodiments, the air gap AG1 surrounds the lower portion of the first bit line 13 and is disposed between the first partial layer 153 of the first gap sublayer 15' and the first partial layer 173 of the second gap sublayer 17'. . In some embodiments, the air gap AG3 surrounds the upper portion of the first bit line 13 and is disposed between the first partial layer 153 of the first gap sublayer 15' and the first partial layer 193 of the third gap sublayer 19'. . In some embodiments, the air gap AG3 extends from the top of the first gap substructure toward the substrate 11 . In some embodiments, the air gap AG1 is elongated perpendicular to the base 11 , while the air gap AG3 tapers toward the air gap AG1 . In some embodiments, air gap AG3 is separate from air gap AG1. In some embodiments, the air gap AG1 is sealed by the upper portion 193T of the first sub-layer 193 of the third gap sub-layer 19 ′.

In some embodiments, the air gap AG2 surrounds the lower part of the second bit line 14, and is configured in the second partial layer 154 of the first gap sublayer 15' and the second partial layer 174 of the second gap sublayer 17'. between. In some embodiments, the air gap AG4 surrounds the upper portion of the second bit line 14 and is disposed between the second partial layer 154 of the first gap sublayer 15' and the second partial layer 194 of the third gap sublayer 19'. between. In some embodiments, the air gap AG4 extends from the top of the second gap substructure toward the substrate 11 . In some embodiments, the air gap AG2 is elongated perpendicular to the substrate 11 , and the air gap AG4 is tapered toward the air gap AG2 . In some embodiments, air gap AG4 is separate from air gap AG2. In some embodiments, the air gap AG2 is sealed by the upper portion 194T of the second partial layer 194 of the third gap sub-layer 19 ′.

In some embodiments, the thickness of the first gap substructure above the air gap AG1 is substantially equal to the total thickness of the first gap sublayer 15 ′ and the third gap sublayer 19 ′. in some embodiments , the thickness of the second gap substructure at the air gap AG1 is substantially equal to the total thickness of the first gap sublayer 15', the dielectric layer 16', the second gap sublayer 17' and the third gap sublayer 19' . The air gap AG1 and the first partial layer 173 of the second gap sublayer 17' only surround the lower part 13B of the first bit line 13 (as shown in FIG. 8 ), so that the first gap sublayer structure extends from the substrate 11 to the first bit line The top of line 13 tapers. Likewise, in some embodiments, the thickness of the second gap substructure above the air gap AG2 is substantially equal to the total thickness of the first gap sublayer 15 ′ and the third gap sublayer 19 ′. In some embodiments, the thickness of the second gap substructure at the air gap AG2 is substantially equal to the thickness of the first gap sublayer 15', the dielectric layer 16', the second gap sublayer 17' and the third gap sublayer 19. 'total thickness. The air gap AG2 and the second partial layer 174 of the second gap sublayer 17' only surround the lower part 14B of the second bit line 14 (as shown in FIG. 8 ), so that the second gap sublayer structure extends from the substrate 11 to the second bit line The top of the element wire 14 tapers.

In some embodiments, the height H20 ′ of the contact 20 ′ from the base 11 to the top of the contact 20 ′ is less than the distance D1 between the top of the air gap AG1 and the base 11 . In some embodiments, the height H20' of the contact 20' is less than the distance D2 between the top of the air gap AG2 and the base 11. In some embodiments, the distance D1 is greater than a height H132 of the metal layer 132 of the first bit line 13 from the base 11 to the top of the metal layer 132 . In some embodiments, the distance D2 is greater than a height H142 of the metal layer 142 of the second bit line 14 from the base 11 to the top of the metal layer 142 . In some embodiments, distance D1 is substantially equal to distance D1 because both distance D1 and distance D2 are defined by height H17B of second gap sublayer 17' (measured from the top of second gap sublayer 17B to substrate 11). D2.

In some embodiments, dielectric layer 23 seals air gap AG3 and air gap AG4 . In some embodiments, the dielectric layer 23 is in physical contact with the second interstitial substructure and/or the second interstitial substructure. More specifically, in such embodiments, the dielectric layer 23 is in physical contact with the first interstitial sublayer 15' and/or the third interstitial sublayer 19'. Therefore, in such an embodiment, the air gap The top of AG3 is lower than the top of first bit line 13 , and/or the top of air gap AG4 is lower than the top of second bit line 14 . In some embodiments, the dielectric layer 23 is separated from the first interstitial substructure and/or the second interstitial substructure. More specifically, in such embodiments, dielectric layer 23 is associated with first gap sub-layer 15 ′ and third gap sub-layer 19 around first bit line 13 and/or around second bit line 14 'separate. Thus, in such embodiments, the top of air gap AG3 is higher than the top of first bit line 13 , and/or the top of air gap AG4 is higher than the top of second bit line 14 .

In some embodiments, the first spacer sublayer 15', the second spacer sublayer 17' and the third spacer sublayer 19' are all nitrides. In some embodiments, the first interstitial sublayer 15', the second interstitial sublayer 17' and the third interstitial sublayer 19' are formed from different deposits. In some embodiments, there is no observable interface between any two of the first interstitial sublayer 15', the second interstitial sublayer 17', and the third interstitial sublayer 19'. In some embodiments, the first gap sublayer 15', the second gap sublayer 17' and the third gap sublayer 19' may be defined as one dielectric layer. In some embodiments, dielectric layer 23 includes nitride. In some embodiments, there is no observable interface between any two of dielectric layer 23 , first interstitial sublayer 15 ′, and third interstitial sublayer 19 ′.

FIG. 2 is a flowchart of a method M1 for manufacturing a semiconductor structure 2 similar to the semiconductor structure 1 shown in FIG. 1 . The manufacturing method M1 includes: (S11) forming a bit line on a substrate; (S12) forming a first gap sublayer on the bit line and conforming thereto; (S13) forming a sacrificial layer on the first gap sublayer and (S14) forming a second gap sublayer on the sacrificial layer and conforming thereto; (S15) forming a mask layer covering the lower part of the second gap sublayer. (S16) remove the upper part of the second gap sublayer; (S17) remove the sacrificial layer; and (S18) form the third gap sublayer on the first gap sublayer and the second gap sublayer, thus forming the second gap sublayer The lower part of the layer surrounds the first air gap. In some embodiments, the semiconductor structure 1 is also fabricated according to the fabrication method M1.

To further illustrate the concepts of the present disclosure, various examples are provided below. for For clarity and simplicity, reference signs of elements having the same or similar functions are repeated in different embodiments. However, such usage is not intended to limit the present disclosure to particular embodiments or particular elements. In addition, as long as the used parameters or conditions do not conflict, conditions or parameters described in different embodiments can be combined or modified to obtain different combinations of embodiments.

Referring to FIG. 3 , according to some embodiments of the present disclosure and operation S11 of the manufacturing method M1 , a first bit line 13 and a second bit line 14 are formed on a substrate 11 . In some embodiments, the first bit line 13 and the second bit line 14 are adjacent. In some embodiments, the first bit line 13 is a multi-layer structure. In some embodiments, the first bit line 13 includes a nitride layer 131 , a metal layer 132 and a mask layer 133 sequentially stacked on the substrate 11 . In some embodiments, the second bitline 14 is formed simultaneously with the first bitline 13 . In some embodiments, the second bit line 14 is similar to the first bit line 13 , including a nitride layer 141 , a metal layer 142 and a mask layer 143 sequentially stacked on the substrate 11 .

In some embodiments, operation S11 includes: (S111) performing a first blanket deposition to form a blanket nitride layer on the substrate 11; (S112) performing a second blanket deposition to form a blanket on the blanket nitride layer (S113) performing a third blanket deposition to form a blanket mask layer on the blanket metal layer; and (S114) patterning the blanket nitride layer, the blanket metal layer, and the blanket mask layer to form a plurality of bit lines. It should be noted that the first bit line 13 and the second bit line 14 are examples of a plurality of bit lines. The semiconductor structure of the present invention may include more than two bit lines.

The thickness of the layers of the first bitline 13 and the second bitline 14 depends on different applications. For example, the thickness of the metal layer 132 and the thickness of the metal layer 142 can be adjusted and can vary from generation to generation of different components. In some embodiments, the thickness of the metal layer 132 and the thickness of the metal layer 142 are substantially equal. However, the present disclosure is not limited thereto. first bit line 13 and The arrangement details of the stacked material of the second bit line 14 are not limited here, and can be adjusted according to different applications.

Referring to FIG. 4 , according to some embodiments of the present disclosure and operation S12 of the manufacturing method M1 , the first gap sublayer 15 is conformally formed on the first bit line 13 and the second bit line 14 . In some embodiments, lateral portions of the first interstitial sublayer 15 are in contact with the substrate 11 . In some embodiments, the first gap sublayer 15 conforms to the contours of the first bitline 13 , the second bitline 14 and the substrate 11 . In some embodiments, the first interstitial sublayer 15 is formed by deposition of a nitride layer. In some embodiments, the first interstitial sublayer 15 is formed by atomic layer deposition (ALD). In some embodiments, the thickness of the first interstitial sublayer 15 is between 4 and 8 nanometers.

Referring to FIG. 5 , according to some embodiments of the present disclosure and operation S13 of the manufacturing method M1 , a sacrificial layer SA1 is conformally formed on the first gap sublayer 15 . In some embodiments, the sacrificial layer SA1 is formed by conformal deposition. In some embodiments, the sacrificial layer SA1 is formed by atomic layer deposition (ALD). In some embodiments, sacrificial layer SA1 conformally covers substrate 11 , first bitline 13 and second bitline 14 . In some embodiments, the sacrificial layer SA1 has a conformal profile with the first interstitial sublayer 15 . In some embodiments, the sacrificial layer SA1 is a dielectric layer. In some embodiments, the sacrificial layer SA1 includes a dielectric material different from that of the first gap sublayer 15 . In some embodiments, the sacrificial layer SA1 is an oxide layer. In some embodiments, the sacrificial layer SA1 includes silicon oxide. In some embodiments, the thickness of the sacrificial layer SA1 is smaller than the thickness of the first gap sublayer 15 . In some embodiments, the thickness of the sacrificial layer SA1 is between 1 and 3 nm. In some embodiments, the thickness of the sacrificial layer SA1 is used to determine the width of the air gap formed later in the process.

Referring to FIG. 6 , according to some embodiments of the present disclosure and operation S14 of the manufacturing method M1 , the second gap sublayer 17 is conformally formed on the sacrificial layer SA1 . In some embodiments, the second gap sublayer 17 is formed by conformal deposition. In some embodiments, the second gap sublayer 17 It is formed by atomic layer deposition (ALD). In some embodiments, the second gap sublayer 17 conformally covers the substrate 11 , the first bitline 13 and the second bitline 14 . In some embodiments, the second spacer sub-layer 17 has a conformal profile with the sacrificial layer SA1. In some embodiments, the second gap sublayer 17 is a dielectric layer. In some embodiments, the second gap sublayer 17 includes a dielectric material different from that of the sacrificial layer SA1. In some embodiments, the second gap sublayer 17 includes the same dielectric material as the first gap sublayer 15 . In some embodiments, the second interstitial sublayer 17 is a nitride layer. In some embodiments, the second gap sublayer 17 includes silicon nitride. In some embodiments, the thickness of the second gap sublayer 17 is greater than the thickness of the sacrificial layer SA1. In some embodiments, the thickness of the second gap sublayer 17 is substantially equal to the thickness of the first gap sublayer 15 . In some embodiments, the thickness of the second interstitial sublayer 17 is between 4 and 8 nanometers.

Referring to FIGS. 7 to 8 , illustrating some embodiments of the present disclosure and operation S15 of the manufacturing method M1 , a photoresist PR1 is formed to cover the lower portion of the second gap sub-layer 17 . The photoresist PR1 is used to define the height of the lower portion of the second gap sub-layer 17 , and further defines the height of the air gap to be formed in the subsequent process. In some embodiments, the photoresist PR1 can be any type of mask layer or protective layer. In some embodiments, operation S15 includes a plurality of steps: ( S151 ) forming the photoresist PR1 ; and ( S152 ) removing a portion of the photoresist PR1 , thus exposing the upper portion of the second gap sublayer 17 .

Referring to FIG. 7 , according to some embodiments of the present disclosure and step S151 of operation S15 of the manufacturing method M1 , a photoresist PR1 covering the first bit line 13 , the second bit line 14 and the substrate 11 is formed. In some embodiments, the photoresist PR1 covers the second gap sublayer 17 .

Referring to FIG. 8 , according to some embodiments of the present disclosure and step S152 of operation S15 of the manufacturing method M1 , a portion of the photoresist PR1 surrounding the upper portion 17T of the second gap sublayer 17 is removed. The remaining portion of the photoresist PR1 becomes the photoresist PR1 ′ surrounding the lower portion 17B of the second gap sublayer 17 . The photoresist PR1' is used to determine the height of the air gap formed later in the process.

The height HPR1 ′ measured from the top of the photoresist PR1 ′ to the substrate 11 is designed to be greater than or equal to the height H132 of the metal layer 132 measured from the top of the metal layer 132 to the substrate 11 . The height HPR1 ′ is also designed to be greater than or equal to the height H142 of the metal layer 142 measured from the top of the metal layer 142 to the base 11 . In some embodiments, the upper portion 17T of the second gap sublayer 17, the upper portion of the sacrificial layer SA1, the upper portion 15T of the first gap sublayer 15, the upper portion 13T of the first bit line 13, and the upper portion of the second bit line 14 14T is exposed through photoresist PR1'. In some embodiments, the lower portion 17B of the second gap sublayer 17, the lower portion of the sacrificial layer SA1, the lower portion 15B of the first gap sublayer 15, the lower portion 13B of the first bit line 13, and the lower portion of the second bit line 14 14B is surrounded by photoresist PR1'. In some embodiments, the photoresist PR1' has a thickness between 80 and 130 nm.

Referring to FIG. 9 , according to some embodiments of the present disclosure and operation S16 of the manufacturing method M1 , the upper portion 17T of the second gap sublayer 17 is removed. The upper portion of the sacrificial layer SA1 is exposed through the lower portion 17B of the second gap sublayer 17 . In some embodiments, a dry etch is performed to remove the upper portion 17T of the second gap sublayer 17 . For convenience of description, the lower portion 17B of the second gap sublayer 17 in the intermediate structure formed after operation S16 is referred to as a second gap sublayer 17B.

The height H17B of the second spacer sublayer 17B measured from the substrate 11 is defined by the photoresist PR1'. As shown in FIG. 9, the height HPR1' and the height H17B of the photoresist PR1' are substantially equal. In some embodiments, the height H17B of the second gap sublayer 17B is designed to be equal to or greater than the height H132 of the metal layer 132 and/or the height H142 of the metal layer 142 , wherein the height H132 and the height H142 are measured from the substrate 11 . In some embodiments, the second gap sublayer 17B surrounds at least the metal layer 132 of the first bit line 13 . In some embodiments, the second gap sublayer 17B surrounds at least the metal layer 142 of the second bitline 14 .

Referring to FIG. 10 , according to some embodiments of the present disclosure and operation S17 of the manufacturing method M1 , a portion of the sacrificial layer SA1 is removed. In some embodiments, through photoresist PR1' or The exposed upper portion of the sacrificial layer SA1 of the second gap sub-layer 17B is removed. In some embodiments, at least a portion of the vertical portion of the sacrificial layer SA1 below the top of the photoresist PR1 ′ or the top of the second gap sub-layer 17B is also removed. In some embodiments, a wet etch is performed to remove the upper and vertical portions of the sacrificial layer SA1. In some embodiments, an etchant with a high oxynitride etch rate is used in the wet etch. The remaining part of the sacrificial layer SA1 becomes the dielectric layer 16 . In some embodiments, the dielectric layer 16 extends horizontally between the first gap sublayer 15 and the second gap sublayer 17B. In some embodiments, the overall configuration of the dielectric layer 16 is lower than the top of the photoresist PR1 ′ or lower than the top of the second gap sub-layer 17B. In some embodiments, the distance H1 between the top of the dielectric layer 16 and the top of the second gap sub-layer 17B is in the range of 60 to 100 nm measured adjacent to the first bit line 13 . In some embodiments, the distance H2 between the top of the dielectric layer 16 adjacent to the second bit line 14 and the top of the second gap sub-layer 17B measures in the range of 60 to 100 nanometers. In some embodiments, a native dielectric layer is conformally formed overlying the first gap sublayer 15 and the second gap sublayer 17B (not shown). In some embodiments, the native dielectric layer includes oxide.

Referring to FIG. 11 , according to some embodiments of the present disclosure, after operation S17 , the manufacturing method M1 further includes removing the photoresist PR1 ′. In some embodiments, an etch operation is performed to remove photoresist PR1 ′. In some embodiments, the vapor pressure of the etching operation is controlled during the removal of the photoresist PR1 ′ to avoid damaging or peeling off the second gap sublayer 17B. In some embodiments, after operation S17 , a native dielectric layer (not shown) is more conformally formed on the portion of the second gap sublayer 17B previously covered by the photoresist PR1 ′.

Referring to FIG. 12 , according to some embodiments of the present disclosure and operation S18 of the manufacturing method M1, a third gap sublayer 19 is formed on the first gap sublayer 15 and the second gap sublayer 17B, thereby forming air gaps AG1 and air gaps AG2 . The air gap AG1 and the air gap AG2 are sealed by the third gap sublayer 19 and surrounded by the second gap sublayer 17B. In some embodiments, the air gap AG1 is along the first bit line 13 is elongated and perpendicular to the base 11. In some embodiments, the air gap AG2 extends along the second bit line 14 and is perpendicular to the substrate 11 . In some embodiments, the height of the air gap AG1 and the height of the air gap AG2 are defined by removed portions overlapping the first gap sublayer 15 and the second gap sublayer 17B. In some embodiments, the height of the air gap AG1 is substantially equal to the height H1, and the height of the air gap AG2 is substantially equal to the height H2. For simplicity, in the following description, the height H1 may also represent the height of the air gap AG1 , and the height H2 may also represent the height of the air gap AG2 .

In some embodiments, the air gap AG1 surrounds the lower portion 13B of the first bit line 13 . In some embodiments, the air gap AG2 surrounds the lower portion 14B of the second bit line 14 . In some embodiments, the thickness of the third gap sublayer 19 is greater than the width of the air gap AG1 (or the thickness of the dielectric layer 16 because the width of the air gap AG1 is defined by the sacrificial layer SA1 ). Likewise, in some embodiments, the thickness of the third gap sublayer 19 is greater than the width of the air gap AG2 (or the thickness of the dielectric layer 16 ). In some embodiments, the third gap sublayer 19 is formed by a deposition operation. In some embodiments, the third gap sublayer 19 is formed by chemical vapor deposition. In some embodiments, the deposition rate for forming the third gap sublayer 19 is greater than the deposition rate for forming the sacrificial layer SA1. In some embodiments, the third gap sublayer 19 is not formed between the first gap sublayer 15 and the second gap sublayer 17B. In some embodiments, the third gap sublayer 19 conforms to the contours of the first gap sublayer 15 , the second gap sublayer 17B, the air gap AG1 , and the air gap AG2 . In some embodiments, the third gap sublayer 19 is a dielectric layer. In some embodiments, the third gap sublayer 19 includes the same dielectric material as the second gap sublayer 17B or the first gap sublayer 15 . In some embodiments, the third interstitial sublayer 19 is a nitride layer. In some embodiments, the third gap sublayer 19 includes silicon nitride. In some embodiments, the thickness of the third interstitial sublayer 19 is between 6 and 10 nanometers.

The preparation method M1 may further include additional operations, such as operations S19 to S23 shown in the flowchart in FIG. 33 . Referring to FIG. 13 , according to some embodiments of the present disclosure, after operation S18 Finally, the manufacturing method M1 may further include ( S19 ) exposing the substrate 11 between the first bit line 13 and the second bit line 14 . In some embodiments, lateral portions of the third gap sublayer 19 , the second gap sublayer 17B, the dielectric layer 16 and the first gap sublayer 15 are removed. In some embodiments, the lateral direction of the third gap sublayer 19 disposed between the first bit line 13 and the second bit line 14, on top of the first bit line 13 and on the top of the second bit line 14 Portions are removed, thus forming an etched third interstitial sub-layer 19'. In some embodiments, the lateral portion of the second gap sublayer 17B on the substrate 11 between the first bitline 13 and the second bitline 14 and exposed through the third gap sublayer 19' is removed, thereby An etched second interstitial sublayer 17' is formed. In some embodiments, the lateral portion of the dielectric layer 16 exposed through the second gap sublayer 17' on the substrate 11 between the first bit line 13 and the second bit line 14 is removed, thereby An etched dielectric layer 16' is formed. In some embodiments, the lateral portion of the first gap sublayer 15 exposed through the dielectric layer 16' between the first bit line 13 and the second bit line 14 on the substrate 11 is removed, and the second The lateral portions of the first spacer sublayer 15 exposed by the tops of the bitlines 13 and the second bitlines 14 through the third spacer sublayer 19' are also removed, thus forming the etched first spacer sublayer 15'.

In some embodiments, during operation S19, each of the first gap sublayer 15', the dielectric layer 16', the second gap sublayer 17', and the third gap sublayer 19' is divided into surrounding Different parts of the first bit line 13 and the second bit line 14 . In some embodiments, the first partial layer 153 of the first gap sublayer 15', the first partial layer 163 of the dielectric layer 16', the air gap AG1, the first partial layer 173 of the second gap sublayer 17' and the third The first partial layer 193 of the gap sublayer 19 ′ may be collectively defined as a first gap substructure surrounding the first bit line 13 . In some embodiments, the second partial layer 154 of the first gap sublayer 15', the second partial layer 164 of the dielectric layer 16', the air gap AG2, the second partial layer 174 of the second gap sublayer 17' The second partial layer 194 and the third gap sublayer 19 ′ may be collectively defined as a second gap substructure surrounding the second bit line 14 .

In some embodiments, the first partial layer 193 of the third gap sublayer 19 ′ is divided into an upper portion 193T above the air gap AG1 and a lower portion 193B surrounding the air gap AG1 . In some embodiments, during operation S19 , a lateral portion of the first partial layer 193 disposed on top of the first partial layer 173 of the second gap sublayer 17B is also removed, and the top of the first partial layer 173 is exposed. In such an embodiment, the first partial layer 193 is divided into two discontinuous portions, wherein the upper portion 193T and the lower portion 193B are separated, as shown in FIG. 13 . In other embodiments, due to the greater thickness of the third gap sublayer 19', the top of the second gap sublayer 17B is completely covered by the vertical portion of the third gap sublayer 19', which results in the upper portion 193T completely covering the first portion Layer 173 on top. In such an embodiment, first partial layer 193 is a continuous, stepped layer in which upper portion 193T and lower portion 193B are connected.

Also, in some embodiments, the second partial layer 194 of the third gap sub-layer 19 ′ is divided into an upper portion 194T above the air gap AG2 and a lower portion 194B surrounding the air gap AG2 . In some embodiments, during operation S19, lateral portions of the second partial layer 194 disposed over the top of the second partial layer 174 are also removed, and the top of the second partial layer 174 is exposed. In such an embodiment, the second sub-layer 194 is divided into two discontinuous portions, wherein the upper portion 194T and the lower portion 194B are separated, as shown in FIG. 13 . In other embodiments, due to the greater thickness of the third gap sub-layer 19', the top of the second gap sub-layer 17B is completely covered by the vertical portion of the third gap sub-layer 19', which results in the upper portion 194T being completely covered in the second gap sub-layer 17B. Partial layer 174 on top. In such an embodiment, the second sub-layer 194 is a continuous, stepped layer with the upper portion 194T connected to the lower portion 194B.

In some embodiments, the thickness of the first gap substructure above the air gap AG1 is substantially equal to the total thickness of the first gap sublayer 15 ′ and the third gap sublayer 19 ′. In some embodiments, the thickness of the second gap substructure at the air gap AG1 is substantially equal to the thickness of the first gap sublayer 15', The total thickness of the sacrificial layer SA1, the second spacer sublayer 17' and the third spacer sublayer 19'. The air gap AG1 and the first partial layer 173 of the second gap sublayer 17' only surround the lower part 13B of the first bitline 13, so that the first gap sublayer structure tapers from the substrate 11 to the top of the first bitline 13 . Likewise, in some embodiments, the thickness of the second gap substructure above the air gap AG2 is substantially equal to the total thickness of the first gap sublayer 15 ′ and the third gap sublayer 19 ′. In some embodiments, the thickness of the second gap substructure at the air gap AG2 is substantially equal to the total thickness of the first gap sublayer 15 ′, the sacrificial layer SA1 , the second gap sublayer 17 ′, and the third gap sublayer 19 ′. thickness. The air gap AG2 and the second partial layer 174 of the second gap sublayer 17' only surround the lower part 14B of the second bitline 14, so that the second gap sublayer structure gradually changes from the substrate 11 to the top of the second bitline 14. thin.

In some embodiments, a single etch operation is performed to form the first spacer sublayer 15', the dielectric layer 16', the second spacer sublayer 17', and the third spacer sublayer 19'. In some embodiments, the first spacer sublayer 15', the dielectric layer 16', the second spacer sublayer 17' and the third spacer sublayer 19' are formed by multiple etching operations. In some embodiments, one or more dry etching operations are performed in operation S19. In some embodiments, the top portion of the second gap sub-layer 17' exposed through the third gap sub-layer 19' is further removed in operation S19. In some embodiments, since the thickness of the third gap sublayer 19/19' is greater than the width of the air gap AG1 or the width of the air gap AG2, the air gap AG1 and the air gap AG2 are still formed by the third gap sublayer during operation S19. 19/19' sealed.

Referring to FIG. 14 to FIG. 15 , illustrating some embodiments of the present disclosure, after operation S19 , the manufacturing method M1 further includes: ( S20 ) forming contacts 20 ′ on the substrate 11 . In some embodiments, a contact 20 ′ is formed between the first bit line 13 and the second bit line 14 . In some embodiments, the contact 20 ′ makes physical contact with the substrate 11 so as to be electrically connected to the substrate 11 .

In some embodiments, the operation S20 of the manufacturing method M1 includes: (S201) forming a contact material layer 20 covering the first bit line 13 and the second bit line 14; and (S202) removing A portion of contact material layer 20 is removed to form contact 20'. In some embodiments, the contact material layer 20 includes doped polysilicon. In some embodiments, blanket deposition is performed to form contact material layer 20 . In some embodiments, an etch back operation is performed to remove portions of contact material layer 20, thereby forming contact 20'.

In some embodiments, as shown in FIG. 15 , the contacts 20 ′ surround the first bit line 13 and the second bit line 14 . In some embodiments, the height H20 ′ of the contact 20 ′ above the substrate 11 is less than the distance D1 between the top of the air gap AG1 and the substrate 11 . In some embodiments, the height H20' of the contact 20' is less than the distance D2 between the top of the air gap AG2 and the base 11. In some embodiments, the distance D1 is substantially equal to the distance D2 because both the distance D1 and the distance D2 are defined by the height HPR1 ′ of the photoresist PR1 ′ and/or the height H17B of the second gap sublayer 17B. In some embodiments, the height H20 ′ of the contact 20 ′ is greater than the height H132 of the metal layer 132 of the first bit line 13 . In some embodiments, the height H20 ′ of the contact 20 ′ is greater than the height H142 of the metal layer 142 of the second bit line 14 . In some embodiments, height H20' is between 20 and 60 nanometers.

16, according to some embodiments of the present disclosure, after operation S20, the manufacturing method M1 further includes: (S21) forming a landing layer 22 on the contact 20', the first bit line 13 and the second bit line 14 . In some embodiments, landing layer 22 includes a metallic component. In some embodiments, landing layer 22 includes copper. In some embodiments, blanket deposition is performed to form landing layer 22 . In some embodiments, the landing layer 22 covers the top of the first bit line 13 and the top of the second bit line 14 .

According to some embodiments of the present disclosure, before forming the landing layer 22 , the manufacturing method M1 further includes: forming an adhesion layer (not shown) on the contact 20 ′, the first bit line 13 and the second bit line 14 . In some embodiments, the purpose of the adhesion layer is to increase the adhesion between the landing pads (to be formed later in the process) and the bit lines (e.g., the first bit line 13 and the second bit line 14) force to prevent peeling of the landing pad. In some embodiments, the adhesive layer is continuously and conformally disposed over the contact 20 ′, the first interstitial substructure, the second interstitial substructure, the first bitline 13 and the second bitline 14 . In some embodiments, the adhesive layer is patterned to form a landing pad. In some embodiments, the adhesive layer is completely overlapped by the landing pad after the patterning operation.

Referring to FIG. 17 to FIG. 19 , illustrating some embodiments of the present disclosure, after operation S21, the manufacturing method M1 further includes: (S22) forming an upper air gap AG3 surrounding the first bit line 13 and surrounding the second bit line 14 The upper air gap AG4. In some embodiments, operation S22 includes: (S221) forming openings in gap substructures surrounding first bit line 13 and second bit line 14, respectively; (S222) sealing the openings to form upper air gap AG3 and upper The air gap AG4; and (S223) exposing the landing layer 22.

Referring to FIG. 17 , according to some embodiments of the present disclosure and operation S221 of the manufacturing method M1 , a first opening OP1 is formed around the first bit line 13 , and a second opening OP2 is formed around the second bit line 14 . In some embodiments, directional dry etching is performed to form the first opening OP1 and the second opening OP2.

In some embodiments, a portion of the landing layer 22 covering the top of the first interstitial substructure is removed to form the first opening OP1. In such an embodiment, a hole is formed through the portion of the landing layer 22 overlying the top of the first interstitial substructure, and the first interstitial substructure is exposed. In some embodiments, a portion of the first interstitial sublayer 15' and/or a portion of the third interstitial sublayer 19' is removed. In some embodiments, the first opening OP1 surrounds the first bit line 13 from a plan view (not shown). In some embodiments, a portion of the first opening OP1 is disposed between the first gap sublayer 15' and the third gap sublayer 19' and surrounds the upper portion 13T of the first bitline 13, wherein the upper portion 13T is defined is the part of the first bit line 13 above the air gap AG1. In some embodiments, the first opening OP1 is bounded by the first gap sublayer 15' and/or the third gap sublayer 19' and The air gap AG1 separates. In some embodiments, the first opening OP1 is in contact with the top of the air gap AG1 (not shown).

In some embodiments, a portion of the landing layer 22 covering the top of the second interstitial substructure is removed to form the second opening OP2. In such an embodiment, a hole is formed through the portion of the landing layer 22 overlying the top of the second interstitial substructure, and the second interstitial substructure is exposed. In some embodiments, a portion of the first interstitial sublayer 15' and/or a portion of the third interstitial sublayer 19' is removed. In some embodiments, the second opening OP2 surrounds the second bit line 14 from a top view (not shown). In some embodiments, a portion of the second opening OP2 is disposed between the first gap sublayer 15' and the third gap sublayer 19' and surrounds the upper portion 14T of the second bitline 14, wherein the upper portion 14T is defined as The portion of the second bit line 14 above the air gap AG2. In some embodiments, the second opening OP2 is separated from the air gap AG2 by a second gap substructure. In some embodiments, the second opening OP2 is in contact with the top of the air gap AG2.

Referring to FIG. 18 , according to some embodiments of the present disclosure and operation S222 of the manufacturing method M1 , a dielectric layer 23 is formed on the landing layer 22 . In some embodiments, dielectric layer 23 is formed by deposition of a nitride layer. The dielectric layer 23 fills a part of the first opening OP1 and a part of the second opening OP2 to form air gaps AG3 and air gaps AG4 . In some embodiments, the air gap AG3 surrounds the upper portion 13T of the first bit line 13 and the air gap AG4 surrounds the upper portion 14T of the second bit line 14 . In some embodiments, air gap AG3 extends from the top of the first gap substructure to air gap AG1 , and air gap AG4 extends from the top of the second gap substructure to air gap AG2 . In some embodiments, the dielectric layer 23 is in physical contact with the first interstitial substructure and/or the second interstitial substructure. More specifically, in such embodiments, the dielectric layer 23 is in physical contact with the first interstitial sublayer 15' and/or the third interstitial sublayer 19'. Thus, in such embodiments, the top of air gap AG3 is lower than the top of first bit line 13, and/or the top of air gap AG4 is lower than the top of second bit line 14. top. In some embodiments, the dielectric layer 23 is separated from the first interstitial substructure and/or the second interstitial substructure. More specifically, in such embodiments, dielectric layer 23 is associated with first gap sub-layer 15 ′ and third gap sub-layer 19 around first bit line 13 and/or around second bit line 14 'separate. Thus, in such embodiments, the top of air gap AG3 is higher than the top of first bit line 13 , and/or the top of air gap AG4 is higher than the top of second bit line 14 . In some embodiments, the size of air gap AG3 is smaller than the size of air gap AG1 . In some embodiments, the size of air gap AG4 is smaller than the size of air gap AG2. In some embodiments, the width of the air gap AG3 is smaller than the width of the air gap AG1 . In some embodiments, the width of air gap AG4 is smaller than the width of air gap AG2. In some embodiments, the length of the air gap AG3 is less than the height H1 of the air gap AG1 . In some embodiments, the length of the air gap AG4 is less than the height H2 of the air gap AG2.

Referring to FIG. 19 , according to some embodiments of the present disclosure, and step S223 of operation S22 of the manufacturing method M1 , a portion of the dielectric layer 23 is removed to expose the landing layer 22 . In some embodiments, planarization is performed to remove the portion of dielectric layer 23 . In some embodiments, planarization is stopped when the landing layer 22 is exposed. In some embodiments, at least a portion of the dielectric layer 23 remains in the first opening OP1 and the second opening OP2 to keep the air gaps AG3 and AG4 sealed.

Referring to FIG. 20 , according to some embodiments of the present disclosure, after step S223 of operation S22 , the manufacturing method M1 further includes: ( S23 ) forming a landing pad 22 ′. In some embodiments, a patterning operation is performed to remove portions of the landing layer 22, thereby forming one or more landing pads 22'. For ease of illustration, only the landing pad 22 ′ electrically connected to the contact 20 ′ between the first bit line 13 and the second bit line 14 is described in the following description. In some embodiments, landing pad 22' conforms to contact 20' and an adjacent bit line (eg, second bit line 14). In some embodiments, the adhesion layer (not shown) is patterned simultaneously with the landing layer 22 . In some embodiments, the adhesive layer is on the landing pad 22' and contact 20 ′, and between landing pad 22 ′ and second bit line 14 are configured conformally. In some embodiments, landing pad 22' has rounded corners as a result of the etching operation.

According to some embodiments of the present disclosure, operation S23 is performed before operation S22. In some embodiments, the air gaps AG3 and AG4 are formed at different positions of the first gap substructure and the second gap substructure due to the different order in which operations S22 and S23 are performed. In some embodiments, landing pad 22 ′ and dielectric layer 23 have different configurations than those of the embodiment of semiconductor structure 2 shown in FIG. 20 .

21 to 23 are cross-sectional views illustrating different fabrication stages of the fabrication method M1 of the semiconductor structure 3 . As noted above, in some embodiments, the native dielectric layer is conformally formed with the first interstitial sublayer 15 and the second interstitial sublayer 17B. According to some embodiments of the present disclosure, after operation S16 , a dielectric layer 18 a is formed on the exposed surfaces of the first gap sublayer 15 and the second gap sublayer 17B. According to some embodiments of the present disclosure, after removing the photoresist PR1 ′, a dielectric layer 18 b is formed on the exposed surface of the second spacer sub-layer 17B. In some embodiments, the native dielectric layer 18b is formed on the surface of the second gap sub-layer 17B that is in contact with the photoresist PR1 ′. In some embodiments, dielectric layer 18 a and dielectric layer 18 b are collectively defined as dielectric layer 18 . In some embodiments, the dielectric layer 18 is formed conformally to the contours of the exposed surfaces of the first spacer sub-layer 15 and the second spacer sub-layer 17B. In some embodiments, the dielectric layer 18 is disposed between the first gap sub-layer 15 and the second gap sub-layer 17B, wherein the removed portion of the sacrificial layer SA1 has been disposed. In some embodiments, the dielectric layer 18 is naturally formed when the first spacer sublayer 15 and the second spacer sublayer 17B are exposed to the environment. In some embodiments, dielectric layer 18 is a native oxide layer. The fabrication method M1 as described above is performed on the intermediate structure in FIG. 22 to form the semiconductor structure 3 shown in FIG. 23 . The detailed description will not be repeated here.

24 to 25 are cross-sectional views illustrating a method of manufacturing a semiconductor structure 4 Different stages of preparation of M1. As mentioned above, in some embodiments, the top portion of the second gap sublayer 17' exposed through the third gap sublayer 19' is also removed during operation S19. In some embodiments, a single directional dry etch is performed in operation S19. In some embodiments, the single directional dry etch stops after substrate 11 is exposed. Instead of the intermediate structure of FIG. 13 , the top portion of the second gap sublayer 17 ′, the top portion of the lower portion 193B exposed through the upper portions 193T and 194T, and the top portion of the lower portion 194B are simultaneously removed by directional dry etching. In some embodiments, the top of lower portion 193B and/or the top of lower portion 194B is lower than the top of second gap sublayer 17 ′. In some embodiments, the second gap sublayer 17' has a stepped configuration as shown in FIG. 23 . After the manufacturing method M1 as described above, as shown in FIG. 24 , after operation S20 , a contact 20 ′ having a T-shaped configuration is formed between the first bit line 13 and the second bit line 14 . After operation 20, other operations of the manufacturing method M1 are sequentially performed on the intermediate structure in FIG. 24 to form a semiconductor structure 4 as shown in FIG. 25 . The detailed description will not be repeated here.

26 to 28 are cross-sectional views illustrating different fabrication stages of the fabrication method M1 of the semiconductor structure 5 . Referring to FIG. 26 , in some embodiments, the thickness of the third gap sublayer 19 is greater than or equal to the total thickness of the dielectric layer 16 and the second gap sublayer 17B. In such an embodiment, the top of the second gap sublayer 17B may be completely covered by the vertical portion of the third gap sublayer 19 . During operation S19 , the entire vertical portion of the second gap sublayer 17B is protected by the vertical portion of the third gap sublayer 19 . Referring to Figure 27, in such an embodiment, a portion of the lower portion 193B is protected by the upper portion 193T. In such an embodiment, a portion of the lower portion 194B is protected by the upper portion 194T. Thus, as shown in FIG. 26, the first partial layer 193 is a continuous, stepped layer in which an upper portion 193T is connected to a lower portion 193B. The second partial layer 194 is a continuous and stepped layer with the upper part 194T connected to the lower part 194B. The fabrication method M1 as described above is performed on the intermediate structure in FIG. 27 to form the semiconductor structure 5 shown in FIG. 28 . As mentioned above in the preparation of semiconductor structure 2 As noted, in some embodiments, dielectric layer 23 seals air gaps AG3 and AG4 and is separated from first gap sublayer 15' and/or third gap sublayer 19'. In such an embodiment, the top of air gap AG3 is above the top of first bit line 13 , and/or the top of air gap AG4 is above the top of second bit line 14 . Other elements of the semiconductor structure 5 are similar to those of the semiconductor structure 2 , and will not be described in detail again here.

29 to 32 are cross-sectional views illustrating different fabrication stages of the fabrication method M1 of the semiconductor structure 6 , wherein operation S23 is performed before operation S22 . As mentioned above, in some embodiments, operation S23 is performed before operation S22 to provide different configurations of landing pad 22 ′ and dielectric layer 23 .

Referring to FIG. 29 , which illustrates some embodiments of the present disclosure, an intermediate structure is formed according to operations S11 to S21 described above. In some embodiments, operation S23 is performed on the intermediate structure of FIG. 29 .

Referring to FIG. 30 , according to some embodiments of the present disclosure, operation S23 is performed to form a landing pad 22 ′. In some embodiments, patterning is performed on landing layer 22 to form landing pad 22'. In some embodiments, an etching operation is performed on landing layer 22 to form landing pad 22'. In some embodiments, portions of landing layer 22 are removed by an etching operation. In some embodiments, a plurality of grooves RC are formed between the landing pads 22'. For ease of illustration, in the following description, only the landing pad 22' electrically connected to the contact 20' between the first bit line 13 and the second bit line 14 is described, and only the first bit line Recess RC between line 13 and second bit line 14. In some embodiments, the first partial layer 153 of the first gap sublayer 15 ′ and the upper portion 193T of the first partial layer 193 are exposed. In some embodiments, a portion of the first gap substructure surrounding a portion of the upper portion 13T of the first bitline 13 is also removed by the etching operation. In some embodiments, the second partial layer 154 of the first interstitial sublayer 15 ′ and the upper portion 194T of the second partial layer 194 are exposed. in some real In an embodiment, a portion of the second gap substructure surrounding a portion of the upper portion 14T of the second bitline 14 is also removed by the etching operation. In some embodiments, a portion of the upper portion 13T of the first bitline 13 is further removed by the etching operation. In some embodiments, a portion of the upper portion 14T of the second bitline 14 is further removed by the etching operation. In some embodiments, prior to the etching operation, a patterned mask is formed over at least a portion of the first bitline 13 and at least a portion of the first gap substructure. In some embodiments, a pattern mask is formed over at least a portion of the second bitline 14 and at least a portion of the second gap substructure prior to the etching operation. In some embodiments, a directional dry etch is performed to form landing pads 22'.

Referring to FIG. 31 to FIG. 32 , illustrating some embodiments of the present disclosure, operation S22 is performed after operation S23 on the intermediate structure of FIG. 28 . A first opening OP1 is formed adjacent to the first bit line 13 , and a second opening OP2 is formed adjacent to the second bit line 14 . In some embodiments, directional dry etching is performed to form the first opening OP1 and the second opening OP2.

Referring to FIG. 31 , according to some embodiments of the present disclosure, a first opening OP1 and a second opening OP2 are formed. In some embodiments, a portion of the first partial layer 153 of the first interstitial sublayer 15' and an upper portion 193T of the third interstitial sublayer 19' are removed. In some embodiments, the first opening OP1 is disposed adjacent to the upper portion 13T of the first bit line 13 and extends from a midpoint between the bottom and the top of the upper portion 13T of the first bit line 13 . In some embodiments, the second opening OP2 is disposed adjacent to the upper portion 14T of the second bit line 14 and extends from a midpoint between the bottom and the top of the upper portion 14T of the second bit line 14 . In some embodiments, a portion of the first opening OP1 is disposed between the first partial layer 153 of the first gap sub-layer 15 ′ and the upper portion 193T of the third gap sub-layer 19 ′. In some embodiments, the first opening OP1 is connected to the top of the air gap AG1. In some embodiments, a portion of the second opening OP2 is disposed between the second partial layer 154 of the first gap sub-layer 15' and the upper portion 194T of the third gap sub-layer 19'. In some embodiments, the second opening OP2 and the air gap AG2 connected at the top.

Referring to FIG. 32 , according to some embodiments of the present disclosure, operation 22 is performed on the intermediate structure of FIG. 31 to form a semiconductor structure 6 . In some embodiments, dielectric layer 23 is formed on landing pad 22' of FIG. 31 . In some embodiments, a dielectric layer 23 is formed on the landing pad 22 ′, the first bit line 13 and the second bit line 14 . In some embodiments, the dielectric layer 23 fills the groove and is disposed on top of the first bit line 13 and on top of the second bit line 14 . In some embodiments, the portion of dielectric layer 23 in recess RC seals air gap AG3 and air gap AG4. In some embodiments, blanket deposition is performed to form dielectric layer 23 , and the top surface of dielectric layer 23 is non-planar. In some embodiments, the profile of the top surface of the dielectric layer 23 corresponds to the profile of the landing pad 22 ′, the first bit line 13 and the second bit line 14 after operation S23.

One aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes: a base; a bit line structure disposed on the base; a first dielectric layer surrounding the bit line structure; a second dielectric layer surrounding the first dielectric a lower portion of the layer, wherein the second dielectric layer is separated from the first dielectric layer by the first air gap; and a third dielectric layer surrounding an upper portion of the first dielectric layer And seal the first air gap.

Another aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes: a first bit line and a second gap substructure. The first bit line is configured on a substrate. The second gap substructure surrounds the first bit line and includes a first dielectric layer and a first air gap sealed by the first dielectric layer. The first air gap surrounds a lower portion of the first bit line.

Another aspect of the present disclosure provides a method for fabricating a semiconductor structure. The preparation method includes: forming a bit line on a substrate; forming a first gap sublayer on the bit line and conforming to it; forming a sacrificial layer on the first gap sublayer and conforming to it ; in the sacrificial forming a second gap sublayer on the sacrificial layer and conforming thereto; forming a mask layer covering a lower portion of the second gap sublayer; removing an upper portion of the second gap sublayer; removing the sacrificial layer; And a third gap sublayer is formed on the first gap sublayer and the second gap sublayer, thereby forming a first air gap surrounded by the lower portion of the second gap sublayer.

In conclusion, the present application discloses a semiconductor structure and a method for preparing the semiconductor structure. The semiconductor structure includes an air gap surrounding the lower portion of the bitline, so that parasitic effects between the metal layer of the bitline and the contacts can be minimized. The semiconductor structure may further include an air gap surrounding the upper portion of the bit line and also minimize parasitic effects between the landing pad and the bit line.

Although the present disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions and substitutions can be made hereto without departing from the spirit and scope of the present disclosure as defined by the disclosed claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the disclosure is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that they can use existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such processes, machinery, manufacture, material composition, means, methods, or steps are included in the scope of the patent disclosure of this disclosure.

1: Semiconductor structure

11: Base

13: The first bit line

14: Second bit line

15': First gap sublayer

16': dielectric layer

17': Second gap sublayer

19': Third gap sublayer

20': Contact

22': Landing Pad

23: Dielectric layer

131: Nitride layer

132: metal layer

133: mask layer

141: Nitride layer

142: metal layer

143: mask layer

153: The first part of the layer

154: The second part of the layer

163: The first partial layer

164:Second part layer

173: The first partial layer

174: The second part of the layer

193: The first partial layer

193B: lower part

193T: the upper part

194: The second part of the layer

194B: lower part

194T: the upper part

AG1: air gap

AG2: air gap

AG3: air gap

AG4: air gap

D1: distance

D2: distance

H132: Height

H142: Height

H17B: Height

H20': Height

SA1: sacrificial layer

X: direction

Y: Direction

Claims (20)

A method for preparing a semiconductor structure, comprising: forming a bit line on a substrate; forming a first gap sublayer on the bit line and conforming thereto; forming a sacrificial layer on the first gap sublayer and conforming thereto; forming a second gap sublayer on the sacrificial layer and conforming thereto; forming a mask layer covering a lower portion of the second gap sublayer; removing an upper portion of the second gap sublayer ; removing the sacrificial layer; and forming a third gap sublayer on the first gap sublayer and the second gap sublayer, thereby forming a first air gap surrounded by the lower portion of the second gap sublayer . The preparation method according to claim 1, wherein the first gap sublayer, the first air gap, the second gap sublayer and the third gap sublayer are jointly defined as a gap substructure, and the gap sublayer The structures taper from the base. The manufacturing method according to claim 2, wherein the thickness of the gap substructure on the first air gap is substantially equal to the total thickness of the first gap sublayer and the third gap sublayer. The preparation method as claimed in item 2, wherein the thickness of the gap substructure located at the lower part of the second gap sublayer is substantially equal to the thickness of the first gap sublayer, the sacrificial layer, the second gap sublayer and the first gap sublayer The total thickness of the three interstitial sublayers. The method of claim 1, wherein the boundary between the lower portion of the second gap sublayer and the upper portion of the second gap sublayer is defined by the mask layer. The preparation method as claimed in item 1, wherein the height of the first air gap is defined by the mask layer. The manufacturing method as claimed in claim 1, wherein a wet etching is performed to remove the sacrificial layer disposed between the first gap sublayer and the lower portion of the second gap sublayer. The manufacturing method according to claim 1, further comprising: after the upper portion of the second gap sublayer is removed, conformally forming a native dielectric layer. The preparation method according to claim 1, further comprising: removing a part of the first gap sublayer and a part of the third gap sublayer above the first air gap; A dielectric layer is formed on the third gap sublayer, thereby forming a second air gap. The manufacturing method as claimed in claim 9, wherein a directional dry etching is performed to remove the portion of the first gap sublayer and the portion of the third gap sublayer. The preparation method as claimed in item 1, further comprising: exposing the substrate through the first gap sublayer, the second gap sublayer and the third gap sublayer; and forming a contact to surround the first gas gap, wherein the distance between the top of the first air gap and the base is greater than the distance between the top of the contact and the base. A method of fabricating a semiconductor structure, comprising: forming a first bit line on a substrate; and forming a first gap substructure to surround the first bit line, the first gap substructure including a first dielectric dielectric layer and a first air gap sealed by the first dielectric layer; wherein the first air gap surrounds the lower part of the first bit line. The manufacturing method as claimed in claim 12, wherein the distance between the top of the first air gap and the substrate is greater than the distance between the top of a metal layer of the first bit line and the substrate. The manufacturing method as claimed in item 12, further comprising: forming a contact surrounding the first gap substructure, wherein the distance between the top of the first air gap and the substrate is greater than or equal to the distance between the top of the contact and the substrate. The distance between the bases. The manufacturing method as claimed in claim 14, further comprising: forming a landing pad on the contact and contacting a part of the first gap substructure, wherein the top of the first air gap is surrounded by the landing pad. The manufacturing method according to claim 12, further comprising: forming a second bit line on the substrate adjacent to the first bit line; and forming a second gap surrounding the second bit line The substructure includes a second dielectric layer and a second air gap sealed by the second dielectric layer. The manufacturing method as claimed in item 16, further comprising: forming a contact between the first bit line and the second bit line, wherein the distance between the top of the second air gap and the substrate is greater than The distance between the top of the contact and the base. The manufacturing method as claimed in claim 16, wherein forming the second gap substructure further comprises: forming a third air gap above the first dielectric layer and the first air gap. The preparation method according to claim 18, wherein the third air gap is separated from the first air gap, and the size of the third air gap is smaller than the size of the first air gap. The manufacturing method according to claim 18, wherein forming the first gap substructure further comprises: forming a native dielectric in the first dielectric layer between the first air gap and the third air gap stratum.

Images