TWI798976B - Direct memory access circuit, operation method thereof, and method of generating memory access command - Google Patents

Abstract

A direct memory access (DMA) circuit, its operation method, and a method of generating memory access commands are provided. The DMA circuit is used to access a memory according to a command and includes a first-in first-out (FIFO) register, a first channel controller, and a second channel controller. The operation method of the DMA circuit includes: decoding the command to obtain a first channel code and a second channel code, the first channel code corresponding to the first channel controller, and the second channel code corresponding to the second channel controller; obtaining a state of the first channel controller from the FIFO register according to the first channel code; selecting the second channel controller according to the second channel code; and controlling the second channel controller according to the state.

Description

Direct memory access circuit, its operating method, and method for generating memory access instructions

The present invention relates to memory access, in particular to a direct memory access circuit, its operating method, and a method for generating memory access instructions.

When the electronic device calculates the formula (1) below, the detailed steps are: (i) calculate C11 (that is, formula (1a)); (ii) store the data C11 into the target location of the memory; (iii) from the memory Read data C11 at the target position of ; and (iv) calculate E11 (ie, formula (1b)).

(1)

(1)

(1a)

(1a)

(1b)

(1b)

(2)

(2)

」）不需要等到算式（1）完成後才開始進行。更明確地說，因為讀取資料A12不影響算式（1）的計算，所以計算機或電子裝置較佳地可以於執行算式（1）的乘法運算（即，「

」）時便同時從記憶體讀取資料A12，以提高運算效能。 When the conventional computer or electronic device calculates the formula (1) and the formula (2), it adopts the method of synchronizing the operators as a whole to ensure the correct result. The overall synchronization of operators means that the computer or electronic device will first complete the calculation of formula (1) (that is, after obtaining the result E11), and then perform the calculation of formula (2). However, the multiplication operation of equation (2) (ie, "

”) does not need to wait until formula (1) is completed before starting. More specifically, since the reading data A12 does not affect the calculation of formula (1), the computer or electronic device is preferably able to perform the multiplication operation of formula (1) (ie, "

”), the data A12 is read from the memory at the same time to improve the computing performance.

However, some data (such as the data C11 in formulas (1a) and (1b)) cannot be accessed or modified at any time (that is, the data C11 must be stored before it can be read), otherwise it will lead to erroneous Calculation results. In other words, the memory space storing the data cannot be read or written at any time. Therefore, there is a need for a method for generating a memory access command, a related direct memory access (DMA) circuit and an operation method thereof, so as to improve the performance of a computer or an electronic device.

In view of the deficiencies of the prior art, an object of the present invention is to provide a direct memory access circuit, its operating method, and a method for generating memory access instructions, so as to improve the deficiencies of the prior art.

One embodiment of the present invention provides a direct memory access circuit for accessing a memory according to an instruction, including: a first channel controller, a second channel controller, a decoder, a first-in-first-out register and a controller. The first and second channel controllers are used to access the memory. The decoder is used to decode the instruction to obtain a first channel code and a second channel code, the first channel code corresponds to the first channel controller, and the second channel code corresponds to the second channel controller. The FIFO register is used to store a state of the first channel controller. The controller is coupled to the decoder and the FIFO register, and is used to perform the following steps: obtain the state from the FIFO register according to the first channel code; select the second channel code according to the second channel code. a channel controller; and controlling the second channel controller according to the state.

Another embodiment of the present invention provides a method of operating a direct memory access circuit for accessing a memory according to a command, the direct memory access circuit includes a first-in-first-out buffer memory, a first channel controller and a second channel controller, the method includes: decoding the instruction to obtain a first channel code and a second channel code, wherein the first channel code corresponds to the first channel code a channel controller, and the second channel code corresponds to the second channel controller; obtain a state of the first channel controller from the FIFO register according to the first channel code; according to the second channel code selecting the second channel controller; and controlling the second channel controller according to the state.

Another embodiment of the present invention provides a method for generating a memory access command, wherein a memory block is accessed by a continuous first command and a second command, and the second command follows the second command. After a command, the method includes: when one of the first command and the second command is a read command and the other is a write command, using a channel code of the first command itself as the A parameter for the second command. The own channel code corresponds to a channel controller of a direct memory access circuit, and the channel controller is used to execute the first instruction.

The invention controls the memory access according to the dependency of consecutive memory access instructions. Compared with the prior art, the electronic device or the chip using the direct memory access circuit of the present invention can perform calculation in a more efficient manner and improve the calculation performance.

The characteristics, implementation and effects of the present invention are described in detail as follows with reference to the drawings.

The technical terms in the following explanations refer to the customary terms in this technical field. If some terms are explained or defined in this specification, the explanations of these terms shall be based on the descriptions or definitions in this specification.

The disclosure of the present invention includes a direct memory access circuit, its operating method, and a method for generating memory access instructions. Since some of the components included in the direct memory access circuit of the present invention may be known components individually, on the premise of not affecting the full disclosure and implementability of the device invention, the details of the known components are described below will be omitted.

In the product development process, product development tools (such as computers) analyze data for a computing model (such as a neural network model) and hardware such as an intelligent processing unit (IPU) or direct memory access. Dependencies, and then generate memory access instructions according to the dependencies of the data. The product is, for example, hardware with computing capabilities such as electronic devices and chips, and the product uses direct memory access circuits to control access to memory (including but not limited to cache memory or random access memory) ( read or write). More specifically, software is used to divide the data to be calculated by the calculation model into multiple data pages, each data page is, for example, 4KB in size, and a memory (cache memory or random access memory) is correspondingly allocated Divide into multiple memory blocks, the size of each memory block corresponds to the size of the data page, and use product development tools to track the data dependencies of each data page. In one embodiment, each data page is written into or read from a certain memory block through a corresponding access command, and the product development tool can analyze a certain memory block ( Hereinafter referred to as a target memory block, it is used to store a plurality of access commands of a target data page) to track data dependencies of a data page. The product development tool analyzes two consecutive instructions (the first instruction and the second instruction) that operate on the target memory block, the second instruction is immediately after the first instruction, and the first instruction is the previous instruction of the second instruction ) to determine whether to add a data dependency message (or a data synchronization message), and generate a memory access command for the target data page accordingly. The detailed process is shown in FIG. 1 and includes the following steps.

Step S110: Obtain consecutive first instructions and second instructions, the first instruction and the second instruction access the target memory block (that is, the first instruction and the second instruction read the target data page from the target memory block, Write the target data page into the target memory block, or update the target data page in the target memory block (equivalent to a write operation)). Specifically, the product development tool can obtain consecutive first instructions and second instructions for an access operation to a target data page in a certain operation of the product, and the operation first uses the first instruction to access the target memory block, and then use the second instruction to access the target memory block, and the first instruction and the second instruction do not contain other instructions for accessing the target memory block.

It should be noted that a command (ie, the above-mentioned first command or second command) contains or carries a self-channel code, and the self-channel code corresponds to a channel controller of a direct memory access circuit. In other words, when the direct memory access circuit executes a read (or write) command, it will use the read (or write) command's own channel code to designate a channel controller to perform the read (or write) operation .

Step S120: The product development tool determines whether the first command and the second command include a read command and a write command. If yes (that is, one of the first command and the second command is a read command and the other is a write command), it means that there is a data dependency between the first command and the second command, and the product development tool executes Step S130; otherwise (ie, the first command and the second command are both read commands or both are write commands), the product development tool executes step S140.

Step S130: The product development tool uses the own channel code of the first command as a parameter of the second command (ie, the dependent channel code described below), and this parameter is the data dependency message. Please refer to FIG. 2, which shows an embodiment of the command format of the present invention. The format of FIG. 2 is for example only, and is not intended to limit the present invention. In the example in Figure 2, a command can contain five parameters: "read/write", "own channel code", "dependent channel code", "address" and "write content", the first command is write (with "W" indicates) command, the second command is a read (indicated by "R") command, and the dependent channel code "FF" of the first command is a default value (it can also be "0" or other values). As shown in FIG. 2 , both the "self channel code" parameter of the first command and the "dependent channel code" parameter of the second command are "ID1", indicating that the second command is dependent on the first command. And "FF" means that the first command does not depend on its previous command.

Step S140: The product development tool sets the dependent channel code of the second command as a default value. Please refer to FIG. 3, which shows another embodiment of the command format of the present invention. The format of FIG. 3 is for example only, and is not intended to limit the present invention. Because the first command and the second command are both read commands in the example in FIG. instruction. Please note that when both the first command and the second command are write commands, the dependent channel code of the second command is also the default value “FF”.

The product development tool continues the process of FIG. 1 to scan the operation's access commands to each data page to determine whether each command is dependent on its previous command. In some embodiments, the process of FIG. 1 is implemented by software; in other words, the product development tool completes the process of FIG. 1 by executing program codes or program instructions.

The following will explain how the DMA circuit operates according to the "own channel code" and the "dependent channel code".

FIG. 4 is a functional block diagram of an embodiment of the direct memory access circuit of the present invention. The components of FIG. 4 are part of the aforementioned product, including processor 10, direct memory access circuit 20, and memory 25 (including but not limited to cache memory 30 and random access memory 40). The processor 10 accesses the cache memory 30 and the random access memory 40 through the direct memory access circuit 20 . The direct memory access circuit 20 includes a decoder 210, a FIFO register 220, a controller 230, a bus 250, and m channel controllers 260 (260_1, 260_2, ..., 260_m, m is an integer greater than 1) and busbar 270 . The channel codes of the m channel controllers 260 are ID1, ID2, . . . and IDm, respectively.

When the processor 10 intends to write a target data page into the memory 25 or read it from the memory 25 , the processor 10 sends a target command to the DMA circuit 20 . The decoder 210 decodes the target command sent by the processor 10 to obtain all parameters of the target command, and transmits the parameters to the controller 230 . The FIFO register 220 stores the states of the m channel controllers 260 . The controller 230 is coupled to the decoder 210 and the FIFO register 220, and is used for controlling the corresponding channel controller 260 to execute the task of the target command according to its own channel code of the target command. In addition to accessing the cache memory 30 or the random access memory 40 , the channel controller 260 also updates its own state in the FIFO register 220 . Please refer to FIG. 5 . FIG. 5 is an example of a state table 500 of the channel controller 260 , and the state table 500 is stored in the FIFO register 220 . "BUSY" means that the channel controller is in a busy state (such as accessing the cache memory 30 or the random access memory 40 ), and "IDLE" means that the channel controller is in an idle state.

FIG. 6 is a flowchart of an embodiment of an operating method of a direct memory access circuit. The operation of the DMA circuit 20 will be described below with reference to FIG. 6 .

Step S610: The DMA circuit 20 receives the target command from the processor 10, and the target command carries a first channel code (ie, the dependent channel code) and a second channel code (ie, its own channel code). For example, when the target command is the second command in FIG. 2 , the first channel code is "ID1", and the second channel code is "ID2".

Step S620: The decoder 210 decodes the target command to obtain the first channel code, the second channel code and other parameters of the target command. The processor 10 encodes the target instruction in an encoding manner, and the decoder 210 decodes the target instruction in a decoding manner corresponding to the encoding manner. The decoding operation is well known to those skilled in the art, so details will not be repeated here.

Step S630: The controller 230 selects a second channel controller according to the second channel code. Continuing from the above example (that is, the target command is the second command in FIG. 2 ), the controller 230 selects the second channel controller 260_2 corresponding to the second channel code “ID2”.

Step S640: The controller 230 determines whether the first channel code is a preset value. If the first channel code is a preset value (representing that the target command is not dependent on the previous command, that is, the target command and the previous command are the same operation (both are read operations or both are write operations)), then the controller 230 Execute step S650. If the first channel code is not a preset value (representing that the target instruction is dependent on the previous instruction, that is, the target instruction is not the same operation as the previous instruction (one is a read operation, the other is a write operation)), then the control The controller 230 executes steps S660 and S670. Here, the previous instruction and the target instruction are consecutive instructions for operating the target memory block, that is, for the target memory block, the target instruction is immediately after the previous instruction. However, for the processor 10 and the controller 230, there may be other instructions between the previous instruction and the target instruction, and the or these other instructions do not access the target memory block.

Step S650: The controller 230 controls the second channel controller 260_2 to access the memory 25, that is, the channel controller 260_2 executes the task of the target instruction.

Step S660: The controller 230 acquires a state of the first channel controller from the FIFO register 220 according to the first channel code. Continuing from the above example (that is, the target command is the second command in FIG. 2 , and the state of the channel controller 260 is shown in FIG. 5 ), the controller 230 uses the first channel code "ID1" as an index to query in the state table 500 The status of the first channel controller 260_1 corresponding to “ID1” is busy.

Step S670: The controller 230 controls the second channel controller 260_2 according to the state of the first channel controller 260_1. Details of step S670 are described in detail below with FIG. 7 .

Please refer to FIG. 7 . FIG. 7 shows a flowchart of an embodiment of step S670 , including the following steps.

Step S710: The controller 230 determines whether the state of the first channel controller 260_1 is an idle state. If not, execute step S720, step S730 and step S740; if yes, execute step S750 and step S740.

Step S720: The controller 230 waits for the state of the first channel controller 260_1 to become idle. After any channel controller 260 completes a task (for example, completes a read operation or a write operation), it will change its state in the state table 500 to idle. Conversely, any channel controller 260 will change its status in the status table 500 to busy after receiving the task. In other words, in step S720, the controller 230 waits for the first channel controller 260_1 to complete the current task to ensure that the data is correct.

Step S730 : After the state of the first channel controller 260_1 becomes idle, the controller 230 controls the second channel controller 260_2 to access the memory 25 . Step S730 is the same as step S650.

Step S740: After receiving the task, the second channel controller 260_2 changes its state in the state table 500 to a non-idle state (ie, busy state).

Step S750 : the controller 230 controls the second channel controller 260_2 to access the memory 25 . Step S750 is the same as steps S730 and S650.

FIG. 8 shows a functional block diagram of an embodiment of the channel controller 260 of the present invention. The channel controller 260 includes a finite state machine 262 , a read/write controller 264 and a register set 266 . The register group 266 stores system parameters (including but not limited to bus 250 and bus 270 information, the width of each read/write data, the parameters of the direct memory access circuit 20, the parameters of the random access memory 40 wait). The finite state machine 262 controls the read-write controller 264 to perform read and write operations according to the system parameters and various parameters of the target command stored in the register set 266 . In addition, the finite state machine 262 also switches the state (idle or busy) according to whether the channel controller 260 is executing a task, and updates the corresponding column of the state table 500 stored in the FIFO register 220 .

Those skilled in the art can design the controller 230 according to the above disclosure. In some embodiments, the controller 230 can be realized by circuits or hardware such as a programmable logic device (Programmable Logic Device, PLD); in other embodiments, the controller 230 can execute codes or programs command to complete the above operations.

To sum up, the direct memory access circuit 20 and its operating method of the present invention track its dependencies according to the continuous instructions of each data page, and control the channel controller accordingly, so as to ensure that the direct memory access circuit 20 immediately after the write operation A read operation and a write operation immediately following a read operation will not cause data errors. In this way, electronic devices or chips using the DMA circuit 20 can perform calculations in a more efficient manner. Taking the aforementioned formula (1) and formula (2) as an example, by finding out the dependence of data C11 in formula (1a) and formula (1b) (that is, by specifying the dependent channel code), the present invention can ensure The correct data C11 is obtained when calculating the formula (1b); in this way, compared with the prior art, the operators are synchronized as a whole, and the present invention can calculate the formula (2) in advance. In other words, the present invention can more finely arrange data calculation, so the calculation performance can be improved.

Although the embodiments of the present invention are as described above, these embodiments are not intended to limit the present invention, and those skilled in the art can make changes to the technical characteristics of the present invention according to the explicit or implicit contents of the present invention. All these changes may belong to the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention must be defined by the scope of patent application in this specification.

10: Processor 20: Direct memory access circuit 25: memory 30: Cache memory 40: Random Access Memory 210: decoder 220: FIFO register 230: controller 250,270: busbar 260, 260_2, 260_1, 260_m: channel controller ID1, ID2, IDm: channel code 500: status table 262: Finite state machine 264: read and write controller 266: Register group S110, S120, S130, S140, S610, S620, S630, S640, S650, S660, S670, S710, S720, S730, S740, S750: steps

Fig. 1 is the flowchart of one embodiment of the generation method of memory access instruction of the present invention; Fig. 2 shows an embodiment of the instruction format of the present invention; Fig. 3 shows another embodiment of the instruction format of the present invention; FIG. 4 is a functional block diagram of an embodiment of the direct memory access circuit of the present invention; Figure 5 shows an example of a state table of a channel controller; 6 is a flowchart of an embodiment of an operating method of a direct memory access circuit; Fig. 7 shows the flowchart of one embodiment of step S670; And FIG. 8 shows a functional block diagram of an embodiment of the channel controller of the present invention.

S610, S620, S630, S640, S650, S660, S670: steps

Claims (9)

A direct memory access circuit for accessing a memory according to an instruction, comprising: a first channel controller for accessing the memory; a second channel controller for accessing the memory ; A decoder for decoding the instruction to obtain a first channel code and a second channel code, the first channel code corresponds to the first channel controller, and the second channel code corresponds to the second channel a controller; a FIFO register for storing a state of the first channel controller; and a controller coupled to the decoder and the FIFO register for performing the following steps: according to The first channel code obtains the status from the first-in first-out register; selects the second channel controller according to the second channel code; when the status indicates that the first channel controller is not idle, waits for the second channel controller A channel controller is in an idle state, then controlling the second channel controller to access the memory; and when the status indicates that the first channel controller is in an idle state, controlling the second channel controller to access the memory . The direct memory access circuit of claim 1, wherein the state is a first state, and the first-in-first-out register further stores a second state of the second channel controller, and when the second channel control When the device starts to access the memory, the second channel controller changes the second state to a non-idle state. The direct memory access circuit of claim 1, wherein the state is a first state, and the first-in-first-out register further stores a second state of the second channel controller, and when the second channel control When the device starts to access the memory, the second channel controller changes the second state to a non-idle state. The direct memory access circuit of claim 1, wherein, before receiving the command, the direct memory access circuit receives a previous command, and the previous command is to control the first channel controller to the memory A memory block performs a read operation, and the instruction controls the second channel controller to perform a write operation on the memory block of the memory. An operation method of a direct memory access circuit, the direct memory access circuit is used to access a memory according to an instruction, the direct memory access circuit includes a first-in-first-out temporary register, a first channel control device and a second channel controller, the method includes: decoding the instruction to obtain a first channel code and a second channel code, wherein the first channel code corresponds to the first channel controller, and the second The channel code corresponds to the second channel controller; obtain a state of the first channel controller from the FIFO register according to the first channel code; select the second channel controller according to the second channel code; When the status indicates that the first channel controller is not idle, waiting for the first channel controller to be idle, and then controlling the second channel controller to access the memory; and when the status indicates the first channel When the controller is in an idle state, the second channel controller is controlled to access the memory. As the operation method of claim item 5, wherein, the state is a first state, and the first-in-first-out register further stores a second state of the second channel controller, and the method further includes: when the second channel control When the device starts to access the memory, the second state is changed to a non-idle state. The operation method according to claim 5, wherein, before receiving the command, the direct memory access circuit receives a previous command, and the previous command controls the first channel controller to a memory of the memory The block performs a read operation, and the instruction controls the second channel controller to perform a write operation on the memory block of the memory. A method for generating a memory access instruction, wherein a memory block is accessed by a continuous first instruction and a second instruction, the second instruction immediately following the first instruction, the method comprising: When one of the first command and the second command is a read command and the other is a write command, a channel code of the first command is used as a parameter of the second command; , the own channel code is corresponding to a channel controller of a direct memory access circuit, and the channel controller is used to execute the first instruction. The generating method of claim 8 further includes: when both the first command and the second command are the read command or the write command, setting the parameter of the second command to a default value.

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