TWI796740B - Motor driving system with automatic phase adjustment mechanism - Google Patents

Abstract

A motor driving system with an automatic phase adjustment mechanism is provided. A time difference calculator circuit divides one period of one of Hall signals of three phases of a three-phase motor into N times based on transition time points of the Hall signals of the three phases of the three-phase motor. The time difference calculator circuit defines each of the times as an actual Hall state time. The time difference calculator circuit calculates a difference between each of the actual Hall state times and an ideal commutation time. A phase adjusting circuit compensates the Hall signal according to the differences to generate a compensation signal. A driving circuit drives a bridge circuit connected to the three-phase motor according to the compensation signals.

Description

Motor drive system with automatic phase adjustment mechanism

The invention relates to a motor, in particular to a motor drive system with an automatic phase adjustment mechanism.

Motors play a pivotal role in the development of today's automation technology. Especially when applied to fans, since the motor can drive the fan to rotate to induce airflow, and then achieve the purpose of driving wind and heat dissipation, it is quite suitable for heat dissipation of electronic products in the electronics industry.

However, during the operation of the motor, due to the hysteresis of the Hall element itself and the displacement of the placement of the Hall element, the motor will commutate at an incorrect position, resulting in vibration and noise of the motor.

The technical problem to be solved by the present invention is to provide a motor drive system with an automatic phase adjustment mechanism, which is suitable for three-phase motors. The motor drive system with automatic phase adjustment mechanism includes a hall sensor, an ideal time setting circuit, a time difference calculation circuit, a phase adjustment circuit, a bridge circuit and a drive circuit. The Hall sensor is configured to sense Hall signals of each of the three phases of the three-phase motor. The ideal time setting circuit is connected to each Hall sensor. The ideal time setting circuit configuration is to divide the cycle time of the Hall signal to be compensated by N to divide this The cycle time is divided into N equal parts, where N is an integer value greater than 1, and the time of each equal part is defined as the ideal commutation time. Each ideal commutation time is equal to the other ideal commutation times. The time difference calculating circuit is connected with the ideal time setting circuit. The time difference calculation circuit is configured to divide the cycle time of the Hall signal to be compensated into N equal parts with different time lengths according to the transition time points of the multiple Hall signals of the three phases of the three-phase motor. The time difference calculation circuit is configured to define the time of each equal division of the cycle time of the Hall signal as an actual Hall state time. The multiple actual Hall state times respectively correspond to multiple ideal commutation times based on the timings occurring in the Hall signal. The time difference calculation circuit is configured to calculate the difference between each actual Hall state time and the corresponding ideal commutation time as a commutation time difference. The phase adjustment circuit is configured to compensate the Hall signal according to all the plurality of commutation time differences to generate a compensation signal. The drive circuit is connected to the phase adjustment circuit. The drive circuit is configured to drive the bridge circuit according to the compensation signal.

In one embodiment, the time difference calculation circuit calculates the ideal commutation times corresponding to the actual Hall state time to be compensated in the Hall signal and all the actual Hall state times that occur earlier in the same cycle time The sum is used as the first operand value. The time difference calculation circuit subtracts all actual Hall state times in the same cycle before the actual Hall state time to be compensated from the first calculated value to calculate the second calculated value. The time difference calculation circuit calculates the ratio of the second operation value to the actual Hall state time before the actual Hall state time to be compensated. The phase adjustment circuit compensates the actual Hall state time of the Hall signal according to the ratio.

In an embodiment, the time difference calculation circuit divides each ideal commutation time into M sub-divisions, and the time of each sub-division is defined as a sub-commutation time, wherein M is an integer value not less than 1. The time difference calculating circuit multiplies the M value by the second calculated value to calculate a third calculated value. The time difference calculation circuit divides the third calculated value by the actual Hall state time before the actual Hall state time to be compensated to calculate the compensated radial angle. The phase adjustment circuit compensates the actual Hall state time of the Hall signal according to the compensated radial angle.

In one embodiment, the time difference calculation circuit multiplies the ideal commutation time by a desired radial angle to calculate the fourth operation value. The time difference calculating circuit subtracts the fourth calculated value from the third calculated value to obtain a fifth calculated value. The time difference calculation circuit divides the fifth calculated value by the actual Hall state time before the actual Hall state time to be compensated to calculate a phase adjustment radial angle. The phase adjustment circuit compensates the actual Hall state time of the Hall signal according to the phase adjustment radial angle.

In one embodiment, the first time point of part of the actual Hall state time is aligned with the upper edge of the Hall signal of one of the three phases of the three-phase motor and the end time point is aligned with the three phases of the three-phase motor. The lower edge of the Hall signal in the other phase.

In one embodiment, the beginning time point of part of the actual Hall state time is aligned with the lower edge of the Hall signal of one of the three phases of the three-phase motor and the end time point is aligned with the three phases of the three-phase motor. The upper edge of the Hall signal of the other phase.

As mentioned above, the present invention provides a motor drive system with an automatic phase adjustment mechanism, which can detect the signal detected by the Hall sensor under the hysteresis of the Hall element itself and the offset state of the Hall element. The Hall signal compensates and adjusts the phase, so that the motor commutates at the correct time point, so that the motor can run normally and stably, while greatly reducing vibration and noise.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings related to the present invention. However, the provided drawings are only for reference and description, and are not intended to limit the present invention.

10: Ideal time setting circuit

20: Time difference calculation circuit

30: Phase adjustment circuit

40: Drive circuit

50: load

61~63: Hall sensor

M1: the first upper bridge transistor

M2: The second upper bridge transistor

M3: The third upper bridge transistor

M4: The first lower bridge transistor

M5: Second lower bridge transistor

M6: The third lower bridge transistor

501: three-phase motor

502: bridge circuit

U, V, W: phase

VDD: common voltage

UHS, VHS, WHS: Hall signal

T1~T6: Actual Hall state time

T: ideal commutation time

ASL1~ASL6: phase adjustment radial angle

FIG. 1 is a block diagram of a motor drive system with an automatic phase adjustment mechanism according to an embodiment of the present invention.

2 is a circuit layout diagram of a drive circuit, a bridge circuit, and a motor of a motor drive system with an automatic phase adjustment mechanism according to an embodiment of the present invention.

FIG. 3 is a waveform diagram of a Hall signal of a motor drive system with an automatic phase adjustment mechanism according to an embodiment of the present invention.

FIG. 4 is a waveform diagram of a Hall signal of a motor drive system with an automatic phase adjustment mechanism according to an embodiment of the present invention.

5 is a schematic diagram of the difference between the actual Hall state time and the ideal commutation time of the motor drive system with an automatic phase adjustment mechanism according to an embodiment of the present invention.

FIG. 6 is a graph of the uncompensated Hall signal of the motor drive system with an automatic phase adjustment mechanism according to an embodiment of the present invention.

FIG. 7 is a graph of the compensated Hall signal of the motor drive system with an automatic phase adjustment mechanism according to an embodiment of the present invention.

FIG. 8 is a waveform diagram of a Hall signal of a motor drive system with an automatic phase adjustment mechanism according to an embodiment of the present invention.

The implementation of the present invention is described below through specific specific examples, and those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only for simple illustration, and are not drawn according to the actual size, which is stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention. In addition, the term "or" used herein may include any one or a combination of more of the associated listed items depending on the actual situation.

Please refer to Figures 1 to 4, wherein Figure 1 is a block diagram of a motor drive system with an automatic phase adjustment mechanism according to an embodiment of the present invention; Figure 2 is a motor drive system with an automatic phase adjustment mechanism according to an embodiment of the present invention The circuit layout diagram of the drive circuit, the bridge circuit and the motor of the drive system; Fig. 3 is a waveform diagram of the Hall signal of the motor drive system with an automatic phase adjustment mechanism of the embodiment of the present invention; Fig. 4 is the waveform diagram of the motor drive system of the embodiment of the present invention Waveform diagram of the Hall signal of the motor drive system with automatic phase adjustment mechanism.

The motor drive system with an automatic phase adjustment mechanism in the embodiment of the present invention may include an ideal time setting circuit 10, a time difference calculation circuit 20, a phase adjustment circuit 30, a driving circuit 40, and a plurality of Hall sensors 61 as shown in FIG. 1 ~63.

The Hall sensors 61 - 63 shown in FIG. 2 can be provided in the three-phase motor 501 . The Hall sensors 61 - 63 can sense the respective Hall signals of the three phases U, V, and W of the three-phase motor 501 , such as the Hall signals UHS, VHS, and WHS shown in FIG. 3 .

The ideal time setting circuit 10 can be connected to the Hall sensors 61-63 to receive the three-phase U, V, W Hall signals of the three-phase motor 501 from the Hall sensors 61-63. The ideal time setting circuit 10 can divide a cycle time of any phase of the Hall signal by N to divide the cycle time of the Hall signal into N equal parts, wherein N is an integer value greater than 1. For convenience of description, each equal division time is defined as an ideal commutation time. Each ideal commutation time is as long as the other ideal commutation times.

For example, the ideal time setting circuit 10 can take the starting time point (that is, the time point of the rising edge of this waveform) of a cycle waveform of the U-phase Hall signal UHS shown in FIG. 4 to the end time point of this waveform (that is, One cycle time between the rising edge time points of the next cycle waveform).

The ideal time setting circuit 10 can divide a cycle time of the U-phase Hall signal UHS by 6 (that is, N=6), so as to divide this cycle time of the Hall signal into 6 equal parts, and the time definition of each equal part is the ideal commutation time T, and there are 6 ideal commutation times T in this cycle time.

In practice, N can be other values, and the present invention is not limited to N=6. Furthermore, each or any other period of the Hall signal UHS before or after this period of the U-phase Hall signal UHS can also be divided into N equal parts to compensate for all or part of the equal parts . Similarly, each or any period of the Hall signal of V-phase and W-phase can also be divided into N equal parts, so that all or part of the part for compensation.

As shown in FIG. 1 , the time difference calculation circuit 20 can be connected to the ideal time setting circuit 10 . The time difference calculation circuit 20 can calculate the Hall signals of any one of the three phases of the three-phase motor 501 according to the transition time points (or commutation time points) of the three phases of the three-phase motor 501 respectively. A cycle of the Seoul signal is divided into N equal parts. For the convenience of description, the time of each equal part of the cycle time of the Hall signal is defined as an actual Hall state time. The multiple actual Hall state times respectively correspond to multiple ideal commutation times based on the timings occurring in the Hall signal.

When the hysteresis of the Hall element itself and the offset of the placement of the Hall element or other factors will cause the multiple actual Hall state times divided in the same cycle of the Hall signal, all or at least part of the actual The Hall state time is not as long as the other actual Hall state times. To solve this problem, perform the following compensation work.

The start time point of the actual Hall state time of the Hall signal may be aligned with the upper edge of the Hall signal of one of the three phases of the three-phase motor 501, and the end time point of the actual Hall state time may be aligned with The lower edge of the Hall signal of the other phase of the three phases of the three-phase motor 501 . The start time point of other actual Hall state time in the Hall signal may be aligned with the lower edge of the Hall signal of one of the three phases of the three-phase motor 501 and the end time point may be aligned with the three phases of the three-phase motor 501. The upper edge of the Hall signal of the other phase in the phase.

The time difference calculation circuit 20 as shown in FIG. 1 can take a cycle time of the U-phase Hall signal UHS, and divide this cycle time into six actual Hall state times T1~T6 as shown in FIG. 3 , and the details are as follows .

As shown in FIG. 3 , the start time point of the actual Hall state time T1 is aligned with the time point of the upper edge of one cycle waveform of the U-phase Hall signal UHS of the three-phase motor 501 (that is, the transition from low level to high level). State time point), and the end time point of the actual Hall state time T1 is aligned with the time point of the lower edge of one cycle waveform of the W-phase Hall signal WHS of the three-phase motor 501 (that is, the transition from high level to low level state time point).

As shown in FIG. 3 , the start time point of the actual Hall state time T2 is aligned with the time point of the lower edge of one cycle of the Hall signal WHS of the W-phase of the three-phase motor 501 (that is, the transition from high level to low level). State time point), and the end time point of the actual Hall state time T2 is aligned with the upper edge time point of one cycle waveform of the V-phase Hall signal VHS of the three-phase motor 501 (ie, the transition from low level to high level state time point).

As shown in FIG. 3 , the start time point of the actual Hall state time T3 is aligned with the time point of the upper edge of one cycle waveform of the V-phase Hall signal VHS of the three-phase motor 501 (that is, the transition from low level to high level). state time point), and the end time point of the actual Hall state time T3 is aligned with the time point of the lower edge of one cycle waveform of the U-phase Hall signal UHS of the three-phase motor 501 (that is, the transition from high level to low level state time point).

As shown in FIG. 3 , the start time point of the actual Hall state time T4 is aligned with the time point of the lower edge of one cycle waveform of the U-phase Hall signal UHS of the three-phase motor 501 (that is, the transition from high level to low level). state time point), and the end time point of the actual Hall state time T4 is aligned with the upper edge time point of the next cycle waveform of the W-phase Hall signal WHS of the three-phase motor 501 (that is, the transition from low level to high level transition time).

As shown in FIG. 3 , the start time point of the actual Hall state time T5 is aligned with the upper edge time point of the next cycle waveform of the W-phase Hall signal WHS of the three-phase motor 501 (that is, the transition from low level to high level). Transition time point), and the end time point of the actual Hall state time T5 is aligned with the lower edge time point of the next cycle waveform of the V-phase Hall signal VHS of the three-phase motor 501 (that is, the high level turns to the low level transition time).

As shown in FIG. 3 , the start time point of the actual Hall state time T6 is aligned with the time point of the lower edge of the next cycle waveform of the V-phase Hall signal VHS of the three-phase motor 501 (that is, when the low level turns to high level. Transition time point), and the end time point of the actual Hall state time T6 is aligned with the upper edge time point of the next cycle waveform of the U-phase Hall signal UHS of the three-phase motor 501 (that is, the low level turns to the high level transition time).

It should be understood that in practice, the time difference calculation circuit 20 can divide a period of the Hall signal UHS into more or less equal parts, and N can be any appropriate integer value greater than 1, not limited to 6, or the time difference calculation circuit 20 It is also possible to take a period of the W-phase Hall signal WHS or the V-phase Hall signal VHS and divide it into N equal parts. This embodiment is only for illustration, and the present invention is not limited thereto.

Please refer to FIGS. 1 to 7, wherein FIG. 5 is a schematic diagram of the difference between the actual Hall state time and the ideal commutation time of the motor drive system with an automatic phase adjustment mechanism of the embodiment of the present invention; FIG. 6 is the schematic diagram of the embodiment of the present invention The graph of the uncompensated Hall signal of the motor drive system with the automatic phase adjustment mechanism; FIG. 7 is the graph of the compensated Hall signal of the motor drive system with the automatic phase adjustment mechanism of the embodiment of the present invention.

The time difference calculation circuit 20 shown in FIG. 1 can calculate the difference between the actual Hall state times T1 ˜ T6 and the ideal commutation time T within one cycle of the Hall signal UHS shown in FIG. 4 . For the convenience of description, this difference is defined as the commutation time difference. As shown in Figure 5, due to the difference between the actual Hall state time T1~T6 and the ideal commutation time T, it needs to be compensated.

The phase adjustment circuit 30 can be connected to the time difference calculation circuit 20 . The phase adjustment circuit 30 can compensate each actual Hall state time T1~T6 divided by one cycle time of the Hall signal according to the commutation time difference between each actual Hall state time T1~T6 and the ideal commutation time T , to generate a compensation signal. For example, as shown in Figure 6, the actual Hall state times T1~T6 are divided into N times divided by one cycle of the U-phase Hall signal UHS before compensation. Each of the N times of the signal UHS is equal in length and equal to the ideal commutation time T.

For example, the time difference calculation circuit 20 can calculate the ideal commutation times corresponding to the actual Hall state time to be compensated in the Hall signal and all the actual Hall state times that occur earlier in the same cycle time The sum is used as the first operand value. Next, the time difference calculation circuit 20 may subtract all actual Hall state times in the same cycle before the actual Hall state time to be compensated from the first calculation value to calculate a second calculation value. Then, the time difference calculation circuit 20 can calculate The ratio of the second operation value to the previous actual Hall state time of the actual Hall state time to be compensated. The phase adjustment circuit 30 compensates the actual Hall state time of the Hall signal according to this ratio.

If necessary, the following operations can be carried out further. The time difference calculation circuit 20 can divide each ideal commutation time into M sub-divisions and each sub-division time is defined as a sub-commutation time, where M is an integer value not less than 1, such as but not limited to 32. Then, the time difference calculation circuit 20 can multiply the M value by the second operation value to calculate the third operation value. Then, the time difference calculation circuit 20 can divide the third calculated value by the actual Hall state time before the actual Hall state time to be compensated to calculate a compensated radial angle.

The time difference calculation circuit 20 can use the following formula to calculate the compensation radial angle of the actual Hall state time T1: AS1=M-(M×T/T6), wherein AS1 represents the compensation radial angle of the actual Hall state time T1 (or is called compensation time), M represents the number of multiple sub-commutation times divided by the actual Hall state time T1 to be compensated, T represents the ideal commutation time, and T6 represents the previous actual time of the actual Hall state time T1 to be compensated Hall state time.

The time difference calculation circuit 20 can use the following formula to calculate the compensation radial angle of the actual Hall state time T2: AS2=M-[M×(2T-T1)/T1], wherein AS2 represents the compensation radius of the actual Hall state time T2 Angle (or compensation time), M represents the number of multiple sub-commutation times divided by the actual Hall state time T2 to be compensated, T represents the ideal commutation time, and T1 represents the actual Hall state time T2 to be compensated The previous actual Hall state time.

The time difference calculation circuit 20 can use the following formula to calculate the compensation radial angle of the actual Hall state time T3: AS3=M-[M×(3T-T1-T2)/T2], Among them, AS3 represents the compensation radial angle (or compensation time) of the actual Hall state time T3, M represents the number of multiple sub-commutation times divided by the actual Hall state time T3 to be compensated, and T represents the ideal commutation Time, T2 and T1 represent the actual Hall state time before the actual Hall state time T3 to be compensated.

The time difference calculation circuit 20 can use the following formula to calculate the compensation radial angle of the actual Hall state time T4: AS4=M-[M×(4T-T1-T2-T3)/T3], wherein AS4 represents the actual Hall state time The compensation radial angle (or compensation time) of T4, M represents the number of multiple sub-commutation times divided by the actual Hall state time T4 to be compensated, T represents the ideal commutation time, and T3, T2, T1 represent the desired The actual Hall state time before the compensated actual Hall state time T4.

The time difference calculation circuit 20 can use the following formula to calculate the compensation radial angle of the actual Hall state time T5: AS5=M-[M×(5T-T1-T2-T3-T4)/T4], wherein AS5 represents the actual Hall state time T5 The compensation radial angle (or compensation time) of the state time T5, M represents the number of sub-commutation times divided by the actual Hall state time T5 to be compensated, T represents the ideal commutation time, T4, T3, T2 , T1 represents the actual Hall state time before the actual Hall state time T5 to be compensated.

The time difference calculation circuit 20 can adopt the following formula to calculate the compensation radial angle of the actual Hall state time T6: AS6=M-[M×(6T-T1-T2-T3-T4-T5)/T5], wherein AS6 represents the actual The compensation radial angle (or compensation time) of the Hall state time T6, M represents the number of sub-commutation times divided by the actual Hall state time T6 to be compensated, T represents the ideal commutation time, T5, T4 , T3, T2, T1 represent the actual Hall state time before the actual Hall state time T6 to be compensated.

The phase adjustment circuit 30 can compensate the actual Hall state time of the Hall signal according to all compensation radial angles, as shown in FIG. The six long actual Hall state times T1~T6 can be compensated to be equal to each other and equal to the six ideal commutation times T as shown in FIG. 7 . The phase adjustment circuit 30 can generate a compensation signal according to the compensated Hall signal.

As shown in FIG. 1 , the driving circuit 40 can be connected to the phase adjustment circuit 30 and the load 50 . The load 50 shown in FIG. 1 can be, for example, a three-phase motor 501 as shown in FIG. 2 , and a bridge circuit 502 can be connected between the driving circuit 40 and the three-phase motor 501 . The bridge circuit 502 may include multiple transistors such as the first upper bridge transistor M1 shown in FIG. 2 , the first lower bridge transistor M4 , the second upper bridge transistor M2 , the second lower bridge transistor M5 , the third The upper bridge transistor M3 and the third lower bridge transistor M6. The driving circuit 40 can be connected to the control terminals of each transistor.

One end of the U-phase of the three-phase motor 501 can be connected to a node between the second end of the first upper bridge transistor M1 and the first end of the first lower bridge transistor M4 . One terminal of the V-phase of the three-phase motor 501 can be connected to a node between the second terminal of the second high-bridge transistor M2 and the first terminal of the second low-bridge transistor M5 . One end of the W phase of the three-phase motor 501 can be connected to a node between the second end of the third upper bridge transistor M3 and the first end of the third lower bridge transistor M6 .

The driving circuit 40 can receive the compensation signal from the time difference calculation circuit 20 , and can output a driving signal according to the compensation signal to drive the bridge circuit 502 , and then drive the three-phase motor 501 . In this way, the phases of the three-phase motor 501 can be commutated at the correct time, so that vibration and noise will not be generated during the normal and stable operation of the three-phase motor 501 .

Please refer to FIGS. 1 to 8 , wherein FIG. 8 is a waveform diagram of a Hall signal of a motor drive system with an automatic phase adjustment mechanism according to an embodiment of the present invention. The time difference calculation circuit 20 shown in FIG. 1 can multiply the ideal commutation time by a desired radial angle to calculate the fourth calculation value. Then, the time difference calculation circuit 20 can calculate the above-mentioned third operation value Subtracting the fourth operation value to obtain the fifth operation value. Then, the time difference calculation circuit 20 can divide the fifth calculated value by the actual Hall state time before the actual Hall state time to be compensated to calculate a phase adjustment radial angle. The phase adjustment circuit 30 can adjust the radial angle according to the phase to compensate the actual Hall state time of the Hall signal to generate a compensation signal.

For example, the time difference calculation circuit 20 can use the following formula to calculate the phase adjustment radial angle of the actual Hall state time T1: ASP1=M-(M×T/T6-ASL1×T), where ASP1 represents the actual Hall state Phase adjustment radial angle of time T1 (or expected adjustment time), M represents the number of multiple sub-commutation times divided by the actual Hall state time T1 to be compensated, T represents the ideal commutation time, and T6 represents the desired compensation The previous actual Hall state time of the actual Hall state time T1, ASL1 represents the expected radial angle (or expected time) of the actual Hall state time T1.

The time difference calculation circuit 20 can use the following formula to calculate the phase adjustment radial angle of the actual Hall state time T2: ASP2=M-{[M×(2T-T1)-ASL2×T]/T1}, wherein ASP2 represents the actual Hall state time T2 The phase adjustment radial angle of Hall state time T2, M represents the number of multiple sub-commutation times divided by the actual Hall state time T2 to be compensated, T represents the ideal commutation time, and T1 represents the actual Hall state to be compensated The previous actual Hall state time of time T2, ASL2 represents the desired radial angle of the actual Hall state time T2.

The time difference calculation circuit 20 can use the following formula to calculate the phase adjustment radial angle of the actual Hall state time T3: ASP3=M-{[M×(3T-T1-T2)-ASL3×T]/T2}, wherein ASP3 represents The phase adjustment radial angle of the actual Hall state time T3, M represents the number of multiple sub-commutation times divided by the actual Hall state time T3 to be compensated, T represents the ideal commutation time, and T2 and T1 represent the sub-commutation times to be compensated the actual Hall state time before the actual Hall state time T3, ASL3 represents the desired radial angle of the actual Hall state time T3.

The time difference calculation circuit 20 can use the following formula to calculate the phase adjustment radial angle of the actual Hall state time T4: ASP4=M-{[M×(4T-T1-T2-T3)-ASL4×T]/T3}, wherein, ASP4 represents the phase adjustment radial angle of the actual Hall state time T4, M represents the number of multiple sub-commutation times divided by the actual Hall state time T4 to be compensated, T represents the ideal commutation time, T3, T2, T1 represents the actual Hall state time before the actual Hall state time T4 to be compensated, and ASL4 represents the expected radial angle of the actual Hall state time T4.

The time difference calculation circuit 20 can use the following formula to calculate the phase adjustment radial angle of the actual Hall state time T5: ASP5=M-{[M×(5T-T1-T2-T3-T4)-ASL5×T]/T4}, Among them, ASP5 represents the phase adjustment radial angle of the actual Hall state time T5, M represents the number of multiple sub-commutation times divided by the actual Hall state time T5 to be compensated, T represents the ideal commutation time, T4, T3 , T2, and T1 represent the actual Hall state time before the actual Hall state time T5 to be compensated, and ASL5 represents the expected radial angle of the actual Hall state time T5.

The time difference calculation circuit 20 can use the following formula to calculate the phase adjustment radial angle of the actual Hall state time T6: ASP6=M-{[M×(6T-T1-T2-T3-T4-T5)-ASL6×T]/T5 }, where ASP6 represents the phase adjustment radial angle of the actual Hall state time T6, M represents the number of multiple sub-commutation times divided by the actual Hall state time T6 to be compensated, T represents the ideal commutation time, and T5 , T4, T3, T2, T1 represent the actual Hall state time before the actual Hall state time T6 to be compensated, and ASL6 represents the expected radial angle of the actual Hall state time T6.

It should be understood that the above-mentioned expected radial angles ASL1~ASL6 may be equal or unequal in length to each other, And it is expected that the radial angles ASL1~ASL6 can be positive or negative, or the above-mentioned subtraction operation can be changed to addition, so that the phase of the Hall signal can be adjusted to lead or fall behind. The above is only an example, and the present invention is not limited thereto. . Furthermore, this article only exemplifies the compensation of one cycle time of the Hall signal, in fact, multiple continuous or discontinuous cycle times of any phase of the Hall signal can be compensated.

To sum up, the present invention provides a motor drive system with an automatic phase adjustment mechanism, which can sense the Hall sensor under the hysteresis of the Hall element itself and the offset state of the Hall element. The Hall signal is used to compensate and adjust the phase, so that the motor commutates at the correct time point, so that the motor can run normally and stably, while greatly reducing vibration and noise.

The content disclosed above is only a preferred feasible embodiment of the present invention, and does not therefore limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the description and drawings of the present invention are included in the application of the present invention. within the scope of the patent.

10: Ideal time setting circuit

20: Time difference calculation circuit

30: Phase adjustment circuit

40: Drive circuit

50: load

61~63: Hall sensor

Claims (6)

A motor drive system with an automatic phase adjustment mechanism, suitable for a three-phase motor, the motor drive system with an automatic phase adjustment mechanism includes: a Hall sensor configured to sense a Hall signal of each of the three phases of the three-phase motor; An ideal time setting circuit, connected to each of the Hall sensors, configured to divide a cycle time of the Hall signal to be compensated by N, so as to divide this cycle time into N equal parts, and the time definition of each equal part is an ideal commutation time, each ideal commutation time is equal to the other ideal commutation times, wherein N is an integer value greater than 1; A time difference calculation circuit, connected to the ideal time setting circuit, configured to divide the cycle time of the Hall signal to be compensated according to a plurality of transition time points of the Hall signal in the three phases of the three-phase motor For N equal parts with different time lengths, the time of each equal part of this cycle time of the Hall signal is defined as an actual Hall state time, and a plurality of the actual Hall state times are based on The time sequence corresponds to a plurality of the ideal commutation times, and the difference between each actual Hall state time and the corresponding ideal commutation time is calculated as a commutation time difference; A phase adjustment circuit, connected to the time difference calculation circuit, configured to compensate the Hall signal according to all the plurality of commutation time differences to generate a compensation signal; a bridge circuit connected to the three-phase motor; and A drive circuit, connected to the phase adjustment circuit and the bridge circuit, configured to drive the bridge circuit according to the compensation signal. The motor drive system with an automatic phase adjustment mechanism as described in Claim 1, wherein the time difference calculation circuit calculates the actual Hall state time to be compensated in the Hall signal and all the earlier occurrence times in the same cycle time The sum of a plurality of ideal commutation times corresponding to the actual Hall state time is used as a first calculation value, and the first calculation value is subtracted from the actual Hall state time to be compensated. The actual Hall state time is used to calculate a second operation value, and a ratio of the second operation value to the actual Hall state time before the actual Hall state time to be compensated is calculated, and the phase adjustment circuit is based on the ratio To compensate the actual Hall state time of the Hall signal. The motor drive system with an automatic phase adjustment mechanism as described in claim 2, wherein the time difference calculation circuit divides each ideal commutation time into M sub-equal parts, and the time of each sub-division is defined as a sub-commutation time , multiplying the M value by the second calculation value to calculate a third calculation value, dividing the third calculation value by the actual Hall state time before the actual Hall state time to be compensated to calculate a Compensating the radial angle, the phase adjustment circuit compensates the actual Hall state time of the Hall signal according to the compensated radial angle, wherein M is an integer value not less than 1. The motor drive system with an automatic phase adjustment mechanism as described in Claim 3, wherein the time difference calculation circuit multiplies the ideal commutation time by a desired radial angle to calculate a fourth calculation value, and the third calculation subtract the fourth calculated value to obtain a fifth calculated value, and divide the fifth calculated value by the actual Hall state time before the actual Hall state time to be compensated to calculate a phase adjustment radial Angle, the phase adjustment circuit compensates the actual Hall state time of the Hall signal according to the phase adjustment radial angle. The motor drive system with an automatic phase adjustment mechanism as described in claim 1, wherein the first start time point of part of the actual Hall state time is aligned with the Hall signal of one of the three phases of the three-phase motor The upper edge and an end time point are aligned with the lower edge of the Hall signal of the other phase of the three phases of the three-phase motor. The motor drive system with an automatic phase adjustment mechanism as described in claim 1, wherein the first start time point of part of the actual Hall state time is aligned with the Hall signal of one of the three phases of the three-phase motor The lower edge and an end time point are aligned with the upper edge of the Hall signal of the other phase of the three phases of the three-phase motor.

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