TWI796672B - Multi-bit flip-flop and control method thereof - Google Patents

Abstract

A multi-bit flip-flop (MBFF) comprising: a first flip-flop, arranged to output a first data-out signal, wherein the first flip-flop comprises: a first selection circuit, arranged to transmit a first data signal or a first test signal to an output node of the first selection circuit to serve as a first input signal; a first latch-based circuit, arranged to generate a first signal according to the first input signal; and a first data-out stage circuit, arranged to generate the first data-out signal according to the first signal; wherein when the MBFF operates in a test mode, the first selection circuit transmits the first test signal to the output node of the first selection circuit to serve as the first input signal, and the first data-out stage circuit keeps the first data-out signal at a fixed voltage level.

Description

Multi-bit flip-flop and its control method

The present invention relates to a flip-flop design, and more particularly, to a multi-bit flip-flop with power-saving features that applies a gating function to data in a test mode. output (data-out) signal and/or apply hold function to scan-out (scan-out) signal in normal mode (normal mode).

Scan chains are applied to detect various manufacturing faults in combinational logic blocks during the testing process. Usually, the scan chain is composed of a plurality of flip-flops connected in series, and in normal mode, the data output terminal of each flip-flop is connected to a combinational logic circuit for normal data transmission. However, in the test mode, the data output terminal of each flip-flop still has data transmission, so the combinational logic circuit is still working, resulting in unnecessary power consumption.

The invention provides a multi-bit flip-flop and its control method, which can reduce power consumption.

A multi-bit flip-flop provided by the present invention may include: a plurality of flip-flops connected to form an internal scan chain, wherein the plurality of flip-flops includes a first flip-flop arranged as A first data output signal is output at the first data output terminal, and the first flip-flop includes: a first selection circuit arranged to output the first data signal or the second data signal at the first data input terminal of the multi-bit flip-flop a test signal is sent to an output node of the first selection circuit as a first input signal; a first latch circuit, coupled to the output node of the first selection circuit, is arranged to signal generating a first signal; and a first data output stage circuit arranged to receive said first signal and generate said first data output signal based on said first signal; wherein, when said multiple When the bit flip-flop is operating in a test mode, the first selection circuit is arranged to transmit the first test signal to the output node of the first selection circuit as the first input signal, and the The first data output stage circuit is arranged to maintain the first data output signal at a fixed voltage level irrespective of the voltage level of the first test signal.

A control method provided by the present invention is applied to a multi-bit flip-flop (MBFF) connected with N flip-flops to form an internal scan chain, wherein the multi-bit flip-flop includes a The scanning input terminals of the N flip-flops are respectively coupled to the N data output terminals of the N flip-flops, wherein N is a positive integer not less than 1, and the control method includes: responding to the multi-bit flip-flops in the An external test signal is received at the scan input terminal, and the external test signal is transmitted through the internal scan chain; a scan output signal having a voltage level that varies with the voltage level of the external test signal is generated, wherein the outputting a scan output signal from one of the N flip-flops to one of the N data output terminals; and outputting one of the (N-1) data output signals regardless of the voltage level of the external test signal Each is maintained at a fixed voltage level, wherein the (N-1) data output signals are respectively output from the remaining (N-1) flip-flops of the N flip-flops to the N data output terminals The remaining (N-1) output terminals.

Another control method provided by the present invention is applied to a multi-bit flip-flop connected with N flip-flops to form an internal scan chain, wherein the multi-bit flip-flop includes a scan coupled to one of the N flip-flops An input terminal coupled to the scan output terminal of another one of the N flip-flops, and N data output terminals respectively coupled to the N flip-flops, where N is a positive integer not less than 1; The control method includes: in response to receiving an external test signal at the scan input terminal of the multi-bit flip-flop, passing the external test signal through the internal scan chain; generating a voltage having a voltage corresponding to the external test signal A scan output signal of a voltage level that changes in level, wherein the scan output signal is output from the other flip-flop of the N flip-flops to the scan output terminal; and regardless of the external test signal Regardless of the voltage level, the N data output signals are kept at a fixed voltage level level, wherein the N data output signals are respectively output from the N flip-flops to the N data output terminals of the multi-bit flip-flops.

As mentioned above, the embodiment of the present invention maintains the data output signal at a fixed voltage level when a test signal is received, thereby reducing power consumption.

100,800,1000: Multi-bit flip-flops

D1, D2, D(N-1), DN: data input terminals

SI: scan input terminal

SE: Test enable terminal

CLK: clock input terminal

102_1,102_2,102(N-1),102_N,802_1,802_2,802_(N-1), 802_N, 1002_1, 1002_2, 1002_(N-1), 1002_N: Trigger

210_1, L1, 210_2, 210_(N-1), 212, 300, 400, 500, 600, 700: data output stage circuit

104: Internal scan chain

INT2, INT(N-1), INTN, S11, INT3: test signal

Q1, Q2, Q(N-1), QN: data output terminals

SCK, CLKB, CLK1: clock signal

STE, STEB: test enable signal

S10, S20, SN0: data signal

202: clock generation circuit

204: Signal generating circuit

206_1, 206_2, 206_N: selection circuit

S12, S22, SN2: input signal

208_1, 208_2, 208_N: latch circuit

N1, N2: output nodes

S13, S23, SN3: signal

S14, S24, SN4: data output signal

211: NOR gate

213,608,708,1508,1608: inverter

302, 1202: OR gate

402, 1302: NAND gate

502, 1402: AND gate

602, 604, 706, 1502, 1504, 1606: PMOS transistors

606, 702, 704, 1506, 1602, 1604: NMOS transistors

1004, L2, 1200, 1300, 1400, 1500, 1600: scanning output stage circuit

SN5: scan output signal

FIG. 1 is a schematic diagram illustrating a first multi-bit flip-flop (MBFF) with power-saving characteristics according to an embodiment of the present invention.

FIG. 2 is a diagram showing a first circuit design of an MBFF according to an embodiment of the present invention.

Figure 3 is a diagram showing a first alternative design of a data output stage circuit with hold function according to an embodiment of the present invention.

Figure 4 is a diagram illustrating a second alternative design of a data output stage circuit with hold function according to an embodiment of the present invention.

Fig. 5 is a diagram showing a third alternative design of a data output stage circuit with hold function according to an embodiment of the present invention.

Figure 6 is a diagram showing a fourth alternative design of a data output stage circuit with hold function according to an embodiment of the present invention.

Fig. 7 is a diagram showing a fifth alternative design of a data output stage circuit with hold function according to an embodiment of the present invention.

FIG. 8 is a schematic diagram illustrating a second MBFF having power saving characteristics according to an embodiment of the present invention.

Fig. 9 is a diagram showing a second circuit design of an MBFF according to an embodiment of the present invention.

FIG. 10 is a schematic diagram illustrating a third MBFF having power saving characteristics according to an embodiment of the present invention.

FIG. 11 is a diagram showing a third circuit design of an MBFF according to an embodiment of the present invention.

Fig. 12 is a diagram showing a first alternative design of a scan output stage circuit with hold function according to an embodiment of the present invention.

Fig. 13 is a diagram showing a second alternative design of a scan output stage circuit with hold function according to an embodiment of the present invention.

Fig. 14 is a diagram showing a third alternative design of a scan output stage circuit with hold function according to an embodiment of the present invention.

Fig. 15 is a diagram showing a fourth alternative design of a scan output stage circuit with hold function according to an embodiment of the present invention.

Fig. 16 is a diagram showing a fifth alternative design of a scan output stage circuit with hold function according to an embodiment of the present invention.

Certain terms are used in the specification and claims to refer to particular elements. Those skilled in the art should understand that hardware manufacturers may use different terms to refer to the same component. This description and the scope of the patent application do not use the difference in name as a way to distinguish components, but use the difference in function of components as a criterion for distinguishing. "Includes" and "comprising" mentioned throughout the specification and scope of patent application are open-ended terms, so they should be interpreted as "including but not limited to". "Substantially" means that within an acceptable error range, a person with ordinary knowledge in the technical field can solve the technical problem within a certain error range and basically achieve the technical effect. In addition, the term "coupled" includes any direct and indirect electrical connection means. Therefore, if it is described in the text that a first device is coupled to a second device, it means that the first device may be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means. device. The following description is a preferred mode of implementing the present invention, the purpose of which is to illustrate the spirit of the present invention rather than to limit the protection scope of the present invention. The protection scope of the present invention should be defined by the scope of the appended patent application.

The following description is of the best contemplated embodiment of the invention. These descriptions are used to illustrate the general principles of the invention and should not be used to limit the invention. The scope of protection of the present invention should be determined on the basis of referring to the patent scope of the present invention.

2)。MBFF 100的電路佈局可以是集成電路(IC)設計所使用的單元庫中的一個單元(cell)。如第1圖所示，MBFF 100具有N個資料輸入端子D1，D2，..，D(N-1)和DN，掃描輸入端子SI，測試使能端子SE，時鐘輸入端子CLK和N個資料輸出端子Q1，Q2，...，Q(N-1)和QN。此外，MBFF 100包括N個連接在一起的觸發器(Flip-Flop，FF)102_1、102_2，...，102_(N-1)和102_N，以形成內部掃描鏈104，即如虛線所示，通過內部拼接(stitching)觸發器102_1-102_N來形成的掃描鏈。當MBFF 100在正常模式下操作時，資料輸入端子D1-DN用於接收資料信號，並且分別耦接到觸發器102_1-102_N。當MBFF 100在正常模式下操作時，資料輸出端子Q1-QN用於輸出資料輸出信號，並且分別耦接到觸發器102_1-102_N。掃描輸入端子SI用於接收外部測試信號，並且掃描輸入端子SI處的外部測試信號通過內部掃描鏈104傳輸，其中當前的觸發器102_n的測試信號(n≠1)是從前一級觸發器102_(n-1)獲得的內部測試信號。例如，從觸發器102_1獲得觸發器102_2的測試信號INT2，從觸發器102_2獲得另一觸發器(未示出)的測試信號INT3，從再一觸發器(未示出)獲得觸發器102_(N-1)的測試信號INT(N-1)，並且從觸發器102_(N-1)獲得觸發器102_N的測試信號INTN。觸發器102_1-102_(N-1)中的每一個具有資料輸出級電路(標記為“L1”)210_1、210_2，...，210_(N-1)，這些資料輸出級電路具有在測試模式下被啟用(enabled)，並在正常模式下被禁用(disabled)的保持功能。 FIG. 1 is a schematic diagram illustrating a first multi-bit flip-flop (Multi-Bit Flip-Flop, MBFF) with power saving characteristics according to an embodiment of the present invention. In this embodiment, MBFF 100 is an N-bit scan flip-flop, where N is a positive integer not less than 1 (ie, N

2). The circuit layout of MBFF 100 may be a cell in a library of cells used in integrated circuit (IC) design. As shown in Figure 1, MBFF 100 has N data input terminals D1, D2, ..., D(N-1) and DN, scan input terminal SI, test enable terminal SE, clock input terminal CLK and N data input terminals Output terminals Q1, Q2, . . . , Q(N-1) and QN. In addition, MBFF 100 includes N flip-flops (Flip-Flop, FF) 102_1, 102_2, . A scan chain is formed by internally stitching flip-flops 102_1-102_N. When the MBFF 100 operates in the normal mode, the data input terminals D1-DN are used to receive data signals, and are respectively coupled to the flip-flops 102_1-102_N. When the MBFF 100 operates in the normal mode, the data output terminals Q1-QN are used to output data output signals, and are respectively coupled to the flip-flops 102_1-102_N. The scan input terminal SI is used to receive an external test signal, and the external test signal at the scan input terminal SI is transmitted through the internal scan chain 104, wherein the test signal (n≠1) of the current flip-flop 102_n is obtained from the previous stage flip-flop 102_(n -1) Internal test signal obtained. For example, the test signal INT2 of the flip-flop 102_2 is obtained from the flip-flop 102_1, the test signal INT3 of another flip-flop (not shown) is obtained from the flip-flop 102_2, and the flip-flop 102_(N -1) of the test signal INT(N-1), and the test signal INTN of the flip-flop 102_N is obtained from the flip-flop 102_(N-1). Each of the flip-flops 102_1-102_(N-1) has data output stage circuits (labeled "L1") 210_1, 210_2, . . . , 210_(N-1) which have The hold function is enabled in normal mode and disabled in normal mode.

In the case where the MBFF 100 operates in the normal mode, the data output stage circuit 210_1 generates and outputs a data output signal to the data output terminal Q1, wherein the voltage level of the data output signal is responsive to the voltage level of the data signal at the data input terminal D1. The data output stage circuit 210_2 generates and outputs a data output signal to the data output terminal Q2, wherein the voltage level of the data output signal changes in response to the voltage level of the data signal at the data input terminal D2; The data output stage circuit 210_(N-1) generates and outputs a data output signal to the data output terminal Q(N-1), wherein the voltage level of the data output signal is responsive to the voltage level at the data input terminal D(N-1) The voltage level of the data signal changes. In addition, the data output terminal QN is shared by normal data transmission and test data transmission. Accordingly, the flip-flop 102_N generates a data output signal whose voltage level changes in response to the voltage level of the data signal at the data input terminal DN and outputs it to the data output terminal QN.

In another case where the MBFF 100 operates in the test mode, the data output stage circuit 210_1 generates and outputs a data output signal to the data output terminal Q1, wherein the voltage level of the data output signal is maintained at a fixed voltage level regardless of the scan What is the voltage level of the test signal at the input terminal SI; the data output stage circuit 210_2 generates a data output signal and outputs it to the data output terminal Q2, wherein the voltage level of the data output signal is maintained at a fixed voltage level, while The test signal INT2 obtained by the flip-flop 102_1 is irrelevant; the data output stage circuit 210_(N-1) generates and outputs the data output signal to the data output terminal Q(N-1), wherein the voltage level of the data output signal is kept at a fixed voltage level regardless of the voltage level of the test signal INT(N-1) obtained from the previous stage flip-flop (not shown). In addition, the data output terminal QN is shared by normal data transmission and test data transmission. Thus, the flip-flop 102_N generates and outputs a scan-out signal to the data output terminal QN, wherein the voltage level of the scan-out signal is responsive to the test signal INTN (which is detected in the internal scan chain 104 by an external test signal at the scan-in terminal S1 ). The voltage level obtained during transmission) changes.

FIG. 2 is a diagram showing a first circuit design of an MBFF according to an embodiment of the present invention. By way of example and not limitation, the MBFF 100 shown in Figure 1 can be implemented using the circuit structure shown in Figure 2 now. In addition to the flip-flops 102_1 - 102_N, the MBFF 100 may further include a signal generation circuit 204 and a clock generation circuit 202 . The signal generation circuit 204 receives a test enable signal STE (which is an external test enable signal) to generate another test enable signal STEB, and the test enable signal STEB is inverse to the test enable signal STE. In the embodiment of FIG. 2, the signal generating circuit 204 includes an inverter. In other embodiments, the signal generation circuit 204 may be realized by any other circuit structure capable of receiving the test enable signal STE and generating the test enable signal STEB which is inverse to the test enable signal STE.

The clock generating circuit 110 receives a clock signal SCK (which is an external clock signal received via a clock terminal CK), and generates clock signals CLKB and CLK1 according to the clock signal SCK, wherein the clock signal CLKB is the inversion of the clock signal SCK, and the clock signal CLK1 is Inversion of the clock signal CLKB. In the embodiment of FIG. 2, the clock generation circuit 202 includes two inverters. In other embodiments, the clock generation circuit 202 can be realized by any other circuit structure capable of receiving the clock signal SCK, generating the clock signal CLKB which is the opposite phase of the clock signal SCK, and generating the clock signal CLK1 which is the reverse phase of the clock signal CLKB.

Each of the flip-flops 102_1-102_(N-1) may have the same circuit structure. For example, the flip-flop 102_1 is arranged to output the data output signal S14 at the data output terminal Q1 of the MBFF 100, which includes the selection circuit 206_1, the latch circuit 208_1 and the data output stage circuit 210_1; The data output terminal Q2 outputs a data output signal S24, which includes a selection circuit 206_2, a latch circuit 208_2 and a data output stage circuit 210_2. Regarding flip-flop 102_1, selection circuit 206_1 is arranged to send data signal S10 at data input terminal D1 of MBFF 100 or test signal S11 at scan input terminal SI of MBFF 100 to an output node of selection circuit 206_1 for use as input signal S12 The latch circuit 208_1 is coupled to the output node of the selection circuit 206_1 and is arranged to generate a signal S13 according to the input signal S12; the data output stage circuit 210_1 is arranged to receive the signal S13 and generate a data output signal S14 according to the signal S13. In this embodiment, the selection circuit 206_1 may include an inverter and transmission gates, wherein each transmission gate includes a P-type transistor (for example, a P-channel metal oxide compound semiconductor (PMOS) transistors) and N-type transistors (such as N-channel metal oxide semiconductor (NMOS) transistors), and are controlled by test enable signals STE and STEB. In addition, the latch circuit 208_1 may include an inverter and a transfer gate, wherein each transfer gate includes a P-type transistor (for example, a PMOS transistor) and an N-type transistor (for example, an NMOS transistor), and is controlled by a clock signal CLK1 and CLKB control. Since the present invention does not focus on the circuit design of the selection circuit 206_1 and the latch circuit 208_1 , those skilled in the art should easily understand the principle of the selection circuit 206_1 and the latch circuit 208_1 shown in FIG. 2 . Therefore, for the sake of brevity, further descriptions of the selection circuit 206_1 and the latch circuit 208_1 are omitted here.

The data output stage circuit 210_1 is equipped with a hold function that is enabled in the test mode of the MBFF 100 and disabled in the normal mode of the MBFF 100 . For example, when the MBFF 100 operates in the normal mode, the selection circuit 206_1 sends the data signal S10 to the output node of the selection circuit 206_1 as the input signal S12, and the data output stage circuit 210_1 generates the data output signal S14, which has A voltage level that varies in response to the voltage level of the data signal S10. Specifically, the voltage level of the data output signal S14 changes in response to the voltage level of the signal S13, which changes in response to the voltage level of the data signal S10. When the MBFF 100 operates in the test mode, the selection circuit 206_1 sends the test signal S11 to the output node of the selection circuit 206_1 as the input signal S12, and the data output stage circuit 210_1 maintains the data output signal S14 at a fixed voltage level (e.g. , high voltage level or low voltage level), regardless of the voltage level of the test signal S11. Specifically, the voltage level of the data output signal S14 does not change in response to the voltage level of the signal S13, but the voltage level of the signal S13 changes in response to the voltage level of the test signal S11.

Contrary to the first flip-flop 102_1 receiving the test signal S11 via the scan-in terminal SI, the subsequent flip-flop 102_2 receives the test signal INT2 obtained from the preceding flip-flop 102_1 (especially the latch circuit 208_1 of the flip-flop 102_1 ). With respect to the flip-flop 102_2, the selection circuit 206_2 is arranged to input the data signal S20 at the terminal D2 of the MBFF 100 or the test obtained from the latch circuit 208_1. The signal INT2 is sent to the output node of the selection circuit 206_2 as the input signal S22; the latch circuit 208_2 is coupled to the output node of the selection circuit 206_2 and arranged to generate the signal S23 according to the input signal S22. The data output stage circuit 210_2 is arranged to receive the signal S23 and generate a data output signal S24 according to the signal S23. Similarly, the data output stage circuit 210_2 is equipped with the same hold function, which is enabled in the test mode of the MBFF 100 and disabled in the normal mode of the MBFF 100 .

The last flip-flop 102_N is arranged to generate an output signal SN4 on the data output terminal QN of the MBFF 100 , which comprises a selection circuit 206_N, a latch circuit 208_N and an output stage circuit 212 . The output stage circuit 212 is implemented using an inverter 213 . The selection circuit 206_N is arranged to send the data signal SN0 at the data input terminal DN of the MBFF 100 or the test signal INTN obtained from a previous stage flip-flop to the output node of the selection circuit 206_N as input signal SN2. Latch circuit 208_N is coupled to the output node of selection circuit 206_N and is arranged to generate signal SN3 from input signal SN2. The output stage circuit 212 is arranged to receive the signal SN3 and to generate an output signal SN4 from the signal SN3. In this embodiment, the data output terminal QN is shared by normal data transmission and test data transmission. When the MBFF 100 is operating in the normal mode, the selection circuit 206_N sends the data signal SN0 to the output node of the selection circuit 206_N as an input signal SN2, and the output stage circuit 212 generates an output signal SN4 as a data output signal having A voltage level that changes in response to the voltage level of the data signal SN0. Specifically, the voltage level of the output signal SN4 (data output signal) changes in response to the voltage level of the signal SN3, which changes in response to the voltage level of the data signal SN0. When the MBFF 100 operates in the test mode, the selection circuit 206_N sends the test signal INTN to the output node of the selection circuit 206_N as the input signal SN2, and the output stage circuit 212 generates the output signal SN4 as a scan output signal having A voltage level that changes in response to the voltage level of the test signal INTN. Specifically, the voltage level of the output signal SN4 (scan out signal) changes in response to the voltage level of the signal SN3, which changes in response to the voltage level of the test signal INTN.

In this embodiment, each data output stage circuit with hold function can be implemented using a NOR gate 211, wherein one input node of the NOR gate 211 is arranged to receive the output signal of the previous stage latch circuit, NOR Another input node of the gate 211 is arranged to receive a test enable signal STE, and an output node of the NOR gate 211 is arranged to output a data output signal to a data output terminal of the MBFF 100 . Taking the data output stage 210_1 as an example, one input node of the NOR gate 211 receives the signal S13 at the output node N1 of the latch circuit 208_1, the other input node of the NOR gate 211 receives the test enable signal STE, and the output of the NOR gate 211 The node outputs the data output signal S14 to the data output terminal Q1 of the MBFF 100 . When the MBFF 100 is operating in the normal mode (STE=0), the voltage level of the data output signal S14 changes in response to the voltage level of the signal S13. Specifically, the data output signal S14 is the inversion of the signal S13, wherein the signal S13 is the inversion of the data signal S10. When the MBFF 100 operates in the test mode (STE=1), the voltage level of the data output signal S14 remains at a fixed voltage level (eg, ground voltage) regardless of the voltage level of the test signal S11 . Specifically, the voltage level of the data output signal S14 does not change in response to the voltage level of the signal S13, which is the inverse of the test signal S11.

The circuit structure shown in FIG. 2 is for illustrative purpose only, and does not mean to limit the present invention. For example, the selection circuit may be implemented by any other circuit structure capable of selecting one of the normal data input and the test data input as the input signal of the subsequent latch circuit. For another example, the latch circuit may be realized by any other circuit structure capable of processing an input signal obtained from a previous stage selection circuit to generate a signal and outputting the generated signal to a subsequent stage data output stage circuit having a hold function. As another example, the data output stage circuit with holding function can be implemented by any other circuit structure capable of holding the data output signal at a fixed voltage level when the MBFF is operating in the test mode.

Figure 3 is a diagram showing a first alternative design of a data output stage circuit with hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1 - 210_(N−1) can be implemented using the data output stage circuit 300 . The data output stage circuit 300 adopts an OR (OR) gate 302, wherein one of the input nodes of the OR gate 302 is coupled to the output node N1 of the previous stage latch circuit, and the OR The other input node of the gate 302 is arranged to receive the test enable signal STE, and the output node of the OR gate 302 is arranged to output the data output signal to the data output terminal Qn of the MBFF 100, where n is from 1 to (N-1) A positive integer selected in the range of . When the MBFF 100 operates in the normal mode (STE=0), the voltage level of the data output signal generated by the OR gate 302 changes in response to the voltage at the output node N1 of the previous-stage latch circuit. When the MBFF 100 operates in the test mode (STE=1), the data output signal generated by the OR gate 302 is maintained at a fixed voltage level (such as a power supply voltage), and is different from the signal at the output node N1 of the previous stage latch circuit voltage is irrelevant.

Figure 4 is a diagram illustrating a second alternative design of a data output stage circuit with hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1 - 210_(N−1) can be implemented using the data output stage circuit 400 . The data output stage circuit 400 adopts a NAND (NAND) gate 402, wherein one of the input nodes of the NAND gate 402 is coupled to the output node N1 of the previous stage latch circuit, and the other input node of the NAND gate 402 is arranged to receive a test enable signal STEB, and the output node of the NAND gate 402 is arranged to output the data output signal to the data output terminal Qn of the MBFF 100, where n is a positive integer selected from the range of 1 to (N-1). When the MBFF 100 operates in the normal mode (STEB=1), the voltage level of the data output signal generated by the NAND gate 402 changes in response to the voltage of the signal at the output node N1 of the latch circuit of the previous stage. When the MBFF 100 operates in the test mode (STEB=0), the data output signal generated by the NAND gate 402 is maintained at a fixed voltage level (such as a power supply voltage), and is different from the signal at the output node N1 of the previous stage latch circuit. voltage is irrelevant.

Fig. 5 is a diagram showing a third alternative design of a data output stage circuit with hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1 - 210_(N−1) can be implemented using the data output stage circuit 500 . The data output stage circuit 500 adopts an AND gate 502, one of the input nodes of the AND gate 502 is coupled to the output node N1 of the previous stage latch circuit, and the other input node of the AND gate 502 is arranged to receive the test enable signal STEB, and the AND gate 502 The output node of is arranged to output the data output signal to the data output terminal Qn of the MBFF 100, where n is a positive integer selected from the range of 1 to (N-1). When the MBFF 100 operates in the normal mode (STEB=1), the voltage level of the data output signal generated by the AND gate 502 changes in response to the voltage of the signal at the output node N1 of the latch circuit of the previous stage. When the MBFF 100 operates in the test mode (STEB=0), the data output signal generated by the AND gate 502 is maintained at a fixed voltage level (for example, ground voltage), regardless of the output node N1 of the previous stage latch circuit. What about the signal voltage.

Figure 6 is a diagram showing a fourth alternative design of a data output stage circuit with hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1 - 210_(N−1) can be implemented using the data output stage circuit 600 . Data output stage circuit 600 includes PMOS transistors 602 and 604 , NMOS transistor 606 and inverter 608 . The gate (gate) of the PMOS transistor 604 receives the test enable signal STEB, the source (source) of the PMOS transistor 604 is coupled to a reference voltage (such as a power supply voltage), and the drain (drain) of the PMOS transistor 604 is coupled to to the input node of inverter 608 . PMOS transistor 602 and NMOS transistor 606 form a transmission gate. The gate of the PMOS transistor 602 receives the test enable signal STE, the source of the PMOS transistor 602 is coupled to the output node N1 of the previous stage latch circuit, and the drain of the PMOS transistor 602 is coupled to the input of the inverter 608 node. The gate of the NMOS transistor 606 receives the test enable signal STEB, the drain of the NMOS transistor 606 is coupled to the output node N1 of the previous stage latch circuit, and the source of the NMOS transistor 606 is coupled to the input of the inverter 608 node.

When the MBFF 100 operates in normal mode (STE=0 & STEB=1), the transmission gate composed of the PMOS transistor 602 and the NMOS transistor 606 is enabled, and the PMOS transistor 604 is turned off (turn off), thereby The level voltage of the data output signal at the data output terminal Qn (n is a positive integer from 1 to (N-1)) changes in response to the voltage level of the signal at the output node N1 of the previous stage latch circuit. When MBFF 100 is operating in test mode (STE=1 & STEB=0), the transmission gate consisting of PMOS transistor 602 and NMOS transistor 606 is disabled, and PMOS transistor 604 is turned on, thereby enabling The voltage level of the data output signal at the data output terminal Qn is maintained at a fixed voltage level (for example, ground voltage), regardless of the voltage level of the signal at the output node N1 of the previous-stage latch circuit.

Fig. 7 is a diagram showing a fifth alternative design of a data output stage circuit with hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1 - 210_(N−1) can be implemented using the data output stage circuit 700 . The data output stage circuit 700 includes NMOS transistors 702 and 704 , a PMOS transistor 706 and an inverter 708 . The gate of the NMOS transistor 704 receives the test enable signal STE, the source of the NMOS transistor 704 is coupled to a reference voltage (for example, ground voltage), and the drain of the NMOS transistor 704 is coupled to the input node of the inverter 708 . PMOS transistor 706 and NMOS transistor 702 form a transmission gate. The gate of the PMOS transistor 706 receives the test enable signal STE, the source of the PMOS transistor 706 is coupled to the output node N1 of the previous stage latch circuit, and the drain of the PMOS transistor 706 is coupled to the input of the inverter 708 node. The gate of the NMOS transistor 702 receives the test enable signal STEB, the drain of the NMOS transistor 702 is connected to the output node N1 of the previous stage latch circuit, and the source of the NMOS transistor 702 is coupled to the input node of the inverter 708 .

When the MBFF 100 operates in the normal mode (STE=0 & STEB=1), the transmission gate composed of the PMOS transistor 706 and the NMOS transistor 702 is enabled, and the NMOS transistor 704 is turned off, so that the data output terminal Qn The voltage level of the data output signal at (n is a positive integer from 1 to (N-1)) changes in response to the voltage level of the signal at the output node N1 of the previous-stage latch circuit. When the MBFF 100 operates in the test mode (STE=1 & STEB=0), the transmission gate composed of the PMOS transistor 706 and the NMOS transistor 702 is disabled, and the NMOS transistor 704 is turned on, thereby enabling the data output terminal Qn The voltage level of the data output signal at is maintained at a fixed voltage level (for example, the power supply voltage) regardless of the voltage level of the signal at the output node N1 of the preceding latch circuit.

The MBFF 100 with N flip-flops 102_1 - 102_N connected to form an internal scan chain 104 is designed to have power-saving features. For example, when the external test signal S11 is received at the scan input terminal SI in the test mode, the MBFF 100 transmits the external test signal S11 through the internal scan chain 104, and generates a scan scan output signal SN4, the scan output signal SN4 is output from the flip-flop 102_N to the data output terminal QN, and the voltage level of the scan output signal SN4 changes in response to the voltage level of the external test signal S11, and regardless of the voltage level of the external test signal S11 Regardless of the level, each of the (N-1) data output signals (respectively output from flip-flops 102_1-102_(N-1) to output terminals Q1-Q(N-1)) is kept at a fixed voltage level . Since the (N−1) data output signals do not have signal level conversion in the test mode of the MBFF 100 , the power consumption of the MBFF 100 and downstream combinatorial logic can be reduced.

In the embodiments shown in FIG. 1 and FIG. 2 , MBFF 100 has a data output terminal QN shared by normal data transmission and test data transmission. However, this is for illustrative purposes only and is not meant to limit the invention. In an alternative design, the MBFF may be configured with additional terminals serving as dedicated scan-out terminals for outputting scan-out signals.

2)。MBFF 800的電路佈局可以是IC設計所使用的單元庫中的一個單元。如第8圖所示，MBFF 800具有N個資料輸入端子D1，D2，...，D(N-1)和DN，掃描輸入端子SI，測試使能端子SE，時鐘輸入端子CLK，N個資料輸出端子Q1，Q2，...，Q(N-1)和QN，以及掃描輸出端子SQ。此外，MBFF 800包括N個觸發器(FF)802_1，802_2，...，802_(N-1)和802_N，它們連接以形成內部掃描鏈104。MBFF100和800之間的主要區別在於MBFF 800的觸發器802_N具有當MBFF 800在測試模式下操作時用於輸出掃描輸出信號的掃描輸出端子SQ，並且還具有有保持功能的資料輸出級電路210_N(標記為“L1”)，該保持功能在測試模式下啟用而在正常模式下禁用。 FIG. 8 is a schematic diagram illustrating a second MBFF having power saving characteristics according to an embodiment of the present invention. In this embodiment, MBFF 800 is an N-bit scan flip-flop, where N is a positive integer not less than 1 (ie, N

2). The circuit layout of MBFF 800 may be a cell in a cell library used in IC design. As shown in Figure 8, MBFF 800 has N data input terminals D1, D2, ..., D(N-1) and DN, scan input terminal SI, test enable terminal SE, clock input terminal CLK, N Data output terminals Q1, Q2, . . . , Q(N-1) and QN, and a scan output terminal SQ. Furthermore, MBFF 800 includes N flip-flops (FFs) 802_1 , 802_2 , . The main difference between the MBFF 100 and 800 is that the flip-flop 802_N of the MBFF 800 has a scan output terminal SQ for outputting a scan output signal when the MBFF 800 operates in a test mode, and also has a data output stage circuit 210_N ( marked "L1"), the holdover function is enabled in test mode and disabled in normal mode.

When the MBFF 800 operates in the normal mode, the data output stage circuit 210_N generates a data output signal and outputs it to the data output terminal QN, wherein the voltage level of the data output signal corresponds to the voltage level of the data signal at the data input terminal DN. And change. When MBFF 800 is operating in test mode , the scan output stage circuit (not shown) generates a scan output signal and outputs it to the scan output terminal SQ, wherein the voltage level of the scan output signal changes in response to the voltage level of the data signal at the data input terminal DN. In addition, the data output stage circuit 210_N generates a data output signal and outputs it to the data output terminal QN, wherein the voltage level of the data output signal is maintained at a fixed voltage level (for example, a high voltage level or a low voltage level), Regardless of the voltage level of the test signal INTN obtained from the flip-flop 802_(N-1) of the previous stage.

Fig. 9 is a diagram showing a second circuit design of an MBFF according to an embodiment of the present invention. By way of example and not limitation, the MBFF 800 shown in FIG. 8 can be implemented using the circuit structure shown in FIG. 9 . Each flip-flop 802_1-802_(N-1) may have the same circuit structure as that shown in FIG. 2 . Similar descriptions are omitted for brevity. Regarding the last flip-flop 802_N, it is arranged to output the data output signal SN4 at the data output terminal QN of the MBFF 800 and to output the scan output signal SN5 at the scan output terminal SQ of the MBFF 800 . As shown in FIG. 9, the flip-flop 802_N includes a data output stage circuit 210_N, a scan output stage circuit 902, the selection circuit 206_N and the latch circuit 208_N. Similar to the output stage circuit 212 shown in FIG. 2 , the scan output stage circuit 902 is realized by an inverter 213 . Like the data output stage circuits 210_1 and 210_2 , the data output stage circuit 210_N is equipped with a hold function that is enabled in the test mode of the MBFF 800 and disabled in the normal mode of the MBFF 800 . When the MBFF 800 operates in the normal mode, the selection circuit 206_N sends the data signal SN0 to the output node of the selection circuit 206_N as the input signal SN2, and the data output stage circuit 210_N generates the data output signal SN4, the voltage level of which is The level changes in response to the voltage level of the data signal SN0. Specifically, the voltage level of the data output signal SN4 changes in response to the voltage level of the signal SN3, which changes in response to the voltage level of the data signal SN0. When the MBFF 800 is operating in the test mode, the selection circuit 206_N sends the test signal INTN to the output node of the selection circuit 206_N as the input signal SN2, and the data output stage circuit 210_N maintains the data output signal SN4 at a fixed voltage level (e.g., high voltage level or low voltage level), regardless of the test signal What is the voltage level of No. INTN. Specifically, the voltage level of the data output signal SN4 does not change in response to the voltage level of the signal SN3, but the voltage level of the signal SN3 changes in response to the voltage level of the test signal INTN.

The circuit configuration shown in FIG. 9 is for illustrative purposes only, and is not meant to limit the present invention. For example, the selection circuit may be implemented by any other circuit structure capable of selecting one of the normal data input and the test data input as the input signal of the subsequent latch circuit. For another example, the latch circuit may be implemented by any other circuit structure capable of processing an input signal obtained from a selection circuit of a previous stage to generate a signal and output the generated signal to a data output stage circuit of a subsequent stage with a holding function. As another example, the data output stage circuit with holding function can be implemented by any other circuit structure capable of holding the data output signal at a fixed voltage level when the MBFF is operating in the test mode. Therefore, one or a plurality of flip-flops 802_1-802_N can use the data output stage circuit 300 shown in FIG. 3, the data output stage circuit 400 shown in FIG. 4, and the data output stage circuit 500 shown in FIG. 5. , the data output stage circuit 600 shown in FIG. 6 or the data output stage circuit 700 shown in FIG. 7.

The MBFF 800 with N flip-flops 802_1 - 802_N connected to form the internal scan chain 104 is designed to have power-saving features. For example, when the external test signal S11 is received at the scan input terminal SI, the MBFF 800 transmits the external test signal S11 through the internal scan chain 104 to generate a scan output signal SN4 output from the flip-flop 802_N to the scan output terminal SQ, and the scan output signal The voltage level of SN4 changes in response to the voltage level of the external test signal S11, and maintains each of the N data output signals (output from N flip-flops 802_1-802_N to N The voltage level of the output terminals Q1-QN) is at a fixed voltage level. Since there is no signal level conversion for the N data output signals in the test mode of the MBFF 800 , the power consumption of the MBFF 800 and downstream combinatorial logic can be reduced.

In the embodiment shown in FIG. 9, the scan output stage circuit 902 does not have a hold function. As a result, when the MBFF 800 operates in any one of the normal mode and the test mode, the voltage level of the scan output signal SN5 changes in response to the voltage level of the signal SN3. In an alternative design, MBFF Can be configured as a scan output stage circuit with a hold function.

2)。MBFF 1000的電路佈局可以是IC設計所使用的單元庫中的一個單元。如第10圖所示，MBFF 1000具有N個資料輸入端子D1，D2，...，D(N-1)和DN，掃描輸入端子SI，測試使能端子SE，時鐘輸入端子CLK，N個資料輸出端子Q1，Q2，...，Q(N-1)和QN，以及掃描輸出端子SQ。此外，MBFF 1000包括N個觸發器(FF)1002_1，1002_2，...，1002_(N-1)，1002_N連接形成內部掃描鏈104。MBFF1000和MBFF800之間的主要區別是MBFF 1000的最後一個觸發器1002_N具有有保持功能的掃描輸出級電路1004(由“L2”標記)，該保持功能在正常模式下被啟用而在測試模式下被禁用。 FIG. 10 is a schematic diagram illustrating a third MBFF having power saving characteristics according to an embodiment of the present invention. In this embodiment, MBFF 1000 is an N-bit scan flip-flop, where N is a positive integer not less than 1 (ie, N

2). The circuit layout of MBFF 1000 may be a cell in a cell library used in IC design. As shown in Figure 10, MBFF 1000 has N data input terminals D1, D2, ..., D(N-1) and DN, scan input terminal SI, test enable terminal SE, clock input terminal CLK, N Data output terminals Q1, Q2, . . . , Q(N-1) and QN, and a scan output terminal SQ. In addition, MBFF 1000 includes N flip-flops (FF) 1002_1 , 1002_2 , . The main difference between MBFF1000 and MBFF800 is that the last flip-flop 1002_N of MBFF 1000 has a scan output stage circuit 1004 (marked by "L2") with a hold function that is enabled in normal mode and disabled in test mode. disabled.

When the MBFF 1000 operates in the normal mode, the data output stage circuit 210_N generates a data output signal and outputs it to the data output terminal QN, wherein the voltage level of the data output signal corresponds to the voltage level of the data signal at the data input terminal DN. The scan output stage circuit 1004 generates and outputs a scan output signal to the scan output terminal SQ, wherein the voltage level of the scan output signal is maintained at a fixed voltage level (for example, a high voltage level or a low voltage level), Regardless of the voltage level of the data signal at the data input terminal DN.

When the MBFF 1000 operates in the test mode, the scan output stage circuit 1004 generates a scan output signal and outputs it to the scan output terminal SQ, wherein the voltage level of the scan output signal is obtained in response to The voltage level of the test signal INTN varies. The data output stage circuit 210_N generates and outputs a data output signal to the data output terminal QN, wherein the voltage level of the data output signal is maintained at a fixed voltage level (such as a high voltage level or a low voltage level) regardless of the trigger from the previous stage. What is the voltage level of the test signal INTN obtained by the device 1002_(N-1).

FIG. 11 is a diagram showing a third circuit design of an MBFF according to an embodiment of the present invention. do By way of example and not limitation, the MBFF 1000 shown in FIG. 10 can be implemented using the circuit structure shown in FIG. 11 . Each of the flip-flops 1002_1-1002_(N-1) may have the circuit structure shown in FIG. 2 or FIG. 9 . For brevity, further description is omitted. Regarding the last flip-flop 1002_N, it is arranged to output the data output signal SN4 at the data output terminal QN of the MBFF 1000 and to output the scan output signal SN5 at the scan output terminal SQ of the MBFF 1000 . The main difference between flip-flops 802_N and 1002_N is that flip-flop 1002_N employs a scan output stage circuit 1004 with a hold function that is enabled in the normal mode of the MBFF 1000 and disabled in the test mode of the MBFF 1000 . When the MBFF 1000 is operating in the test mode, the selection circuit 206_N sends the test signal INTN to the output node of the selection circuit 206_N to be used as the input signal SN2, and the scan output stage circuit 1004 generates a scan output signal SN5 having a response to Test the voltage level of signal INTN to change the voltage level. Specifically, the voltage level of the scan output signal SN5 changes in response to the voltage level of the signal SN3, which changes in response to the voltage level of the test signal INTN. When the MBFF 1000 is operating in the normal mode, the selection circuit 206_N sends the data signal SN0 to the output node of the selection circuit 206_N as the input signal SN2, and the scan output stage circuit 1004 maintains the scan output signal SN5 at a fixed voltage level (e.g., high voltage level or low voltage level), regardless of the voltage level of the data signal SN0. Specifically, the voltage level of the scan output signal SN5 does not change in response to the voltage level of the signal SN3, whereas the voltage level of the signal SN3 changes in response to the voltage level of the data signal SN0.

Like the data output stage circuits 210_1, 210_2 and 210_N, the scan output stage circuit 1004 is implemented by a NOR gate, wherein one input node of the NOR gate is arranged to receive the signal SN3 at the output node N2 of the latch circuit 208_N, The other input node of the NOR gate is arranged to receive the test enable signal STEB, and the output node of the NOR gate is arranged to output the scan output signal SN5 to the scan output terminal SQ of the MBFF 1000 . Therefore, when the MBFF 1000 is operating in normal mode (STEB=1), the holdover function is enabled at the NOR gate. When MBFF 100 is operating in test mode (STEB=0), in NOR The hold function is disabled at the door.

The circuit configuration shown in FIG. 11 is for illustrative purposes only and is not meant to limit the present invention. For example, the selection circuit may be implemented by any other circuit structure capable of selecting one of the normal data input and the test data input as the input signal of the subsequent latch circuit. For another example, the latch circuit may be realized by any other circuit structure capable of processing an input signal obtained from a selection circuit of a previous stage to generate a signal and output the generated signal to a data output stage circuit of a subsequent stage having a holding function. As another example, the data output stage circuit with holding function can be implemented by any other circuit structure capable of holding the data output signal at a fixed voltage level when the MBFF is operating in the test mode. As another example, the scan output stage circuit with hold function can be realized by any other circuit structure capable of maintaining the scan output signal at a fixed voltage level when the MBFF operates in normal mode.

Fig. 12 is a diagram showing a first alternative design of a scan output stage circuit with hold function according to an embodiment of the present invention. For example, scan output stage circuit 1200 may be used to implement scan output stage circuit 1004 . The scanning output stage circuit 1200 adopts an OR (OR) gate 1202, wherein one input node of the OR gate 1202 is coupled to the output node N2 of the latch circuit at the front end, and the other input node of the OR gate 1202 is arranged to receive a test enable signal The output node of the STEB, OR gate 1202 is arranged to output the scan output signal to the output terminal SQ of the scan MBFF 1000 . When the MBFF 1000 operates in the test mode (STEB=0), the voltage level of the scan output signal generated by the OR gate 1202 changes in response to the voltage of the signal at the output node N2 of the latch circuit of the front end. When the MBFF 1000 is operating in the normal mode (STEB=1), the scan output signal generated by the OR gate 1202 is maintained at a fixed voltage level (such as a power supply voltage), and is compared with the signal at the output node N2 of the latch circuit of the front end voltage is irrelevant.

Fig. 13 is a diagram showing a second alternative design of a scan output stage circuit with hold function according to an embodiment of the present invention. For example, scan output stage circuit 1300 may be used to implement scan output stage circuit 1004 . The scanning output stage circuit 1300 adopts a NAND gate 1302, wherein one input node of the NAND gate 1302 is coupled to the output node N2 of the previous stage latch circuit, and the other of the NAND gate 1302 The input node is arranged to receive the test enable signal STE, and the output node of the NAND gate 1302 is arranged to output a scan output signal to the scan terminal SQ of the MBFF 1000 . When the MBFF 1000 operates in the test mode (STE=1), the voltage level of the scan output signal generated by the NAND gate 1302 varies in response to the voltage of the signal at the output node N2 of the latch circuit of the previous stage. When the MBFF 1000 is operating in the normal mode (STE=0), the scan output signal generated by the NAND gate 1302 is maintained at a fixed voltage level (such as a power supply voltage), which is different from the signal at the output node N2 of the previous stage latch circuit Voltage is independent.

Fig. 14 is a diagram showing a third alternative design of a scan output stage circuit with hold function according to an embodiment of the present invention. For example, scan output stage circuit 1400 may be used to implement scan output stage circuit 1004 . The scanning output stage circuit 1400 adopts an AND (AND) gate 1402, wherein one input node of the AND gate 1402 is coupled to the output node N2 of the latch circuit at the previous stage, and the other input node of the AND gate 1402 is arranged to receive a test enable signal STE, and the output node of the AND gate 1402 is arranged to output the scan-out signal to the scan-out terminal SQ of the MBFF 1000 . When the MBFF 1000 operates in the test mode (STE=1), the voltage level of the scan output signal generated by the AND gate 1402 changes in response to the voltage of the signal at the output node N2 of the latch circuit of the previous stage. When the MBFF 1000 is operating in normal mode (STE=0), the scan output signal generated by the AND gate 1402 is maintained at a fixed voltage level (eg, ground voltage), which is different from the signal at the output node N2 of the previous latch circuit voltage is irrelevant.

Fig. 15 is a diagram showing a fourth alternative design of a scan output stage circuit with hold function according to an embodiment of the present invention. For example, scan output stage circuit 1500 may be used to implement scan output stage circuit 1004 . Scan output stage circuit 1500 includes PMOS transistors 1502 and 1504 , NMOS transistor 1506 and inverter 1508 . The gate of the PMOS transistor 1504 receives the test enable signal STE, the source of the PMOS transistor 1504 is coupled to a reference voltage (eg, supply voltage), and the drain of the PMOS transistor 1504 is coupled to the input of the inverter 1508 node. PMOS transistor 1502 and NMOS transistor 1506 form a transmission gate. The gate of the PMOS transistor 1502 receives the test enable signal STEB, the source of the PMOS transistor 1502 is coupled to the output node N2 of the previous stage latch circuit, and the drain of the PMOS transistor 1502 is coupled to Connect to the input node of inverter 1508. The gate of the NMOS transistor 1506 receives the test enable signal STE, the drain of the NMOS transistor 1506 is connected to the output node N2 of the previous stage latch circuit, and the source of the NMOS transistor 1506 is coupled to the input node of the inverter 1508 .

When the MBFF 1000 operates in the test mode (STE=1 & STEB=0), the transmission gate composed of the PMOS transistor 1502 and the NMOS transistor 1506 is enabled, and the PMOS transistor 1504 is turned off, thereby enabling the scan output terminal The voltage level of the scan output signal at SQ changes in response to the voltage level of the signal at the output node N2 of the latch circuit of the preceding stage. When the MBFF 1000 is operating in the normal mode (STE=0 & STEB=1), the transmission gate composed of the PMOS transistor 1502 and the NMOS transistor 1506 is disabled, and the PMOS transistor 1504 is turned on, so that the scan output terminal SQ The voltage level of the scan-out signal of the scan output signal is maintained at a fixed voltage level (for example, ground voltage) regardless of the voltage level of the signal at the output node N2 of the previous-stage latch circuit.

Fig. 16 is a diagram showing a fifth alternative design of a scan output stage circuit with hold function according to an embodiment of the present invention. For example, scan output stage circuit 1600 may be used to implement scan output stage circuit 1004 . The scan output stage circuit 1600 includes NMOS transistors 1602 and 1604 , a PMOS transistor 1606 and an inverter 1608 . The gate of the NMOS transistor 1604 receives the test enable signal STEB, the source of the NMOS transistor 1604 is coupled to a reference voltage (eg, ground voltage), and the drain of the NMOS transistor 1604 is coupled to the input node of the inverter 1608 . PMOS transistor 1606 and NMOS transistor 1602 form a transmission gate. The gate of the PMOS transistor 1606 receives the test enable signal STEB, the source of the PMOS transistor 1606 is coupled to the output node N2 of the previous stage latch circuit, and the drain of the PMOS transistor 1606 is coupled to the inverter 1608 Enter the node. The gate of the NMOS transistor 1602 receives the test enable signal STE, the drain of the NMOS transistor 1602 is connected to the output node N2 of the previous stage latch circuit, and the source of the NMOS transistor 1602 is coupled to the input node of the inverter 1608 .

When MBFF 1000 is operating in test mode (STE=1 & STEB=0), the transmission gate consisting of PMOS transistor 1606 and NMOS transistor 1602 is enabled, and NMOS transistor 1604 is turned off is turned off so that the voltage level of the scan output signal at the scan output terminal SQ changes in response to the voltage level of the signal at the output node N2 of the latch circuit of the preceding stage. When the MBFF 1000 operates in the normal mode (STE=0 & STEB=1), the transmission gate composed of the PMOS transistor 1606 and the NMOS transistor 1602 is disabled, and the NMOS transistor 1604 is turned on, so that the scan output terminal SQ The scan output signal of the 10 is maintained at a fixed voltage level (for example, the power supply voltage) regardless of the voltage level of the signal at the output node N2 of the latch circuit of the previous stage.

The MBFF 1000 with N flip-flops 1002_1 - 1002_N connected to form the internal scan chain 104 is designed with power-saving features. For example, when MBFF 1000 receives external test signal S11 at scan input terminal SI, MBFF 1000 transmits external test signal S11 through internal scan chain 104 to generate scan output signal SN5 output from flip-flop 1002_N to scan output terminal SQ, and And the voltage level of the scan output signal SN5 changes in response to the voltage level of the external test signal S11, and maintains N data output signals (output from N flip-flops 1002_1-1002_N to N data output terminals Q1-QN) Each of is a fixed voltage level regardless of the voltage level of the external test signal S11. Since there is no signal level conversion for the N data output signals in the test mode of the MBFF 1000, the power consumption of the MBFF 1000 and downstream combinatorial logic can be reduced.

In addition, when the data signal SN0 is received at the data input terminal DN, the MBFF 1000 generates the data output signal SN4 output from the flip-flop 1002_N to the data output terminal QN, and the voltage level of the data output signal SN4 responds to the voltage level of the data signal SN0. The voltage level is changed, and the scan output signal SN5 (output from the flip-flop 1002_N to the scan output terminal SQ) is maintained at a fixed voltage level regardless of the voltage level of the data signal SN0. Since there is no signal level conversion of the scan output signal in the normal mode of the MBFF 1000, the power consumption of the MBFF 1000 and downstream logic can be reduced.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. , so the protection scope of the present invention should be regarded as defined by the scope of the patent application as allow.

100: Multi-bit flip-flops

D1, D2, DN: data input terminals

SI: scan input terminal

SE: Test enable terminal

CLK: clock input terminal

102_1, 102_2, 102_N: Trigger

210_1, 210_2, 212: data output stage circuit

INT2,INTN,S11,INT3: test signal

Q1, Q2, QN: data output terminals

SCK, CLKB, CLK1: clock signal

STE, STEB: test enable signal

S10, S20, SN0: data signal

202: clock generation circuit

204: Signal generation circuit

206_1, 206_2, 206_N: selection circuit

S12, S22, SN2: input signal

208_1, 208_2, 208_N: latch circuit

N1: output node

S13, S23, SN3: signal

S14, S24, SN4: data output signal

211: NOR gate

213: Inverter

Claims (12)

A multi-bit flip-flop comprising: a plurality of flip-flops connected to form an internal scan chain, wherein the plurality of flip-flops includes a first flip-flop arranged to be output at a first data output of the multi-bit flip-flop A first data output signal is output at the terminal, and the first flip-flop includes: a first selection circuit arranged to send the first data signal or the first test signal at the first data input terminal of the multi-bit flip-flop to an output node of said first selection circuit as a first input signal; a first latch circuit, coupled to said output node of said first selection circuit, arranged to generate a first signal; and a first data output stage circuit arranged to receive said first signal and generate said first data output signal based on said first signal; wherein, when said multi-bit flip-flop is operating in a test mode , the first selection circuit is arranged to transmit the first test signal to the output node of the first selection circuit as the first input signal, and the first data output stage circuit is arranged to maintain the first data output signal at a fixed voltage level regardless of the voltage level of the first test signal; the plurality of flip-flops further includes a second flip-flop arranged as A second data output signal or a scan output signal is output at a second data output terminal, and the second flip-flop includes: a second selection circuit arranged to switch the multi-bit flip-flop to The second data signal at the second data input terminal of the bit flip-flop is sent to the output node of the second selection circuit as the second input signal, or when the multi-bit flip-flop is operating in the test mode, the second test a signal is sent to an output node of the second selection circuit as the second input signal; a second latch circuit, coupled to the output node of the second selection circuit, is arranged to operate according to the second the input signal generates a second signal; and The second data output stage circuit is arranged to receive the second signal and generate a second data output signal or a scan output signal according to the second signal, wherein when the multi-bit flip-flop is in the normal mode In operation, the second data output stage circuit generates a second data output signal according to the second signal and outputs the second data output signal at the second data output terminal, when the multi-bit flip-flop is in When operating in the test mode, the second data output stage circuit generates a scan output signal according to the second signal and outputs the scan output signal at the second data output terminal. The multi-bit flip-flop according to claim 1, wherein a test enable signal is received at a test enable terminal of the multi-bit flip-flop, and the first data output stage circuit is further arranged to be controlled by the test The enable signal controls to generate the first data output signal according to the first signal. According to the multi-bit flip-flop according to claim 1, wherein the first data output stage circuit is further arranged to receive a second test enable signal, the second test enable signal is in the multi-bit flip-flop The inversion of the first test enable signal received at the test enable terminal of the test enable terminal, and is controlled by the second test enable signal to generate the first data output signal according to the first signal. The multi-bit flip-flop according to claim 1, wherein a first test enable signal is received at the test enable terminal of the multi-bit flip-flop, and the first test enable signal is inverted via an inverter obtaining a second test enable signal, the first data output stage circuit is further arranged to be controlled by the first test enable signal and the second test enable signal to generate the first test enable signal according to the first signal A data output signal. The multi-bit flip-flop according to claim 1, wherein the first test signal is an external test signal received at a scan input terminal of the multi-bit flip-flop. The multi-bit flip-flop according to claim 1, wherein the plurality of flip-flops further includes a third flip-flop arranged to output a third data output signal at a third data output terminal of the multi-bit flip-flop, The third flip-flop includes a third selection circuit arranged to send a third data signal or a third test signal at a third data input terminal of the multi-bit flip-flop to a third selection circuit of the third selection circuit. an output node as a third input signal; a third latch circuit, coupled to the output node of the third selection circuit, and arranged to generate the first test signal and the third test signal according to the third input signal signal; and a third data output stage circuit arranged to receive said third signal and generate said third data output signal from said third signal. The multi-bit flip-flop according to claim 6, wherein when the multi-bit flip-flop is operating in the test mode, the third selection circuit is arranged to transmit the third test signal to the The output node of the third selection circuit is used as the third input signal, and the third data output stage circuit is arranged to output the third data output signal regardless of the voltage level of the third test signal maintained at a fixed voltage level. The multi-bit flip-flop according to claim 7, wherein the third data output stage circuit is further arranged to receive a test enable signal at the test enable terminal of the multi-bit flip-flop, and the test The enable signal controls to generate the third data output signal according to the third signal. According to the multi-bit flip-flop according to claim 7, wherein, the third data output stage circuit is further arranged to receive a second test enable signal, and the second test enable signal is in the multi-bit trigger The inversion of the first test enable signal received at the test enable terminal of the device, and is controlled by the second test enable signal to generate the third data output signal according to the third signal. The multi-bit flip-flop according to claim 7, wherein a first test enable signal is received at the test enable terminal of the multi-bit flip-flop, and the first test enable signal is inverted via an inverter obtaining a second test enable signal, the third data output stage circuit is further arranged to be controlled by the first test enable signal and the second test enable signal to generate the first test enable signal according to the third signal Three data output signals. The multi-bit flip-flop according to claim 1, wherein the first latch circuit is further arranged to generate a third test signal according to the first input signal, and the plurality of flip-flops further includes a third trigger is arranged to output a third data output signal at a third data output terminal of the multi-bit flip-flop, the third flip-flop includes: a third selection circuit arranged to output a third data output signal of the multi-bit flip-flop The third data signal at the third data input terminal or the third test signal obtained from the first latch circuit is sent to the output node of the third selection circuit as a third input signal; the third latch a circuit coupled to the output node of the third selection circuit and generating a third signal based on the third input signal; and a third data output stage circuit arranged to receive the third signal and generate a third signal based on The third signal generates the third data output signal. A control method applied to a multi-bit flip-flop connected with N flip-flops to form an internal scan chain, wherein the multi-bit flip-flop includes a scan input terminal coupled to one of the N flip-flops, coupled to connected to the N data input terminals of the N flip-flops, and respectively coupled to the N flip-flops N data output terminals of the multi-bit flip-flop, wherein N is a positive integer not less than 1, and the control method includes: when the multi-bit flip-flop operates in the normal mode, responding to the multi-bit flip-flop in the N data signals are received at the N data input terminals, and N data output signals having voltage levels varying with the voltage levels of the N data signals are generated, wherein the N data output signals are obtained from the N flip-flops output to the N data output terminals; when the multi-bit flip-flop operates in a test mode, in response to receiving an external test signal at the scan input terminal of the multi-bit flip-flop, passing the external test signal through the internal scan chain; generating a scan-out signal having a voltage level that varies with the voltage level of the external test signal, wherein the scan-out signal is derived from the N flip-flops one of the N data output terminals is output to one of the N data output terminals; and regardless of the voltage level of the external test signal, all the remaining (N-1) data output terminals in the N data output terminals are Each of the (N-1) data output signals is maintained at a fixed voltage level.

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