CN113659964A

CN113659964A - Multi-bit flip-flop and control method thereof

Info

Publication number: CN113659964A
Application number: CN202110437732.7A
Authority: CN
Inventors: 池其辉; 邱怡洪
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2020-05-12
Filing date: 2021-04-22
Publication date: 2021-11-16
Also published as: TWI796672B; TW202143643A

Abstract

The present invention provides a multi-bit flip-flop and a method of controlling the same, the multi-bit flip-flop comprising a first flip-flop arranged to output a first data output signal, the first flip-flop comprising: a first selection circuit arranged to send a first data signal or a first test signal to an output node of the first selection circuit as a first input signal; a first latch circuit arranged to generate a first signal from the first input signal; and a first data output stage circuit arranged to generate a first data output signal in dependence on the first signal; when the multi-bit flip-flop operates in a test mode, the first selection circuit transmits the first test signal to the output node of the first selection circuit as the first input signal, and the first data output stage circuit maintains a first data output signal at a fixed voltage level. The embodiment of the invention can reduce power consumption.

Description

Multi-bit flip-flop and control method thereof

Technical Field

The present invention relates to a flip-flop (flip-flop) design, and more particularly, to a multi-bit flip-flop having a power saving characteristic and a method for controlling the same.

Background

Scan chains are used to detect various manufacturing faults in combinational logic blocks during the testing process. In general, the scan chain is composed of a plurality of flip-flops connected in series, and a data output terminal of each flip-flop is connected to the combinational logic circuit in the normal mode for normal data transfer. However, in the test mode, the data output terminal of each flip-flop still has data transmission, and therefore the combinational logic circuit is still operating, resulting in unnecessary power consumption.

Disclosure of Invention

The invention provides a multi-bit trigger and a control method thereof, which can reduce power consumption.

The invention provides a multi-bit flip-flop which comprises: a plurality of flip-flops connected to form an internal scan chain, wherein the plurality of flip-flops comprises a first flip-flop arranged to output a first data output signal at a first data output terminal of the multi-bit flip-flop, the first flip-flop comprising: a first selection circuit arranged to send a first data signal or a first test signal at a first data input terminal of the multi-bit flip-flop to an output node of the first selection circuit as a first input signal; a first latch circuit coupled to the output node of the first selection circuit arranged to generate a first signal from the first input signal; and a first data output stage circuit arranged to receive the first signal and to generate the first data output signal in dependence on the first signal; wherein, when the multi-bit flip-flop operates in a test mode, the first selection circuit is arranged to transmit the first test signal to the output node of the first selection circuit as the first input signal, and the first data output stage circuit is arranged to maintain the first data output signal at a fixed voltage level regardless of the voltage level of the first test signal.

The control method provided by the invention is applied to a multi-bit flip-flop connected with N flip-flops to form an internal scan chain, wherein the multi-bit flip-flop comprises a scan input terminal coupled to one of the N flip-flops and N data output terminals respectively coupled to the N flip-flops, wherein N is a positive integer not less than 1, and the control method comprises the following steps: passing an external test signal through the internal scan chain in response to receiving the external test signal at the scan input terminal of the multi-bit flip-flop; generating a scan output signal having a voltage level that varies with a voltage level of the external test signal, wherein the scan output signal is output from one of the N flip-flops to one of the N data output terminals; and maintaining each of the (N-1) data output signals at a fixed voltage level regardless of a voltage level of the external test signal, wherein the (N-1) data output signals are respectively output from the remaining (N-1) flip-flops of the N flip-flops to the remaining (N-1) output terminals of the N data output terminals.

The other control method provided by the invention is applied to a multi-bit flip-flop connected with N flip-flops to form an internal scan chain, wherein the multi-bit flip-flop comprises a scan input terminal coupled to one of the N flip-flops, a scan output terminal coupled to the other one of the N flip-flops, and N data output terminals respectively coupled to the N flip-flops, wherein N is a positive integer not less than 1; the control method comprises the following steps: passing an external test signal through the internal scan chain in response to receiving the external test signal at the scan input terminal of the multi-bit flip-flop; generating a scan output signal having a voltage level that varies with a voltage level of the external test signal, wherein the scan output signal is output from the other flip-flop of the N flip-flops to the scan output terminal; and maintaining the N data output signals at fixed voltage levels regardless of voltage levels of the external test signal, the N data output signals being output from the N flip-flops to N data output terminals of the multi-bit flip-flop, respectively.

As described above, the embodiments of the present invention maintain the data output signal at a fixed voltage level in the case of receiving the test signal, thereby reducing power consumption.

Drawings

Fig. 1 is a schematic diagram illustrating a first multi-bit flip-flop (MBFF) having a power saving characteristic according to an embodiment of the present invention.

Fig. 2 is a diagram illustrating a first circuit design of an MBFF according to an embodiment of the invention.

Fig. 3 is a diagram illustrating a first alternative design of a data output stage circuit with a retention function according to an embodiment of the present invention.

Fig. 4 is a diagram showing a second alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention.

Fig. 5 is a diagram showing a third alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention.

Fig. 6 is a diagram showing a fourth alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention.

Fig. 7 is a diagram showing a fifth alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention.

Fig. 8 is a schematic diagram illustrating a second MBFF having a power saving characteristic according to an embodiment of the present invention.

FIG. 9 is a diagram illustrating a second circuit design of an MBFF according to an embodiment of the invention.

Fig. 10 is a schematic diagram showing a third MBFF having a power saving characteristic according to an embodiment of the present invention.

Fig. 11 is a diagram showing a third circuit design of an MBFF according to an embodiment of the invention.

Fig. 12 is a diagram illustrating a first alternative design of a scanout stage circuit with a hold function according to an embodiment of the present invention.

Fig. 13 is a diagram illustrating a second alternative design of a scanout stage circuit with a hold function according to an embodiment of the present invention.

Fig. 14 is a diagram illustrating a third alternative design of a scanout stage circuit with a hold function according to an embodiment of the present invention.

Fig. 15 is a diagram showing a fourth alternative design of a scanout stage circuit having a hold function according to an embodiment of the present invention.

Fig. 16 is a diagram showing a fifth alternative design of a scanout stage circuit having a hold function according to an embodiment of the present invention.

Detailed Description

Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This specification and claims do not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. "substantially" means within an acceptable error range, within which a person skilled in the art can solve the technical problem to substantially achieve the technical result. Furthermore, the term "coupled" is intended to include any direct or indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. The following is a preferred embodiment of the invention for the purpose of illustrating the spirit of the invention and not for the purpose of limiting the scope of the invention, which is defined by the claims.

The following description is of the best embodiments contemplated by the present invention. The description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention should be determined with reference to the claims that follow.

Fig. 1 is a schematic diagram showing a first Multi-Bit Flip-Flop (MBFF) having a power saving characteristic according to an embodiment of the present invention. In this embodiment, MBFF100 is an N-bit scan flip-flop, where N is a positive integer no less than 1 (i.e., N ≧ 2). The circuit layout of the MBFF100 may be one cell (cell) in a cell library used by an Integrated Circuit (IC) design. As shown in FIG. 1, MBFF100 has N data input terminals D1, D2,. D (N-1) and DN, a scan input terminal SI, a test enable terminal SE, a clock input terminal CLK, and N data output terminals Q1, Q2, …, Q (N-1) and QN. In addition, MBFF100 includes N Flip-flops (FF) 102_1, 102_2, …, 102_ (N-1) and 102_ N connected together to form an internal scan chain 104, i.e., a scan chain formed by internally stitching Flip-flops 102_1-102_ N as shown by the dashed lines. When MBFF100 is operating in the normal mode, data input terminals D1-DN are used to receive data signals and are coupled to flip-flops 102_1-102_ N, respectively. When MBFF100 is operating in the normal mode, data output terminals Q1-QN are used to output data output signals and are coupled to flip-flops 102_1-102_ N, respectively. The scan-in terminal SI is used for receiving an external test signal, and the external test signal at the scan-in terminal SI is transmitted through the internal scan chain 104, wherein the test signal (n ≠ 1) of the current flip-flop 102_ n is an internal test signal obtained from the previous flip-flop 102_ (n-1). For example, the test signal INT2 of the flip-flop 102_2 is obtained from the flip-flop 102_1, the test signal INT3 of another flip-flop (not shown) is obtained from the flip-flop 102_2, the test signal INT (N-1) of the flip-flop 102_ N (N-1) is obtained from another flip-flop (not shown), and the test signal INTN of the flip-flop 102_ N is obtained from the flip-flop 102_ N (N-1). Each of the flip-flops 102_1-102_ (N-1) has a data output stage circuit (labeled "L1") 210_1, 210_2, …, 210_ (N-1) with a retention function that is enabled in the test mode and disabled in the normal mode.

In the case where the MBFF100 operates in the normal mode, the data output stage circuit 210_1 generates and outputs a data output signal to the data output terminal Q1, wherein the voltage level of the data output signal changes in response to the voltage level of the data signal at the data input terminal D1; the data output stage circuit 210_2 generates and outputs a data output signal to the data output terminal Q2, wherein a voltage level of the data output signal changes in response to a voltage level of the data signal at the data input terminal D2; the data output stage circuit 210_ (N-1) generates and outputs a data output signal, the voltage level of which changes in response to the voltage level of the data signal at the data input terminal D (N-1), to the data output terminal Q (N-1). Further, the data output terminal QN is shared by the normal data transmission and the test data transmission. Accordingly, the flip-flop 102_ N generates and outputs a data output signal to the data output terminal QN, wherein a voltage level of the data output signal changes in response to a voltage level of the data signal at the data input terminal DN.

In another case where the MBFF100 operates in the test mode, the data output stage circuit 210_1 generates and outputs a data output signal to the data output terminal Q1, wherein the voltage level of the data output signal is maintained at a fixed voltage level regardless of the voltage level of the test signal at the scan input terminal SI; the data output stage circuit 210_2 generates and outputs a data output signal to the data output terminal Q2, wherein the voltage level of the data output signal is maintained at a fixed voltage level regardless of the test signal INT2 obtained from the flip-flop 102_ 1; the data output stage circuit 210_ (N-1) generates and outputs a data output signal to the data output terminal Q (N-1), wherein the voltage level of the data output signal is maintained at a fixed voltage level regardless of the voltage level of the test signal INT (N-1) obtained from the previous stage flip-flop (not shown). Further, the data output terminal QN is shared by the normal data transmission and the test data transmission. Accordingly, the flip-flop 102_ N generates and outputs a scan-out signal to the data output terminal QN, wherein the voltage level of the scan-out signal changes in response to the voltage level of the test signal INTN (which is obtained by the transmission of the external test signal at the scan-in terminal S1 in the internal scan chain 104).

Fig. 2 is a diagram illustrating a first circuit design of an MBFF according to an embodiment of the invention. By way of example and not limitation, the MBFF100 shown in fig. 1 may be implemented using the circuit architecture shown in fig. 2. In addition to the flip-flops 102_1-102_ N, the MBFF100 may also include a signal generation circuit 204 and a clock generation circuit 202. The signal generation circuit 204 receives the test enable signal STE, which is an external test enable signal, to generate another test enable signal STEB, which is inverted (inverse) from the test enable signal STE. In the embodiment of fig. 2, the signal generation circuit 204 includes an inverter. In other embodiments, the signal generation circuit 204 may be implemented by any other circuit structure capable of receiving the test enable signal STE and generating the test enable signal STEB that is inverted from the test enable signal STE.

The clock generation circuit 110 receives a clock signal SCK (which is an external clock signal received via a clock terminal CK), and generates clock signals CLKB and CLK1 from the clock signal SCK, where the clock signal CLKB is an inverse of the clock signal SCK and the clock signal CLK1 is an inverse of the clock signal CLKB. In the embodiment of fig. 2, the clock generation circuit 202 includes two inverters. In other embodiments, clock generation circuit 202 may be implemented by any other circuit structure capable of receiving clock signal SCK, generating clock signal CLKB that is inverted from clock signal SCK, and generating clock signal CLK1 that is inverted from clock signal CLKB.

Each of the flip-flops 102_1-102_ (N-1) may have the same circuit configuration. For example, the flip-flop 102_1 is arranged to output a data output signal S14 at the data output terminal Q1 of the MBFF100, which includes the select circuit 206_1, the latch circuit 208_1, and the data output stage circuit 210_ 1; the flip-flop 102_2 is arranged to output a data output signal S24 at the data output terminal Q2 of the MBFF100, which includes the selection circuit 206_2, the latch circuit 208_2, and the data output stage circuit 210_ 2. With respect to the flip-flop 102_1, the selection circuit 206_1 is arranged to send either the data signal S10 at the data input terminal D1 of the MBFF100 or the test signal S11 at the scan input terminal SI of the MBFF100 to the output node of the selection circuit 206_1 for use as the input signal S12; the latch circuit 208_1 is coupled to the output node of the selection circuit 206_1 and is arranged to generate a signal S13 from the input signal S12; the data output stage circuit 210_1 is arranged to receive the signal S13 and generate a data output signal S14 from the signal S13. In this embodiment, the selection circuit 206_1 may include an inverter and transmission gates, wherein each transmission gate includes a P-type transistor (e.g., a P-channel metal oxide semiconductor (PMOS) transistor) and an N-type transistor (e.g., an N-channel metal oxide semiconductor (NMOS) transistor) and is controlled by the test enable signals STE and STEB. In addition, the latch circuit 208_1 may include inverters and transmission gates, wherein each transmission gate is comprised of a P-type transistor (e.g., a PMOS transistor) and an N-type transistor (e.g., an NMOS transistor), and is controlled by the clock signals CLK1 and CLKB. Since the present invention does not focus on the circuit design of the selection circuit 206_1 and the latch circuit 208_1, those skilled in the art should easily understand the principle of the selection circuit 206_1 and the latch circuit 208_1 shown in fig. 2. Therefore, further description of the selection circuit 206_1 and the latch circuit 208_1 is omitted here for the sake of brevity.

The data output stage circuit 210_1 is equipped with a hold function that is enabled in the test mode of the MBFF100 and disabled in the normal mode of the MBFF 100. For example, when the MBFF100 operates in the normal mode, the selection circuit 206_1 sends the data signal S10 to the output node of the selection circuit 206_1 for use as the input signal S12, and the data output stage circuit 210_1 generates the data output signal S14, the data output signal S14 having a voltage level that varies in response to the voltage level of the data signal S10. Specifically, the voltage level of the data output signal S14 changes in response to the voltage level of the signal S13, wherein the voltage level of the signal S13 changes in response to the voltage level of the data signal S10. When the MBFF100 operates in the test mode, the selection circuit 206_1 sends the test signal S11 to the output node of the selection circuit 206_1 for use as the input signal S12, and the data output stage circuit 210_1 maintains the data output signal S14 at a fixed voltage level (e.g., a high voltage level or a low voltage level) regardless of the voltage level of the test signal S11. Specifically, the voltage level of the data output signal S14 does not change in response to the voltage level of the signal S13, and the voltage level of the signal S13 changes in response to the voltage level of the test signal S11.

In contrast to the first flip-flop 102_1 receiving the test signal S11 through the scan-in terminal SI, the subsequent flip-flop 102_2 receives the test signal INT2 obtained from the previous stage flip-flop 102_1 (particularly, the latch circuit 208_1 of the flip-flop 102_ 1). With respect to the flip-flop 102_2, the selection circuit 206_2 is arranged to send a data signal S20 at the data input terminal D2 of the MBFF100 or a test signal INT2 obtained from the latch circuit 208_1 to an output node of the selection circuit 206_2 as an input signal S22; the latch circuit 208_2 is coupled to the output node of the selection circuit 206_2 and is arranged to generate a signal S23 from the input signal S22. The data output stage circuit 210_2 is arranged to receive the signal S23 and generate a data output signal S24 from the signal S23. Similarly, the data output stage circuit 210_2 is equipped with the same retention function that is enabled in the test mode of the MBFF100 and disabled in the normal mode of the MBFF 100.

The last flip-flop 102_ N is arranged to generate an output signal SN4 on the data output terminal QN of the MBFF100, which includes a selection circuit 206_ N, a latch circuit 208_ N and an output stage circuit 212. The output stage circuit 212 is implemented using an inverter 213. The selection circuit 206_ N is arranged to send a data signal SN0 at the data input terminal DN of the MBFF100 or a test signal INTN obtained from a previous stage flip-flop to an output node of the selection circuit 206_ N as an input signal SN 2. The latch circuit 208_ N is coupled to an output node of the selection circuit 206_ N and is arranged to generate the signal SN3 from the input signal SN 2. The output stage circuit 212 is arranged to receive the signal SN3 and to generate an output signal SN4 from the signal SN 3. In this embodiment, the data output terminal QN is shared by the normal data transmission and the test data transmission. When the MBFF100 operates in the normal mode, the selection circuit 206_ N sends the data signal SN0 to the output node of the selection circuit 206_ N for use as the input signal SN2, and the output stage circuit 212 generates the output signal SN4 as a data output signal having a voltage level that changes in response to the voltage level of the data signal SN 0. Specifically, the voltage level of the output signal SN4 (data output signal) changes in response to the voltage level of the signal SN3, where the voltage level of the signal SN3 changes in response to the voltage level of the data signal SN 0. When the MBFF100 operates in the test mode, the selection circuit 206_ N sends the test signal INTN to the output node of the selection circuit 206_ N to serve as the input signal SN2, and the output stage circuit 212 generates the output signal SN4 as a scan output signal having a voltage level that changes in response to the voltage level of the test signal INTN. Specifically, the voltage level of the output signal SN4 (scan output signal) changes in response to the voltage level of the signal SN3, wherein the voltage level of the signal SN3 changes in response to the voltage level of the test signal INTN.

In this embodiment, each data output stage circuit having a hold function may be implemented using a NOR (NOR) gate 211, in which one input node of the NOR gate 211 is arranged to receive an output signal of a previous stage latch circuit, the other input node of the NOR gate 211 is arranged to receive a test enable signal STE, and the output node of the NOR gate 211 is arranged to output a data output signal to a data output terminal of the MBFF 100. Taking the data output stage 210_1 as an example, one input node of the NOR gate 211 receives the signal S13 at the output node N1 of the latch circuit 208_1, the other input node of the NOR gate 211 receives the test enable signal STE, and the output node of the NOR gate 211 outputs the data output signal S14 to the data output terminal Q1 of the MBFF 100. When the MBFF100 operates in the normal mode (STE ═ 0), the voltage level of the data output signal S14 changes in response to the voltage level of the signal S13. Specifically, the data output signal S14 is an inverse of the signal S13, where the signal S13 is an inverse of the data signal S10. When the MBFF100 operates in the test mode (STE ═ 1), the voltage level of the data output signal S14 is maintained at a fixed voltage level (e.g., ground voltage) regardless of the voltage level of the test signal S11. Specifically, the voltage level of the data output signal S14 does not change in response to the voltage level of the signal S13, where the signal S13 is an inverse of the test signal S11.

The circuit configuration shown in fig. 2 is for illustrative purposes only and is not meant to limit the present invention. For example, the selection circuit may be implemented by any other circuit configuration capable of selecting one of the normal data input and the test data input as an input signal of the subsequent latch circuit. For another example, the latch circuit may be implemented by any other circuit configuration capable of processing an input signal obtained from a previous-stage selection circuit to generate a signal and outputting the generated signal to a subsequent-stage data output stage circuit having a hold function. For another example, the data output stage circuit having the hold function may be implemented by any other circuit structure capable of holding the data output signal at a fixed voltage level when the MBFF operates in the test mode.

Fig. 3 is a diagram showing a first alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1-210_ (N-1) may be implemented using the data output stage circuit 300. The data output stage circuit 300 employs an OR gate 302, one of input nodes of the OR gate 302 being coupled to the output node N1 of the previous stage latch circuit, the other input node of the OR gate 302 being arranged to receive the test enable signal STE, the output node of the OR gate 302 being arranged to output a data output signal to the data output terminal Qn of the MBFF100, where N is a positive integer selected from the range of 1 to (N-1). When the MBFF100 operates in the normal mode (STE ═ 0), the voltage level of the data output signal generated by the OR gate 302 changes in response to the voltage at the output node N1 of the preceding stage latch circuit. When the MBFF100 operates in the test mode (STE ═ 1), the data output signal generated by the OR gate 302 is held at a fixed voltage level (e.g., the power supply voltage) regardless of the voltage of the signal at the output node N1 of the previous stage latch circuit.

Fig. 4 is a diagram showing a second alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1-210_ (N-1) may be implemented using the data output stage circuit 400. The data output stage circuit 400 employs a NAND (NAND) gate 402, one of the input nodes of the NAND gate 402 is coupled to the output node N1 of the previous stage latch circuit, the other input node of the NAND gate 402 is arranged to receive a test enable signal STEB, and the output node of the NAND gate 402 is arranged to output a data output signal to the data output terminal Qn of the MBFF100, where N is a positive integer selected from the range of 1 to (N-1). When the MBFF100 operates in the normal mode (step ═ 1), the voltage level of the data output signal generated by the NAND gate 402 changes in response to the voltage of the signal at the output node N1 of the preceding stage latch circuit. When the MBFF100 operates in the test mode (step ═ 0), the data output signal generated by the NAND gate 402 is held at a fixed voltage level (e.g., the power supply voltage) regardless of the voltage of the signal at the output node N1 of the previous stage latch circuit.

Fig. 5 is a diagram showing a third alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1-210_ (N-1) may be implemented using the data output stage circuit 500. The data output stage circuit 500 employs an AND (AND) gate 502, one of input nodes of the AND gate 502 is coupled to the output node N1 of the previous stage latch circuit, the other input node of the AND gate 502 is arranged to receive the test enable signal STEB, AND the output node of the AND gate 502 is arranged to output a data output signal to the data output terminal Qn of the MBFF100, where N is a positive integer selected from the range of 1 to (N-1). When the MBFF100 operates in the normal mode (STEB ═ 1), the voltage level of the data output signal generated by the AND gate 502 changes in response to the voltage of the signal at the output node N1 of the preceding stage latch circuit. When MBFF100 operates in the test mode (STEB ═ 0), the data output signal generated by AND gate 502 is maintained at a fixed voltage level (e.g., ground voltage) regardless of the signal voltage at output node N1 of the previous stage latch circuit.

Fig. 6 is a diagram showing a fourth alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1-210_ (N-1) may be implemented using the data output stage circuit 600. The data output stage circuit 600 includes

PMOS transistors

602 and 604, NMOS transistor 606, and inverter 608. The gate (gate) of the PMOS transistor 604 receives the test enable signal STEB, the source (source) of the PMOS transistor 604 is coupled to a reference voltage (e.g., a power supply voltage), and the drain (drain) of the PMOS transistor 604 is coupled to the input node of the inverter 608. The PMOS transistor 602 and the NMOS transistor 606 form a transmission gate. The gate of the PMOS transistor 602 receives the test enable signal STE, the source of the PMOS transistor 602 is coupled to the output node N1 of the previous stage latch circuit, and the drain of the PMOS transistor 602 is coupled to the input node of the inverter 608. The gate of the NMOS transistor 606 receives the test enable signal STEB, the drain of the NMOS transistor 606 is coupled to the output node N1 of the previous stage latch circuit, and the source of the NMOS transistor 606 is coupled to the input node of the inverter 608.

When the MBFF100 operates in the normal mode (STE 0& STEB 1), the transfer gate composed of the PMOS transistor 602 and the NMOS transistor 606 is enabled, and the PMOS transistor 604 is turned off (turn off), so that the level voltage of the data output signal at the data output terminal Qn (N is a positive integer from 1 to (N-1)) varies in response to the voltage level of the signal at the output node N1 of the previous stage latch circuit. When the MBFF100 operates in the test mode (STE ═ 1& STEB ═ 0), the transmission gate composed of the PMOS transistor 602 and the NMOS transistor 606 is disabled, and the PMOS transistor 604 is turned on (turn on), thereby keeping the voltage level of the data output signal at the data output terminal Qn at a fixed voltage level (for example, ground voltage) regardless of the voltage level of the signal at the output node N1 of the preceding stage latch circuit.

Fig. 7 is a diagram showing a fifth alternative design of a data output stage circuit with a hold function according to an embodiment of the present invention. For example, one or more of the data output stage circuits 210_1-210_ (N-1) may be implemented using the data output stage circuit 700. The data output stage circuit 700 includes

NMOS transistors

702 and 704, a PMOS transistor 706, and an inverter 708. The gate of the NMOS transistor 704 receives the test enable signal STE, the source of the NMOS transistor 704 is coupled to a reference voltage (e.g., ground voltage), and the drain of the NMOS transistor 704 is coupled to the input node of the inverter 708. PMOS transistor 706 and NMOS transistor 702 form a transmission gate. The gate of the PMOS transistor 706 receives the test enable signal STE, the source of the PMOS transistor 706 is coupled to the output node N1 of the previous stage latch circuit, and the drain of the PMOS transistor 706 is coupled to the input node of the inverter 708. The gate of the NMOS transistor 702 receives the test enable signal STEB, the drain of the NMOS transistor 702 is connected to the output node N1 of the previous-stage latch circuit, and the source of the NMOS transistor 702 is coupled to the input node of the inverter 708.

When the MBFF100 operates in the normal mode (STE 0& STEB 1), the transfer gate composed of the PMOS transistor 706 and the NMOS transistor 702 is enabled, and the NMOS transistor 704 is turned off, so that the voltage level of the data output signal at the data output terminal Qn (N is a positive integer from 1 to (N-1)) changes in response to the voltage level of the signal at the output node N1 of the previous stage latch circuit. When the MBFF100 operates in the test mode (STE ═ 1& STEB ═ 0), the transmission gate composed of the PMOS transistor 706 and the NMOS transistor 702 is disabled, and the NMOS transistor 704 is turned on, thereby keeping the voltage level of the data output signal at the data output terminal Qn at a fixed voltage level (e.g., the power supply voltage) regardless of the voltage level of the signal at the output node N1 of the preceding latch circuit.

MBFF100, having N flip-flops 102_1-102_ N connected to form an internal scan chain 104, is designed to have power saving characteristics. For example, when the external test signal S11 is received at the scan-in terminal SI in the test mode, the MBFF100 transmits the external test signal S11 through the internal scan chain 104 and generates the scan-out signal SN4, the scan-out signal SN4 is output from the flip-flop 102_ N to the data-out terminal QN, and the voltage level of the scan-out signal SN4 changes in response to the voltage level of the external test signal S11, and each of the (N-1) data-out signals (output from the flip-flops 102_1-102_ (N-1) to the output terminal Q1-Q (N-1), respectively) is maintained at a fixed voltage level regardless of the voltage level of the external test signal S11. Since there is no signal level transition for the (N-1) data output signals in the test mode of MBFF100, the power consumption of MBFF100 and downstream combinational logic can be reduced.

In the embodiment shown in fig. 1 and 2, MBFF100 has a data output terminal QN shared by normal data transfer and test data transfer. However, this is for illustrative purposes only and is not meant to be a limitation of the present invention. In an alternative design, the MBFF may be configured with an additional terminal that serves as a dedicated scan-out terminal for outputting scan-out signals.

Fig. 8 is a schematic diagram illustrating a second MBFF having a power saving characteristic according to an embodiment of the present invention. In this embodiment, MBFF800 is an N-bit scan flip-flop, where N is a positive integer no less than 1 (i.e., N ≧ 2). The circuit layout of MBFF800 may be one cell in a cell library used by an IC design. As shown in FIG. 8, MBFF800 has N data input terminals D1, D2, …, D (N-1) and DN, a scan input terminal SI, a test enable terminal SE, a clock input terminal CLK, N data output terminals Q1, Q2, …, Q (N-1) and QN, and a scan output terminal SQ. In addition, MBFF800 includes N flip-flops (FFs) 802_1, 802_2, …, 802_ (N-1) and 802_ N, which are connected to form the internal scan chain 104. The main difference between

MBFFs

100 and 800 is that the flip-flop 802_ N of MBFF800 has a scan output terminal SQ for outputting a scan output signal when MBFF800 is operating in a test mode, and also has a data output stage circuit 210_ N (labeled "L1") with a retention function that is enabled in the test mode and disabled in the normal mode.

When the MBFF800 operates in the normal mode, the data output stage circuit 210_ N generates and outputs a data output signal to the data output terminal QN, wherein a voltage level of the data output signal changes in response to a voltage level of the data signal at the data input terminal DN. When the MBFF800 operates in the test mode, a scan output stage circuit (not shown) generates and outputs a scan output signal to the scan output terminal SQ, wherein a voltage level of the scan output signal changes in response to a voltage level of a data signal at the data input terminal DN. Further, the data output stage circuit 210_ N generates and outputs a data output signal to the data output terminal QN, wherein the voltage level of the data output signal is maintained at a fixed voltage level (e.g., a high voltage level or a low voltage level) regardless of the voltage level of the test signal INTN obtained from the previous stage flip-flop 802_ (N-1).

FIG. 9 is a diagram illustrating a second circuit design of an MBFF according to an embodiment of the invention. By way of example, and not limitation, MBFF800 shown in fig. 8 may be implemented using the circuit architecture shown in fig. 9. Each of the flip-flops 802_1 to 802_ (N-1) may have the same circuit configuration as that shown in fig. 2. For the sake of brevity, similar descriptions are omitted. As for the last flip-flop 802_ N, it is arranged to output a data output signal SN4 at the data output terminal QN of the MBFF800 and a scan output signal SN5 at the scan output terminal SQ of the MBFF 800. As shown in fig. 9, the flip-flop 802_ N includes the data output stage circuit 210_ N, the scan output stage circuit 902, and the selection circuit 206_ N and the latch circuit 208_ N described above. Like the output stage circuit 212 shown in fig. 2, the scanout stage circuit 902 is implemented by an inverter 213. Like the data output stage circuits 210_1 and 210_2, the data output stage circuit 210_ N is equipped with a retention function that is enabled in the test mode of the MBFF800 and disabled in the normal mode of the MBFF 800. When the MBFF800 operates in the normal mode, the selection circuit 206_ N sends the data signal SN0 to the output node of the selection circuit 206_ N to be used as the input signal SN2, and the data output stage circuit 210_ N generates the data output signal SN4, the voltage level of the data output signal SN4 changing in response to the voltage level of the data signal SN 0. Specifically, the voltage level of the data output signal SN4 changes in response to the voltage level of the signal SN3, where the voltage level of the signal SN3 changes in response to the voltage level of the data signal SN 0. When the MBFF800 operates in the test mode, the selection circuit 206_ N sends the test signal INTN to the output node of the selection circuit 206_ N to be used as the input signal SN2, and the data output stage circuit 210_ N keeps the data output signal SN4 at a fixed voltage level (e.g., a high voltage level or a low voltage level) regardless of the voltage level of the test signal INTN. Specifically, the voltage level of the data output signal SN4 does not change in response to the voltage level of the signal SN3, and the voltage level of the signal SN3 changes in response to the voltage level of the test signal INTN.

The circuit configuration shown in fig. 9 is for illustrative purposes only and is not meant to limit the present invention. For example, the selection circuit may be implemented by any other circuit configuration capable of selecting one of the normal data input and the test data input as an input signal of the subsequent latch circuit. For another example, the latch circuit may be implemented by any other circuit configuration capable of processing an input signal obtained from a previous-stage selection circuit to generate a signal and outputting the generated signal to a subsequent-stage data output stage circuit having a hold function. For another example, the data output stage circuit having the hold function may be implemented by any other circuit structure capable of holding the data output signal at a fixed voltage level when the MBFF operates in the test mode. Accordingly, one or more of the flip-flops 802_1-802_ N may be implemented using the data output stage circuit 300 shown in fig. 3, the data output stage circuit 400 shown in fig. 4, the data output stage circuit 500 shown in fig. 5, the data output stage circuit 600 shown in fig. 6, or the data output stage circuit 700 shown in fig. 7.

MBFF800, which has N flip-flops 802_1-802_ N connected to form internal scan chain 104, is designed to have power saving characteristics. For example, when the external test signal S11 is received at the scan-in terminal SI, the MBFF800 passes the external test signal S11 through the internal scan chain 104, generates the scan-out signal SN4 output from the flip-flop 802_ N to the scan-out terminal SQ, the voltage level of the scan-out signal SN4 varies in response to the voltage level of the external test signal S11, and maintains the voltage level of each of the N data-out signals (output from the N flip-flops 802_1 to 802_ N to the N output terminals Q1 to QN, respectively) at a fixed voltage level regardless of the external test signal S11. Since there is no signal level transition for the N data output signals in the test mode of MBFF800, the power consumption of MBFF800 and downstream combinational logic can be reduced.

In the embodiment shown in fig. 9, the scanout stage 902 does not have a hold function. As a result, when the MBFF800 operates in any one of the normal mode and the test mode, the voltage level of the scan output signal SN5 changes in response to the voltage level of the signal SN 3. In an alternative design, the MBFF may be configured as a scanout stage circuit with a hold function.

Fig. 10 is a schematic diagram showing a third MBFF having a power saving characteristic according to an embodiment of the present invention. In this embodiment, MBFF1000 is an N-bit scan flip-flop, where N is a positive integer no less than 1 (i.e., N ≧ 2). The circuit layout of MBFF1000 may be one cell in a cell library used by an IC design. As shown in fig. 10, the MBFF1000 has N data input terminals D1, D2, …, D (N-1) and DN, a scan input terminal SI, a test enable terminal SE, a clock input terminal CLK, N data output terminals Q1, Q2, …, Q (N-1) and QN, and a scan output terminal SQ. In addition, MBFF1000 includes N flip-flops (FFs) 1002_1, 1002_2, …, 1002_ (N-1), 1002_ N connected to form internal scan chain 104. The primary difference between MBFF1000 and MBFF800 is that the last flip-flop 1002_ N of MBFF1000 has a scanout stage circuit 1004 (labeled "L2") with a hold function that is enabled in the normal mode and disabled in the test mode.

When the MBFF1000 operates in the normal mode, the data output stage circuit 210_ N generates and outputs a data output signal to the data output terminal QN, wherein a voltage level of the data output signal changes in response to a voltage level of the data signal at the data input terminal DN; the scan output stage circuit 1004 generates and outputs a scan output signal to the scan output terminal SQ, wherein the voltage level of the scan output signal is maintained at a fixed voltage level (e.g., a high voltage level or a low voltage level) regardless of the voltage level of the data signal at the data input terminal DN.

When the MBFF1000 operates in the test mode, the scan output stage circuit 1004 generates and outputs a scan output signal whose voltage level varies in response to the voltage level of the test signal INTN obtained from the previous stage flip-flop 1002_ (N-1) to the scan output terminal SQ. The data output stage circuit 210_ N generates and outputs a data output signal, the voltage level of which is maintained at a fixed voltage level (e.g., a high voltage level or a low voltage level), to the data output terminal QN regardless of the voltage level of the test signal INTN obtained from the previous stage flip-flop 1002_ (N-1).

Fig. 11 is a diagram showing a third circuit design of an MBFF according to an embodiment of the invention. By way of example, and not limitation, MBFF1000 shown in fig. 10 may be implemented using the circuit structure shown in fig. 11. Each of the flip-flops 1002_1 to 1002_ (N-1) may have the circuit configuration shown in fig. 2 or fig. 9. Further description is omitted for the sake of brevity. With regard to the last flip-flop 1002_ N, it is arranged to output a data output signal SN4 at the data output terminal QN of the MBFF1000 and a scan output signal SN5 at the scan output terminal SQ of the MBFF 1000. The main difference between flip-flops 802_ N and 1002_ N is that flip-flop 1002_ N employs a scanout stage circuit 1004 having a retention function that is enabled in the normal mode of MBFF1000 and disabled in the test mode of MBFF 1000. When the MBFF1000 operates in the test mode, the selection circuit 206_ N sends the test signal INTN to the output node of the selection circuit 206_ N to serve as the input signal SN2, and the scan output stage circuit 1004 generates the scan output signal SN5, the scan output signal SN5 having a voltage level that changes in response to the voltage level of the test signal INTN. Specifically, the voltage level of the scan output signal SN5 changes in response to the voltage level of the signal SN3, wherein the voltage level of the signal SN3 changes in response to the voltage level of the test signal INTN. When the MBFF1000 operates in the normal mode, the selection circuit 206_ N sends the data signal SN0 to the output node of the selection circuit 206_ N for use as the input signal SN2, and the scanout stage circuit 1004 maintains the scanout signal SN5 at a fixed voltage level (e.g., a high voltage level or a low voltage level) regardless of the voltage level of the data signal SN 0. Specifically, the voltage level of the scan output signal SN5 does not change in response to the voltage level of the signal SN3, and the voltage level of the signal SN3 changes in response to the voltage level of the data signal SN 0.

Like the data output stage circuits 210_1, 210_2, and 210_ N, the scan output stage circuit 1004 is implemented by a NOR (NOR) gate, wherein one input node of the NOR gate is arranged to receive the signal SN3 at the output node N2 of the latch circuit 208_ N, the other input node of the NOR gate is arranged to receive the test enable signal STEB, and the output node of the NOR gate is arranged to output the scan output signal SN5 to the scan output terminal SQ of the MBFF 1000. Thus, when MBFF1000 is operating in normal mode (step ═ 1), the retention function is enabled at the NOR gate. When MBFF100 is operating in test mode (STEB ═ 0), the retention function is disabled at the NOR gate.

The circuit configuration shown in fig. 11 is for illustrative purposes only and is not meant to limit the present invention. For example, the selection circuit may be implemented by any other circuit configuration capable of selecting one of the normal data input and the test data input as an input signal of the subsequent latch circuit. For another example, the latch circuit may be implemented by any other circuit configuration capable of processing an input signal obtained from a previous-stage selection circuit to generate a signal and outputting the generated signal to a subsequent-stage data output stage circuit having a hold function. For another example, the data output stage circuit having the hold function may be implemented by any other circuit structure capable of holding the data output signal at a fixed voltage level when the MBFF operates in the test mode. For another example, the scan output stage circuit having the hold function may be implemented by any other circuit structure capable of holding the scan output signal at a fixed voltage level when the MBFF operates in the normal mode.

Fig. 12 is a diagram illustrating a first alternative design of a scanout stage circuit with a hold function according to an embodiment of the present invention. For example, the scanout stage circuit 1004 may be implemented using the scanout stage circuit 1200. The scan output stage circuit 1200 employs an OR (OR) gate 1202, wherein one input node of the OR gate 1202 is coupled to the output node N2 of the front-end latch circuit, the other input node of the OR gate 1202 is arranged to receive the test enable signal STEB, and the output node of the OR gate 1202 is arranged to output the scan output signal to the output terminal SQ of the scan MBFF 1000. When the MBFF1000 operates in the test mode (STEB ═ 0), the voltage level of the scan output signal generated by the OR gate 1202 changes in response to the voltage of the signal at the output node N2 of the latch circuit of the front end. When the MBFF1000 operates in the normal mode (STEB ═ 1), the scan output signal generated by the OR gate 1202 is held at a fixed voltage level (e.g., the power supply voltage) regardless of the voltage of the signal at the output node N2 of the front-end latch circuit.

Fig. 13 is a diagram illustrating a second alternative design of a scanout stage circuit with a hold function according to an embodiment of the present invention. For example, the scanout stage circuit 1004 may be implemented using the scanout stage circuit 1300. The scan output stage circuit 1300 employs a NAND (NAND) gate 1302, wherein one input node of the NAND gate 1302 is coupled to the output node N2 of the previous stage latch circuit, the other input node of the NAND gate 1302 is arranged to receive the test enable signal STE, and the output node of the NAND gate 1302 is arranged to output a scan output signal to the scan terminal SQ of the MBFF 1000. When MBFF1000 operates in the test mode (STE ═ 1), the voltage level of the scan output signal generated by NAND gate 1302 changes in response to the voltage of the signal at output node N2 of the preceding stage latch circuit. When MBFF1000 operates in the normal mode (STE ═ 0), the scan output signal generated by NAND gate 1302 is maintained at a fixed voltage level (e.g., the power supply voltage) regardless of the signal voltage at output node N2 of the previous stage latch circuit.

Fig. 14 is a diagram illustrating a third alternative design of a scanout stage circuit with a hold function according to an embodiment of the present invention. For example, the scanout stage circuit 1004 may be implemented using the scanout stage circuit 1400. The scan output stage circuit 1400 employs an AND (AND) gate 1402, wherein one input node of the AND gate 1402 is coupled to the output node N2 of the latch circuit at the previous stage, the other input node of the AND gate 1402 is arranged to receive the test enable signal STE, AND the output node of the AND gate 1402 is arranged to output a scan output signal to the scan output terminal SQ of the MBFF 1000. When the MBFF1000 operates in the test mode (STE ═ 1), the voltage level of the scan output signal generated by the AND gate 1402 changes in response to the voltage of the signal at the output node N2 of the preceding stage latch circuit. When MBFF1000 operates in normal mode (STE ═ 0), the scan output signal generated by AND gate 1402 is held at a fixed voltage level (e.g., ground voltage) regardless of the voltage of the signal at output node N2 of the previous latch circuit.

Fig. 15 is a diagram showing a fourth alternative design of a scanout stage circuit having a hold function according to an embodiment of the present invention. For example, the scanout stage circuit 1004 may be implemented using the scanout stage circuit 1500. The scanout stage circuit 1500 includes

PMOS transistors

1502 and 1504, NMOS transistor 1506, and inverter 1508. The gate of the PMOS transistor 1504 receives the test enable signal STE, the source of the PMOS transistor 1504 is coupled to a reference voltage (e.g., a supply voltage), and the drain of the PMOS transistor 1504 is coupled to the input node of the inverter 1508. The PMOS transistor 1502 and the NMOS transistor 1506 form a transmission gate. The gate of the PMOS transistor 1502 receives the test enable signal STEB, the source of the PMOS transistor 1502 is coupled to the output node N2 of the previous-stage latch circuit, and the drain of the PMOS transistor 1502 is coupled to the input node of the inverter 1508. The gate of the NMOS transistor 1506 receives the test enable signal STE, the drain of the NMOS transistor 1506 is connected to the output node N2 of the previous stage latch circuit, and the source of the NMOS transistor 1506 is coupled to the input node of the inverter 1508.

When the MBFF1000 operates in the test mode (STE ═ 1& STEB ═ 0), the transmission gate composed of the PMOS transistor 1502 and the NMOS transistor 1506 is enabled, and the PMOS transistor 1504 is turned off, so that the voltage level of the scan output signal at the scan output terminal SQ changes in response to the voltage level of the signal at the output node N2 of the preceding stage latch circuit. When the MBFF1000 operates in the normal mode (STE ═ 0& STEB ═ 1), the transmission gate composed of the PMOS transistor 1502 and the NMOS transistor 1506 is disabled, and the PMOS transistor 1504 is turned on, so that the voltage level of the scan output signal at the scan output terminal SQ is maintained at a fixed voltage level (for example, ground voltage) regardless of the voltage level of the signal at the output node N2 of the previous stage latch circuit.

Fig. 16 is a diagram showing a fifth alternative design of a scanout stage circuit having a hold function according to an embodiment of the present invention. For example, the scanout stage circuit 1004 may be implemented using the scanout stage circuit 1600. The scanout stage circuit 1600 includes

NMOS transistors

1602 and 1604, a PMOS transistor 1606, and an inverter 1608. The gate of NMOS transistor 1604 receives the test enable signal STEB, the source of NMOS transistor 1604 is coupled to a reference voltage (e.g., ground voltage), and the drain of NMOS transistor 1604 is coupled to the inverter 1608 input node. PMOS transistor 1606 and NMOS transistor 1602 form a transmission gate. A gate of the PMOS transistor 1606 receives the test enable signal STEB, a source of the PMOS transistor 1606 is coupled to the output node N2 of the previous stage latch circuit, and a drain of the PMOS transistor 1606 is coupled to the input node of the inverter 1608. The gate of the NMOS transistor 1602 receives the test enable signal STE, the drain of the NMOS transistor 1602 is connected to the output node N2 of the previous-stage latch circuit, and the source of the NMOS transistor 1602 is coupled to the input node of the inverter 1608.

When the MBFF1000 operates in the test mode (STE ═ 1& STEB ═ 0), the transmission gate composed of the PMOS transistor 1606 and the NMOS transistor 1602 is enabled, and the NMOS transistor 1604 is turned off, so that the voltage level of the scan output signal at the scan output terminal SQ changes in response to the voltage level of the signal at the output node N2 of the preceding stage latch circuit. When the MBFF1000 operates in the normal mode (STE ═ 0& STEB ═ 1), the transmission gate composed of the PMOS transistor 1606 and the NMOS transistor 1602 is disabled, and the NMOS transistor 1604 is turned on, so that the scan output signal at the scan output terminal SQ is kept at a fixed voltage level (e.g., a power supply voltage) regardless of the voltage level of the signal at the output node N2 of the latch circuit of the previous stage.

MBFF1000 with N flip-flops 1002_1-1002_ N connected to form internal scan chain 104 is designed to have power saving characteristics. For example, when the MBFF1000 receives the external test signal S11 at the scan-in terminal SI, the MBFF1000 transmits the external test signal S11 through the internal scan chain 104, generates the scan-out signal SN5 output from the flip-flop 1002_ N to the scan-out terminal SQ, and the voltage level of the scan-out signal SN5 changes in response to the voltage level of the external test signal S11, and maintains each of the N data-out signals (output from the N flip-flops 1002_ N to the N data-out terminals Q1-QN) at a fixed voltage level regardless of the voltage level of the external test signal S11. Since there is no signal level transition for the N data output signals in the test mode of MBFF1000, the power consumption of MBFF1000 and downstream combinational logic can be reduced.

Further, when the data signal SN0 is received at the data input terminal DN, the MBFF1000 generates the data output signal SN4 output from the flip-flop 1002_ N to the data output terminal QN, and the voltage level of the data output signal SN4 changes in response to the voltage level of the data signal SN0, and holds the scan output signal SN5 (output from the flip-flop 1002_ N to the scan output terminal SQ) at a fixed voltage level regardless of the voltage level of the data signal SN 0. Since there is no signal level transition of the scan output signal in the normal mode of MBFF1000, power consumption of MBFF1000 and downstream logic can be reduced.

Although the present invention has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A multi-bit flip-flop, comprising:

a plurality of flip-flops connected to form an internal scan chain, wherein the plurality of flip-flops comprises a first flip-flop arranged to output a first data output signal at a first data output terminal of the multi-bit flip-flop, the first flip-flop comprising:

a first selection circuit arranged to send a first data signal or a first test signal at a first data input terminal of the multi-bit flip-flop to an output node of the first selection circuit as a first input signal;

a first latch circuit coupled to the output node of the first selection circuit arranged to generate a first signal from the first input signal; and

a first data output stage circuit arranged to receive the first signal and to generate the first data output signal in dependence on the first signal;

wherein, when the multi-bit flip-flop operates in a test mode, the first selection circuit is arranged to transmit the first test signal to the output node of the first selection circuit as the first input signal, and the first data output stage circuit is arranged to maintain the first data output signal at a fixed voltage level regardless of the voltage level of the first test signal.

2. The multi-bit flip-flop of claim 1, wherein said first data output stage circuit is further arranged to receive a test enable signal at a test enable terminal of said multi-bit flip-flop and to generate said first data output signal as a function of said first signal as controlled by said test enable signal.

3. The multi-bit flip-flop of claim 1, wherein said first data output stage circuit is further arranged to receive a second test enable signal at a test enable terminal of said multi-bit flip-flop, said second test enable signal being an inverse of a first test enable signal, and to generate said first data output signal from said first signal as controlled by said second test enable signal.

4. The multi-bit flip-flop of claim 1, wherein said first data output stage circuit is further arranged to receive a first test enable signal and a second test enable signal inverted from said first test enable signal at a test enable terminal of said multi-bit flip-flop and to generate said first data output signal from said first signal as controlled by said first test enable signal and said second test enable signal.

5. The multi-bit flip-flop of claim 1, wherein said first test signal is an external test signal received at a scan input terminal of said multi-bit flip-flop.

6. The multi-bit flip-flop of claim 1, wherein said plurality of flip-flops further comprises a second flip-flop arranged to output a second data output signal at a second data output terminal of said multi-bit flip-flop, said second flip-flop comprising:

a second selection circuit arranged to send a second data signal or a second test signal at a second data input terminal of the multi-bit flip-flop to an output node of the second selection circuit as a second input signal;

a second latch circuit coupled to the output node of the second selection circuit and arranged to generate the first test signal and a second signal from the second input signal; and

a second data output stage circuit arranged to receive the second signal and to generate the second data output signal in dependence on the second signal.

7. The multi-bit flip-flop of claim 6, wherein when said multi-bit flip-flop is operating in said test mode, said second selection circuit is arranged to transmit said second test signal to said output node of said second selection circuit for use as said second input signal, and said second data output stage circuit is arranged to maintain said second data output signal at a fixed voltage level regardless of a voltage level of said second test signal.

8. The multi-bit flip-flop of claim 7, wherein the second data output stage circuit is further arranged to receive a test enable signal at a test enable terminal of the multi-bit flip-flop and to generate the second data output signal as a function of the second signal as controlled by the test enable signal.

9. The multi-bit flip-flop of claim 7, wherein the second data output stage circuit is further arranged to receive a second test enable signal at a test enable terminal of the multi-bit flip-flop, the second test enable signal being an inverse of the first test enable signal, and to generate the second data output signal as a function of the second signal as controlled by the second test enable signal.

10. The multi-bit flip-flop of claim 7, wherein the second data output stage circuit is further arranged to receive a first test enable signal and a second test enable signal inverted from the first test enable signal at a test enable terminal of the multi-bit flip-flop, and to generate the second data output signal from the second signal as controlled by the first test enable signal and the second test enable signal.

11. The multi-bit flip-flop of claim 1, wherein the first latch circuit is further arranged to generate a second test signal from the first input signal, and the plurality of flip-flops further comprises a second flip-flop arranged to output a second data output signal at a second data output terminal of the multi-bit flip-flop, the second flip-flop comprising:

a second selection circuit arranged to send a second data signal at a second data input terminal of the multi-bit flip-flop to an output node of the second selection circuit as a second input signal at or obtained from the first latch circuit;

a second latch circuit coupled to the output node of the second selection circuit and generating a second signal according to the second input signal; and

12. The multi-bit flip-flop of claim 1, wherein said first flip-flop is further arranged to output a scan out signal at a scan out terminal of said multi-bit flip-flop, and further comprising:

a scan output stage circuit arranged to receive the first signal and generate a scan output signal in dependence thereon, wherein when the multi-bit flip-flop operates in a test mode, the scan output stage circuit is arranged to generate a scan output signal and a voltage level of the scan output signal changes in response to a voltage level of the first test signal.

13. The multi-bit flip-flop of claim 12, wherein when the multi-bit flip-flop is operating in a normal mode, the first selection circuit is arranged to send the first data signal to the output node of the first selection circuit for use as the first input signal, and the scanout stage circuit is arranged to maintain the scanout signal at a fixed voltage level regardless of the voltage level of the first data signal.

14. The multi-bit flip-flop of claim 13, wherein the scanout stage circuit is further arranged to receive a test enable signal at a test enable terminal of the multi-bit flip-flop and to generate the scanout signal as a function of the first signal as controlled by the test enable signal.

15. The multi-bit flip-flop of claim 13, wherein the scan output stage circuit is further arranged to receive a second test enable signal at a test enable terminal of the multi-bit flip-flop, the second test enable signal being inverted from the first test enable signal and controlled by the second test enable signal to generate the scan output signal in accordance with the first signal.

16. The multi-bit flip-flop of claim 13, wherein the scan output stage circuit is further arranged to receive a first test enable signal and a second test enable signal inverted from the first test at a test enable terminal of the multi-bit flip-flop and to generate the scan output signal from the first signal as controlled by the first test enable signal and the second test enable signal.

17. A control method applied to a multi-bit flip-flop to which N flip-flops are connected to form an internal scan chain, wherein the multi-bit flip-flop includes a scan input terminal coupled to one of the N flip-flops, and N data output terminals coupled to the N flip-flops, respectively, where N is a positive integer not less than 1, the control method comprising:

passing an external test signal through the internal scan chain in response to receiving the external test signal at the scan input terminal of the multi-bit flip-flop;

generating a scan output signal having a voltage level that varies with a voltage level of the external test signal, wherein the scan output signal is output from one of the N flip-flops to one of the N data output terminals; and

each of the (N-1) data output signals is maintained at a fixed voltage level regardless of a voltage level of the external test signal, wherein the (N-1) data output signals are respectively output from the remaining (N-1) of the N flip-flops to the remaining (N-1) of the N data output terminals.

18. A control method is applied to a multi-bit flip-flop connected with N flip-flops to form an internal scan chain, wherein the multi-bit flip-flop comprises a scan input terminal coupled to one of the N flip-flops, a scan output terminal coupled to another one of the N flip-flops, and N data output terminals respectively coupled to the N flip-flops, wherein N is a positive integer not less than 1; the control method comprises the following steps:

generating a scan output signal having a voltage level that varies with a voltage level of the external test signal, wherein the scan output signal is output from the other flip-flop of the N flip-flops to the scan output terminal; and

the N data output signals, which are respectively output from the N flip-flops to N data output terminals of the multi-bit flip-flop, are maintained at fixed voltage levels regardless of voltage levels of the external test signals.

19. The control method of claim 18, wherein the multi-bit flip-flop further comprises N data input terminals coupled to the N flip-flops, respectively; and, the control method further comprises:

in response to receiving a data signal at a data input terminal coupled to the other of the N flip-flops, maintaining the scan output signal at a fixed voltage level regardless of a voltage level of the data signal.