TWI794109B - 具有銲墊層之半導體元件的製備方法 - Google Patents

具有銲墊層之半導體元件的製備方法 Download PDF

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TWI794109B
TWI794109B TW111120318A TW111120318A TWI794109B TW I794109 B TWI794109 B TW I794109B TW 111120318 A TW111120318 A TW 111120318A TW 111120318 A TW111120318 A TW 111120318A TW I794109 B TWI794109 B TW I794109B
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layer
pad
die
substrate opening
pad layer
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TW111120318A
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TW202236525A (zh
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施信益
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南亞科技股份有限公司
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    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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Abstract

本揭露係關於一種具有銲墊層之半導體元件的製備方法。該半導體元件包括一第一晶粒，一第二晶粒，一銲墊層，一填充層以及一阻擋層。該第二晶粒設置在該第一晶粒上。該銲墊層設置在該第一晶粒中。該填充層包括一上部及一凹陷部。該阻擋層設置在該第二晶料與該填充層的該上部之間、該第一晶粒與該填充層的該上部之間、以及該銲墊層與該填充層的該凹陷部之間。該填充層的該上部沿該第二晶粒與該第一晶粒設置，且該填充層的該凹陷部由該上部延伸且設置在該銲墊層中。

Description

具有銲墊層之半導體元件的製備方法
本申請案是2021年5月31日申請之第110119716號申請案的分割案，第110119716號申請案主張2020年7月31日申請之美國正式申請案第16/945,096號的優先權及益處，該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體元件及其製備方法。特別是有關於一種具有銲墊層之半導體元件及其製備方法
對於許多現代應用，半導體元件是不可或缺的。舉例而言，半導體元件係廣泛地運用在各種電子應用中，例如個人電腦、行動電話、數位相機以及其他電子設備。再者，隨著電子科技的進步，半導體元件的尺寸變得越來越小，於此同時提供較佳的功能以及包含較大的積體電路數量。然而，隨著半導體元件的按比例縮小，相鄰導電元件之間的間隔係逐漸縮小，其係可縮減內連接結構的製程裕度(process window)。因此，在半導體元件中製造內連接結構則越來越困難因此，在提高品質、良率、效能以及可靠性以及降低複雜性的方面仍持續存在挑戰性。
上文之「先前技術」說明僅係提供背景技術，並未承認上 文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體元件，該半導體元件包括一第一晶粒，一第二晶粒，一銲墊層，一填充層以及一阻擋層。該第二晶粒設置在該第一晶粒上。該銲墊層設置在該第一晶粒中。該填充層包括一上部及一凹陷部。該阻擋層設置在該第二晶料與該填充層的該上部之間、該第一晶粒與該填充層的該上部之間、以及該銲墊層與該填充層的該凹陷部之間。該填充層的該上部沿該第二晶粒與該第一晶粒設置，且該填充層的該凹陷部由該上部延伸且設置在該銲墊層中。
在一實施例中，該填充層的該凹陷部的一深度大於該銲墊層一厚度的一半且小於該銲墊層的該厚度。
在一實施例中，該填充層的該上部的側壁與該填充層的該凹陷部的側壁之間的一水平距離等於或小於該填充層的該凹陷部的該深度。
在一實施例中，該填充層的該凹陷部的側壁係彎曲。
在一實施例中，該填充層的該凹陷部的一底表面係彎曲。
在一實施例中，該半導體元件包括一隔離層，設置在該第二晶粒與該填充層的該上部之間，且設置在該第一晶粒與該填充層的該上部之間。
在一實施例中，該半導體元件包括一鈍化層，設置在該第二晶粒上，且該填充層的該上部沿該鈍化層、該第二晶粒以及該第一晶粒設置。該鈍化層由氮化矽、氮氧化矽、氧化矽、氧化氮化矽(silicon nitride oxide)、環氧樹脂、聚酰亞胺(polyimide)、苯環丁烯(benzocyclobutene)或聚苯并噁唑(polybenzoxazole)形成。
在一實施例中，該半導體元件包括一附著層，設置在該填充層與該阻擋層之間。該附著層由鈦、鉭、鈦鎢或氮化錳形成。
在一實施例中，該半導體元件包括一種子層，設置在該附著層與該填充層之間。該種子層的一厚度係在約10nm到約40nm範圍內。
在一實施例中，該半導體元件包括一銲墊阻擋層，分別相應地設置在該銲墊層上與該銲墊層下。
在一實施例中，該鈍化層與該填充層的上部之間的界面係錐形。
在一實施例中，該鈍化層的一頂表面與一界面之間的角度在大約120度到135度範圍內，其中該界面係在該鈍化層與該填充層的該上部之間。
在一實施例中，該填充層係由多晶矽、鎢、銅、奈米碳管或銲鍚合金形成。
在一實施例中，該隔離層由氧化矽、氮化矽、氮氧化矽或四乙基正矽酸鹽(TEOS)形成。
本揭露之另一實施例提供一種半導體元件的製方法，包括，執行一接合製程，將一第二晶粒接合到具有一銲墊層的一第一晶粒上；沿該第二晶粒形成延伸到該第一晶粒中的該銲墊層的一貫穿基底開口；共形地形成一隔離層在該貫穿基底開口中；執行一沖孔蝕刻製程以去除一部分隔離層且曝露執行一沖孔蝕刻製程以去除該隔離層的一部分且曝露該銲墊層的一頂表面的一部分；執行一等向性蝕刻製程係形成由該貫穿 基底開口且在該焊盤層中延伸的一凹陷空間；共形地形成一阻擋層在該貫穿基底開口中與該凹陷空間中；以及，形成一填充層在該貫穿基底開口與該凹陷空間中。
在一實施例中，該等向性蝕刻具有該銲墊層對該隔離層的一蝕刻速率比，係在大約100：1到大約1.05：1範圍內。
在一實施例中，該隔離層由氧化矽、氮化矽、氮氧化矽或四乙基正矽酸鹽形成。
在一實施例中，該填充層係由多晶矽、鎢、銅、奈米碳管或銲鍚合金形成。
在一實施例中，該製備方法包括一步驟：形成一鈍化層在該第二晶粒上。該貫穿基底開口沿該鈍化層與該第二晶粒係形成且延伸到該第一晶粒中的該銲墊層。
在一實施例中，該鈍化層由氮化矽、氮氧化矽、氧化矽、氧化氮化矽、環氧樹脂、聚酰亞胺、苯環丁烯或聚苯并噁唑形成。
由於本揭露的半導體元件的設計，該填充層的該上部可增加該填充層與該阻擋層之間的接觸表面，進而實現減小該阻擋層的接觸電阻。因此，可提高該半導體元件的可靠性。另外，由於該保護層的幾何形狀，可形成沒有任何空隙的該填充層。因此，可提高該半導體元件的製造良率。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改 或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
1A:半導體元件
1B:半導體元件
1C:半導體元件
10:製備方法
100:第一晶粒
101:第一基底
103:第一介電層
105:第一結合層
107:第一元件部件
109:第一虛設導電層
200:第二晶粒
201:第二基底
201TS:頂表面
203:第二介電層
205:第二接合層
207:第二元件部件
209:第二虛設導電層
301TS:頂表面
301:鈍化層
303:銲墊層
305:銲墊阻擋層
307:銲墊阻擋層
309:保護層
401:隔離層
401S:側壁
401TP:最高點
403:阻擋層
403C:覆蓋部
403R:凹部
403U:上部
405:填充層
405R:凹陷部
405RS:凹陷部側壁
405U:上部
501:貫穿基底開口
503:凹陷空間
503BS:底表面
503S:側壁
505:導電材料
D1:深度
D2:深度
D3:深度
H1:水平距離
H2:水平距離
IF01:界面
S11:步驟
S13:步驟
S15:步驟
S17:步驟
S19:步驟
S21:步驟
S23:步驟
S25:步驟
T1:厚度
W1:寬度
α:角度
參閱實施方式與申請專利範圍合併考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。
圖1為依據本揭露一實施例一種半導體元件之製備方法的流程示意圖。
圖2到圖10為依據本揭露一些實施例該半導體元件之製備流程的剖視示意圖。
圖11到圖14為依據本揭露另一實施例一種半導體元件之製備流程的剖視示意圖。
圖15到圖17為依據本揭露另一實施例一種半導體元件之製備流程的剖視示意圖。
圖18為依據本揭露另一實施例一種半導體元件的剖視示意圖。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式，說明本揭露之實施例，然而本揭露並不受限於該實施例。此外，以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性，然而並非每一實施例必須包含該特定特徵、結構或是特性。再者，重複使用「在實施例中」一語並非必須指相同實施例，然而可 為相同實施例。
為了使得本揭露可被完全理解，以下說明提供詳細的步驟與結構。顯然，本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外，已知的結構與步驟不再詳述，以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而，除了詳細說明之外，本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容，而是由申請專利範圍定義。
應當理解，以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列形式的具體實施例或實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，元件的尺寸並非僅限於所揭露範圍或值，而是可相依於製程條件及/或裝置的所期望性質。此外，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。為簡潔及清晰起見，可按不同比例任意繪製各種特徵。在附圖中，為簡化起見，可省略一些層/特徵。
此外，為易於說明，本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對關係用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係用語旨在除圖中所繪示的取向外亦囊括元件在使用或操作中的不同取向。所述裝置可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對關係描述語可 同樣相應地進行解釋。
圖1為依據本揭露一實施例一種半導體元件1A之製備方法10的流程示意圖。圖2到圖10為依據本揭露一些實施例半導體元件1A之製備流程的剖視示意圖。
參考圖1及圖2，在製備方法10的步驟S11中，可執行一接合製程，係將一第二晶粒200接合到具有一銲墊層303的第一晶粒100上。
參考圖2，第一晶粒100及第二晶粒200可獨立製備，但本揭露不限於此。第一晶粒100及第二晶粒200係可具有不同的功能性。舉例來說，例如第一晶粒100可提供一邏輯功能，而第二晶粒200係可提供一記憶功能。在一些實施例中，第一晶粒100及第二晶粒200可具有相同的功能性。
參考圖2，第一晶粒100可包括一第一基底101、一第一介電層103、一第一接合層105、一第一元件部件107以及一第一虛設導電層109。
仍請參考圖2，在一些實施例中，第一基底101係整體由至少一種半導體材料組成的一體(bulk)半導體基底。該體半導體基底的材料可包括具有半導體特性的任何材料或材料堆疊，包括但不限於矽、鍺、矽鍺合金、III-V族化合物半導體或II-VI族化合物半導體的材料。III-V族化合物半導體是包括元素週期表的第III族的至少一種元素與元素週期表的第V族的至少一種元素的材料。II-VI化合物半導體是包括元素週期表的第II族的至少一種元素與元素週期表的第VI族的至少一種元素的材料。
仍請參考圖2，在一些實施例中，第一基底101可包括一絕緣體上覆矽(SOI)結構，該SOI結構由下而上係包括一處理基底、一絕緣 層以及一最上的半導體材料層所組成。該處理基底及該最上的半導體材料層可使用與該體半導體基底相同的材料形成。該絕緣層係可一結晶或非結晶介電材料，例如一氧化物及/或氮化物。舉例來說，該絕緣層係可氧化矽的一介電氧化物。再舉例來說，該絕緣層為氮化矽或氮化硼的一介電氮化物。又舉例來說，該絕緣層可包括介電氧化物與介電氮化物的堆疊，例如以任何順序的排列的氧化矽及氮化矽或氮化硼的堆疊。該絕緣層可具有約10nm到200nm範圍內之間的厚度。
在一些實施例中，可藉由晶圓接合而形成該SOI結構。在一些實施例中，該SOI結構可藉由一植入製程形成，例如一植氧分離(separation by implantation of oxygen，SIMOX)製程。在一些實施例中，該SOI結構的該最頂層半導體材料層係藉由一熱混合製程或一熱冷凝製程形成。該熱混合製程係可包括在一惰性環境(氦氣及/或氬氣)中退火，而該熱冷凝製程可包括在一氧化性環境(空氣、氧氣、臭氧及/或NO2)中進行退火。該熱混合製程與該熱冷凝製程的退火溫度可在約600℃到約1200℃範圍內。
仍請參考圖2，第一介電層103可在第一基底101上形成。第一介電層103係可一堆疊層結構。第一介電層103可包括多個第一絕緣子層。該多個第一絕緣子層中的每個可具有大約0.5微米到大約3.0微米範圍內的厚度。該多個第一絕緣子層可由下列材料形成：例如氧化矽、硼磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、氟化矽酸鹽玻璃、低k介電材料、類似的材料或其組合。該多個第一絕緣子層可由不同的材料所形成，但是本揭露不限於此。低k介電材料可具有小於3.0或甚至小於2.5的介電常數。在一些實施例中，低k介電材料可具有小於2.0的介電常數。
第一介電層103可藉由例如一化學氣相沉積、一電漿增強化學氣相沉積、一蒸鍍或一旋塗的沉積製程形成。可在沉積製程後分別相應地執行一平面化製程，去除多餘的材料且為隨後的處理步驟提供一實質上平坦的表面。可在第一介電層103的形成期間形成第一元件部件107、導電部件(未示出)、銲墊層303以及銲墊阻擋層305、307。
仍請參考圖2，焊銲墊層303可在第一介電層103中形成。銲墊阻擋層305、307可分別對應地在焊銲墊層303上與銲墊層303下形成。在一些實施例中，銲墊阻擋層307的頂表面可與第一介電層103的頂表面實質上共面。第一接合層105的頂表面可被稱為第一晶粒100的頂表面。焊銲墊層303可由例如鋁、銅、鋁銅合金、鋁合金、銅合金或其他適合的導電材料形成。銲墊阻擋層305、307可由例如鈦、氮化鈦、氮化鉭，或鈦/氮化鈦雙層的材料形成。銲墊層30及阻擋層305、307可由例如一化學氣相沉積、一物理氣相沉積、一蒸鍍或一濺鍍的沉積製程以及隨後的一黃光-蝕刻製程銲墊層303與銲墊阻擋層305、307的圖案。
仍請參考圖2，第一接合層105可在第一介電層103上形成。在一些實施例中，第一接合層105可由一非有機材料形成，例如選自未摻雜的矽酸鹽玻璃、氮化矽、氮氧化矽、氧化矽、氮氧化矽及其組合的材料形成。在一些實施例中，第一接合層105可由一聚合物形成，例如環氧樹脂、聚酰亞胺、苯並環丁烯、聚苯並噁唑或其類似材料形成。第一接合層105可由例如一化學氣相沉積、一電漿增強化學氣相沉積、一蒸鍍或一旋塗的沉積製程形成。
應當理解，在本揭露中，氮氧化矽是指包含矽、氮及氧且其中氧的比例大於氮的比例。氮化矽是指包含矽、氧及氮且其中氮的比例 大於氧的比例的物質。
仍請參考圖2，可藉由一鑲嵌製程(damascene process)在第一接合層105中形成第一虛設導電層109。第一虛設導電層109的頂面與第一接合層105的頂面是實質上共面。第一虛設導電層109可由下列材料製成：例如鎢，鈷、鋯、鉭、鈦、鋁、釕、銅、金屬碳化物(例如碳化鉭、碳化鈦、碳化鉭、碳化鎂)、金屬氮化物(例如氮化鈦等)、過渡金屬鋁化物，或其組合。
應當理解，在本揭露的描述中，將元件稱為“虛擬”元件是指當半導體元件1A在操作中時，沒有外部電壓或電流施加到該元件。
側請參考圖2，一第二晶粒200可具有與第一晶粒100類似的結構。該第二晶粒200可包括一第二基底201、一第二介電層203、一第二接合層205、第二元件207的部件、以及一第二虛設導電層209。第一晶粒100及第二晶粒200之間的相似參考標號可由相同的材料形成且可藉由相似的製程形成，但是本揭露不限於此。舉例來說，第二基底201可由與第一基底101相同的材料所形成。
仍請參考圖2，第二晶粒200在接合製程期間可用一種上下相反的方式放置。意即，該第一晶粒100和第二晶粒200係可一面對面的方式接合。具體而言，在接合製程期間，第二接合層205可被放置在述第一晶粒100上。該第二介電層203係可在第二接合層205上。該第二基底201可在第二介電層203上。該第二虛設導電層209可在第二接合層205中。第二虛設導電層209的底表面與第二接合層205的底表面實質上共面。在一些實施例中，第二晶粒200與第一晶粒100係以背對面的方式接合。
在一些實施例中，可在接合製程以執行一個熱處理以實現第二晶粒200與第一晶粒100的元件之間的混合接合。接合製程的溫度可在約300℃到約450℃的範圍。該混合接合可包括介電質到介電質接合及/或金屬到金屬接合。該介電質到介電質接合可從第二接合層205和第一接合層105之間的接合開始。該金屬對金屬的接合可從第二虛設導電層209和第一虛設導電層109之間的接合開始。意即，第一虛設導電層109和第二虛設導電層209可促進在接合製程中第一晶粒100和第二晶粒200之間的接合。另外，第一虛設導電層109和第二虛設導電層209可分別相應地提高第一晶粒100和第二晶粒200的機械強度。
參考圖1及圖3，在步驟13，一鈍化層301可在第二晶粒200上形成。
參考圖3，可在第二基底201上執行一減薄製程以減少該第二基底201的厚度，該減薄製程使用一蝕刻製程、一化學拋光製程，或一研磨製程。
仍請參考圖3，可藉由例如一化學氣相沉積、一電漿增強化學氣相沉積、一蒸鍍或一旋塗的沉積製程形成鈍化層301。在一些實施例中，鈍化層301可由一非有機材料形成，例如選自氮化矽、氮氧化矽、氧化矽、氮氧化矽及其組合的材料形成。在一些實施例中，鈍化層301可由一聚合物形成，例如環氧樹脂、聚酰亞胺、苯並環丁烯、聚苯並噁唑或其類似材料形成。在一些實施例中，該鈍化層301可藉由對第二基底201的第二晶粒200具有蝕刻選擇性的材料形成。在一些實施例中，該鈍化層301可做為一高蒸汽阻擋以防止上方進入的水氣。在一些實施例中，鈍化層301可在貫穿基底開口形成的期間，做為一硬遮罩層，稍後將詳述製 程。在一些實施例中，鈍化層301可做為一緩衝層，防止在一填充層形成的期間，金屬到矽的洩漏，稍後將詳述製程。
參考圖1及圖4，在步驟S15，可沿著鈍化層301與第二晶粒200且延伸至銲墊阻擋層307的頂表面，形成一貫穿基底開口501。
參考圖4，貫穿基底開口501可藉由使用一種或多種蝕刻製程、銑削、電射技術或類似的製程形成。銲墊阻擋層307的頂表面的一部分可藉由貫穿基底開口501曝露。在一些實施例中，貫穿基底開口501的寬度W1可在大約5μm到大約15μm範圍內。在一些實施例中，貫穿基底開口501可具有在大約20μm到大約160μm範圍的一深度D1。具體地，貫穿基底開口501的深度D1可在大約50μm到大約130μm的範圍內。在一些實施例中，貫穿基底開口501可具有在大約1：2到大約1：35範圍內的縱橫比。具體地，貫穿基底開口501的縱橫比可在大約1：10到大約1：25範圍內。
參考圖1及圖5，在步驟S17中，一隔離層401可共形地形成在貫穿基底開口501中。
參考圖5，具體地，隔離層401可共形地形成在貫穿基底開口501中，且可共形地形成在鈍化層301的頂表面上。在一些實施例中，隔離層401可由例如，氧化矽、氮化矽、氮氧化矽、原矽酸四乙酯或其組合的材料所形成。隔離層401可具有在大約50nm到大約200nm範圍內的厚度。隔離層401可藉由例如一化學氣相沉積或一電漿增強化學氣相沉積形成。在一些實施例中，隔離層401可由例如聚對二甲苯、環氧樹脂或聚對二甲苯所形成。隔離層401可具有在大約1μm到大約5μm範圍內的厚度。隔離層401可藉由具有塗層且後續固化的旋塗製程形成。
參考圖1及圖6，在步驟19，可執行一沖孔蝕刻製程以曝露銲墊層303的一頂表面的一部分。
參考圖6，在該沖孔蝕刻製程中，在銲墊阻擋層307的頂表面上形成的隔離層401可被去除，且在銲墊層303的頂表面上形成的隔離層401去除後曝露的銲墊阻擋層307的部分可被去除。結果，銲墊層303的頂表面的一部份可被曝露。
該沖孔蝕刻製程係可一非等向性蝕刻製程，例如一非等向乾式蝕刻製程，因此在隔離層401側壁上形成的貫穿基底開口501可依舊完整。在沖孔蝕刻製程之後，隔離層401可被分成多個部分。在一些實施例中，隔離層401的沖孔蝕刻製程的蝕刻速率可比鈍化層301的沖孔蝕刻製程的蝕刻速率更快，以避免矽/硬遮罩層界面的損壞。在一些實施例中，銲墊阻擋層307的沖孔蝕刻製程的蝕刻速率可比銲墊層303的沖孔蝕刻製程的蝕刻速率更快。隔離層401可電隔離一填充層(將在後面製成)，該填充層形成在鈍化層301、第二晶粒200以及第一接合層105中。在一些實施例中，在鈍化層301的頂表面上形成的隔離層401也可在沖壓蝕刻的製程期間被去除(圖6中未示出)。
參考圖1及圖7，在步驟S21，可執行一等向性蝕刻製程以在銲墊層303中形成一凹陷空間503。
參考圖7，在一些實施例中，銲墊層303的等向性蝕刻的蝕刻速率可比隔離層401的等向性蝕刻的蝕刻速率更快。舉例來說，在等向性蝕刻期間，銲墊層303與隔離層401的蝕刻速率比可在大約100：1到大約1.05：1的範圍。再舉例來說，在等向性蝕刻期間，銲墊層303與隔離層401的蝕刻速率比可在大約20：1到大約10：1的範圍內。
仍請參考圖7，可由貫穿基底開口501向下延伸形成一凹陷空間503。凹陷空間503的一深度D2，係銲墊阻擋層307的底表面與凹陷空間503的一底表面503BS之間的垂直距離，深度D2可大於銲墊層303的厚度T1的一半且小於銲墊層303的厚度T1。隔離層401的一側壁401S與凹陷空間503的一側壁503S之間的一水平距離H1可等於或小於凹陷空間503的深度D2。在一些實施例中，凹陷空間503的底表面503BS及側壁503S係平坦面。在一些實施例中，凹陷空間503的底表面503BS和凹陷空間503的側壁503S係彎曲面。在一些實施例中，凹陷空間503的底表面503BS及凹陷空間503的側壁503S的相交點係彎曲。相交點是彎曲可避免彎角效應(Corner effect)。
參考圖1及圖8，在步驟23，在貫穿基底開口501及凹陷空間50中共形地形成一阻擋層403。
參考圖8，阻擋層307可形成在隔離層401的頂表面、隔離層401的側壁401S、銲墊阻擋層307的側壁、凹陷空間503的側壁503S以及凹陷空間503的底表面503BS上。形成在隔離層401的凹陷空間503的頂部表面上的阻擋層403可被稱為阻擋層403的覆蓋部403C。形成在隔離層401的側壁401S與銲墊阻擋層307的側壁上的的阻擋層403可被稱為的阻擋層403的上部403U。形成在凹陷空間503的側壁503S與凹陷空間503的底表面503BS的阻擋層403可被稱為阻擋層403的凹部403R。
舉例來說，阻擋層403可由鉭、氮化鉭、鈦、氮化鈦、錸、硼化鎳、或氮化鉭/鉭雙層材料形成。阻擋層403可藉由一沉積製程形成，例如一物理氣相沉積製程、一原子層沉積製程、一化學氣相沉積製程，或一濺射製程。阻擋層403可抑制一填充層(將在後面製成)的導電材 料的擴散進入鈍化層301、第二晶粒200以及第一接合層105。另外，阻擋層403的凹部403R可增加阻擋層403與銲墊層303之間的接觸表面。因此，可減小阻擋層403的接觸電阻。因此，可提高半導體元件1A的可靠性。
相反地，倘若凹陷空間503未形成，阻擋層403係直接形成在貫穿基底開口501中的焊銲墊層303的曝露部份上。此情況下，阻擋層403與銲墊層303之間的接觸面是小於上述阻擋層403的凹部403R與銲墊層303之間的接觸表面。因此，阻擋層403的接觸電阻係更高且可靠性相關的問題將提高。
仍請參考圖8，一個附著層(為清楚起見未示出)可被共形地形成在阻擋層403上以及在貫穿基底開口部501與凹陷空間503中。該附著層係可，例如鈦、鉭、鈦鎢、錳氮化物的材料所製。該附著層可藉由一沉積製程形成，例如一物理氣相沉積製程、一原子層沉積製程、一化學氣相沉積製程，或一濺射製程。附著層可改善一種子層(後面將詳述)與阻擋層403之間的接合。
仍請參考圖8，可在附著層上及在貫穿基底開口501與凹陷空間503中共形地形成一種子層(為了清楚起見未示出)。該種子層可具有大約10nm到大約40nm範圍內的的厚度。該種子層可由例如銅形成。該種子層可藉由一沉積製程形成，例如一物理氣相沉積製程、一原子層沉積製程、一化學氣相沉積製程，或一濺射製程。該種子層可降低一填充層的形成製程中，貫穿基底開口501及凹陷空間503的電阻率。
參考圖1、圖9及圖10，在步驟25，可在貫穿基底開口501與凹陷空間50中形成一填充層405。
參考圖9，可形成導電材料505的一層以完全填充貫穿基底 開口501及凹陷空間503且覆蓋阻擋層403的覆蓋部403C。導電材料505可由例如多晶矽、鎢、銅、奈米碳管或錫合金所形成。導電材料505的該層可藉由一電鍍製程、一物理氣相沉積製程、一化學氣相沉積製程或一濺鍍製程形成。
舉例來說，導電材料505的層可藉由在具有硫酸銅、硫酸、氯化鈉、抑製劑、促進劑以及平整劑的酸槽(acid bath)中電鍍，而形成在貫穿基底開口501與凹陷空間503中。抑製劑可與氯離子相互作用以抑制銅沉積。促進劑可吸附在電極表面上，在該表面上促進劑可逐漸取代抑製劑，從而可進行銅的電鍍。平整劑可用於改善填充效能，減小表面粗糙度且防止銅沉積在貫穿基底開口501的上部。抑製劑係可例如聚乙二醇的聚合物。促進劑及整平劑係可例如3-巰基-1-丙烷磺酸鹽、(3-磺丙基丙基)二硫化物或3,3-硫代雙(1-丙烷磺酸鹽)。
在一些實施例中，可在圖9所示的中間半導體元件上執行一退火製程。該退火製程可減少後續的半導體製程期間銅蹺(copper-pumping)的不利影響，提高導電材料505的層與隔離層401之間的附著性，以及穩的導電材料505的層的微結構。
參考圖10，可執行例如化學機械拋光或研磨的一平坦化製程直到曝露隔離層401，以去除過量的材料，以提供實質上平坦的表面係用於隨後的處理步驟，且同時將導電材料505的層變成填充層405。在一些實施例中，可執行一平坦化製程直到曝露鈍化層301。在一些實施例中，該平坦化製程可執行直到曝露第二基底201。
仍請參考圖10，形成在貫穿基底開口501中的填充層405可被稱為填充層405的上部405U。形成在凹陷空間503中的填充層405可被 稱為填充層405的凹陷部405R。凹陷部405R的一深度D3可大於銲墊層303一半的厚度T1且小於銲墊層303的厚度T1。上部405U一側壁405US與凹陷部405R的一側壁405RS之間的一水平距離H2可等於或小於上部405U的深度D3。
應當理解，整個附圖中所使用的相同或相似的附圖標記用於表示相同或相似的特徵、元件或結構，因此，對於每個附圖中相同或相似的特徵、元件或結構的詳細說明，將不再重複。
圖11到圖14為依據本揭露另一實施例一種半導體元件1B之製備流程的剖視示意圖。
參考圖11，一中間半導體元件可由圖2到圖4所示的製程製造形成。可執行一擴展蝕刻製程以擴張鈍化層301中的貫穿基底開口501。在擴展蝕刻製程期間，鈍化層301與第二晶粒200的第二基底201的蝕刻速率之比可在大約100：1到大約1.05：1的範圍內。在一些實施例中，該擴展蝕刻製程係使用一濕蝕刻溶液的一濕蝕刻製程。該濕蝕刻溶液係可具有6：1緩衝氧化物蝕刻劑且包括7%w/w(質量百分濃度)的氫氟酸、34%w/w的氟化銨以及59%w/w的水的一氫氟酸溶液。在一些實施例中，該擴展蝕刻製程係一乾蝕刻製程，該乾蝕刻製程使用選自CH2F2、CHF3及C4F8組成的一組氣體。
在該擴展蝕刻製程之後，鈍化層301中的貫穿基底開口501的寬度可擴大，且第二晶粒200或第一晶粒100中的貫穿基底開口501的寬度可不變。結果，在擴展蝕刻製程之後，鈍化層301中的貫穿基底開口501的側壁可逐漸變細。在鈍化層301中的擴大貫穿基底開口部501可得到一改善的公差範圍以用於無空隙填充層形成，其中該改善的公差範圍藉由 提供額外的空間，消除來自鈍化層301中貫穿基底開口501的較快沉積速率所產生的不利影響。
參考圖12，隔離層401可在貫穿基底開口501中共形地形成，且可在鈍化層301的頂表面上共形地形成。鈍化層301與隔離層401之間的界面IF01係可錐形。鈍化層301中隔離層401的側壁401S還係一錐形。隔離層401可用類似圖5中所示的製程形成。鈍化層301的頂表面301TS與界面IF01(鈍化層301與隔離層401之間)之間的角度α可在大約120度到135度的範圍內。
參考圖13，可執行該沖孔蝕刻製程以曝露銲墊層303的頂表面的一部分。由於隔離層401形成在界面IF01(鈍化層301與隔離層401之間)上且隔離層401形成在鈍化層301的頂表面上，與形成在銲墊阻擋層307的頂表面上的隔離層401的厚度相比可具有更大的厚度。因此，形成在界面IF01(鈍化層301與隔離層401之間)上與形成在鈍化層301的頂表面上的隔離層401可僅在沖孔蝕刻製程之後變薄。
參考圖14，阻擋層403、該附著層、該種子層以及填充層405可藉由圖7到圖10所示的相似的製程形成。
圖15到圖17為依據本揭露另一實施例一種半導體元件1C之製備流程的剖視示意圖。
參考圖15，可提供圖12中所述的一中間半導體元件，且可執行一沖孔蝕刻製程。在該沖孔蝕刻製程之後，可曝露銲墊層303的頂表面的一部分，且形成在界面IF01上(鈍化層301與隔離層401之間)的隔離層401與形成在鈍化層301的頂表面上的隔離層401可去除。隔離層401的最高點401TP可在等於或低於第二基底201的頂表面201TS的垂直高度處。 而隔離層401的最高點401TP的垂直高度低於第二基底201的頂表面201TS的垂直高度。在填充層405的形成的期間，金屬到矽的洩漏可能發生。
參考圖16，可形成一保護層309以覆蓋隔離層401的上部。保護層309可藉由例如原子層沉積方法的一沉積製程形成，該沉積製程精確地控制該原子層沉積方法的第一前趨物的量。舉例來說，保護層309可由例如氧化鋁、氧化鉿、氧化鋯、氧化鈦、氮化鈦、氮化鎢、氮化矽或氧化矽所形成。
在一些實施例中，當保護層309由氧化鋁形成時，該原子層沉積方法的第一前趨物係可三甲基鋁，而該原子層沉積方法的第二前趨物係可水或臭氧。
在一些實施例中，當保護層309由氧化鉿形成時，該原子層沉積方法的第一前趨物係可四氯化鉿、叔丁醇鉿、二甲醯胺鉿、乙基甲醯胺鉿、二乙醯胺鉿或甲氧基叔丁醇鉿，以及該原子層沉積方法的第二前趨物係可水或臭氧。
在一些實施例中，當保護層309由氧化鋯形成時，該原子層沉積方法的第一前趨物係可四氯化鋯，而原子層沉積方法的第二前趨物係可水或臭氧。
在一些實施例中，當保護層309由氧化鈦形成時，該原子層沉積方法的第一前趨物係可四氯化鈦、鈦酸四乙酯或異丙醇鈦，而該原子層沉積方法的第二前趨物可水或臭氧。
在一些實施例中，當保護層309由氮化鈦形成時，該原子層沉積方法的第一前趨物係可四氯化鈦和氨。
在一些實施例中，當保護層309由氮化鎢形成時，該原子 層沉積方法的第一前趨物係可六氟化鎢和氨。
在一些實施方式中，當保護層309由氮化矽形成，該原子層沉積方法的第一前趨物係可亞甲矽烷、氯、氨及/或四氫化二氮。
在一些實施例中，當保護層309由氧化矽形成時，該原子層沉積方法的第一前趨物係可四異氰酸矽或CH3OSi(NCO)3，而該原子層沉積方法的第二前趨物係可氫或臭氧。
由於鈍化層301中的貫穿基底開口501的錐形側壁，所以保護層309的側壁309S係可實質上垂直的。保護層309可在隨後的半導體製程期間向鈍化層301和第二晶粒200提供額外的保護。因此，在填充層405的形成的期間，金屬到矽洩漏可被避免。因此，半導體元件1C的效能/產量可得到改善。
應當理解，在本發揭露的描述中，如果存在一個垂直平面，則該表面(或側壁)是“垂直的”，該表面與該垂直平面的偏離不超過平方根表面粗糙度的三倍。
參考圖17，阻擋層403、該附著層、該種子層以及填充層405可藉由圖7到圖10所示的相似的製程形成。在一些實施例中，如圖10中所示的平坦化製程可被執行直到曝露保護層309。在一些實施例中，如圖310所示的平坦化製程可被執行直到曝露鈍化層301。在一些實施例中，如圖103中所示的平坦化製程可被執行直到曝露第二基底201。
另外，由於保護層309的存在，可降低導電材料505在貫穿基底開口501的側壁上的沉積速率。因此，導電材料505在導電材料層505的側壁上的沉積速率與凹陷空間503中的導電材料505的沉積速率可彼此接近。因此，可在沒有任何空隙形成的情況下填充貫穿基底開口501及凹 陷空間503。可提高半導體元件1C的良率。
圖18為依據本揭露另一實施例一種半導體元件1D的剖視示意圖。
參考圖18，半導體元件1D可藉由與圖2到圖10所示的製程形成。主要區別在於：在第一晶粒100的第一接合層105中形成銲墊層303與銲墊阻擋層305、307，而不是在第一晶粒100的第一介電層103中形成銲墊層303與銲墊阻擋層305。銲墊阻擋層307的頂表面可與第一接合層105的頂表面實質上共面。
本揭露之一實施例提供一種半導體元件，該半導體元件包括一第一晶粒，一第二晶粒，一銲墊層，一填充層以及一阻擋層。該第二晶粒設置在該第一晶粒上。該銲墊層設置在該第一晶粒中。該填充層包括一上部及一凹陷部。該阻擋層設置在該第二晶料與該填充層的該上部之間、該第一晶粒與該填充層的該上部之間、以及該銲墊層與該填充層的該凹陷部之間。該填充層的該上部沿該第二晶粒與該第一晶粒設置，且該填充層的該凹陷部由該上部延伸且設置在該銲墊層中。
本揭露之另一實施例提供一種半導體元件的製方法，包括，執行一接合製程，將一第二晶粒接合到具有一銲墊層的一第一晶粒上；沿該第二晶粒形成延伸到該第一晶粒中的該銲墊層的一貫穿基底開口；共形地形成一隔離層在該貫穿基底開口中；執行一沖孔蝕刻製程以去除一部分隔離層且曝露執行一沖孔蝕刻製程以去除該隔離層的一部分且曝露該銲墊層的一頂表面的一部分；執行一等向性蝕刻製程係形成由該貫穿基底開口且在該焊盤層中延伸的一凹陷空間；共形地形成一阻擋層在該貫穿基底開口中與該凹陷空間中；以及，形成一阻擋層在該貫穿基底開口與 該凹陷空間中。
由於本揭露的半導體元件的設計，填充層405的上部405U可增加填充層405與阻擋層403之間的接觸表面，進而實現減小阻擋層403的接觸電阻。因此，可提高半導體元件1A的可靠性。另外，由於保護層309的幾何形狀，可形成沒有任何空隙的填充層405。因此，可提高半導體元件1C的製造良率。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
1A:半導體元件
100:半導體元件結構
100:第一晶粒
101:第一基底
103:第一介電層
105:第一結合層
107:第一元件部件
109:第一虛設導電層
200:第二晶粒
201:第二基底
203:第二介電層
205:第二接合層
207:第二元件部件
209:第二虛設導電層
301:鈍化層
303:銲墊層
305:銲墊阻擋層
307:銲墊阻擋層
401:隔離層
401S:側壁
403:阻擋層
403R:凹部
403U:上部
405:填充層
405R:凹陷部
405RS:凹陷部側壁
405U:上部
503:凹陷空間
D3:深度
H2:水平距離
T1:厚度

Claims (6)

  1. 一種半導體元件的製備方法，包括：執行一接合製程，將一第二晶粒接合到具有一銲墊層的一第一晶粒上；沿該第二晶粒形成延伸到該第一晶粒中的該銲墊層的一貫穿基底開口；共形地形成一隔離層在該貫穿基底開口中；執行一沖孔蝕刻製程以去除該隔離層的一部分且曝露該銲墊層的一頂表面的一部分；執行一等向性蝕刻製程係形成由該貫穿基底開口且在該焊盤層中延伸的一凹陷空間；共形地形成一阻擋層在該貫穿基底開口中與該凹陷空間中；以及形成一填充層在該貫穿基底開口與該凹陷空間中。
  2. 如請求項1所述之製備方法，其中該等向性蝕刻具有該銲墊層對該隔離層的一蝕刻速率比，係在大約100：1到大約1.05：1範圍內。
  3. 如請求項2所述之製備方法，其中該隔離層由氧化矽、氮化矽、氧氮化矽或原矽酸四乙酯形成。
  4. 如請求項2所述之製備方法，其中該填充層係由多晶矽、鎢、銅、奈米碳管或銲鍚合金形成。
  5. 如請求項4所述之製備方法，還包括一步驟：形成一鈍化層在該第二晶粒上，其中該貫穿基底開口沿該鈍化層與該第二晶粒係形成且延伸到該第一晶粒中的該銲墊層。
  6. 如請求項5所述之製備方法，其中該鈍化層由氮化矽、氮氧化矽、氧化矽、氧化氮化矽、環氧樹脂、聚酰亞胺、苯環丁烯或聚苯并噁唑形成。
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