TWI794092B - Memory device having double sided capacitor - Google Patents

Abstract

The present application provides a memory device having a double-sided capacitor. The memory device includes a semiconductor substrate; a capacitor protruding from the semiconductor substrate; a first supporting layer disposed on the semiconductor substrate and surrounding the capacitor; and a second supporting layer disposed above the first supporting layer and surrounding the capacitor, wherein the second supporting layer includes a first opening extending through the second supporting layer and disposed adjacent to the capacitor.

Description

Memory components with double-sided capacitors

This application claims priority to U.S. Provisional Application No. 63/291,547, filed December 20, 2021 (priority date is "December 20, 2021"). In addition, this application also claims the priority of US formal application Nos. 17/694,862 and 17/695,245 filed on March 15, 2022. The entire contents of the above-mentioned patent applications are hereby incorporated by reference and constitute a part of this specification.

The disclosure relates to a memory device. More particularly, it relates to a memory device having a capacitor with an improved parasitic capacitance and a strengthened overall structure.

Dynamic Random Access Memory (DRAM) is a semiconductor device used to store multiple bits of data in individual capacitors within an integrated circuit (IC). DRAMs are typically formed as capacitor DRAM cells. A DRAM memory circuit is fabricated by replicating DRAM cells on a single semiconductor wafer. Each DRAM cell can store one bit of data. A DRAM cell is composed of a storage capacitor and an access transistor. A widely used capacitor is called a tank capacitor, which has a cylindrical shape and a circular cross section. The bulk capacitor may be double-sided, wherein both sides of the lower electrode are surrounded by an upper electrode connected to a reference voltage in a surrounding area of the DRAM memory circuit.

Over the past few decades, as semiconductor manufacturing technology has continued to improve, the size of DRAM memory circuits has decreased accordingly. As the size of DRAM cells decreases to several nanometers in length, the strength of one structure of DRAM cells is a concern. May collapse or shake during manufacture. Accordingly, it would be desirable to develop improvements to address related manufacturing challenges.

An embodiment of the disclosure provides a memory device. The memory element includes a semiconductor base; a capacitor protruding from the semiconductor base; a first support layer disposed on the semiconductor base and surrounding the capacitor; and a second support layer disposed on the first support layer and surrounding the capacitor; wherein the second support layer includes a first opening extending through the second support layer and disposed adjacent to the capacitor.

In some embodiments, the first support layer and the second support layer are separated from each other.

In some embodiments, the capacitor includes a conductive layer electrically connected to the semiconductor substrate.

In some embodiments, the conductive layer includes a first portion and a second portion, the first portion is disposed on the semiconductor substrate and surrounded by the first support layer, the second portion protrudes from the first portion and is coupled to connected to the first part and surrounded by the second supporting layer.

In some embodiments, the conductive layer is an electrode of the capacitor.

In some embodiments, the conductive layer includes titanium nitride (TiN) or titanium silicon nitride (TiSiN).

In some embodiments, the first supporting layer and the second supporting layer include lattice nitride.

In some embodiments, the first support layer passes at least partially through the first opening exposed.

In some embodiments, the memory device further includes a third supporting layer disposed on the second supporting layer and surrounding the capacitor.

In some embodiments, the third support layer includes lattice nitride.

In some embodiments, the third support layer includes a second opening extending through the third support layer.

In some embodiments, the second opening is disposed on the first opening.

Another embodiment of the disclosure provides a method for manufacturing a memory device. The preparation method includes providing a semiconductor base; setting a first supporting layer on the semiconductor base; setting a first molding layer on the first supporting layer; setting a second supporting layer on the first molding layer ; removing a portion of the second support layer to form a first opening; placing a second molding layer on the second support layer and within the first opening; forming a groove to extend through the first support layer, the first molding layer, the second support layer, and the second molding layer; disposing a conductive layer conformal to the trench; and removing the first molding layer and the second molding layer .

In some embodiments, the first molding layer contacts the second molding layer at least partially through the first opening.

In some embodiments, the first opening extends between the first molding layer and the second molding layer.

In some embodiments, the first opening is formed before the first molding layer is removed.

In some embodiments, the first molding layer and the second molding layer are removed by a wet etching process.

In some embodiments, the first opening is formed before the second molding layer is disposed form.

In some embodiments, the first molding layer and the second molding layer include oxide.

In some embodiments, the portion of the second support layer is removed by a dry etching process.

In some embodiments, the first opening is formed before the conductive layer is disposed.

In some embodiments, a portion of the conductive layer is removed during removal of the first molding layer and the second molding layer.

In some embodiments, the conductive layer is at least partially disposed on the semiconductor substrate.

In some embodiments, removal of the first molding layer is performed immediately after removal of the second molding layer.

In some embodiments, the first molding layer extends at least partially through the second support layer after the first opening is formed.

In some embodiments, after the first molding layer and the second molding layer are removed, the first support layer and the second support layer surround the conductive layer.

Yet another embodiment of the present disclosure provides a method for manufacturing a memory device. The preparation method includes providing a semiconductor base; setting a first supporting layer on the semiconductor base; setting a first molding layer on the first supporting layer; setting a second supporting layer on the first molding layer forming a first opening through the second supporting layer to at least partially expose the first molding layer; providing a second molding layer on the second molding layer and within the first opening; providing a first Three support layers are on the second molding layer; a groove is formed to extend through the first support layer, the second support layer a molding layer, the second supporting layer, the second molding layer, and the third supporting layer; disposing a conductive layer conformal to the trench; removing a portion of the third supporting layer to form a second opening and at least partially exposing the second molding layer; and removing the first molding layer and the second molding layer.

In some embodiments, the first opening is formed before the portion of the third support portion is removed.

In some embodiments, the removal of the first molding layer and the second molding layer is performed immediately after the removal of the third support layer.

In some embodiments, the portion of the third support layer is removed by a dry etching process.

In some embodiments, during the removal of the portion of the third support layer, a portion of the conductive layer is removed.

In some embodiments, the first opening is formed before the third supporting layer is disposed.

In some embodiments, the first support layer, the second support layer and the third support layer comprise a same material.

In some embodiments, the first opening is formed before the trench is formed.

In some embodiments, the conductive layer is surrounded by the first support layer, the second support layer and the third support layer.

In summary, since an opening is formed in an intermediate support layer before a molding layer is disposed on the intermediate support layer, a subsequent etching of the molding layer can be performed in one go. Thus, accidental reduction of a conductive layer of a capacitor can be prevented or minimized during etching of the molding layer. Therefore, a strength of an overall structure of the capacitor can be improved. To improve an overall performance of a memory device and a process for manufacturing the memory device.

The technical features and advantages of the present disclosure have been broadly summarized above, so that the following detailed description of the present disclosure can be better understood. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those skilled in the art of the present disclosure should understand that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the disclosure defined by the appended claims.

100: the first memory element

101:Semiconductor substrate

101a: upper surface

101b: lower surface

102: The first support layer

103: The first molding layer

104: Second support layer

104a: first opening

105: Second molding layer

106: The third support layer

106a: second opening

107: Capacitor

107a: conductive layer

107b: Part I

107c: Part II

107d: electrode

108: Groove

109: The third opening

200: the second memory element

S300: Preparation method

S301: step

S302: step

S303: step

S304: step

S305: step

S306: step

S307: step

S308: step

S309: step

When referring to the drawings in conjunction with the embodiments and the patent scope of the application, the disclosure content of the application can be more fully understood. It should be understood that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 is a schematic cross-sectional side view illustrating a first memory device according to some embodiments of the disclosure.

FIG. 2 is a schematic top view illustrating the first memory device of FIG. 1 according to some embodiments of the present disclosure.

FIG. 3 is a schematic cross-sectional side view illustrating a second memory device according to other embodiments of the disclosure.

FIG. 4 is a schematic top view illustrating the second memory device of FIG. 3 according to other embodiments of the disclosure.

FIG. 5 is a schematic flow diagram illustrating a method for preparing a memory device according to some embodiments of the present disclosure.

6 to 23 are schematic cross-sectional views illustrating some embodiments of the present disclosure in the formation of memory elements the various intermediate stages.

Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Certainly, these embodiments are only for illustration, and are not intended to limit the scope of the present disclosure. For example, where a first component is formed on a second component, it may include embodiments where the first and second components are in direct contact, or may include an additional component formed between the first and second components, An embodiment such that the first and second parts do not come into direct contact. In addition, embodiments of the present disclosure may repeat reference numerals and/or letters in many instances. These repetitions are for the purpose of simplicity and clarity and, unless otherwise indicated in the context, do not in themselves imply a specific relationship between the various embodiments and/or configurations discussed.

Additionally, the present disclosure may repeat element numbers and/or letters in various instances. This repetition is for the purposes of simplicity and clarity, and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Additionally, for ease of description, spaces such as "beneath", "below", "lower", "above", "upper" may be used herein Relative relationship terms are used to describe the relationship of one element or feature to another (other) element or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be at other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

FIG. 1 is a schematic cross-sectional side view illustrating a first memory device 100 according to some embodiments of the disclosure. Furthermore, FIG. 2 is a schematic top view illustrating the first memory device 100 of FIG. 1 according to some embodiments of the present disclosure. In some embodiments, the first memory element 100 includes It includes several unit capacitor cells, and the unit capacitor cells are arranged in rows and columns.

In some embodiments, the first memory device 100 includes a semiconductor substrate 101 . In some embodiments, the semiconductor substrate 101 includes a semiconductor material such as silicon, germanium, gallium arsenide or a combination thereof. In some embodiments, the semiconductor substrate 101 includes bulk semiconductor material. In some embodiments, the semiconductor substrate 101 is a semiconductor wafer (such as a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (such as a silicon-on-insulator wafer). In some embodiments, the semiconductor substrate 101 is a silicon substrate. In some embodiments, the semiconductor substrate 101 includes lightly doped single crystal silicon. In some embodiments, the semiconductor substrate 101 is a p-type substrate.

In some embodiments, the semiconductor substrate 101 includes active areas (AA), which are doped regions in the semiconductor substrate 101 . In some embodiments, the active region extends horizontally on or below one of the upper surfaces of the semiconductor substrate 101 . In some embodiments, each active region includes a dopant of the same type. In some embodiments, each active region includes a different type of dopant than the type of dopant contained in the other active regions. In some embodiments, each active region has the same conductivity type.

In some embodiments, the semiconductor substrate 101 includes an upper surface 101a and a lower surface 101b, and the lower surface 101b is disposed opposite to the upper surface 101a. In some embodiments, the upper surface 101 a is a front side of the semiconductor substrate 101 , wherein a plurality of electronic devices or elements are sequentially formed on the upper surface 101 a and configured to be electrically connected to an external circuit. In some embodiments, the lower surface 101b is a rear side of the semiconductor substrate 101 without electronic devices or components.

In some embodiments, a landing pad is disposed on the upper surface 101 a of the semiconductor substrate 101 . The landing pad is configured to be electrically connected to an external conductive component. In some embodiments, the landing pad includes a conductive material such as copper (Cu), tungsten (W), or the like.

In some embodiments, the first memory element 100 includes a capacitor 107, protruding from the semiconductor substrate 101 . In some embodiments, the capacitor 107 is a container capacitor and has a circular, elliptical or polygonal cross-sectional shape. In some embodiments, the capacitor 107 has a circular cross section as shown in FIG. 2 . In some embodiments, the capacitor 107 is a double-sided capacitor in which the lower electrode is surrounded by two upper electrodes. In some embodiments, the capacitor 107 is disposed on the landing pad of the semiconductor substrate 101 and electrically connected to the landing pad of the semiconductor substrate 101 .

In some embodiments, the capacitor 107 includes a conductive layer 107 a electrically connected to the semiconductor substrate 101 . In some embodiments, the conductive layer 107 a is an electrode 107 d of a capacitor 107 or a part of the electrode 107 d of the capacitor 107 . In some embodiments, the conductive layer 107 a is the lower electrode of the capacitor 107 . In some embodiments, the electrode 107d of the capacitor 107 is electrically connected to the landing pad. In some embodiments, the conductive layer 107a includes a conductive material, such as titanium nitride (TiN) or titanium silicon nitride (TiSiN).

In some embodiments, the conductive layer 107a includes a first portion 107b and a second portion 107c, the first portion 107b is disposed on the semiconductor substrate 101, and the second portion 107c protrudes from the first portion 107b and is coupled to the first portion 107b. In some embodiments, the first portion 107b contacts the upper surface 101a of the semiconductor substrate 101 . In some embodiments, the second portion 107c extends away from the semiconductor substrate 101 and stands upright. In some embodiments, the first portion 107b is substantially orthogonal to the second portion 107c. In some embodiments, the first portion 107b and the second portion 107c have the same thickness.

In some embodiments, the first memory element 100 includes a first supporting layer 102 disposed on the semiconductor substrate 101 and surrounding the capacitor 107 . In some embodiments, the first portion 107b of the conductive layer 107a is surrounded by the first support layer 102 . In some embodiments, the first support layer 102 surrounds a portion of the second portion 107c of the conductive layer 107a. in some embodiments Among them, the first support layer 102 is an etch stop layer. In some embodiments, the first support layer 102 includes nitride, lattice nitride, silicon nitride, or the like.

In some embodiments, the first memory device 100 includes a second supporting layer 104 disposed on the first supporting layer 102 and surrounding the capacitor 107 . In some embodiments, the second portion 107c of the conductive layer 107a of the capacitor 107 is surrounded by the second support layer 104 . In some embodiments, the first support layer 102 and the second support layer 104 are separated from each other. In some embodiments, a thickness of the second support layer 104 is substantially equal to a thickness of the first support layer 102 . In some embodiments, the second support layer 104 is an etch stop layer. In some embodiments, the second supporting layer 104 and the first supporting layer 102 include the same material. In some embodiments, the second support layer 104 includes nitride, lattice nitride, silicon nitride, or the like.

In some embodiments, the second supporting layer 104 includes a first opening 104 a extending through the second supporting layer 104 and disposed adjacent to the capacitor 107 . In some embodiments, the first supporting layer 102 is at least partially exposed through the first opening 104a. The first opening 104a is disposed on the first supporting layer 102 . In some embodiments, the first opening 104a is surrounded by the second portion 107c of the conductive layer 107a of the capacitor 107 . In some embodiments, the first opening 104a is configured to allow an etchant to flow therethrough. In some embodiments, the first opening 104 a tapers toward the first support layer 102 .

In some embodiments, the first memory device 100 includes a third support layer 106 disposed on the second support layer 104 . In some embodiments, third support layer 106 surrounds capacitor 107 . In some embodiments, the third support layer 106 surrounds the second portion 107c of the conductive layer 107a of the capacitor 107 . In some embodiments, an upper surface of the third support layer 106 is substantially coplanar with an upper surface of the conductive layer 107a. In some embodiments, a thickness of the third support layer 106 is substantially greater than a thickness of the second support layer 104 . In some embodiments, the third support layer 106 The thickness is substantially greater than the thickness of the first supporting layer 102 .

In some embodiments, the second support layer 104 is disposed between the first support layer 102 and the third support layer 106 . In some embodiments, the third support layer 106 is spaced apart from the first support layer 102 and the second support layer 104 . In some embodiments, the third support layer 106 is an etch stop layer. In some embodiments, the third support layer 106 includes the same material as the first support layer 102 and the second support layer 104 . In some embodiments, the third support layer 106 includes nitride, lattice nitride, silicon nitride, or the like.

In some embodiments, the third supporting layer 106 includes a second opening 106 a extending through the third supporting layer 106 and disposed adjacent to the capacitor 107 . In some embodiments, the first supporting layer 102 is at least partially exposed through the second opening 106a. In some embodiments, the second supporting layer 104 is at least partially exposed through the second opening 106a. In some embodiments, the second opening 106a is disposed over the first opening 104a. In some embodiments, the second opening 106 a is disposed on the second supporting layer 104 .

In some embodiments, the second opening 106a is surrounded by the second portion 107c of the conductive layer 107a of the capacitor 107 . In some embodiments, the second opening 106a is configured to allow an etchant to flow therethrough. In some embodiments, a width of the first opening 104a is substantially smaller than a width of the second opening 106a. In some embodiments, the second opening 106 a is tapered toward the second support layer 104 and the first support layer 102 .

Since the second support layer 104 has a first opening 104a configured to allow the etchant to flow therethrough, accidental reduction of the conductive layer 107a of the capacitor 107 can be prevented or minimized during the manufacture of the first memory element 100. . Therefore, a strength of an overall structure of the capacitor 107 can be improved. An overall performance of the first memory device 100 is improved.

FIG. 3 is a schematic cross-sectional side view illustrating a first embodiment according to other embodiments of the disclosure. Two memory elements 200 . Furthermore, FIG. 4 is a schematic top view illustrating the second memory device 200 of FIG. 3 according to other embodiments of the disclosure. The second memory element 200 is similar to the first memory element 100 of FIG. 1, except that some portions of the conductive layer 107a are removed to enlarge the second opening 106a compared to the first memory element 100 of FIG. 1, thus forming Outside a third opening 109 as shown in FIG. 3 .

In some embodiments, the third opening 109 is disposed on the capacitor 107 . In some embodiments, the third opening 109 tapers toward the capacitor 107 . In some embodiments, a width of the third opening 109 is substantially greater than a width of the second opening 106 a of the first memory device 100 . In some embodiments, the upper surface of the second portion 107 c of the conductive layer 107 a is located on a plane lower than the upper surface of the third supporting layer 106 . In some embodiments, a height of the capacitor 107 in the second memory device 200 is substantially smaller than a height of the capacitor 107 in the first memory device 100 .

FIG. 5 is a schematic flowchart illustrating a method S300 of manufacturing the first memory device 100 or the second memory device 200 according to some embodiments of the present disclosure. 6 to 23 are schematic cross-sectional views illustrating various intermediate stages in the formation of the first memory device 100 or the second memory device 200 in some embodiments of the present disclosure.

The stages shown in FIGS. 6 to 23 are also illustratively described in the flowchart in FIG. 5 . In the following discussion, the fabrication stages shown in FIGS. 6 through 23 are discussed with reference to the processing steps shown in FIG. 5 . The preparation method S300 includes some steps, and the description and description thereof are not considered as limiting the order of the steps. The preparation method S300 includes some steps (S301, S302, S303, S304, S305, S306, S307, S308, S309).

Please refer to FIG. 6 , according to step S301 of FIG. 5 , a semiconductor substrate 101 is provided. In some embodiments, the semiconductor substrate 101 includes semiconductor materials such as silicon, germanium, Gallium arsenide or combinations thereof. In some embodiments, the semiconductor substrate 101 includes an upper surface 101a and a lower surface 101b, and the lower surface 101b is disposed opposite to the upper surface 101a. In some embodiments, the upper surface 101 a is a front side of the semiconductor substrate 101 , wherein a plurality of electronic devices or elements are sequentially formed on the upper surface 101 a and configured to be electrically connected to an external circuit. In some embodiments, the lower surface 101b is a rear side of the semiconductor substrate 101 without electronic devices or components.

In some embodiments, a landing pad is disposed on the upper surface 101 a of the semiconductor substrate 101 . The landing pad is configured to be electrically connected to an external conductive component. In some embodiments, the landing pad includes a conductive material such as copper (Cu), tungsten (W), or the like.

Please refer to FIG. 7 , according to step S302 of FIG. 5 , a first supporting layer 102 is disposed on the semiconductor substrate 101 . In some embodiments, the first support layer 102 is deposited by deposition, atomic layer deposition (ALD), or any other suitable process. In some embodiments, the first supporting layer 102 is disposed on the upper surface 101 a of the semiconductor substrate 101 to completely cover the semiconductor substrate 101 . In some embodiments, the first support layer 102 includes nitride, lattice nitride, silicon nitride, or the like.

Please refer to FIG. 8 , according to step S303 of FIG. 5 , a first molding layer 103 is disposed on the first supporting layer 102 . In some embodiments, the first molding layer 103 is formed by thin film coating, chemical vapor deposition (CVD), or any other suitable process. In some embodiments, the first molding layer 103 completely covers the first supporting layer 102 . In some embodiments, the first molding layer 103 includes a dielectric material such as an oxide, a doped oxide film, borophosphosilicate glass (BPSG), or the like.

Please refer to FIG. 9 , according to step S304 of FIG. 5 , a second supporting layer 104 is disposed on the first molding layer 103 . In some embodiments, the second support layer 104 is formed by deposition, ALD or any other suitable process. In some embodiments, the second support layer 104 completely covers Cover the first molding layer 103 . In some embodiments, the second support layer 104 includes nitride, lattice nitride, silicon nitride, or the like. In some embodiments, the first supporting layer 102 and the second supporting layer 104 include the same material.

Referring to FIG. 10 and FIG. 11 , according to step S305 of FIG. 5 , a part of the second supporting layer 104 is removed to form a first opening 104 a. FIG. 11 is a top view of FIG. 10 . In some embodiments, the portion of the second support layer 104 is removed by etching, dry etching, or any other suitable process. In some embodiments, the first opening 104 a extends through the second support layer 104 .

In some embodiments, the first molding layer 103 is at least partially exposed through the first opening 104a. In some embodiments, after the first opening 104 a is formed, the first molding layer 103 is at least partially exposed through the second supporting layer 104 . In some embodiments, the first opening 104a is configured to allow an etchant to flow therethrough. In some embodiments, the first opening 104 a tapers toward the first molding layer 103 .

Please refer to FIG. 12 , according to step S306 of FIG. 5 , a second molding layer 105 is disposed on the second supporting layer 104 and inside the first opening 104 a. In some embodiments, the first molding layer 103 at least partially contacts the second molding layer 105 through the first opening 104a. In some embodiments, the first opening 104 a extends between the first molding layer 103 and the second molding layer 105 . In some embodiments, the first opening 104a is formed before the second molding layer 105 is disposed.

In some embodiments, the second molding layer 105 is formed by thin film coating, CVD, or any other suitable process. In some embodiments, the second molding layer 105 includes a dielectric material such as an oxide, a doped oxide film, BPSG, or the like. In some embodiments, the first molding layer 103 and the second molding layer 105 include the same material.

In some embodiments, after the second molding layer 105 is disposed, a third supporting layer 106 is disposed on the second molding layer 105 as shown in FIG. 13 . Set on the third supporting layer 106 Before, the first opening 104a is formed. In some embodiments, the third supporting layer 106 is formed by deposition, ALD or any other suitable process. In some embodiments, the third support layer 106 completely covers the second molding layer 105 . In some embodiments, the third support layer 106 includes nitride, lattice nitride, silicon nitride, or the like. In some embodiments, the first support layer 102 , the second support layer 104 and the third support layer 106 include the same material.

Please refer to FIG. 14 and FIG. 15, according to step S307 of FIG. Layer 105. In some embodiments, trench 108 extends through third support layer 106 . FIG. 15 is a top view of FIG. 14 . In some embodiments, the first opening 104a is formed before the trench 108 is formed. In some embodiments, the trench 108 is fabricated by removing portions of the first support layer 102 , the first molding layer 103 , the second support layer 104 , and the second molding layer 105 .

In some embodiments, portions of the first support layer 102 , the first molding layer 103 , the second support layer 104 , and the second molding layer 105 are removed all at once or sequentially. In some embodiments, portions of the first supporting layer 102 , the first molding layer 103 , the second supporting layer 104 and the second molding layer 105 are removed by etching or any other suitable process. In some embodiments, the semiconductor substrate 101 is at least partially exposed through the trench 108 .

Please refer to FIG. 16 and FIG. 17 , according to step S308 in FIG. 5 , a conductive layer 107 a is conformally disposed on the trench 108 . FIG. 17 is a top view of FIG. 16 . In some embodiments, the conductive layer 107a includes a conductive material, such as TiN or TiSiN. In some embodiments, the conductive layer 107a is formed by deposition or any other suitable process. In some embodiments, the conductive layer 107 a is disposed conformally to each sidewall of the first supporting layer 102 , the first molding layer 103 , the second supporting layer 104 , the second molding layer 105 and the third supporting layer 106 . In some embodiments, at least part of the conductive layer 107a are disposed on the semiconductor substrate 101. In some embodiments, an upper surface of the third supporting layer 106 is exposed through the conductive layer 107a. In some embodiments, the upper surface of the third supporting layer 106 is substantially coplanar with an upper surface of the conductive layer 107a.

In some embodiments, the first opening 104a is formed before the conductive layer 107a is disposed. In some embodiments, the conductive layer 107 a is surrounded by the first supporting layer 102 , the second supporting layer 104 and the third supporting layer 106 . In some embodiments, the conductive layer 107 a is surrounded by the first molding layer 103 and the second molding layer 105 .

In some embodiments, as shown in FIG. 18 and FIG. 19 , a part of the third supporting layer 106 is removed to form a second opening 106 a and at least partially expose the second molding layer 105 . FIG. 19 is a top view of FIG. 18 . In some embodiments, the portion of the third support layer 106 is removed by etching, dry etching, or any other suitable process.

In some embodiments, the first opening 104a is formed before the portion of the third support layer 106 is removed. In some embodiments, the second opening 106a is configured to allow an etchant to flow therethrough. In some embodiments, the second opening 106a is disposed over the first opening 104a. In some embodiments, the second opening 106a is tapered toward the second support layer 104 and the first support layer 102 .

Please refer to FIG. 20 , according to step S309 of FIG. 5 , the first molding layer 103 and the second molding layer 105 are removed. In some embodiments, the first molding layer 103 and the second molding layer 105 are removed by etching, wet etching or any other suitable process. In some embodiments, the removing includes flowing an etchant from the second opening 106a to the first opening 104a. In some embodiments, the etchant flows through the second opening 106 a to remove the second molding layer 105 , and then the etchant flows through the first opening 104 a to remove the first molding layer 103 . In some embodiments, the etchant is a wet etchant, such as hydrofluoric acid or the like.

In some embodiments, the first opening 104a is formed before the first molding layer 103 is removed. In some embodiments, the removal of the first molding layer 103 is performed immediately after the removal of the second molding layer 105 . In some embodiments, the removal of the first molding layer 103 and the second molding layer 105 is performed immediately after the portion of the third support layer 106 is removed. In some embodiments, after the first molding layer 103 and the second molding layer 105 are removed, the first supporting layer 102 and the second supporting layer 104 surround the conductive layer 107a.

In some embodiments, the conductive layer 107 a is an electrode 107 d of the capacitor 107 or a part of the electrode 107 d of the capacitor 107 . In some embodiments, the conductive layer 107 a is the lower electrode of the capacitor 107 . In some embodiments, the electrode 107d of the capacitor 107 is electrically connected to the landing pad. In some embodiments, a first memory device 100 as shown in FIG. 1 is formed.

Because the second support layer 104 has the first opening 104a configured to allow the etchant to flow therethrough before the second molding layer 105 is removed, the first can be performed immediately after the second molding layer 105 is removed. Removal of the molding layer 103 . In this way, accidental reduction of the conductive layer 107a can be prevented or minimized during the formation of the first opening 104a. Therefore, a strength of the overall structure of the capacitor 107 can be enhanced.

In some embodiments, after the conductive layer 107a shown in FIG. 16 is disposed, the fabrication technique of the second memory device 200 in FIG. 2 may include the following steps. After the conductive layer 107a shown in FIG. 16 is disposed, a third opening 109 as shown in FIGS. 21 and 22 is formed. In some embodiments, some portions of the third supporting layer 106 , the second molding layer 105 and the conductive layer 107 a are removed to form the third opening 109 . In some embodiments, the portions of the third supporting layer 106, the second molding layer 105, and the conductive layer 107a are removed by etching or any other suitable process. In some embodiments, the third opening 109 is configured to allow an etchant to flow therethrough.

In some embodiments, as shown in FIG. 23 , after the formation of the third opening 109 , the first molding layer 103 and the second molding layer 105 are removed in a manner similar to step S309 described above. In some embodiments, a second memory element 200 as shown in FIG. 3 is formed.

An embodiment of the disclosure provides a memory device. The memory element includes a semiconductor base; a capacitor protruding from the semiconductor base; a first support layer disposed on the semiconductor base and surrounding the capacitor; and a second support layer disposed on the first support layer and surrounding the capacitor; wherein the second support layer includes a first opening extending through the second support layer and disposed adjacent to the capacitor.

Another embodiment of the disclosure provides a method for manufacturing a memory device. The preparation method includes providing a semiconductor base; setting a first supporting layer on the semiconductor base; setting a first molding layer on the first supporting layer; setting a second supporting layer on the first molding layer ; removing a portion of the second support layer to form a first opening; placing a second molding layer on the second support layer and within the first opening; forming a groove to extend through the first support layer, the first molding layer, the second support layer, and the second molding layer; disposing a conductive layer conformal to the trench; and removing the first molding layer and the second molding layer .

Yet another embodiment of the present disclosure provides a method for manufacturing a memory device. The preparation method includes providing a semiconductor base; setting a first supporting layer on the semiconductor base; setting a first molding layer on the first supporting layer; setting a second supporting layer on the first molding layer forming a first opening through the second supporting layer to at least partially expose the first molding layer; providing a second molding layer on the second molding layer and within the first opening; providing a first Three supporting layers on the second molding layer; forming a groove extending through the first supporting layer, the first molding layer, the second supporting layer, the second molding layer and the third supporting layer ; providing a conductive layer conformal to the trench; removing a portion of the third support layer to form a second opening, and to exposing a small portion of the second molding layer; and removing the first molding layer and the second molding layer.

In summary, since an opening is formed in an intermediate support layer before a molding layer is disposed on the intermediate support layer, a subsequent etching of the molding layer can be performed in one go. Thus, accidental reduction of a conductive layer of a capacitor can be prevented or minimized during etching of the molding layer. Therefore, a strength of an overall structure of the capacitor can be improved. To improve an overall performance of a memory device and a process for manufacturing the memory device.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be performed in different ways and replaced by other processes or combinations thereof.

Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, A composition of matter, means, method, or step. Accordingly, such process, machinery, manufacture, material composition, means, method, or steps are included in the patent scope of this application.

100: the first memory element

101:Semiconductor substrate

101a: upper surface

101b: lower surface

102: The first support layer

104: Second support layer

104a: first opening

106: The third support layer

106a: second opening

107: Capacitor

107a: conductive layer

107b: Part I

107c: Part II

107d: electrode

Claims (12)

A memory element comprising: a semiconductor substrate; a capacitor protruding from the semiconductor substrate; a first supporting layer disposed on the semiconductor substrate and surrounding the capacitor; and a second supporting layer disposed on the first The supporting layer surrounds the capacitor; wherein the second supporting layer includes a first opening extending through the second supporting layer and located between different electrode layers of the capacitor. The memory device according to claim 1, wherein the first support layer and the second support layer are separated from each other. The memory device as claimed in claim 1, wherein the capacitor includes a conductive layer electrically connected to the semiconductor substrate. The memory element as claimed in item 3, wherein the conductive layer includes a first part and a second part, the first part is disposed on the semiconductor substrate and surrounded by the first support layer, and the second part is separated from the The first portion protrudes and is coupled to the first portion, and is surrounded by the second supporting layer. The memory device as claimed in claim 4, wherein the conductive layer is an electrode of the capacitor. The memory device as claimed in claim 4, wherein the conductive layer comprises titanium nitride or silicon titanium nitride. The memory device as claimed in claim 1, wherein the first support layer and the second support layer comprise lattice nitride. The memory device as claimed in claim 1, wherein the first supporting layer is at least partially exposed through the first opening. The memory device according to claim 1, further comprising a third supporting layer disposed on the second supporting layer and surrounding the capacitor. The memory device as claimed in claim 9, wherein the third supporting layer comprises lattice nitride. The memory device as claimed in claim 9, wherein the third support layer includes a second opening extending through the third support layer. The memory device as claimed in claim 11, wherein the second opening is disposed on the first opening.

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