TWI792971B - Voltage regulating circuit and current limiting circuit - Google Patents

Voltage regulating circuit and current limiting circuit Download PDF

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TWI792971B
TWI792971B TW111113391A TW111113391A TWI792971B TW I792971 B TWI792971 B TW I792971B TW 111113391 A TW111113391 A TW 111113391A TW 111113391 A TW111113391 A TW 111113391A TW I792971 B TWI792971 B TW I792971B
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clamping
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transistor
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TW202340898A (en
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李銘富
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盛群半導體股份有限公司
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Priority to CN202210486389.XA priority patent/CN116931647A/en
Priority to CN202221068237.XU priority patent/CN217426005U/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

A voltage regulating circuit and a current limiting circuit are provided. The voltage regulation circuit includes an error amplifier, an output transistor, and a current limit circuit. The error amplifier provides a control signal in response to variations of an output voltage. The output transistor receives an input voltage and adjusts the output voltage in response to the control signal and the input voltage. The current limiting circuit includes a sensing circuit, a voltage clamping circuit and a control signal clamping circuit. The sensing circuit provides a sensing current according to the output current. The voltage clamping circuit provides a clamping current according to the comparison result between a voltage value of the input voltage and the at least one clamping voltage value. The control signal clamping circuit clamps a voltage value of the control signal in response to the clamping current and a current value of the sensing current, so that a limited output current value flowing through the output transistor and the input voltage value have a negative correlation.

Description

電壓調節電路以及電流限制電路Voltage regulation circuit and current limit circuit

本發明是有關於一種電壓調節電路以及電流限制電路。本發明的電流限制電路依據輸入電壓值，分段調整輸出電流的限制值。本發明的電流限制電路在輸出空載狀態下具有低靜態電流，能夠實現於低靜態電流的電壓調節電路。The invention relates to a voltage regulating circuit and a current limiting circuit. The current limiting circuit of the present invention adjusts the limiting value of the output current in sections according to the input voltage value. The current limiting circuit of the present invention has low quiescent current in an output no-load state, and can be implemented in a voltage regulation circuit with low quiescent current.

靜態電流（Quiescent Current）是輸出空載狀態下，裝置所消耗的電流。一般來說，依據輸入電壓調整輸出限流值的電流限制電路，都會消耗額外的靜態電流。基於環保以及低功率消耗的規範，低靜態電流的電路是本領域技術人員的研究重點之一。The quiescent current is the current consumed by the device in the output no-load state. Generally speaking, the current limit circuit that adjusts the output current limit value according to the input voltage will consume additional quiescent current. Based on the standards of environmental protection and low power consumption, circuits with low quiescent current are one of the research focuses of those skilled in the art.

本發明的電流限制電路依據輸入電壓值，分段調整輸出電流的限制值。本發明的電流限制電路在輸出空載狀態下具有低靜態電流，能夠實現於低靜態電流的電壓調節電路。The current limiting circuit of the present invention adjusts the limiting value of the output current in sections according to the input voltage value. The current limiting circuit of the present invention has low quiescent current in an output no-load state, and can be implemented in a voltage regulation circuit with low quiescent current.

本發明的電壓調節電路包括誤差放大器、輸出電晶體以及電流限制電路。誤差放大器反應於輸出電壓的變動來提供控制訊號。輸出電晶體耦接於誤差放大器的輸出端。輸出電晶體接收輸入電壓，並反應於控制訊號以及輸入電壓來調節輸出電壓。電流限制電路包括感測電路、箝位電路以及控制訊號箝制電路。感測電路依據輸出電流提供感測電流。箝位電路提供至少一箝位電壓值，並依據輸入電壓的電壓值與所述至少一箝位電壓值的比較結果來提供箝位電流。控制訊號箝制電路耦接於誤差放大器的輸出端、感測電路以及箝位電路。控制訊號箝制電路反應於感測電流和箝位電流的電流值來箝制控制訊號的電壓值，使得流經輸出電晶體的輸出電流限制值與輸入電壓值呈現負相關。The voltage regulating circuit of the present invention includes an error amplifier, an output transistor and a current limiting circuit. The error amplifier provides a control signal in response to changes in the output voltage. The output transistor is coupled to the output terminal of the error amplifier. The output transistor receives the input voltage and responds to the control signal and the input voltage to adjust the output voltage. The current limiting circuit includes a sensing circuit, a clamping circuit and a control signal clamping circuit. The sensing circuit provides sensing current according to the output current. The clamping circuit provides at least one clamping voltage value, and provides a clamping current according to a comparison result between the voltage value of the input voltage and the at least one clamping voltage value. The control signal clamping circuit is coupled to the output terminal of the error amplifier, the sensing circuit and the clamping circuit. The control signal clamping circuit responds to the current values of the sensing current and the clamping current to clamp the voltage value of the control signal, so that the output current limit value flowing through the output transistor is negatively correlated with the input voltage value.

本發明的電流限制電路用於對輸出電晶體的輸出電流值進行限制。輸出電晶體受控於控制訊號。電流限制電路包括感測電路、箝位電路以及控制訊號箝制電路。感測電路依據輸出電流提供感測電流。箝位電路提供至少一箝位電壓值，並依據輸入電壓的電壓值與所述至少一箝位電壓值的比較結果來提供箝位電流。控制訊號箝制電路耦接於輸出電晶體的控制端、感測電路以及箝位電路。控制訊號箝制電路反應於感測電流和箝位電流的電流值來箝制控制訊號的電壓值，使得輸出電流限制值與輸入電壓值呈現負相關。The current limiting circuit of the present invention is used to limit the output current value of the output transistor. The output transistor is controlled by the control signal. The current limiting circuit includes a sensing circuit, a clamping circuit and a control signal clamping circuit. The sensing circuit provides sensing current according to the output current. The clamping circuit provides at least one clamping voltage value, and provides a clamping current according to a comparison result between the voltage value of the input voltage and the at least one clamping voltage value. The control signal clamping circuit is coupled to the control terminal of the output transistor, the sensing circuit and the clamping circuit. The control signal clamping circuit responds to the current values of the sensing current and the clamping current to clamp the voltage value of the control signal, so that the output current limit value is negatively correlated with the input voltage value.

基於上述，本發明的電流限制電路依據輸入電壓的電壓值與所述至少一箝位電壓值的比較結果來提供箝位電流，並反應於感測電流和箝位電流的電流值來箝制控制訊號的電壓值。電流限制電路能夠使輸入電壓的電壓值與輸出電流值呈現負相關。在輸出不抽載時，感測電流和箝位電流接近零電流，不增加額外的靜態電流。Based on the above, the current limiting circuit of the present invention provides the clamping current according to the comparison result of the voltage value of the input voltage and the at least one clamping voltage value, and clamps the control signal in response to the current value of the sensing current and the clamping current. voltage value. The current limiting circuit can make the voltage value of the input voltage negatively correlated with the output current value. When the output is not pumped, the sensing current and clamping current are close to zero current, and no additional quiescent current is added.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

本發明的部份實施例接下來將會配合附圖來詳細描述，以下的描述所引用的元件符號，當不同附圖出現相同的元件符號將視為相同或相似的元件。這些實施例只是本發明的一部份，並未揭示所有本發明的可實施方式。更確切的說，這些實施例只是本發明的專利申請範圍中的範例。Parts of the embodiments of the present invention will be described in detail with reference to the accompanying drawings. For the referenced reference symbols in the following description, when the same reference symbols appear in different drawings, they will be regarded as the same or similar components. These embodiments are only a part of the present invention, and do not reveal all possible implementation modes of the present invention. Rather, these embodiments are only examples within the scope of the patent application of the present invention.

請參考圖1，圖1是依據本發明的第一實施例所繪示的電壓調節電路的示意圖。在本實施例中，電壓調節電路100包括誤差放大器EA、輸出電晶體MO以及電流限制電路110。誤差放大器EA反應於輸出電壓VOUT的變動來提供控制訊號VG。輸出電晶體MO耦接於誤差放大器EA的輸出端。輸出電晶體MO接收輸入電壓VIN，並反應於控制訊號VG以及輸入電壓VIN來調節輸出電壓VOUT。Please refer to FIG. 1 , which is a schematic diagram of a voltage regulating circuit according to a first embodiment of the present invention. In this embodiment, the voltage regulating circuit 100 includes an error amplifier EA, an output transistor MO and a current limiting circuit 110 . The error amplifier EA responds to the change of the output voltage VOUT to provide the control signal VG. The output transistor MO is coupled to the output terminal of the error amplifier EA. The output transistor MO receives the input voltage VIN, and responds to the control signal VG and the input voltage VIN to adjust the output voltage VOUT.

舉例來說，誤差放大器EA的第一輸入端接收參考電壓值VREF。誤差放大器EA的第二輸入端接收回饋電壓值FB。回饋電壓值FB關聯於輸出電壓VOUT的電壓值。誤差放大器EA會依據參考電壓值VREF以及回饋電壓值FB的比較結果來經由誤差放大器EA的輸出端提供控制訊號VG。輸出電晶體MO的第一端接收輸入電壓VIN。輸出電晶體MO的第二端作為電壓調節電路100的輸出端。輸出電晶體MO的控制端耦接於誤差放大器EA的輸出端。因此，輸出電晶體MO受控於控制訊號VG以調節輸出電壓VOUT。For example, the first input terminal of the error amplifier EA receives the reference voltage VREF. The second input terminal of the error amplifier EA receives the feedback voltage value FB. The feedback voltage value FB is related to the voltage value of the output voltage VOUT. The error amplifier EA provides the control signal VG through the output terminal of the error amplifier EA according to the comparison result of the reference voltage VREF and the feedback voltage FB. The first terminal of the output transistor MO receives the input voltage VIN. The second terminal of the output transistor MO serves as the output terminal of the voltage regulation circuit 100 . The control terminal of the output transistor MO is coupled to the output terminal of the error amplifier EA. Therefore, the output transistor MO is controlled by the control signal VG to adjust the output voltage VOUT.

在本實施例中，電流限制電路110包括感測電路111、箝位電路112以及控制訊號箝制電路113。感測電路111依據輸出電流值IOUT提供感測電流ISEN。箝位電路112提供至少一箝位電壓值，並依據輸入電壓VIN的電壓值與所述至少一箝位電壓值的比較結果來提供箝位電流IPS。舉例來說，輸入電壓VIN的電壓值越高，箝位電路112產生箝位電流IPS的電流值比較大。在另一方面，輸入電壓VIN的電壓值越低，箝位電路112產生箝位電流IPS的電流值比較小。In this embodiment, the current limiting circuit 110 includes a sensing circuit 111 , a clamping circuit 112 and a control signal clamping circuit 113 . The sensing circuit 111 provides a sensing current ISEN according to the output current value IOUT. The clamping circuit 112 provides at least one clamping voltage value, and provides a clamping current IPS according to a comparison result between the voltage value of the input voltage VIN and the at least one clamping voltage value. For example, the higher the voltage value of the input voltage VIN is, the larger the current value of the clamping current IPS generated by the clamping circuit 112 is. On the other hand, the lower the voltage value of the input voltage VIN is, the smaller the current value of the clamping current IPS generated by the clamping circuit 112 is.

控制訊號箝制電路113耦接於誤差放大器EA的輸出端、感測電路111以及箝位電路112。控制訊號箝制電路113反應於感測電流ISEN的電流值和箝位電流IPS的電流值來箝制控制訊號VG的電壓值。舉例來說，箝位電流IPS的電流值越多，輸出電流值IOUT限制的越低。在另一方面，箝位電流IPS的電流值越小，輸出電流值IOUT限制的越大。因此，基於電流限制電路110的操作，流經輸出電晶體MO的輸出電流限制值與輸入電壓VIN的電壓值呈現負相關。The control signal clamping circuit 113 is coupled to the output terminal of the error amplifier EA, the sensing circuit 111 and the clamping circuit 112 . The control signal clamping circuit 113 clamps the voltage value of the control signal VG in response to the current value of the sensing current ISEN and the current value of the clamping current IPS. For example, the larger the current value of the clamping current IPS, the lower the output current value IOUT is limited. On the other hand, the smaller the current value of the clamping current IPS, the larger the output current value IOUT is limited. Therefore, based on the operation of the current limit circuit 110 , the limit value of the output current flowing through the output transistor MO has a negative correlation with the voltage value of the input voltage VIN.

在此值得一提的是，電流限制電路110依據輸入電壓VIN的電壓值與所述至少一箝位電壓值的比較結果來提供箝位電流IPS，並反應於感測電流ISEN的電流值和箝位電流IPS的電流值來箝制控制訊號VG的電壓值。因此，電流限制電路110能夠使輸入電壓VIN的電壓值與輸出電流限流值呈現負相關。在輸出電流值IOUT為零時，感測電流ISEN和箝位電流IPS接近零電流，不增加額外的靜態電流。It is worth mentioning here that the current limiting circuit 110 provides the clamping current IPS according to the comparison result between the voltage value of the input voltage VIN and the at least one clamping voltage value, and responds to the current value of the sensing current ISEN and the clamping voltage value. The current value of the bit current IPS clamps the voltage value of the control signal VG. Therefore, the current limiting circuit 110 can make the voltage value of the input voltage VIN negatively correlated with the output current limiting value. When the output current value IOUT is zero, the sensing current ISEN and the clamping current IPS are close to zero current, and no additional quiescent current is added.

在本實施例中，輸出電晶體MO可以是由任意形式的雙極性電晶體（Bipolar Junction Transistor，BJT）或場效電晶體（Field-Effect Transistor，FET）來實現。在本實施例中，輸出電晶體MO以p型金氧半場效電晶體（Metal-Oxide-Semiconductor FET，MOSFET）來示例。因此，誤差放大器EA的第一輸入端是反相輸入端。誤差放大器EA的第二輸入端是非反相輸入端。在本實施例中，電壓調節電路100包括分壓電阻器RD1、RD2。分壓電阻器RD1耦接於輸出電晶體MO的第二端與誤差放大器EA的第二輸入端之間。分壓電阻器RD2耦接於誤差放大器EA的第二輸入端與參考低電壓VL（例如是接地）之間。分壓電阻器RD1、RD2會對輸出電壓VOUT的電壓值進行分壓以產生回饋電壓值FB。In this embodiment, the output transistor MO may be implemented by any form of bipolar junction transistor (Bipolar Junction Transistor, BJT) or field effect transistor (Field-Effect Transistor, FET). In this embodiment, the output transistor MO is exemplified by a p-type Metal-Oxide-Semiconductor FET (MOSFET). Therefore, the first input terminal of the error amplifier EA is an inverting input terminal. The second input terminal of the error amplifier EA is a non-inverting input terminal. In this embodiment, the voltage regulating circuit 100 includes voltage dividing resistors RD1, RD2. The voltage dividing resistor RD1 is coupled between the second terminal of the output transistor MO and the second input terminal of the error amplifier EA. The voltage dividing resistor RD2 is coupled between the second input terminal of the error amplifier EA and the reference low voltage VL (for example, ground). The voltage dividing resistors RD1 and RD2 divide the voltage value of the output voltage VOUT to generate a feedback voltage value FB.

請參考圖2，圖2是依據本發明的第二實施例所繪示的電壓調節電路的示意圖。在本實施例中，電壓調節電路200包括誤差放大器EA、輸出電晶體MO以及電流限制電路210。在本實施例中，誤差放大器EA以及輸出電晶體MO的實施細節可以在圖1的實施例中獲得足夠的教示，故不在此重述。Please refer to FIG. 2 , which is a schematic diagram of a voltage regulating circuit according to a second embodiment of the present invention. In this embodiment, the voltage regulating circuit 200 includes an error amplifier EA, an output transistor MO and a current limiting circuit 210 . In this embodiment, the implementation details of the error amplifier EA and the output transistor MO can be sufficiently taught in the embodiment of FIG. 1 , so it will not be repeated here.

在本實施例中，電流限制電路210包括感測電路211、箝位電路212以及控制訊號箝制電路213。感測電路211包括感測電晶體MS。感測電晶體MS反應於控制訊號VG來提供感測電流ISEN，因此感測電流ISEN的電流值會與流經輸出電晶體MO的輸出電流值IOUT相關。In this embodiment, the current limiting circuit 210 includes a sensing circuit 211 , a clamping circuit 212 and a control signal clamping circuit 213 . The sensing circuit 211 includes a sensing transistor MS. The sensing transistor MS responds to the control signal VG to provide the sensing current ISEN, so the current value of the sensing current ISEN is related to the output current value IOUT flowing through the output transistor MO.

在本實施例中，感測電晶體MS的第一端接收輸入電壓VIN。感測電晶體MS的第二端耦接至控制訊號箝制電路213。感測電晶體MS的控制端耦接於誤差放大器EA的輸出端。在本實施例中，感測電晶體MS以及輸出電晶體MO可以是由相同形式的BJT或FET來實現。以本實施例為例，感測電晶體MS以PMOS場效電晶體來實現。In this embodiment, the first end of the sensing transistor MS receives the input voltage VIN. The second terminal of the sensing transistor MS is coupled to the control signal clamping circuit 213 . The control terminal of the sensing transistor MS is coupled to the output terminal of the error amplifier EA. In this embodiment, the sensing transistor MS and the output transistor MO can be realized by the same type of BJT or FET. Taking this embodiment as an example, the sensing transistor MS is realized by a PMOS field effect transistor.

在本實施例中，箝位電路212包括箝位電晶體MC以及電壓箝位元件EVC。箝位電晶體MC反應於控制訊號VG而被導通。電壓箝位元件EVC與箝位電晶體MC串聯耦接於輸入電壓VIN與控制訊號箝制電路213之間。電壓箝位元件EVC提供箝位電壓值。當輸入電壓VIN的電壓值大於箝位電壓值時，電壓箝位元件EVC被導通（conduct），因此，箝位電晶體MC會提供箝位電流IPS。在另一方面，當輸入電壓VIN的電壓值小於或等於箝位電壓值時，電壓箝位元件EVC會被斷開（cut-off），因此，箝位電晶體MC停止提供箝位電流IPS。In this embodiment, the clamping circuit 212 includes a clamping transistor MC and a voltage clamping element EVC. The clamp transistor MC is turned on in response to the control signal VG. The voltage clamping element EVC and the clamping transistor MC are coupled in series between the input voltage VIN and the control signal clamping circuit 213 . The voltage clamping element EVC provides the clamping voltage value. When the voltage value of the input voltage VIN is greater than the clamping voltage value, the voltage clamping element EVC is turned on (conducted), therefore, the clamping transistor MC provides a clamping current IPS. On the other hand, when the voltage value of the input voltage VIN is less than or equal to the clamping voltage value, the voltage clamping element EVC will be cut-off, so the clamping transistor MC stops providing the clamping current IPS.

在本實施例中，箝位電晶體MC所產生的箝位電流IPS的電流值與流經輸出電晶體MO的輸出電流值IOUT相關。箝位電晶體MC的第一端接收輸入電壓VIN。箝位電晶體MC的第二端耦接至電壓箝位元件EVC的第一端。箝位電晶體MC的控制端耦接於誤差放大器EA的輸出端。電壓箝位元件EVC的第二端耦接至控制訊號箝制電路213。在本實施例中，電壓箝位元件EVC可以是由一或多個二極體串聯來實現或者是由一或多個二極體連接式（diode-connected）的電晶體形式來實現。本實施例以電壓箝位元件EVC以單一個稽納二極體（Zener diode）來示例，本發明並不以此為限。稽納二極體的陰極耦接於電壓箝位元件EVC的第二端。稽納二極體的陽極耦接於控制訊號箝制電路213。在一些實施例中，電壓箝位元件EVC可以是由串聯耦接的多個稽納二極體來實現。In this embodiment, the current value of the clamping current IPS generated by the clamping transistor MC is related to the output current value IOUT flowing through the output transistor MO. The first end of the clamp transistor MC receives the input voltage VIN. The second end of the clamping transistor MC is coupled to the first end of the voltage clamping element EVC. The control terminal of the clamp transistor MC is coupled to the output terminal of the error amplifier EA. The second terminal of the voltage clamping element EVC is coupled to the control signal clamping circuit 213 . In this embodiment, the voltage clamping element EVC may be realized by one or more diodes connected in series or by one or more diode-connected transistors. In this embodiment, the voltage clamping element EVC is exemplified by a single Zener diode, and the present invention is not limited thereto. The cathode of the Zener diode is coupled to the second terminal of the voltage clamping element EVC. The anode of the Zener diode is coupled to the control signal clamping circuit 213 . In some embodiments, the voltage clamping element EVC may be realized by a plurality of Zener diodes coupled in series.

舉例來說，單一個稽納二極體的逆向偏壓可提供5.6伏特的箝位電壓值。串聯耦接的6個稽納二極體逆向偏壓則可以提供33.6伏特的箝位電壓值。在另一個實施例中，單一個二極體順向偏壓可提供0.7伏特的箝位電壓值。串聯耦接的2個二極體順向偏壓則可以提供1.4伏特的箝位電壓值。因此，箝位電路212的導通或斷開不需要比較器即可達成，如此一來，箝位電路212具有較快的反應速度。For example, reverse biasing a single Zener diode provides a clamping voltage of 5.6 volts. Six Zener diodes coupled in series can provide a clamping voltage of 33.6 volts in reverse bias. In another embodiment, a single diode is forward biased to provide a clamping voltage of 0.7 volts. The forward bias of the two diodes coupled in series can provide a clamping voltage of 1.4V. Therefore, the clamping circuit 212 can be turned on or off without a comparator, so that the clamping circuit 212 has a faster response speed.

在本實施例中，箝位電晶體MC以及輸出電晶體MO可以是由相同形式的BJT或FET來實現。以本實施例為例，箝位電晶體MC以PMOS場效電晶體來實現。In this embodiment, the clamping transistor MC and the output transistor MO can be realized by the same type of BJT or FET. Taking this embodiment as an example, the clamping transistor MC is realized by a PMOS field effect transistor.

在本實施例中，感測電晶體MS被設計以使感測電流ISEN的電流值明顯小於輸出電流值IOUT，一般而言，感測電流ISEN的電流值會是輸出電流值IOUT的0.001~0.01倍。箝位電晶體MC被設計以使單一箝位電流IPS的電流值明顯小於輸出電流值IOUT。舉例來說，感測電流ISEN的電流值以及單一箝位電流IPS的電流值被設計以等於輸出電流值IOUT的0.001~0.01倍（本發明並不以此為限）。由於輸出電流值IOUT為零時，感測電流ISEN和箝位電流IPS接近零電流，使得電流限制電路210本身具有相當低的靜態電流。如此一來，電壓調節電路200仍可以維持低靜態電流。In this embodiment, the sensing transistor MS is designed so that the current value of the sensing current ISEN is significantly smaller than the output current value IOUT. Generally speaking, the current value of the sensing current ISEN will be 0.001~0.01 of the output current value IOUT times. The clamping transistor MC is designed so that the current value of the single clamping current IPS is significantly smaller than the output current value IOUT. For example, the current value of the sensing current ISEN and the current value of the single clamping current IPS are designed to be equal to 0.001˜0.01 times of the output current value IOUT (the present invention is not limited thereto). Since the sensing current ISEN and the clamping current IPS are close to zero current when the output current value IOUT is zero, the current limiting circuit 210 itself has a rather low quiescent current. In this way, the voltage regulation circuit 200 can still maintain a low quiescent current.

請同時參考圖2以及圖3，圖3是依據圖2所繪示的輸出電流與輸入電壓的關係示意圖。在本實施例中，電壓箝位元件EVC提供箝位電壓值VC1。當輸入電壓VIN的電壓值小於或等於箝位電壓值VC1時，箝位電路212不會提供箝位電流IPS。也就是說，箝位電流等於零。因此，控制訊號箝制電路213基於感測電流ISEN來箝制控制訊號VG的電壓值。因此，當輸入電壓VIN的電壓值小於或等於箝位電壓值VC1時，輸出電流值IOUT約為電流值IOC1。Vin,max是電流限制電路210的最大輸入限制電壓。Please refer to FIG. 2 and FIG. 3 at the same time. FIG. 3 is a schematic diagram of the relationship between the output current and the input voltage shown in FIG. 2 . In this embodiment, the voltage clamping element EVC provides a clamping voltage value VC1. When the voltage value of the input voltage VIN is less than or equal to the clamp voltage value VC1 , the clamp circuit 212 will not provide the clamp current IPS. That is, the clamping current is equal to zero. Therefore, the control signal clamping circuit 213 clamps the voltage value of the control signal VG based on the sensing current ISEN. Therefore, when the voltage value of the input voltage VIN is less than or equal to the clamp voltage value VC1, the output current value IOUT is approximately the current value IOC1. Vin,max is the maximum input limit voltage of the current limit circuit 210 .

在另一方面，當輸入電壓VIN的電壓值大於箝位電壓值VC1時，箝位電路212會提供箝位電流IPS。也就是說，箝位電路212被導通。因此，控制訊號箝制電路213基於感測電流ISEN以及箝位電流IPS的電流值總和來箝制控制訊號VG的電壓值。因此，當輸入電壓VIN的電壓值大於箝位電壓值VC1時，輸出電流值IOUT被限制在電流值IOC2。應注意的是，電流值IOC2小於電流值IOC1。也就是說，控制訊號箝制電路213能夠隨著輸入電壓VIN的不同電壓值範圍來對輸出電流值IOUT進行分段的限制。On the other hand, when the voltage value of the input voltage VIN is greater than the clamping voltage VC1 , the clamping circuit 212 provides the clamping current IPS. That is, the clamp circuit 212 is turned on. Therefore, the control signal clamping circuit 213 clamps the voltage value of the control signal VG based on the sum of the sensing current ISEN and the clamping current IPS. Therefore, when the voltage value of the input voltage VIN is greater than the clamp voltage value VC1, the output current value IOUT is limited to the current value IOC2. It should be noted that the current value IOC2 is smaller than the current value IOC1. That is to say, the control signal clamping circuit 213 can limit the output current value IOUT in stages according to different voltage value ranges of the input voltage VIN.

在一個實施例中，箝位電壓值VC1被設計為36伏特，電流值IOC2被設計為160毫安培（mA）。在上述規格下，吾人實際應用於第一樣品以及第二樣品。關於第一樣品，當輸入電壓VIN的電壓值等於4.8伏特時，輸入電壓VIN的電壓值小於箝位電壓值VC1。第一樣品的輸出電流值IOUT約為電流值IOC1，約等於220 mA。當輸入電壓VIN的電壓值等於24伏特時，輸入電壓VIN的電壓值小於箝位電壓值VC1。第一樣品的輸出電流值IOUT約為電流值IOC1，約等於220 mA。當輸入電壓VIN的電壓值等於40伏特時，輸入電壓VIN的電壓值大於箝位電壓值VC1時，第一樣品的輸出電流值IOUT被限制在電流值IOC2，即160 mA。當輸入電壓VIN的電壓值等於48伏特時，輸入電壓VIN的電壓值大於箝位電壓值VC1時，第一樣品的輸出電流值IOUT被限制在電流值IOC2，即160 mA。In one embodiment, the clamping voltage VC1 is designed to be 36 volts, and the current value IOC2 is designed to be 160 milliamps (mA). Under the above specifications, we actually applied to the first sample as well as the second sample. Regarding the first sample, when the voltage value of the input voltage VIN is equal to 4.8 volts, the voltage value of the input voltage VIN is smaller than the clamp voltage value VC1. The output current value IOUT of the first sample is approximately the current value IOC1, which is approximately equal to 220 mA. When the voltage value of the input voltage VIN is equal to 24V, the voltage value of the input voltage VIN is less than the clamping voltage value VC1. The output current value IOUT of the first sample is approximately the current value IOC1, which is approximately equal to 220 mA. When the voltage value of the input voltage VIN is equal to 40V and the voltage value of the input voltage VIN is greater than the clamp voltage value VC1, the output current value IOUT of the first sample is limited to the current value IOC2, ie 160 mA. When the voltage value of the input voltage VIN is equal to 48V and the voltage value of the input voltage VIN is greater than the clamp voltage value VC1, the output current value IOUT of the first sample is limited to the current value IOC2, ie 160 mA.

關於第二樣品，當輸入電壓VIN的電壓值等於4.8伏特時，輸入電壓VIN的電壓值小於箝位電壓值VC1。第一樣品的輸出電流值IOUT約為電流值IOC1，約等於210 mA。當輸入電壓VIN的電壓值等於24伏特時，輸入電壓VIN的電壓值小於箝位電壓值VC1。第一樣品的輸出電流值IOUT約為電流值IOC1，約等於210 mA。當輸入電壓VIN的電壓值等於40伏特時，輸入電壓VIN的電壓值大於箝位電壓值VC1時，第一樣品的輸出電流值IOUT被限制在電流值IOC2，即160 mA。當輸入電壓VIN的電壓值等於48伏特時，輸入電壓VIN的電壓值大於箝位電壓值VC1時，第一樣品的輸出電流值IOUT被限制在電流值IOC2，即160 mA。Regarding the second sample, when the voltage value of the input voltage VIN is equal to 4.8 volts, the voltage value of the input voltage VIN is smaller than the clamp voltage value VC1. The output current value IOUT of the first sample is approximately the current value IOC1, which is approximately equal to 210 mA. When the voltage value of the input voltage VIN is equal to 24V, the voltage value of the input voltage VIN is less than the clamping voltage value VC1. The output current value IOUT of the first sample is approximately the current value IOC1, which is approximately equal to 210 mA. When the voltage value of the input voltage VIN is equal to 40V and the voltage value of the input voltage VIN is greater than the clamp voltage value VC1, the output current value IOUT of the first sample is limited to the current value IOC2, ie 160 mA. When the voltage value of the input voltage VIN is equal to 48V and the voltage value of the input voltage VIN is greater than the clamp voltage value VC1, the output current value IOUT of the first sample is limited to the current value IOC2, ie 160 mA.

請同時參考圖3以及圖4，圖4是依據本發明的第三實施例所繪示的電壓調節電路的示意圖。在本實施例中，電壓調節電路300包括誤差放大器EA、輸出電晶體MO以及電流限制電路310。誤差放大器EA以及輸出電晶體MO的實施細節可以在圖1的實施例中獲得足夠的教示，故不在此重述。電流限制電路310包括感測電路311、箝位電路312以及控制訊號箝制電路313。感測電路311以及箝位電路312的實施細節可以在圖1、圖2的實施例中獲得足夠的教示，故不在此重述。Please refer to FIG. 3 and FIG. 4 at the same time. FIG. 4 is a schematic diagram of a voltage regulating circuit according to a third embodiment of the present invention. In this embodiment, the voltage regulating circuit 300 includes an error amplifier EA, an output transistor MO and a current limiting circuit 310 . The implementation details of the error amplifier EA and the output transistor MO can be sufficiently taught in the embodiment of FIG. 1 , so it will not be repeated here. The current limiting circuit 310 includes a sensing circuit 311 , a clamping circuit 312 and a control signal clamping circuit 313 . The implementation details of the sensing circuit 311 and the clamping circuit 312 can be sufficiently taught in the embodiments of FIG. 1 and FIG. 2 , so they will not be repeated here.

在本實施例中，控制訊號箝制電路313依據輸入電壓VIN來產生操作電壓VCTRL，並反應於感測電流ISEN以及由箝位電路312所提供的箝位電流IPS的電流值總和來產生調節電壓VM。控制訊號箝制電路313反應於調節電壓VM來調節操作電壓VCTRL的電壓值，被調節的操作電壓VCTRL決定控制訊號VG的電壓值。In this embodiment, the control signal clamping circuit 313 generates the operating voltage VCTRL according to the input voltage VIN, and responds to the sum of the sensing current ISEN and the clamping current IPS provided by the clamping circuit 312 to generate the regulating voltage VM . The control signal clamping circuit 313 adjusts the voltage value of the operation voltage VCTRL in response to the adjustment voltage VM, and the adjusted operation voltage VCTRL determines the voltage value of the control signal VG.

控制訊號箝制電路313包括電阻器R1、R2以及電晶體M1、M2。電阻器R1的第一端接收輸入電壓VIN。電阻器R1的第二端用以提供操作電壓VCTRL。電晶體M1的第一端接收輸入電壓VIN。電晶體M1的第二端耦接於誤差放大器EA的輸出端。電晶體M1的控制端耦接於電阻器R1的第二端。電晶體M1反應於操作電壓VCTRL的電壓值來決定控制訊號VG的電壓值。電阻器R2的第一端耦接於感測電路311以及箝位電路312。電阻器R2的第二端耦接於參考低電位VL。電阻器R2依據感測電流ISEN以及由箝位電路312所提供箝位電流IPS的電流值總和來產生調節電壓VM。電晶體M2的第一端耦接於電阻器R1的第二端。電晶體M2的第二端耦接於參考低電位VL。電晶體M2的控制端接收調節電壓VM。電晶體M2反應於調節電壓VM的電壓值來調節操作電壓VCTRL的電壓值。在本實施例中，電晶體M1以PMOS場效電晶體來實現。電晶體M2以NMOS場效電晶體來實現。The control signal clamping circuit 313 includes resistors R1, R2 and transistors M1, M2. The first end of the resistor R1 receives the input voltage VIN. The second end of the resistor R1 is used to provide the operating voltage VCTRL. A first terminal of the transistor M1 receives an input voltage VIN. The second terminal of the transistor M1 is coupled to the output terminal of the error amplifier EA. The control terminal of the transistor M1 is coupled to the second terminal of the resistor R1. The transistor M1 responds to the voltage value of the operating voltage VCTRL to determine the voltage value of the control signal VG. A first end of the resistor R2 is coupled to the sensing circuit 311 and the clamping circuit 312 . The second end of the resistor R2 is coupled to the reference low potential VL. The resistor R2 generates the regulating voltage VM according to the sum of the sensing current ISEN and the clamping current IPS provided by the clamping circuit 312 . The first end of the transistor M2 is coupled to the second end of the resistor R1. The second end of the transistor M2 is coupled to the reference low potential VL. The control terminal of the transistor M2 receives the regulating voltage VM. The transistor M2 adjusts the voltage value of the operation voltage VCTRL in response to the voltage value of the adjustment voltage VM. In this embodiment, the transistor M1 is realized by a PMOS field effect transistor. Transistor M2 is realized by NMOS field effect transistor.

舉例來說，輸入電壓VIN的電壓值小於或等於箝位電壓值VC1，箝位電路312不提供箝位電流IPS。因此，電阻器R2依據感測電流ISEN以及電阻器R2本身的電阻值來產生調節電壓VM。當調節電壓VM等於電晶體M2的臨界電壓值(Vt)時，以讓電晶體M2導通，並反應於調節電壓VM來調節操作電壓VCTRL。因此，操作電壓VCTRL透過電晶體M1去限制控制訊號VG，如此一來，輸出電流值IOUT約為電流值IOC1。For example, the voltage value of the input voltage VIN is less than or equal to the clamping voltage value VC1, and the clamping circuit 312 does not provide the clamping current IPS. Therefore, the resistor R2 generates the regulation voltage VM according to the sensing current ISEN and the resistance value of the resistor R2 itself. When the adjustment voltage VM is equal to the threshold voltage (Vt) of the transistor M2, the transistor M2 is turned on, and the operation voltage VCTRL is adjusted in response to the adjustment voltage VM. Therefore, the operating voltage VCTRL limits the control signal VG through the transistor M1, so that the output current value IOUT is approximately the current value IOC1.

當調節電壓VM的電壓值接近電晶體M2的臨界電壓值時，電晶體M2的臨界電壓值如公式(1)所示：When the voltage value of the regulating voltage VM is close to the critical voltage value of the transistor M2, the critical voltage value of the transistor M2 is shown in formula (1):

Figure 02_image001
……公式(1)
Figure 02_image001
……Formula 1)

在公式(1)中，Vt是電晶體M2的臨界電壓值、i_ISEN是感測電流ISEN的電流值、M是輸出電流值IOUT與感測電流ISEN的電流值之間的倍率。r_R2是電阻器R2的電阻值。而根據整理公式(1)，整理成電流值IOC1為主的表示，如公式(2)所示：In the formula (1), Vt is the threshold voltage value of the transistor M2, i_ISEN is the current value of the sensing current ISEN, and M is the ratio between the output current value IOUT and the current value of the sensing current ISEN. r_R2 is the resistance value of resistor R2. According to the sorting formula (1), it is sorted into a representation based on the current value IOC1, as shown in formula (2):

Figure 02_image007
……公式(2)
Figure 02_image007
...Formula (2)

輸入電壓VIN的電壓值大於箝位電壓值VC1，箝位電路312提供箝位電流IPS。因此，電阻器R2依據感測電流ISEN與箝位電流IPS的電流值總和以及電阻器R2本身的電阻值來產生調節電壓VM。當調節電壓VM的電壓值等於電晶體M2的臨界電壓值時，電晶體M2反應於調節電壓VM來調節操作電壓VCTRL。因此，操作電壓VCTRL透過電晶體M1去限制控制訊號VG，如此一來，輸出電流值IOUT被限制在電流值IOC2。應注意的是，電流值IOC2小於電流值IOC1。The voltage value of the input voltage VIN is greater than the clamping voltage VC1, and the clamping circuit 312 provides the clamping current IPS. Therefore, the resistor R2 generates the regulating voltage VM according to the sum of the sensing current ISEN and the clamping current IPS and the resistance value of the resistor R2 itself. When the voltage value of the regulation voltage VM is equal to the threshold voltage value of the transistor M2, the transistor M2 responds to the regulation voltage VM to regulate the operation voltage VCTRL. Therefore, the operating voltage VCTRL limits the control signal VG through the transistor M1, so that the output current value IOUT is limited to the current value IOC2. It should be noted that the current value IOC2 is smaller than the current value IOC1.

舉例來說，輸入電壓VIN的電壓值大於箝位電壓值VC1。當調節電壓VM的電壓值接近電晶體M2的臨界電壓時，電晶體M2的臨界電壓值如公式(3)所示：For example, the voltage value of the input voltage VIN is greater than the clamping voltage value VC1. When the voltage value of the regulating voltage VM is close to the critical voltage of the transistor M2, the critical voltage value of the transistor M2 is shown in formula (3):

Figure 02_image011
……公式(3)
Figure 02_image011
...Formula (3)

在公式(3)中，i_IPS是箝位電流IPS的電流值。N是輸出電流值IOUT與箝位電流IPS的電流值之間的倍率。In the formula (3), i_IPS is the current value of the clamping current IPS. N is a multiplier between the output current value IOUT and the current value of the clamp current IPS.

而根據整理公式(3)，整理成電流值IOC2為主的表示，如公式(4)所示：According to the sorting formula (3), it is sorted into a representation based on the current value IOC2, as shown in formula (4):

Figure 02_image015
……公式(4)
Figure 02_image015
...Formula (4)

請參考圖5以及圖6，圖5是依據本發明的第四實施例所繪示的電壓調節電路的示意圖。圖6是依據圖5所繪示的輸出電流與輸入電壓的關係示意圖。在本實施例中，電壓調節電路400包括誤差放大器EA、輸出電晶體MO以及電流限制電路410。在本實施例中，誤差放大器EA以及輸出電晶體MO的實施細節可以在圖1的實施例中獲得足夠的教示，故不在此重述。電流限制電路410包括感測電路411、箝位電路412以及控制訊號箝制電路413。感測電路411的實施細節可以在圖1、圖2的實施例中獲得足夠的教示，故不在此重述。Please refer to FIG. 5 and FIG. 6 . FIG. 5 is a schematic diagram of a voltage regulating circuit according to a fourth embodiment of the present invention. FIG. 6 is a schematic diagram illustrating the relationship between the output current and the input voltage shown in FIG. 5 . In this embodiment, the voltage regulating circuit 400 includes an error amplifier EA, an output transistor MO and a current limiting circuit 410 . In this embodiment, the implementation details of the error amplifier EA and the output transistor MO can be sufficiently taught in the embodiment of FIG. 1 , so it will not be repeated here. The current limiting circuit 410 includes a sensing circuit 411 , a clamping circuit 412 and a control signal clamping circuit 413 . The implementation details of the sensing circuit 411 can be sufficiently taught in the embodiment of FIG. 1 and FIG. 2 , so it will not be repeated here.

在本實施例中，箝位電路412包括箝位電晶體MC1、MC2以及電壓箝位元件EVC1、EVC2。箝位電晶體MC1反應於控制訊號VG而被導通。電壓箝位元件EVC1與箝位電晶體MC1串聯耦接於輸入電壓VIN與控制訊號箝制電路413之間。電壓箝位元件EVC1提供箝位電壓值VC1。箝位電晶體MC2反應於控制訊號VG而被導通。電壓箝位元件EVC2與箝位電晶體MC2串聯耦接於輸入電壓VIN與控制訊號箝制電路413之間。電壓箝位元件EVC2提供箝位電壓值VC2。箝位電壓值VC2大於箝位電壓值VC1。In this embodiment, the clamping circuit 412 includes clamping transistors MC1 , MC2 and voltage clamping elements EVC1 , EVC2 . The clamp transistor MC1 is turned on in response to the control signal VG. The voltage clamping element EVC1 and the clamping transistor MC1 are coupled in series between the input voltage VIN and the control signal clamping circuit 413 . The voltage clamping element EVC1 provides a clamping voltage value VC1. The clamp transistor MC2 is turned on in response to the control signal VG. The voltage clamping element EVC2 and the clamping transistor MC2 are coupled in series between the input voltage VIN and the control signal clamping circuit 413 . The voltage clamping element EVC2 provides a clamping voltage value VC2. The clamping voltage value VC2 is greater than the clamping voltage value VC1.

在本實施例中，箝位電晶體MC1與輸出電晶體MO形成電流鏡。箝位電晶體MC1所產生的箝位電流IPS1的電流值與流經輸出電晶體MO的輸出電流值IOUT相關。箝位電晶體MC1的第一端接收輸入電壓VIN。箝位電晶體MC1的第二端耦接至電壓箝位元件EVC1的第一端。箝位電晶體MC1的控制端耦接於誤差放大器EA的輸出端。電壓箝位元件EVC1的第二端耦接至控制訊號箝制電路413。箝位電晶體MC2所產生的箝位電流IPS2與流經輸出電晶體MO的輸出電流值IOUT相關。箝位電晶體MC2的第一端接收輸入電壓VIN。箝位電晶體MC2的第二端耦接至電壓箝位元件EVC2的第一端。箝位電晶體MC2的控制端耦接於誤差放大器EA的輸出端。電壓箝位元件EVC2的第二端耦接至控制訊號箝制電路413。In this embodiment, the clamp transistor MC1 and the output transistor MO form a current mirror. The current value of the clamping current IPS1 generated by the clamping transistor MC1 is related to the output current value IOUT flowing through the output transistor MO. The first end of the clamping transistor MC1 receives the input voltage VIN. The second terminal of the clamping transistor MC1 is coupled to the first terminal of the voltage clamping element EVC1. The control terminal of the clamp transistor MC1 is coupled to the output terminal of the error amplifier EA. The second terminal of the voltage clamping element EVC1 is coupled to the control signal clamping circuit 413 . The clamping current IPS2 generated by the clamping transistor MC2 is related to the output current IOUT flowing through the output transistor MO. The first end of the clamping transistor MC2 receives the input voltage VIN. The second terminal of the clamping transistor MC2 is coupled to the first terminal of the voltage clamping element EVC2. The control terminal of the clamp transistor MC2 is coupled to the output terminal of the error amplifier EA. The second terminal of the voltage clamping element EVC2 is coupled to the control signal clamping circuit 413 .

當輸入電壓VIN的電壓值小於或等於箝位電壓值VC1時，電壓箝位元件EVC1會被斷開。此外，電壓箝位元件EVC2會被斷開。因此，箝位電晶體MC1不提供箝位電流IPS1，箝位電晶體MC2不提供箝位電流IPS2。也就是說，箝位電路412提供箝位電流的電流值為零。因此，控制訊號箝制電路413反應於感測電流ISEN來箝制控制訊號VG，從而使輸出電流值IOUT約為電流值IOC1。When the voltage value of the input voltage VIN is less than or equal to the clamping voltage value VC1, the voltage clamping element EVC1 will be disconnected. In addition, the voltage clamping element EVC2 will be disconnected. Therefore, the clamping transistor MC1 does not provide the clamping current IPS1, and the clamping transistor MC2 does not provide the clamping current IPS2. That is to say, the current value of the clamping circuit 412 providing the clamping current is zero. Therefore, the control signal clamping circuit 413 clamps the control signal VG in response to the sensing current ISEN, so that the output current value IOUT is approximately the current value IOC1.

當輸入電壓VIN的電壓值大於箝位電壓值VC1並且小於或等於箝位電壓值VC2時，電壓箝位元件EVC1會被導通。電壓箝位元件EVC2會被斷開。因此，箝位電晶體MC1提供箝位電流IPS1，箝位電晶體MC2則不提供箝位電流IPS2。因此，控制訊號箝制電路413反應於感測電流ISEN以及箝位電流IPS1來箝制控制訊號VG。輸出電流值IOUT被限制在電流值IOC2。電流值IOC2小於電流值IOC1。When the voltage value of the input voltage VIN is greater than the clamping voltage VC1 and less than or equal to the clamping voltage VC2 , the voltage clamping element EVC1 will be turned on. The voltage clamping element EVC2 will be disconnected. Therefore, the clamping transistor MC1 provides the clamping current IPS1, and the clamping transistor MC2 does not provide the clamping current IPS2. Therefore, the control signal clamping circuit 413 clamps the control signal VG in response to the sensing current ISEN and the clamping current IPS1 . The output current value IOUT is limited to the current value IOC2. The current value IOC2 is smaller than the current value IOC1.

當輸入電壓VIN的電壓值大於箝位電壓值VC2時，電壓箝位元件EVC1會被導通。此外，電壓箝位元件EVC2會被導通。因此，箝位電晶體MC1提供箝位電流IPS1，箝位電晶體MC2提供箝位電流IPS2。因此，控制訊號箝制電路413反應於感測電流ISEN以及兩個箝位電流IPS1、IPS2來箝制控制訊號VG。輸出電流值IOUT被限制在電流值IOC3。電流值IOC3小於電流值IOC2。Vin,max是電流限制電路310、410的最大輸入限制電壓。本實施例中，箝位電路412會依據輸入電壓VIN的電壓值來決定電壓箝位元件EVC1、EVC2被導通的數量，並依據電壓箝位元件EVC1、EVC2被導通的數量來調整箝位電流的電流值。考量電流限制電路210、310與410的晶片面積，電壓箝位元件較佳的數量為1個，但使用者可依整體電壓調節電路200、300與400的輸入輸出規格自由調整電壓箝位元件的數量。When the voltage value of the input voltage VIN is greater than the clamping voltage value VC2, the voltage clamping element EVC1 will be turned on. In addition, the voltage clamping element EVC2 is turned on. Therefore, the clamping transistor MC1 provides the clamping current IPS1, and the clamping transistor MC2 provides the clamping current IPS2. Therefore, the control signal clamping circuit 413 clamps the control signal VG in response to the sensing current ISEN and the two clamping currents IPS1 and IPS2 . The output current value IOUT is limited to the current value IOC3. The current value IOC3 is smaller than the current value IOC2. Vin,max is the maximum input limit voltage of the current limit circuit 310 , 410 . In this embodiment, the clamping circuit 412 determines the number of conduction of the voltage clamping elements EVC1 and EVC2 according to the voltage value of the input voltage VIN, and adjusts the clamping current according to the number of conduction of the voltage clamping elements EVC1 and EVC2 current value. Considering the chip area of the current limiting circuits 210, 310, and 410, the preferred number of voltage clamping elements is one, but users can freely adjust the number of voltage clamping elements according to the input and output specifications of the overall voltage regulating circuits 200, 300, and 400. quantity.

請參考圖7，圖7是依據本發明的一實施例所繪示的電流限制電路與裝置的示意圖。裝置500與電流限制電路600電性連接。在本實施例中，裝置500例如是具有輸出電晶體MO的裝置。裝置500例如是線性充電器（本發明並不以此為限）。在本實施例中，電流限制電路600對輸出電晶體MO的輸出電流值IOUT進行限制。輸出電晶體MO受控於電流限制電路600所提供的控制訊號VG。Please refer to FIG. 7 , which is a schematic diagram of a current limiting circuit and device according to an embodiment of the present invention. The device 500 is electrically connected to the current limiting circuit 600 . In this embodiment, the device 500 is, for example, a device with an output transistor MO. The device 500 is, for example, a linear charger (the present invention is not limited thereto). In this embodiment, the current limiting circuit 600 limits the output current value IOUT of the output transistor MO. The output transistor MO is controlled by the control signal VG provided by the current limiting circuit 600 .

在本實施例中，電流限制電路600提供至少一箝位電壓值，依據輸入電壓VIN的電壓值與所述至少一箝位電壓值的比較結果來提供箝位電流。電流限制電路600反應於感測電流和箝位電流的電流值來箝制控制訊號VG的電壓值。電流限制電路600能夠使輸出電流限制值與輸入電壓VIN呈現負相關。在本實施例中，電流限制電路600的內部電路配置與操作細節可以由圖1至圖6的多個實施例中獲得足夠的教示，故不在此重述。In this embodiment, the current limiting circuit 600 provides at least one clamping voltage value, and provides the clamping current according to a comparison result between the voltage value of the input voltage VIN and the at least one clamping voltage value. The current limiting circuit 600 clamps the voltage value of the control signal VG in response to the current values of the sensing current and the clamping current. The current limit circuit 600 can make the output current limit value negatively correlated with the input voltage VIN. In this embodiment, the internal circuit configuration and operation details of the current limiting circuit 600 can be sufficiently taught from the multiple embodiments shown in FIG. 1 to FIG. 6 , so it will not be repeated here.

綜上所述，本發明的電流限制電路依據輸入電壓的電壓值與所述至少一箝位電壓值的比較結果來提供箝位電流，並反應於感測電流和箝位電流的電流值來箝制控制訊號的電壓值。本發明的電流限制電路能夠使輸出電流限制值與輸入電壓呈現負相關。並且，能夠讓電壓調節電路工作在低靜態電流下。To sum up, the current limiting circuit of the present invention provides the clamping current according to the comparison result of the voltage value of the input voltage and the at least one clamping voltage value, and clamps in response to the current value of the sensing current and the clamping current. The voltage value of the control signal. The current limiting circuit of the present invention can make the output current limiting value and the input voltage present a negative correlation. Moreover, the voltage regulating circuit can be operated under low quiescent current.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the scope of the appended patent application.

100、200、300、400、600:電壓調節電路 110、210、310、410:電流限制電路 111、211、311、411:感測電路 112、212、312、412:箝位電路 113、213、313、413:控制訊號箝制電路 500:裝置 EA:誤差放大器 EVC、EVC1、EVC2:電壓箝位元件 FB:回饋電壓值 IOC1、IOC2、IOC3:電流值 IOUT:輸出電流值 IPS、IPS1、IPS2:箝位電流 ISEN:感測電流 M1、M2:電晶體 MO:輸出電晶體 MC、MC1、MC2:箝位電晶體 MS:感測電晶體 R1、R2:電阻器 RD1、RD2:分壓電阻器 VC1、VC2:箝位電壓值 VCTRL:操作電壓 VG:控制訊號 VIN:輸入電壓 VL:參考低電壓 VM:調節電壓 VOUT:輸出電壓 VREF:參考電壓值 100, 200, 300, 400, 600: voltage regulation circuit 110, 210, 310, 410: current limiting circuit 111, 211, 311, 411: sensing circuit 112, 212, 312, 412: clamping circuit 113, 213, 313, 413: control signal clamping circuit 500: device EA: error amplifier EVC, EVC1, EVC2: Voltage Clamping Elements FB: feedback voltage value IOC1, IOC2, IOC3: current value IOUT: output current value IPS, IPS1, IPS2: clamping current ISEN: sense current M1, M2: Transistor MO: output transistor MC, MC1, MC2: clamping transistors MS: Sensing Transistor R1, R2: Resistors RD1, RD2: Divider resistors VC1, VC2: Clamping voltage value VCTRL: operating voltage VG: control signal VIN: input voltage VL: reference low voltage VM: regulating voltage VOUT: output voltage VREF: Reference voltage value

圖1是依據本發明的第一實施例所繪示的電壓調節電路的示意圖。 圖2是依據本發明的第二實施例所繪示的電壓調節電路的示意圖。 圖3是依據圖2所繪示的輸出電流與輸入電壓的關係示意圖。 圖4是依據本發明的第三實施例所繪示的電壓調節電路的示意圖。 圖5是依據本發明的第四實施例所繪示的電壓調節電路的示意圖。 圖6是依據圖5所繪示的輸出電流與輸入電壓的關係示意圖。 圖7是依據本發明的一實施例所繪示的電流限制電路與裝置的示意圖。 FIG. 1 is a schematic diagram of a voltage regulating circuit according to a first embodiment of the present invention. FIG. 2 is a schematic diagram of a voltage regulating circuit according to a second embodiment of the present invention. FIG. 3 is a schematic diagram illustrating the relationship between the output current and the input voltage shown in FIG. 2 . FIG. 4 is a schematic diagram of a voltage regulating circuit according to a third embodiment of the present invention. FIG. 5 is a schematic diagram of a voltage regulating circuit according to a fourth embodiment of the present invention. FIG. 6 is a schematic diagram illustrating the relationship between the output current and the input voltage shown in FIG. 5 . FIG. 7 is a schematic diagram of a current limiting circuit and device according to an embodiment of the present invention.

100:電壓調節電路 100: voltage regulation circuit

110:電流限制電路 110: current limiting circuit

111:感測電路 111: sensing circuit

112:箝位電路 112: clamping circuit

113:控制訊號箝制電路 113: Control signal clamping circuit

EA:誤差放大器 EA: error amplifier

FB:回饋電壓值 FB: feedback voltage value

IOUT:輸出電流值 IOUT: output current value

IPS:箝位電流 IPS: clamping current

ISEN:感測電流 ISEN: sense current

MO:輸出電晶體 MO: output transistor

RD1、RD2:分壓電阻器 RD1, RD2: Divider resistors

VG:控制訊號 VG: control signal

VIN:輸入電壓 VIN: input voltage

VL:參考低電壓 VL: reference low voltage

VOUT:輸出電壓 VOUT: output voltage

VREF:參考電壓值 VREF: Reference voltage value

Claims (8)

一種電壓調節電路，包括：誤差放大器，經配置成反應於輸出電壓的變動以提供控制訊號；輸出電晶體，耦接於所述誤差放大器的輸出端，經配置成接收輸入電壓，並反應於所述控制訊號以及所述輸入電壓以調節所述輸出電壓；以及電流限制電路，包括：感測電路，經配置成依據輸出電流提供感測電流；箝位電路，經配置成提供至少一箝位電壓值，並依據所述輸入電壓的電壓值與所述至少一箝位電壓值的比較結果提供箝位電流；以及控制訊號箝制電路，耦接於所述誤差放大器的輸出端、所述感測電路以及所述箝位電路，經配置成反應於所述感測電流和所述箝位電流來箝制所述控制訊號的電壓值，藉此，調節流經所述輸出電晶體的所述輸出電流；其中所述箝位電路包括：第一箝位電晶體，經配置成反應於所述控制訊號而被導通；以及第一電壓箝位元件，與所述第一箝位電晶體串聯耦接於所述輸入電壓與所述控制訊號箝制電路之間，經配置成提供所述至少一箝位電壓值當中的第一箝位電壓值； 其中，當所述輸入電壓的電壓值大於所述第一箝位電壓值時，所述第一箝位電晶體提供第一箝位電流。 A voltage regulation circuit, comprising: an error amplifier configured to provide a control signal in response to changes in an output voltage; an output transistor coupled to an output terminal of the error amplifier configured to receive an input voltage and respond to the the control signal and the input voltage to adjust the output voltage; and a current limiting circuit, including: a sensing circuit configured to provide a sensing current according to the output current; a clamping circuit configured to provide at least one clamping voltage value, and provide a clamping current according to a comparison result between the voltage value of the input voltage and the at least one clamping voltage value; and a control signal clamping circuit, coupled to the output terminal of the error amplifier, the sensing circuit and the clamping circuit configured to clamp the voltage value of the control signal in response to the sensing current and the clamping current, thereby regulating the output current flowing through the output transistor; Wherein the clamping circuit includes: a first clamping transistor configured to be turned on in response to the control signal; and a first voltage clamping element coupled in series with the first clamping transistor to the between the input voltage and the control signal clamping circuit configured to provide a first clamping voltage value among the at least one clamping voltage value; Wherein, when the voltage value of the input voltage is greater than the first clamping voltage value, the first clamping transistor provides a first clamping current. 如請求項1所述的電壓調節電路，其中所述感測電路包括：感測電晶體，經配置成反應於所述控制訊號來提供所述感測電流，其中所述感測電流的電流值與流經所述輸出電晶體的所述輸出電流的電流值相關。 The voltage regulating circuit according to claim 1, wherein the sensing circuit includes: a sensing transistor configured to provide the sensing current in response to the control signal, wherein the sensing current has a current value It is related to the current value of the output current flowing through the output transistor. 如請求項1所述的電壓調節電路，其中：所述第一箝位電流與流經所述輸出電晶體的所述輸出電流相關。 The voltage regulating circuit according to claim 1, wherein: the first clamping current is related to the output current flowing through the output transistor. 如請求項1所述的電壓調節電路，其中所述箝位電路還包括：第二箝位電晶體，經配置成反應於所述控制訊號而被導通；以及第二電壓箝位元件，與所述第二箝位電晶體串聯耦接於所述輸入電壓與所述控制訊號箝制電路之間，經配置成提供所述至少一箝位電壓值當中的第二箝位電壓值；其中，所述第二箝位電壓值大於所述第一箝位電壓值；其中，當所述輸入電壓的電壓值大於所述第一箝位電壓值並小於或等於所述第二箝位電壓值時，所述第一箝位電晶體提供所述第一箝位電流，所述第二箝位電晶體停止提供第二箝位電流；其中，當所述輸入電壓的電壓值大於所述第二箝位電壓值 時，所述第一箝位電晶體提供所述第一箝位電流，所述第二箝位電晶體提供所述第二箝位電流。 The voltage regulating circuit according to claim 1, wherein the clamping circuit further comprises: a second clamping transistor configured to be turned on in response to the control signal; and a second voltage clamping element, and the The second clamping transistor is coupled in series between the input voltage and the control signal clamping circuit and is configured to provide a second clamping voltage value among the at least one clamping voltage value; wherein the The second clamping voltage value is greater than the first clamping voltage value; wherein, when the voltage value of the input voltage is greater than the first clamping voltage value and less than or equal to the second clamping voltage value, the The first clamping transistor provides the first clamping current, and the second clamping transistor stops providing the second clamping current; wherein, when the voltage value of the input voltage is greater than the second clamping voltage value When , the first clamping transistor provides the first clamping current, and the second clamping transistor provides the second clamping current. 如請求項4所述的電壓調節電路，其中：所述第二箝位電流與流經所述輸出電晶體的所述輸出電流相關。 The voltage regulating circuit according to claim 4, wherein: the second clamping current is related to the output current flowing through the output transistor. 如請求項1所述的電壓調節電路，其中所述控制訊號箝制電路經配置成：依據所述輸入電壓來產生操作電壓，反應於所述感測電流以及由所述箝位電路所提供的所述箝位電流的電流值總和來產生調節電壓，反應於所述調節電壓來調節所述操作電壓的電壓值，並且反應於被調節的所述操作電壓來決定所述控制訊號的電壓值。 The voltage regulating circuit as claimed in claim 1, wherein the control signal clamping circuit is configured to: generate an operating voltage according to the input voltage, responsive to the sensing current and the provided by the clamping circuit The sum of current values of the clamping currents is used to generate an adjustment voltage, the voltage value of the operating voltage is adjusted in response to the adjustment voltage, and the voltage value of the control signal is determined in response to the adjusted operation voltage. 如請求項6所述的電壓調節電路，其中所述控制訊號箝制電路包括：第一電阻器，所述第一電阻器的第一端接收所述輸入電壓，所述第一電阻器的第二端用以提供所述操作電壓；第一電晶體，所述第一電晶體的第一端接收所述輸入電壓，所述第一電晶體的第二端耦接於所述誤差放大器的輸出端，所述第一電晶體的控制端耦接於所述第一電阻器的第二端，經配置成反應於所述操作電壓的電壓值來決定所述控制訊號的電壓值；第二電阻器，所述第二電阻器的第一端耦接於所述感測電路 以及所述箝位電路，所述第二電阻器的第二端耦接於參考低電位，經配置成依據所述感測電流以及由所述箝位電路所提供所述箝位電流的電流值以產生所述調節電壓；以及第二電晶體，所述第二電晶體的第一端耦接於所述第一電阻器的第二端，所述第二電晶體的第二端耦接於所述參考低電位，所述第二電晶體的控制端接收所述調節電壓，經配置成反應於所述調節電壓的電壓值來調節所述操作電壓的電壓值。 The voltage regulating circuit according to claim 6, wherein the control signal clamping circuit includes: a first resistor, the first end of the first resistor receives the input voltage, and the second end of the first resistor The terminal is used to provide the operating voltage; the first transistor, the first terminal of the first transistor receives the input voltage, and the second terminal of the first transistor is coupled to the output terminal of the error amplifier , the control terminal of the first transistor is coupled to the second terminal of the first resistor, configured to respond to the voltage value of the operating voltage to determine the voltage value of the control signal; the second resistor , the first end of the second resistor is coupled to the sensing circuit and the clamping circuit, the second end of the second resistor is coupled to a reference low potential, configured to depend on the sensing current and the current value of the clamping current provided by the clamping circuit to generate the adjustment voltage; and a second transistor, the first terminal of the second transistor is coupled to the second terminal of the first resistor, and the second terminal of the second transistor is coupled to The reference low potential, the control terminal of the second transistor receives the adjustment voltage, and is configured to adjust the voltage value of the operating voltage in response to the voltage value of the adjustment voltage. 一種電流限制電路，用於對輸出電晶體的輸出電流值進行限制，其中所述輸出電晶體受控於控制訊號，包括：感測電路，經配置成依據輸出電流提供感測電流；箝位電路，經配置成提供至少一箝位電壓值，並依據輸入電壓的電壓值與所述至少一箝位電壓值的比較結果來提供箝位電流；以及控制訊號箝制電路，耦接於所述輸出電晶體的控制端、所述感測電路以及所述箝位電路，經配置成反應於所述感測電流和所述箝位電流的電流值來箝制所述控制訊號的電壓值，使得所述電晶體的輸出電流限制值與所述輸入電壓的電壓值呈現負相關；其中所述箝位電路包括：箝位電晶體，經配置成反應於所述控制訊號而被導通；以及電壓箝位元件，與所述箝位電晶體串聯耦接於所述輸入電壓與所述控制訊號箝制電路之間，經配置成提供所述箝位電壓 值；其中，當所述輸入電壓的電壓值大於所述箝位電壓值時，所述箝位電晶體提供所述箝位電流。 A current limiting circuit for limiting the output current value of an output transistor, wherein the output transistor is controlled by a control signal, comprising: a sensing circuit configured to provide a sensing current according to the output current; a clamping circuit , configured to provide at least one clamping voltage value, and provide a clamping current according to a comparison result between the voltage value of the input voltage and the at least one clamping voltage value; and a control signal clamping circuit coupled to the output voltage The control terminal of the crystal, the sensing circuit, and the clamping circuit are configured to clamp the voltage value of the control signal in response to current values of the sensing current and the clamping current, so that the voltage The output current limit value of the crystal is negatively correlated with the voltage value of the input voltage; wherein the clamping circuit includes: a clamping transistor configured to be turned on in response to the control signal; and a voltage clamping element, coupled in series with the clamping transistor between the input voltage and the control signal clamping circuit, configured to provide the clamping voltage value; wherein, when the voltage value of the input voltage is greater than the clamp voltage value, the clamp transistor provides the clamp current.
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