TWI790426B - Point light source type light emitting diode and manufacturing method thereof - Google Patents

Abstract

The present invention provides a point light source type light emitting diode which can simplify the manufacturing steps and has excellent temperature dependence characteristics and a manufacturing method thereof. The point light source type light emitting diode according to the present invention includes: a supporting substrate; a metal layer including a light reflection surface; a current confinement layer; a III-V group compound semiconductor laminate including an n-type semiconductor layer, an active layer, and a p-type semiconductor in this order. layer; and an upper surface electrode, and the upper surface electrode includes an opening for emitting light emitted by the active layer, and the current narrowing layer includes a dielectric layer including a through hole and an intermediate electrode, and includes a middle electrode in a vertical projection relative to the upper surface electrode. In the projected plane of the current confining layer of the electrode, the middle electrode is enclosed in the opening, the upper surface electrode is enclosed in the dielectric layer, and the film thickness of the p-type semiconductor layer is 0.5 μm or more and 3.0 μm or less.

Description

Point light source type light emitting diode and manufacturing method thereof

The invention relates to a point light source type light emitting diode and a manufacturing method thereof.

In recent years, light emitting diodes (Light Emitting Diodes, LEDs) have been used in various applications such as sensors, gas analysis, vehicle cameras, lighting, signals, sterilization, and resin curing according to their light emission wavelengths. Among these, when light emitting diodes are used for sensor light source applications, etc., point light source type light emitting diodes that emit light showing a uniform luminous intensity distribution can be used. In a normal light emitting diode, light is emitted in all directions from the light emitting region, but in a point light source type light emitting diode, only light directed in a specific direction is taken out. Such a point light source type light emitting diode is disclosed in Patent Document 1, for example.

The point light source type light-emitting diode disclosed in Patent Document 1 sequentially includes a metal layer, a first conductivity type layer, an active layer, a second conductivity type layer including a current narrowing structure, and a layer for the active layer on a support substrate. The light generated in the layer exits the opening on the top surface of the electrode. In the point light source type light-emitting diode of Patent Document 1, in order to limit the conduction region in the active layer to a part of its plane, a current confinement structure is formed by providing a current blocking region in the second conductivity type layer.

[Prior art literature] [Patent Document]

[Patent Document 1] Japanese Patent Laid-Open No. 2015-170717

In the above Patent Document 1, a current confinement structure is provided by forming a current blocking region including a non-conductive region having a high resistance value in the second conductivity type layer above the active layer by ion implantation. Therefore, in the technique of Patent Document 1, not only the number of manufacturing steps increases, but also complex patterns need to be combined and formed, which may degrade the yield. In addition, when it is put into practical use, it is required that the luminous output does not change easily with the temperature change of the use environment, and that the temperature dependence characteristics be improved.

Therefore, an object of the present invention is to provide a point light source type light emitting diode and a manufacturing method thereof which can simplify the manufacturing steps and can improve the temperature dependence of the luminous output.

The inventors of the present invention have repeatedly conducted diligent research to solve the above-mentioned problems. Furthermore, while optimizing the arrangement relationship between the current narrowing layer and the upper-surface electrode, an attempt was made to control current diffusion by paying attention to the film thickness of the p-type semiconductor layer. As a result, it was experimentally confirmed that the main light-emitting region in the active layer can be controlled without complicated manufacturing steps, and a point light source type light-emitting diode can be produced with simple manufacturing steps. The present invention was completed based on the above knowledge, and the gist thereof is as follows.

(1) A point light source type light emitting diode, characterized in that comprising: a supporting substrate; The metal layer is located on the support substrate and includes a light reflection surface; the current narrowing layer is located on the metal layer; the III-V group compound semiconductor laminate is located on the current narrowing layer and includes a p-type semiconductor layer, an active layer and n-type semiconductor layer; and an upper surface electrode located on the III-V compound semiconductor laminate, and the upper surface electrode includes an opening for emitting light emitted from the active layer, and the current narrowing layer includes The dielectric layer and the intermediate electrode of the through-hole, the intermediate electrode is arranged in the through-hole and electrically connects the p-type semiconductor layer and the metal layer, and the vertical projection relative to the upper surface electrode includes In the projected plane obtained by the current narrowing layer of the intermediate electrode, the opening part contains the intermediate electrode, and the dielectric layer contains the upper surface electrode, and the film thickness of the p-type semiconductor layer is 0.5 μm or more and 3.3 μm or less.

(2) The point light source type light emitting diode according to (1) above, wherein the opening and the intermediate electrode are arranged at respective centers of gravity of the opening and the intermediate electrode on the projection plane. consistent location.

(3) The point light source type light-emitting diode as described in (1) or (2), wherein the shortest distance between the outer periphery of the active layer and the outermost periphery of the main light-emitting region in the active layer is More than 30μm.

(4) The point light source type light emitting diode according to (3) above, wherein the shortest separation distance is 60 μm or more.

(5) The point light source type light emitting diode described in any one of (1) to (4), wherein the light reflecting surface covers the side surface of the active layer through the dielectric layer at least partly.

(6) A method for manufacturing a point light source type light-emitting diode, characterized in that it includes: a first step of forming a semiconductor laminate sequentially comprising an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on a growth substrate; The second step is to form a current narrowing layer on the p-type semiconductor layer; the third step is to form a metal reflective layer on the current narrowing layer; the fourth step is to make the support substrate with the metal bonding layer on the surface bonded via the metal layer to be bonded to the metal reflective layer, and simultaneously form a metal layer; the fifth step, removing the growth substrate; and the sixth step, forming a removed surface of the growth substrate in the n-type semiconductor layer a surface electrode having an opening through which light emitted from the active layer exits, and in the second step, the current narrowing layer including a dielectric layer and an intermediate electrode is formed, the The dielectric layer includes a through hole, the intermediate electrode is disposed in the through hole and electrically connects the p-type semiconductor layer and the metal layer, and includes the intermediate electrode in a vertical projection relative to the upper surface electrode. In the projected plane of the current narrowing layer of the electrode, the opening part contains the intermediate electrode, and the dielectric layer contains the upper surface electrode, and the film thickness of the p-type semiconductor layer is set to It is 0.5 μm or more and 3.3 μm or less.

According to the present invention, it is possible to provide a point light source type light emitting diode capable of simplifying the manufacturing steps and improving the temperature dependence of the luminous output and a method of manufacturing the same.

10: Support substrate

20: metal layer

21: light reflective surface

25: Metal bonding layer

27: metal reflective layer

30: current narrow layer

31: Dielectric layer

32: Through hole

35: middle electrode

50: Semiconductor laminate

51: p-type semiconductor layer

53: active layer

53A: Main light-emitting area

55: n-type semiconductor layer

70: Upper surface electrode

71: Opening

100, 200: point light source type light emitting diode

E1: pad electrode

E2: back electrode

d: the shortest separation distance

D: electrode diameter

L ₁ : Width of the opening

L ₂ : Outer diameter, width, diameter, and diameter of the intermediate electrode

L ₃ : inner diameter of the middle electrode

FIG. 1 is a schematic sectional view and a plan view showing one aspect of a point light source type light emitting diode according to the present invention.

Fig. 2 is a schematic cross-sectional view showing another aspect of the point light source type light emitting diode according to the present invention.

3 is a plan view for explaining the positional and dimensional relationships between the openings and the intermediate electrodes of the point light source type light emitting diodes of Examples 1 to 4. FIG.

4 is a plan view for explaining the positional and dimensional relationships between the opening and the intermediate electrode of the point light source type light emitting diode of Comparative Example 1. FIG.

FIG. 5A is a graph showing the emission intensity distribution of Example 1. FIG.

FIG. 5B is a graph showing the emission intensity distribution of Example 2. FIG.

FIG. 5C is a graph showing the emission intensity distribution of Example 3. FIG.

FIG. 5D is a graph showing the emission intensity distribution of Example 4. FIG.

Before describing the embodiments according to the present invention, each definition in this specification will be described.

(each definition)

<III-V compound semiconductor>

First, in the present specification, when it is simply referred to as "III-V compound semiconductor", its composition is represented by the general formula: (In _a Ga _b Al _c )(P _x As _y Sb _z ). Here, with regard to the composition ratio of each element, the following relationship holds true.

Regarding group III elements, c=1-a-b, 0≦a≦1, 0≦b≦1, 0≦c≦1

Regarding group V elements, z=1-x-y, 0≦x≦1, 0≦y≦1, 0≦z≦1

<p-type, n-type and i-type and dopant concentration>

In this specification, a layer functioning as p-type electrical properties is referred to as a p-type semiconductor layer (sometimes simply referred to as a “p-type layer”), and a layer functioning as n-type electrical properties is referred to as an n-type semiconductor layer ( Sometimes referred to simply as "n-type layer"). On the other hand, when specific impurities such as Si, Zn, S, Sn, and Mg are not intended to be added and do not function as p-type or n-type electricity, it is called "i-type" or "undoped". Unavoidable impurities during the manufacturing process may be mixed in the undoped group III-V compound semiconductor layer. Specifically, in this specification, a case where the dopant concentration is low (for example, less than 7.6×10 ¹⁵ atoms/cm ³ ) is treated as “undoped”. The values of impurity concentrations such as Si, Zn, S, Sn, and Mg are taken as those obtained through secondary ion mass spectrometry (Secondary Ion Mass Spectroscopy, SIMS) analysis. In addition, since the value of the dopant concentration fluctuates greatly near the boundary of each semiconductor layer, the value of the dopant concentration at the center in the film thickness direction of each layer is taken as the value of the dopant concentration.

<Film thickness and composition of each layer>

In addition, the overall film thickness of each formed layer can be measured using an optical interference type film thickness measuring device. Furthermore, the film thickness of each layer can be calculated by observing the cross-section of the growth layer with an optical interference type film thickness measuring device and a transmission electron microscope. In addition, at each layer of When the film thickness is as small as about several nm similar to the superlattice structure, the film thickness can be measured using a Transmission Electron Microscope-Energy Dispersive Spectrometer (TEM-EDS). In addition, in the cross-sectional view of each layer, when a predetermined layer has an inclined surface, the maximum height from the flat surface of the layer immediately below the layer is used as the film thickness of the layer.

Hereinafter, the point light source type light emitting diode and its manufacturing method according to the present invention will be described sequentially with reference to the drawings. In addition, in principle, the same reference number is attached|subjected to the same component, and overlapping description is abbreviate|omitted. In each figure, for convenience of description, the aspect ratios of the substrate and each layer are shown exaggeratedly based on actual ratios.

(Point light source type light emitting diode)

FIG. 1 shows a schematic sectional view and a top view of a point light source type light emitting diode 100 according to an aspect of the present invention. The point light source type light emitting diode 100 at least includes: a support substrate 10; a metal layer 20 located on the support substrate 10 and including a light reflecting surface 21; a current narrowing layer 30 located on the metal layer 20; a III-V group compound The semiconductor laminate 50 is located on the current narrowing layer 30 and includes a p-type semiconductor layer 51 , an active layer 53 , and an n-type semiconductor layer 55 in sequence; and an upper surface electrode 70 is located on the III-V compound semiconductor laminate 50 . The upper surface electrode 70 includes an opening 71 through which light emitted from the active layer 53 exits. In addition, the current narrowing layer 30 includes a dielectric layer 31 including a through hole 32 and an intermediate electrode 35 disposed in the through hole 32 and electrically connecting the p-type semiconductor layer 55 and the metal layer 20 . Furthermore, in the projected plane obtained by vertically projecting the current narrowing layer 30 including the intermediate electrode 35 with respect to the upper surface electrode 70, the opening 71 encloses the intermediate electrode 35, and the dielectric layer 31 encloses it. The upper surface electrode 70 . Furthermore, the film thickness of the p-type semiconductor layer 51 is not less than 0.5 μm and not more than 3.3 μm. It should be noted that the term "included" in this specification does not include the case where all the areas on the projection plane are completely identical. In addition, in FIG. 1 , a mesa structure is formed in the semiconductor laminate 50 , and a part of the outer peripheral edge of the dielectric layer 31 is exposed in the film thickness direction. Hereinafter, details of each configuration will be sequentially described.

<Support substrate>

The point light source type light emitting diode 100 according to the present invention is formed by the "bonding method" described later (refer to Japanese Patent Application Laid-Open No. 2018-006495). The relationship between the lattice constants is not particularly limited. As a suitable material constituting the support substrate 10, for example, a semiconductor substrate such as a Si substrate, a metal substrate such as Mo or W or Kovar, various submount substrates using AlN or the like, or the like can be used. Furthermore, the supporting substrate 10 is preferably conductive.

<metal layer>

The metal layer 20 is not particularly limited as long as it is a metal that forms the light reflection surface 21 that reflects light and can be electrically connected to the p-type semiconductor layer 51 via the intermediate electrode 35 . Specifically, it is preferable that Au is used as the main component, and more specifically, it is preferable that Au accounts for more than 50 mass %, and it is more preferable that Au accounts for 80 mass % or more. As shown in FIG. 1 , the metal layer 20 can be formed by bonding the metal bonding layer 25 and the metal reflective layer 27 on the support substrate side. In addition, when the metal layer 20 includes a metal layer containing Au (hereinafter referred to as "Au metal layer"), in the total film thickness of the metal layer 20, it is preferable that the film thickness of the Au metal layer is set to exceed 50%. . In the metal constituting the metal layer 20 (ie, Reflective metal), in addition to Au, Al, Pt, Ti, Ag, etc. can also be used. These reflective metal elements become the origin of the reflective metal contained in the metal layer 20 of the point light source type light emitting diode 100 according to the present invention. For example, the metal layer 20 may be a single layer including only Au, or may include two or more Au metal layers as the metal layer 20 . In particular, the light reflecting surface 21 is preferably the surface of the Au metal layer. For example, the film thickness of one layer of the Au metal layer in the metal layer 20 can be set to 400 nm to 2000 nm, and the film thickness of the metal layer containing a metal other than Au can be set to 5 nm to 200 nm, for example.

<current confinement layer>

The current narrowing layer 30 includes a dielectric layer 31 and an intermediate electrode 35 electrically connecting the p-type semiconductor layer 51 and the metal layer 20 . The dielectric layer 31 includes a through hole 32 , and the intermediate electrode 35 is disposed in the through hole 32 . The substantially conductive region in the current narrowing layer 30 is the intermediate electrode 35 formed in the through hole 32 . Furthermore, since the intermediate electrode 35 is filled in the through hole 32, it conforms to the shape of the through hole.

On the projection surface obtained by projecting the current narrowing layer 30 vertically with respect to the upper surface electrode 70, as long as each structure is formed so that the opening 71 wraps the intermediate electrode 35 and the dielectric layer 31 wraps the upper surface electrode 70, the current will flow. The size of the through hole 32 formed in the narrow layer 30 is not particularly limited. The size of the through hole 32 is smaller than that of the opening 71 because the through hole 32 is enclosed in the opening 71 on the projected plane in relation to the opening 71 of the upper surface electrode 70 which will be described in detail below. That is, the maximum length of the cross-sectional shape of the current narrowing layer corresponding to the through hole in the direction of the main surface (referred to as the width of the through hole in this specification) is smaller than the maximum opening diameter of the opening 71 (referred to as the opening portion in this specification). width). Since it depends on the point light source type light emitting diode 100 Therefore, the wafer size is not intended to be limited, and the width of the through hole can be exemplified as 25 μm to 150 μm.

In addition, the shape of the through hole 32 is not particularly limited, and examples thereof include a cylindrical shape, an elliptical cylindrical shape, a (regular) triangular prism, a (regular) square prism, a (regular) polygonal prism, and an indeterminate shape. In addition, the number of through-holes 32 per LED1 chip (that is, the number of intermediate electrodes) is arbitrary, and it is one or more. When a plurality of through-holes 32 are provided, all the through-holes 32 are enclosed in the opening 71 on the projection plane.

<<Dielectric layer material>>

The material of the dielectric layer is not particularly limited, and known materials can be used. For example, SiO ₂ , SiN, AlN, etc. can be used as the dielectric material, and SiO ₂ is particularly preferably used. The reason is that SiO ₂ is easily etched by buffered hydrofluoric acid (buffered hydrofluoric acid, BHF) or the like. In addition, as the material of the dielectric layer 31 , it is preferable to use a material transparent to light emitted from the active layer 53 .

<<Intermediate electrode material>>

The material of the intermediate electrode is not particularly limited, and known materials can be used. For example, the material of the intermediate electrode is preferably a material with lower resistivity than the dielectric layer. Specifically, AuZn-based, AuBe-based, etc. can be mentioned. It is formed by rapid heating at a predetermined temperature. In addition, the shape of the intermediate electrode is not particularly limited, and it is formed to match the shape of the through hole as described above.

<Semiconductor laminate>

The semiconductor laminate 50 is provided on the current narrowing layer 30 . The semiconductor laminate 50 sequentially includes a p-type semiconductor layer 51, an active layer 53, and an n-type semiconductor layer 55, by When electricity is supplied to the active layer 53 , electrons and holes are combined in the active layer 53 to emit light. The composition of each layer of the semiconductor laminate 50 is not particularly limited.

<<p-type semiconductor layer>>

The p-type semiconductor layer 51 is provided on the current narrowing layer 30 . The p-type semiconductor layer 51 may include a p-type contact layer and a p-type cladding layer sequentially from the side of the supporting substrate 10 . An intermediate layer for relaxing the lattice mismatch may also be provided between the p-type cladding layer and the p-type contact layer. In addition, the p-type cladding layer may have a multilayer structure. It is also preferable to provide a p-type spacer layer as the uppermost layer of the p-type semiconductor layer 51 . The composition of the p-type spacer layer may be constant in the direction of crystal growth, may be inclined in the direction of crystal growth, or may be modulated (including discontinuous changes).

<<active layer>>

The active layer 53 is provided on the p-type semiconductor layer 51 . The active layer 53 can be configured as a single layer structure as shown in FIG. 1 , and is also preferably configured as a multiple quantum well (Multiple Quantum Well, MQW) structure. In order to increase light output by suppressing crystal defects, it is more preferable that the active layer 53 has a multiple quantum well structure. The multiple quantum well structure can be formed by a structure in which well layers and barrier layers are alternately repeated. In addition, it is also preferable to set the both ends (i.e., the first and the last) of the active layer 53 in the film thickness direction as barrier layers. When the number of repetitions of the well layer and the barrier layer is set to n, in this case , expressed as the multiple quantum well structure of "n.5 groups".

<<n-type semiconductor layer>>

The n-type semiconductor layer 55 is provided on the active layer 53 . This n-type semiconductor layer 55 can be used as an n-type cladding layer. The n-type semiconductor layer 55 can be a single-layer structure or a stacked layer Composite layer made of multiple layers. In addition, it is also preferable to provide an n-type spacer layer as the lowermost layer (layer on the active layer 53 side) of the n-type semiconductor layer 55 . The composition of the n-type spacer layer may be constant in the direction of crystal growth, or the composition may be inclined or modulated in the direction of crystal growth. In addition, the n-type semiconductor layer 55 may have an n-type contact layer as necessary.

-Film thickness of p-type semiconductor layer-

Here, in the present invention, the film thickness of the p-type semiconductor layer 51 is set to be 0.5 μm or more and 3.3 μm or less. When the p-type semiconductor layer 51 has a plurality of p-type layers, the total film thickness of the p-type layers is set to be 0.5 μm or more and 3.3 μm or less. If the film thickness of the p-type semiconductor layer 51 is within this range, the film thickness of the p-type semiconductor layer 51 is sufficiently thin, so that the current flowing through the intermediate electrode 35 inside the through-hole 32 flows in the in-plane direction of the p-type semiconductor layer 51. Flows to the active layer 53 substantially without diffusion. Therefore, current is concentrated on a specific part of the active layer 53, and local light emission is performed at this part.

Hereinafter, in this specification, a region in the active layer 53 that locally emits light due to current concentrated in a specific portion of the active layer is referred to as a main light emitting region 53A. As described above, the thickness of the p-type semiconductor layer 51 is sufficiently thin, so the size and position of the main light emitting region 53A are considered to be equivalent to a projected body obtained by vertically projecting the intermediate electrode 35 with respect to the active layer 53 . Therefore, in this specification, the main light emitting region 53A is regarded as a projected surface obtained by vertically projecting the intermediate electrode 35 with respect to the active layer 53 . By setting the film thickness of the p-type semiconductor layer 51 within the above-mentioned range, the spread of current can be suppressed, the influence of surface recombination of the active layer in the portion exposed on the side surface of the wafer can be reduced, and the luminous output can be suppressed with respect to temperature. change of change. The reason for this is that if the p-type When the film thickness of the semiconductor layer 51 is within the above-mentioned range, even if the mobility changes due to temperature changes, the rate of occurrence of surface recombination does not change.

As described above, the total film thickness of the p-type semiconductor layer 51 is 0.5 μm to 3.3 μm, and the total film thickness of the p-type semiconductor layer 51 is preferably 0.5 μm to 3.0 μm, more preferably 0.5 μm to 3.0 μm. 0.9 μm or more, more preferably 2.8 μm or less.

The reason for setting the film thickness of the p-type semiconductor layer 51 to 0.5 μm or more is that if it is less than 0.5 μm, the reliability of the light-emitting element decreases, and there is a possibility of freezing due to temperature changes.

In addition, the film thickness of each p-type layer in the p-type semiconductor layer is not limited as long as the above-mentioned total film thickness is satisfied. The thickness of the p-type cladding layer is 0.1 μm to 2.5 μm, the thickness of the p-type contact layer is 10 nm to 100 nm, and the thickness of the p-type spacer layer is 300 nm to 700 nm.

-Composition of each semiconductor layer-

The composition of each of the p-type semiconductor layer 51, the active layer 53, and the n-type semiconductor layer 55 is appropriate according to the composition of the group III-V compound semiconductor in the active layer 53, which is a dominant factor of the light emission wavelength of the point light source type light emitting diode 100. Just decide.

--Composition of active layer--

The active layer contains a III-V compound semiconductor, and the composition of the III-V compound semiconductor of the active layer 53 is expressed as (In _a1 Ga _b1 Al _c1 )(P _x1 As _y1 Sb _z1 ); c ₁ =1-a ₁ -b ₁ , z ₁ =1-x ₁ -y ₁ , 0≦a ₁ ≦1, 0≦b ₁ ≦1, 0≦c ₁ ≦1, 0≦x ₁ ≦1, 0≦y ₁ ≦1 , 0≦z ₁ ≦1.

The active layer 53 may have, for example, a single-layer structure including AlGaAs-based materials, AlGaAsInP-based materials, AlGaAsP-based materials, AlInGaP-based materials, InGaAsSb-based materials, or a laminated structure such as multiple quantum wells. These can be formed by epitaxial growth using known methods such as Metal Organic Chemical Vapor Deposition (MOCVD) method. The emission wavelength can be set in the range of 580 nm to 4000 nm, for example, and it is preferable to set the emission wavelength in the range of 630 nm to 1100 nm. In addition, the film thickness of the active layer is different from the film thickness of the p-type semiconductor layer 51 and is not particularly limited. The active layer is preferably 10 nm to 500 nm.

For example, when the emission center wavelength is set at 630nm to 1100nm, the composition ratio _a1 of In in the active layer (in the case of a form including a well layer and a barrier layer, each layer) can be set at 0.0 to 1.0, and Ga The composition ratio b ₁ of Al is 0.0~1.0, the composition ratio c ₁ of Al is 0.0~0.5, the composition ratio x ₁ of P is 0.0~1.0, and the composition ratio y ₁ of As is 0.0~1.0, The composition ratio z ₁ of Sb is set to 0.0 to 0.5.

--Composition of p-type semiconductor layer--

The composition of the p-type semiconductor layer 51 may be appropriately determined according to the composition of the III-V compound semiconductor of the active layer 53 . As the p-type contact layer, a p-type AlGaAs or p-type InGaAs layer can be exemplified, as the p-type cladding layer, a p-type AlGaAs or p-type InP layer can be exemplified, and as the p-type spacer layer, a p-type AlGaAs layer can be exemplified wait.

--Composition of n-type semiconductor layer--

In addition, regarding the composition of the n-type semiconductor layer 55, the III-V composition of the n-type semiconductor layer 55 is appropriately determined according to the composition of the III-V group compound semiconductor of the active layer 53. The composition of the group compound semiconductor is sufficient. Examples of the n-type spacer layer include n-type AlGaAs, n-type InP, and the like, and examples of the n-type cladding layer include n-type AlGaAs.

-film thickness-

Unlike the overall film thickness of the p-type semiconductor layer 51 , the film thicknesses of the active layer 53 and the n-type semiconductor layer 55 are not limited.

--Film thickness of the active layer--

In the case where the active layer 53 has a quantum well structure, the film thickness of the well layer can be set to 3 nm to 17 nm, the film thickness of the barrier layer can be set to 5 nm to 20 nm, and the number of sets of both can be set to 3 to 50. . In addition, in either case of the single-layer structure and the quantum well structure, the film thickness of the entire active layer can be set to 100 nm to 500 nm.

--Film thickness of n-type semiconductor layer--

The film thickness of the n-type cladding layer is not limited, and examples thereof include 1 μm to 15 μm and 3.5 μm to 12 μm. The film thickness of the n-type spacer layer is also not limited, for example, it can be set at 5 nm to 500 nm. Furthermore, it is preferable to make the overall thickness of the n-type semiconductor layer 55 larger than the overall thickness of the p-type semiconductor layer 51 . The reason is that generally, a p-type semiconductor has low electron mobility and high resistance, and thus is easy to use as a current confinement structure. On the other hand, in the present invention, it is desirable to spread the current on the n-type semiconductor layer side.

--Overall Film Thickness of Semiconductor Laminated Body--

In addition, the overall film thickness of the semiconductor laminate 50 is not limited, and may be, for example, 2 μm to 17 μm.

In addition, each layer constituting the semiconductor laminate 50 may be appropriately doped with a known n-type dopant (Te, Si, etc.) or p-type dopant (Zn, C, Mg, etc.).

Furthermore, since each layer constituting the semiconductor laminate 50 can have a uniform structure in the plane of each layer, composition, etc., complicated manufacturing steps are not required.

<Upper surface electrode>

The upper surface electrode 70 is provided on the semiconductor laminate 50 . The upper surface electrode 70 includes an opening 71 through which light emitted from the active layer 53 is emitted. In addition, in the projected plane of the current narrowing layer 30 including the intermediate electrode 35 perpendicularly projected with respect to the upper electrode 70 , the opening 71 includes the intermediate electrode 35 , and the dielectric layer 31 includes the upper electrode 70 .

In other words, the size of the opening 71 of the upper surface electrode 70 is equal to or larger than that of the intermediate electrode 35 , and the intermediate electrode 35 is included in the opening 71 in plan view viewed from the film thickness direction. Therefore, in the point light source type light emitting diode 100 , the projected body of the intermediate electrode 35 exists in the opening 71 on the projected plane where the intermediate electrode 35 is vertically projected with respect to the upper surface electrode 70 . In addition, the upper surface electrode 70 is included between the outer edge and the inner edge of the dielectric material layer 31 in a plan view viewed from the film thickness direction. Therefore, in the point light source type light emitting diode 100 , on the projected plane obtained by projecting the dielectric layer 31 vertically with respect to the upper surface electrode 70 , the upper surface electrode exists in the inner region of the projection body of the dielectric layer 31 . .

The shape of the opening 71 of the upper electrode 70 is not particularly limited as long as the opening 71 includes the intermediate electrode 35 on a projected plane perpendicularly projecting the intermediate electrode 35 to the upper electrode 70 . The shape of the opening 71 may be circular or elliptical, or star-shaped or polygonal.

In addition, it is preferable that both the opening portion 71 and the intermediate electrode 35 are arranged in a place such as Lower position: a position where the center of gravity (geometric center) of the opening 71 and the intermediate electrode 35 coincide with each other on a projected plane where the intermediate electrode 35 is perpendicularly projected with respect to the upper surface electrode 70 . The size of the main light emitting region 53A and the in-plane position of the main light emitting region 53A are substantially the same as the projected body of the intermediate electrode 35 on the main surface of the active layer 53 . Therefore, in the case of FIG. 1 , the center axis of the opening 71 overlaps with the center of the main light emitting region 53A. In such a case, it is preferable that the light emitted from the main light emitting region 53A can be efficiently extracted to the outside.

<Other electrodes>

The upper surface side pad electrode E1 and the back surface electrode E2 can be respectively provided on the upper surface electrode 70 and the back surface of the supporting substrate 10, and the metal materials used to form each electrode can use metals such as Ti, Pt, Au or form a eutectic with gold. Common materials such as alloy metals (Sn, etc.). The electrode patterns of the upper pad electrode E1 and the back electrode E2 are arbitrary and not limited in any way.

As described above, in the point light source type light emitting diode 100 according to the present invention, the main current flowing between the upper surface electrode 70 and the back surface electrode E2 formed on the back surface of the supporting substrate 10 passes through the through hole 32 provided inside the through hole 32 . The intermediate electrode 35 passes through the main light emitting region 53A of the active layer 53 . At this time, since the resistance of the p-type semiconductor layer 51 is high, the current is narrowed and the current can be concentrated on a specific part of the active layer 53 . As a result, partial light emission can be performed at a specific portion of the active layer 53 . As described above, a point light source type light emitting diode can be obtained in the present invention with a simple structure based on the arrangement relationship between the current narrowing layer 30 and the upper surface electrode 70 and the film thickness of the p-type semiconductor layer 51 . Therefore, the manufacturing steps can be simplified by the present invention, and dots can be made Light source type light emitting diode.

However, if point light source type light emitting diodes are used as light sources for sensors, etc., it is necessary to suppress fluctuations in light output in various severe temperature environments such as high temperature environments and cold regions. As described in detail together with the technical significance of the shortest separation distance below, in the present invention, since the film thickness of the p-type semiconductor layer 51 is limited, the temperature dependence characteristics are also excellent, so the present invention is further advanced in this regard. favorable.

<separation distance>

The shortest distance between the outermost periphery of the main light emitting region 53A and the outer periphery of the active layer 53 is preferably 30 μm or more, more preferably 60 μm or more. Thereby, it is possible to provide a point light source type light emitting diode exhibiting a more excellent temperature dependence characteristic of luminous output. As described above, it is considered that the size and position of the main light emitting region 53A are equal to the projected body obtained by vertically projecting the intermediate electrode 35 with respect to the active layer 53 . Therefore, the outermost periphery of the main light emitting region 53A is defined by the outermost periphery of the projection body. Hereinafter, the reason why the shortest separation distance is preferably 30 μm or more will be described.

As one of the methods of improving the temperature-dependent characteristics of luminous output, it is important to reduce the influence of surface recombination. Such surface recombination of the active layer in the light-emitting diode occurs remarkably at the portion exposed on the side surface of the wafer, and this is considered to be the cause of deterioration of the temperature-dependent characteristics. Furthermore, the range in which surface recombination significantly occurs is set to be about several times the diffusion length of free electrons from the portion where the active layer is exposed on the side surface of the wafer. The film thickness of the p-type semiconductor layer 51 in the present invention is set within a predetermined range. Accordingly, current can be made to flow to active layer 53 without substantially spreading in the in-plane direction of p-type semiconductor layer 51 , or the current flowing in the in-plane direction of p-type semiconductor layer 51 can be reduced. its knot As a result, the current flowing in the in-plane direction of the p-type semiconductor layer 51 is small. Based on this idea, it is considered that as long as the shortest separation distance is ensured and the current is passed through the n-type semiconductor layer 55 before the current reaches the outer periphery of the active layer 53, surface recombination can be further suppressed, which is important for further improving the temperature dependence of the luminous output. Words are valid.

Furthermore, although the upper limit of the shortest distance between the outer periphery of the active layer and the outermost periphery of the main light-emitting region depends on the wafer size of the point light source type light emitting diode 100, as long as a sufficient minimum distance is set, it will not The problem of surface recombination arises, so there is no particular limitation. In addition, as an example, 1000 μm can be illustrated as the upper limit of the shortest separation distance in consideration of the wafer size.

<Coating on the side of the active layer>

Refer to Fig. 2 which shows another aspect of the present invention. In the point light source type light emitting diode 200 , preferably, the light reflection surface 21 of the metal layer 20 covers at least a part of the side surface of the active layer 53 via the dielectric layer 31 . The light radiated from the side surface of the active layer 53 can be blocked on the side surface of the active layer 53, and at the same time, it can be reflected to the inside of the semiconductor laminate 50 by the light reflection surface 21, so that a part of the light can be extracted to the outside, so it is also expected to improve the external quantum. efficiency.

In order to form the light reflection surface 21 covering at least a part of the side surface of the active layer as described above, for example, the following method may be used. First, an n-type semiconductor layer 55 , an active layer 53 , and a p-type semiconductor layer 51 are sequentially formed on a growth substrate by a bonding method. Then, a mesa structure is formed from the side of the p-type semiconductor layer 51 . Next, the dielectric layer 31 and the metal reflective layer 27 are sequentially formed to cover the inclined surfaces of the mesa structure of the p-type semiconductor layer 51 and the active layer 53 . Then, the metal is reflected via the metal bonding layer 25 The layer 27 is bonded to the supporting substrate 10, and the growth substrate is removed. Finally, a mesa structure is formed on the n-type semiconductor layer 55 . Thereby, the point light source type light emitting diode 200 having the light reflection surface 21 of the aspect shown in FIG. 2 can be formed.

Next, an aspect of the method of manufacturing the point light source type light emitting diode 100 (see FIG. 1 ) according to the present invention will be described.

(Manufacturing method of point light source type light emitting diode)

The manufacturing method of the point light source type light emitting diode according to the present invention at least includes: a first step of forming a semiconductor layered body sequentially comprising an n-type semiconductor layer 55, an active layer 53, and a p-type semiconductor layer 51 on a growth substrate. 50; the second step is to form the current narrowing layer 30 on the p-type semiconductor layer 51; the third step is to form the metal reflective layer 27 on the current narrowing layer 30; the fourth step is to make the supporting substrate with the metal bonding layer 25 on the surface 10 via the metal bonding layer 25 and the metal reflective layer 27, and simultaneously form the metal layer 20; the fifth step is to remove the growth substrate; and the sixth step is to form The upper surface electrode 70 has an opening 71 through which light emitted from the active layer 53 exits. Furthermore, in the second step, the current narrowing layer 30 is formed including a dielectric layer 31 including a through hole 32 and an intermediate electrode 35 disposed in the through hole 32 and placing The p-type semiconductor layer 51 is electrically connected to the metal layer 20 . Furthermore, in the projected plane where the current narrowing layer 30 including the intermediate electrode 35 is vertically projected with respect to the upper electrode 70 , the opening 71 includes the intermediate electrode 35 , and the dielectric layer 31 includes the upper electrode 70 . Furthermore, the film thickness of the p-type semiconductor layer 51 is not less than 0.5 μm and not more than 3.3 μm.

The Group III-V compound semiconductor material, dielectric material, and metal material constituting each layer, the film thickness of each layer, and the number of stacked groups are as described above, and repeated descriptions are omitted.

<first step>

In the first step, the semiconductor laminate 50 in which the n-type semiconductor layer 55 , the active layer 53 , and the p-type semiconductor layer 51 are sequentially formed is formed on the growth substrate. An etching stopper layer made of a group III-V compound semiconductor may be formed between the growth substrate and the n-type semiconductor layer 55 if necessary. The etch stop layer can also function as a strain buffer layer. The growth substrate may be suitably selected from GaAs substrates, InP substrates, GaSb substrates, InSb substrates, etc. according to the composition and lattice constant of the semiconductor laminate 50 to be grown thereon. In order to form the n-type semiconductor layer on the growth substrate, it is preferable to use an n-type substrate, but the conductivity type of the growth substrate may be undoped or p-type.

Each layer of the semiconductor laminate layer can be formed by known thin film growth methods such as Metal Organic Chemical Vapor Deposition (MOCVD) method, Molecular Beam Epitaxy (MBE) method, and sputtering method. In the case of an InGaAsP-based semiconductor, for example, trimethylindium (TMIn) as an In source, trimethylgallium (TMGa) as a Ga source, arsine (AsH ₃ ) as an As source, and Phosphine (PH ₃ ) or the like as a P source is vapor-phase-grown with these source gases using a carrier gas, whereby the InGaAsP-based semiconductor layer can be epitaxially grown with a desired film thickness according to the growth time. In addition, in the case of using Al as a group III element, trimethylaluminum (TMA) or the like may be used as the Al source, for example, and in the case of using Sb as a group V element, trimethylaluminum (TMA) may be used as the Sb source. Base antimony (TMSb) and the like will suffice. Furthermore, when doping each semiconductor layer with p-type or n-type, if necessary, the gas which contains the dopant source of Si, Zn, etc. among constituent elements may be used further.

<Second Step~Fourth Step>

Known methods can be used to form the intermediate electrode layer, dielectric layer, metal reflective layer, metal bonding layer, and upper surface electrodes, such as sputtering, electron beam evaporation, or resistance heating. When forming the dielectric layer, known film-forming methods such as plasma chemical vapor deposition (CVD) or sputtering may be used, and if necessary, known etching methods may be used to form unevenness.

<<The second step>>

In the second step, the current narrowing layer 30 including the intermediate electrode 35 is formed on the p-type semiconductor layer 51 . For example, first, the intermediate electrode 35 is formed on a part of the surface of the p-type semiconductor layer 51 by sputtering or the like, and the surface of the remaining part is exposed. Next, the dielectric layer 31 is formed on the exposed portion, and the current narrowing layer 30 can be formed if the height matches the intermediate electrode 35 . In addition, it is assumed that the portion where the intermediate electrode 35 is removed from the current narrowing layer 30 corresponds to the above-mentioned through hole 32 . In addition, after forming the dielectric layer, a part of the dielectric layer may be removed by etching or the like to expose the p-type semiconductor layer 51 to form the through hole 32, and the intermediate electrode 35 may be formed in the through hole 32. .

<<The third step>>

Next, in the third step, a metal reflective layer is formed on the current narrowing layer 30 27. As a result, the light reflection surface 21 is provided on the p-type semiconductor layer 51 side of the semiconductor laminate 50 .

<<The fourth step>>

Next, in the fourth step, a metal bonding layer 25 is provided on one side of the support substrate 10 , and then the support substrate 10 is bonded to the metal reflective layer 27 via the metal bonding layer 25 by bonding, thereby obtaining the metal layer 20 . The metal reflective layer 27 and the metal bonding layer 25 may be arranged to face each other and bonded by heating, compression, or the like.

<The fifth step>

In the fifth step, the growth substrate is removed by a known method. For example, a mixture of ammonia water and hydrogen peroxide water may be used for removal by wet etching, and the etch stop layer may also be used as an end point of the wet etching. In addition, when removing the etching stop layer, wet etching may be performed using an etchant different from that of the substrate for growth (for example, an etchant of dilute hydrochloric acid).

<Step 6>

Finally, in the sixth step, the upper surface electrode 70 is formed on the removed surface of the growth substrate in the n-type semiconductor layer 55 . A known method can be used to form the upper surface electrode, for example, a sputtering method, an electron beam evaporation method, a resistance heating method, or the like can be used. The upper surface electrode 70 includes the opening 71 , and the arrangement relationship of the upper surface electrode 70 , the opening 71 , the dielectric layer 31 , and the intermediate electrode 35 on the projection plane is as described above.

<Additional steps>

After the sixth step, a surface roughening step of forming a plurality of irregularities on the light extraction surface may be performed. Furthermore, it can also be used in point light source type light-emitting diodes The singulated lines to cut form a mesa structure. Then, the back electrode E2 is formed, so that the point light source type light emitting diode of the present invention can be manufactured.

[Example]

Hereinafter, the present invention will be described in more detail using examples, but the present invention is not limited at all by the following examples.

(Experimental example 1)

The target emission center wavelength was set at 850 nm, and the following point light source type light emitting diodes were produced by the bonding method.

<Example 1>

As the growth substrate, an n-type GaAs substrate was used. An etching stopper layer was formed on the (100) plane of the growth substrate by the MOCVD method, and further, each semiconductor layer was sequentially epitaxially grown by the MOCVD method under the following conditions.

<1> n-type Al _0.20 Ga _0.80 As layer with a film thickness of 7100nm (doped with Te, 8.0×10 ¹⁷ atoms/cm ³ ; first n-type cladding layer)

<2> n-type Al _0.40 Ga _0.60 As layer with a film thickness of 400nm (doped with Te, 1.0×10 ¹⁷ atoms/cm ³ ; second n-type cladding layer)

<3>Al _0.24 Ga _0.76 As layer with a film thickness of 500nm (undoped; n-side spacer layer)

<4>Quantum well type active layer with an overall film thickness of 310nm (details will be described below)

<5> p-type Al _0.24 Ga _0.76 As layer (doped with C, 2.0×10 ¹⁶ atoms/cm ³ ) with a film thickness of 500 nm (p-side spacer layer)

<6>Al _0.40 Ga _0.60 As layer with a film thickness of 400nm (doped with C, 1.5×10 ¹⁸ atoms/cm ³ ; second p-type cladding layer)

<7> Al _0.20 Ga _0.80 As layer with a film thickness of 1500 nm (doped with C, 1.5×10 ¹⁸ atoms/cm ³ ; first p-type cladding layer)

<8>p-type Al _0.12 Ga _0.88 As layer with a film thickness of 100nm (doped with Zn, 3×10 ¹⁸ atoms/cm ³ ; p-type contact layer)

The total film thickness of the p-type semiconductor layer in Example 1 (total of the p-type contact layer, p-type cladding layer, and p-side spacer layer) was 2.5 μm. In addition, when forming the active layer, first, an Al _0.2 Ga _0.8 As _0.6 P _0.4 barrier layer with a film thickness of 17.5 nm is formed, and then, 13 sets of Al _0.069 In _0.16 Ga _0.771 As well layers and a film thickness of 5 nm are alternately formed. Al _0.2 Ga _0.8 As _0.6 P _0.4 barrier layers of 17.5 nm were set to 13.5 sets in total.

The respective compositions and dopant concentrations of the respective layers in Example 1 are values measured by SIMS analysis.

Next, a dielectric layer (thickness: 550 nm) made of SiO ₂ was formed on the entire surface on the p-type contact layer by plasma CVD. Next, after forming a resist pattern on the part other than the part where the through hole is formed, the dielectric layer in the part where the through hole is formed is etched and removed by BHF to expose the p-type contact layer, thereby forming a through hole in the dielectric layer. hole.

Next, a columnar intermediate electrode (metal material of the electrode: AuZn, film thickness: 540 nm) having a diameter of _L2 was formed in the through hole portion in the dielectric layer on the p-type contact layer. Furthermore, when forming a columnar pattern, a resist pattern is formed, and then an intermediate electrode is vapor-deposited, and the resist pattern is peeled off.

Next, a metal reflective layer (Al/Au/Pt/Au) was sequentially formed on the entire surface above the current confinement layer by vapor deposition. The film thickness of the metal reflective layer was 1660 nm in total.

On the other hand, a metal bonding layer (Ti/Pt/Au) was formed on a conductive Si substrate (film thickness: 200 μm) serving as a support substrate. The film thickness of the metal bonding layer was 1570 nm in total.

These metal reflective layers and metal bonding layers were arranged to face each other, and thermocompression bonding was performed at 300°C. Then, the growth substrate is wet-etched and removed by using a mixture of ammonia water and hydrogen peroxide water, so that the etch stop layer is exposed, and further, the etch stop layer is removed by wet etching using a dilute hydrochloric acid solution, so that the second n The type coating is exposed.

An n-type electrode (Au (thickness: 10nm)/Ge (thickness: 33nm) )/Au (film thickness: 57nm)/Ni (film thickness: 34nm)/Au (film thickness: 800nm)/Ti (film thickness: 100nm)/Au (film thickness: 1000nm)) as the upper surface electrode. In addition, assuming that the opening diameter of the opening obtained by the resist pattern is L ₁ , they were arranged so that the center of the opening and the center of the intermediate electrode were located on the concentric axis. Furthermore, a spacer portion (Ti (film thickness: 150 nm)/Pt (film thickness: 100 nm)/Au (film thickness: 2500 nm)) was formed on a part of the n-type electrode.

Finally, the semiconductor layer between the elements was removed by mesa etching (etching width: 40 μm) to form dicing lines. Then, a back electrode (Ti (film thickness: 10nm)/Pt (film thickness: 50nm)/Au (film thickness: 200nm)) was formed on the back side of the Si substrate, Wafer was singulated by dicing, and the point light source type light emitting diode of Example 1 was produced. In the double circles in FIG. 3 , the outer circle is the opening in the upper surface electrode, and the inner circle (hatched portion) is the intermediate electrode 35 . Furthermore, the wafer size is 250 μm×400 μm. In addition, the size of the opening in Example 1 (opening diameter d2) is Φ80 μm, the width d1 of the intermediate electrode is Φ40 μm, the maximum diameter of the main light-emitting region and the outermost circumference of the projection of the intermediate electrode (main light-emitting region) and the active layer The shortest distance between the outer circumference of the 68μm.

<Evaluation of Luminous Intensity Distribution>

The point light source type light emitting diode of Example 1 was operated by pulse driving (pulse forward current Ifp: 100 mA, frequency: 10 kHz, duty ratio: 0.2%). The emission intensity distribution of the cross section including the opening at this time is shown in FIG. 5A . Furthermore, the emission intensity distribution was observed using an infrared microscope. The vertical axis in FIG. 5A represents the luminous intensity (relative intensity), and the horizontal axis represents an arbitrary relative position of the cross section. The image observed with an infrared microscope is represented as whiter with stronger luminous intensity and darker with weaker luminous intensity, and the degree of white and black is digitized and graphed. Therefore, the numerical value does not represent zero even in the part with the strongest degree of blackness. Referring to FIG. 5A , it can be seen that most of the light emission is emitted from the opening, and it is confirmed that it has characteristics specific to a point light source. Furthermore, since the luminous intensity within the width (d1) of the intermediate electrode, that is, Φ40 μm, is high, and the luminous intensity decreases toward the end portion of Φ80 μm, that is, the size (d2) of the opening, the total film thickness of the p-type semiconductor layers is 2.5 μm. μm in Example 1, it was confirmed that in the in-plane direction of the p-type semiconductor layer 51 and outside the range corresponding to the intermediate electrode, the current hardly diffuses, the current flows to the active layer 53, and the current concentrates on the active layer 53. layer 53, and perform partial light emission on this part. Furthermore, the point light source type light emitting diode of Example 1 was manufactured using the bonding method, and as described below, it was confirmed that it can be obtained by manufacturing steps simplified compared with the prior art.

Examples of methods for forming a conventionally known current confinement structure include an embedding method, a Zn diffusion method, and an ion implantation method. In the embedding method, two crystal growth steps by the MOCVD method are required. In addition, a patterning step for forming a current narrowing layer, an etching step, and a pretreatment of a growth substrate for re-growth are required between the two growths. In the Zn diffusion method, a patterning step and a Zn diffusion step are also required, and a device for Zn diffusion is also required. In the ion implantation method, a patterning step and an ion implantation step are also required, and a device for ion implantation is also required. Also, ion implantation equipment is more expensive than other equipment. Compared with these conventional methods, the patterning process in the bonding method of Example 1 is simple, and the bonding apparatus is also inexpensive. As mentioned above, it can be seen that in Embodiment 1, the point light source type light emitting diode can be manufactured through simple manufacturing steps, and the manufacturing cost can be reduced because of its simplicity.

(Experimental example 2)

Next, in the same manner as in Experimental Example 1, the target light emission center wavelength was set to 850 nm, and the point light source type light emitting diodes of the following Examples 2 to 4 and Comparative Example 1 were produced by the bonding method, and the light emission intensity was adjusted. Distribution and temperature dependence characteristics were evaluated.

<Example 2~Example 4>

Table 1 shows the wafer size, the size of the opening, the width of the intermediate electrode, the maximum diameter of the main light-emitting region, and the outermost periphery of the projection of the intermediate electrode (main light-emitting region) and the outer periphery of the active layer. The value of , otherwise, is the same as the In the same manner as in Example 1, a point light source type light emitting diode was fabricated. Table 1 shows the respective dimensions including Example 1.

<Comparative example 1>

In Comparative Example 1, the shape of the intermediate electrode was a so-called ring shape (see FIG. 4 ), and an upper surface electrode with a diameter D: Φ120 μm was formed on the center portion of the ring-shaped intermediate electrode. Furthermore, unlike Examples 1 to 4, no openings are provided. The part surrounded by the circle with the smallest diameter of the triple circles in FIG. 4 (lower right hatched part) is the upper surface electrode. In addition, the portion enclosed by the two outer circles of the triple circle (the lower left hatched portion in FIG. 4 ) corresponds to the intermediate electrode. Furthermore, the outer diameter _L2 of the intermediate electrode was 300 μm, and the inner diameter _L3 was 270 μm. In addition, the shortest separation distance d is 25 μm. Other conditions were set to be the same as in Example 1. The respective dimensions are shown in Table 2.

[Table 1]

<Evaluation of Luminous Intensity Distribution>

The emission intensity distributions of Examples 2 to 4 were measured in the same manner as in Experimental Example 1. The results are shown in FIGS. 5B to 5D , respectively. Referring to FIG. 5B to FIG. 5D , similarly to Example 1, in Examples 2 to 4, it can be seen that most of the light emission is emitted from the opening, and it is confirmed that it has characteristics specific to a point light source. Furthermore, since the luminous intensity within the range of the width (d1) of the intermediate electrode is high, and the luminous intensity decreases toward the end of the size (d2) of the opening, when the total film thickness of the p-type semiconductor layers is 2.5 μm, it is confirmed that To: in the in-plane direction of the p-type semiconductor layer 51 and outside the range corresponding to the intermediate electrode, the current does not substantially diffuse, the current flows to the active layer 53, and the current concentrates on a specific part of the active layer 53, where Partial lighting.

<Temperature dependence of luminous output>

The relative value of each output when the point light source type light-emitting diodes of Examples 1 to 4 and Comparative Example 1 were operated at -25°C to 100°C was plotted against the output at 25°C to obtain a straight line The slope rate when approximated as a temperature-dependent characteristic. The smaller the absolute value of the gradient, the better the temperature dependence characteristic (that is, the smaller the temperature dependence of the output). Table 1 and Table 2 show temperature dependence characteristics (%/° C.) at a current value of 20 mA. In addition, in order to measure the temperature dependence characteristic of an output, first, the TO-18 metal stem (metal stem) to which the wafer was mounted was put in a constant temperature bath. Then, by changing the temperature of the constant temperature bath and measuring the output at the window of the constant temperature bath, changes in the output at each temperature were measured.

Here, it should be noted that the narrower the width of the intermediate electrode (intermediate electrode diameter L ₂ ), the better the temperature dependence characteristic. Generally, when the width of the intermediate electrode is narrow, that is, the electrode area of the intermediate electrode is small, the current density becomes high. In such a case, the luminous efficiency in the light emitting layer should be relatively lowered. However, experimental facts show results contrary to this idea. When comparing Example 1 and Example 2 and Example 3 and Example 4, Example 1 and Example 2, which have a small electrode area and high current density, have a small slope rate of output change due to temperature, and the temperature dependence characteristic Get better. This is more considered to be an influence of the shortest separation distance d than an influence of the width of the intermediate electrodes. The reason is considered to be that the influence of the temperature dependence characteristic is affected when the minimum separation distance d is 30 μm as the boundary value, and the influence of the surface recombination of the part where the active layer is exposed on the side surface of the wafer becomes significant. The range in which surface recombination significantly occurs is set to be about several times the diffusion length of free electrons from the portion of the active layer exposed on the side of the wafer. In the case of this example, the boundary value of the shortest separation distance d is considered to be 30 μm. Furthermore, based on the results of Comparative Example 1, it is considered that the boundary value of the shortest separation distance d, which affects the temperature-dependent characteristics, is 30 μm.

(Experimental example 3)

Next, in the same manner as in Experimental Example 1, the target light emission center wavelength was set to 850 nm, and the point light source type light-emitting diodes of the following Example 5, Comparative Example 2, and Comparative Example 3 were produced by the bonding method, so that The influence of the thickness of the type semiconductor layer was evaluated.

<Example 5>

The total film thickness of the p-type semiconductor layer (total of the p-type contact layer, p-type cladding layer, and p-side spacer layer) was set to 3.3 μm thicker than the 2.5 μm in Example 1. 1. The point light source type light emitting diode of Example 5 was produced in the same manner. Furthermore, in Example 5, the thickness of the first p-type cladding layer was changed to 2100 nm, and the thickness of the p-side spacer layer was changed to 700 nm.

<Comparative example 2>

The total film thickness of the p-type semiconductor layer (total of the p-type contact layer, p-type cladding layer, and p-side spacer layer) was set to 5.3 μm thicker than the 2.5 μm in Example 1. 1 was carried out in the same manner to manufacture the point light source type light emitting diode of Comparative Example 2. In addition, in Comparative Example 2, the thickness of the first p-type cladding layer was changed to 4300 nm.

<Comparative example 3>

The total film thickness of the p-type semiconductor layer (total of the p-type contact layer, p-type cladding layer, and p-side spacer layer) was set to 0.41 μm, which was thinner than 2.5 μm in Example 1, and Except that, it carried out similarly to Example 1, and the point light source type light emitting diode of the comparative example 3 was manufactured. Furthermore, in Comparative Example 3, the first p-type cladding layer was removed, the p-type contact layer was changed to 10 nm, the second p-type cladding layer was changed to 100 nm, and the p-side spacer layer was changed to 300 nm.

<Evaluation of Luminous Intensity and Forward Voltage>

Regarding Example 1, Example 5, Comparative Example 2, and Comparative Example 3, the light emission output (mW) and forward voltage at a current of 20 mA were measured using a constant current voltage power supply. The results are shown in Table 3.

<Temperature dependence of luminous output>

Except for changing the current at the time of measurement from 20mA to 5mA, it was carried out in the same manner as in the above-mentioned Experimental Example 2, and the relative value of each output when operating at -25°C to 100°C with respect to the output at 25°C was calculated. Draw the graph, and obtain the slope rate at the time of linear approximation as the temperature dependence characteristic. Furthermore, regarding the temperature dependence of the output, put the TO-18 metal rod with the chip in the constant temperature bath, change the temperature of the constant temperature bath, and measure the output at the window of the constant temperature bath, so as to perform the output at each temperature. Comparison of output changes. In Experimental Example 3, the reason for changing the measurement current from 20 mA to 5 mA when evaluating the temperature-dependent characteristics is that the resistance in the active layer at 5 mA is relatively larger than that at 20 mA. As a result, the current tends to spread, so the reason is that the influence of surface recombination in the part where the active layer is exposed on the side surface of the wafer is significantly manifested, and the slope rate of the temperature dependence becomes larger, which is easier to understand than when the measurement is performed at 20 mA. The temperature dependence is different. The results are shown in Table 3 together with the value of the wall plug efficiency (WPE).

From the results in Table 3, it can be seen that by setting the film thickness of the p-type semiconductor layer 51 to 0.5 μm or more and 3.3 μm or less, a point light source type light emitting diode with high luminous efficiency can be obtained. Furthermore, from the comparison of Example 1, Example 5, and Comparative Example 2, it can be seen that when the total thickness of the p-type semiconductor layers exceeds 3.3 μm, the temperature dependence is greatly deteriorated. On the other hand, as in Comparative Example 3, it can also be seen that when the total thickness of the p-type semiconductor layers is thinner than 0.5 μm, the durability against temperature changes is lost.

[industrial availability]

According to the present invention, it is possible to provide a point light source type light emitting diode which can simplify the manufacturing steps and has excellent temperature dependence characteristics, and a manufacturing method thereof.

10: Support substrate

20: metal layer

21: light reflective surface

25: Metal bonding layer

27: metal reflective layer

30: current narrow layer

31: Dielectric layer

32: Through hole

35: middle electrode

50: Semiconductor laminate

51: p-type semiconductor layer

53: active layer

53A: Main light-emitting area

55: n-type semiconductor layer

70: Upper surface electrode

71: Opening

100: point light source type light emitting diode

E1: pad electrode

E2: back electrode

Claims (4)

A point light source type light-emitting diode, characterized in that it comprises: a supporting substrate; a metal layer located on the supporting substrate and including a light reflecting surface; a current narrowing layer located on the metal layer; a III-V group compound semiconductor laminate body, located on the current narrowing layer and sequentially includes a p-type semiconductor layer, an active layer, and an n-type semiconductor layer; and an upper surface electrode, located on the III-V group compound semiconductor laminate, and the upper surface electrode includes an opening for emitting light emitted from the active layer, the current narrowing layer includes a dielectric layer including a through hole, and an intermediate electrode provided in the through hole and connecting the p-type semiconductor layer and the metal layer are electrically connected, and in a projected plane obtained by vertically projecting the current narrowing layer including the intermediate electrode with respect to the upper surface electrode, the opening part encloses the intermediate electrode, and The dielectric layer includes the upper surface electrode, the thickness of the p-type semiconductor layer is not less than 0.5 μm and not more than 2.8 μm, and the light reflection surface is covered with the active layer via the dielectric layer. In at least a part of the side surface of the layer, the shortest distance between the outer periphery of the active layer and the outermost periphery of the main light emitting region in the active layer is 30 μm or more, The outermost periphery of the main light emitting region is defined by the outermost periphery of a projected volume obtained by vertically projecting the intermediate electrode with respect to the active layer. The point light source type light emitting diode according to claim 1, wherein the opening and the intermediate electrode are disposed at positions where respective centers of gravity of the opening and the intermediate electrode coincide with each other on the projection plane. The point light source type light emitting diode according to claim 1 or claim 2, wherein the shortest separation distance is more than 60 μm. A method for manufacturing a point light source type light-emitting diode, characterized in that it includes: a first step, forming a semiconductor laminate sequentially comprising an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on a growth substrate; a second step, Forming a current narrowing layer on the p-type semiconductor layer; the third step, forming a metal reflective layer on the current narrowing layer; the fourth step, making the support substrate with the metal bonding layer on the surface pass through the metal bonding layer bonding with the metal reflective layer, and simultaneously forming a metal layer including a light reflective surface; the fifth step, removing the growth substrate; and the sixth step, removing the growth substrate in the n-type semiconductor layer forming an upper surface electrode having an opening through which light emitted from the active layer exits, and in the second step, forming the current narrowing layer including a dielectric layer and an intermediate electrode , the dielectric layer includes through holes, and the intermediate electrode is disposed on the The p-type semiconductor layer and the metal layer are electrically connected through the hole, and in a projected plane obtained by vertically projecting the current narrowing layer including the intermediate electrode with respect to the upper surface electrode, the The opening includes the intermediate electrode, the dielectric layer includes the top electrode, the p-type semiconductor layer has a film thickness of 0.5 μm to 2.8 μm, and the light reflection surface Covering at least a part of the side surface of the active layer through the dielectric layer, the shortest distance between the outer periphery of the active layer and the outermost periphery of the main light emitting region in the active layer is 30 μm or more, the The outermost periphery of the main light emitting region is defined by the outermost periphery of a projected volume obtained by vertically projecting the intermediate electrode with respect to the active layer.

Images