TWI789804B - Package structure and manufacturing method thereof - Google Patents

Abstract

A packaging structure including a first die, an encapsulant, a circuit structure, a second die, a third die, and a filler is provided. The encapsulant covers the first die. The circuit structure is disposed on the encapsulant. The second die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die is disposed on the circuit structure and is electrically connected to the circuit structure. The third die has an optical signal transmission area. The filler is disposed between the second die and the circuit structure and between the third die and the circuit structure. The upper surface of the circuit structure has a groove. The upper surface includes a first area and a second area located on opposite sides of the groove. The filler directly contacts the first area. The filler is far away from the second area.

Description

Package structure and manufacturing method thereof

The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a packaging structure with grooves on a redistribution circuit structure and a manufacturing method thereof.

With the increase of data volume and/or the demand of data center, the demand of silicon photonics integrated circuit (silicon photonics integrated circuit) is gradually increasing. Therefore, how to improve the quality or applicability of the packaging structure with silicon photonic integrated circuits has become an urgent problem to be solved.

The invention provides a packaging structure and a manufacturing method thereof, which can have better quality.

The packaging structure of the present invention includes a first chip, a molding body, a redistribution circuit structure, a second chip, a third chip and a filling body. The first wafer includes a silicon substrate and a through-silicon conductor penetrating through the silicon substrate. The molding body covers the first chip. The redistribution circuit structure is located on the molding body. The second chip is configured on the redistribution circuit structure and electrically connected to the redistribution circuit structure. The third chip is configured on the redistribution circuit structure and is electrically connected to the redistribution circuit structure. The third chip has an optical signal transmission area. The filler is located between the second chip and the redistribution circuit structure and between the third chip and the redistribution circuit structure. The upper surface of the redistribution circuit structure has grooves. The upper surface includes a first region and a second region located on opposite sides of the trench. The filler directly contacts the first zone. The filling body is remote from the second zone.

The manufacturing method of the packaging structure of the present invention includes the following steps: providing a preliminary structure, which includes a first chip, a molding body and a redistribution circuit structure, the first chip includes a silicon substrate and a through-silicon conductor penetrating through the silicon substrate, and molding The body covers the first chip, the redistribution circuit structure is located on the molding body and is electrically connected to the first chip, wherein the upper surface of the redistribution circuit structure has a groove, and the upper surface includes first regions located on opposite sides of the groove and the second area; arrange the second chip on the preliminary structure and electrically connect to the redistribution circuit structure; arrange the third chip on the preliminary structure and electrically connect to the redistribution circuit structure, wherein the third chip has an optical signal transmission area and forming filling bodies between the second wafer and the redistribution wiring structure and between the third wafer and the redistribution wiring structure, wherein the filling body directly contacts the first area, and the filling body is away from the second area.

Based on the above, the manufacturing method of the packaging structure of the present invention can make the packaging structure have better quality, and/or the packaging structure of the present invention can have better quality.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Unless expressly stated otherwise, directional terms (eg, up, down, left, right, front, back, top, bottom) used herein are used by way of reference only and are not intended to imply absolute orientation.

Any method described herein is in no way intended to be construed as requiring performance of its steps in a particular order, unless expressly stated otherwise.

The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or magnitude of layers or regions in the drawings may be exaggerated for clarity. The same or similar reference numbers indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

For clarity, some film layers or components are omitted in the drawings, and/or another part of film layers or components are shown in perspective.

1A to 1F are partial cross-sectional schematic diagrams of a partial manufacturing method of a packaging structure according to a first embodiment of the present invention. FIG. 1G is a schematic partial top view of a packaging structure according to the first embodiment of the present invention. FIG. 1F may be an enlarged schematic view of region R1 in FIG. 1E . FIG. 1G may be a schematic top view of FIG. 1E .

Referring to FIG. 1A , the first chip 110 is disposed on the carrier 91 . The present invention has no special limitation on the carrier 91 , as long as the carrier 91 is suitable for supporting the film layer formed thereon or the components arranged thereon.

In one embodiment, the carrier board 91 may have a release layer 92 , but the invention is not limited thereto. The release layer 92 is, for example, a light to heat conversion (LTHC) adhesive layer or other similar release layers 92 , and the invention is not limited thereto.

In this embodiment, the first chip 110 may include a silicon substrate 111 , a plurality of die pads 112 , a chip insulating layer 113 and a through-silicon conductor 114 . One side of the silicon substrate 111 has a device region (not shown), and the surface on which the device region is located may be referred to as the first active surface 110a. The surface opposite to the first active surface 110a may be referred to as a first back surface 110b. The die attach pad 112 may be located on the first active surface 110a. The die insulation layer 113 may cover the die connection pad 112 , and the die insulation layer 113 exposes a part of the die connection pad 112 . In the chip design, the components in the device area (such as: the components in the device area of the first chip 110) can be electrically connected to the corresponding back end metal interconnects (Back End of Line Interconnect; BEOL Interconnect). Die connection pads (eg, part of the die connection pads 112 of the first die 110 ). The through-silicon conductor 114 can penetrate through the silicon substrate 111 , and the through-silicon conductor 114 can be electrically connected to a corresponding die connection pad (eg, a part of the die connection pad 112 of the first chip 110 ). The electronic components located at opposite ends of the first chip 110 can be electrically connected through the through-silicon conductor 114 of the first chip 110 . In one embodiment, the first chip 110 may be called a through silicon via die (TSV die), but the invention is not limited thereto.

In this embodiment, the first active surface 110 a of the first chip 110 may have a plurality of metal bumps 115 . In subsequent steps, the metal bumps 115 may reduce damage to the first active surface 110 a of the first chip 110 .

In this embodiment, the first wafer 110 may have a circuit structure 116 on the first back surface 110b. The circuit structure 116 may include an insulating layer 116a and a conductive layer 116b. Corresponding lines in the conductive layer 116 b can be electrically connected to corresponding through-silicon conductors 114 .

Referring to FIG. 1A to FIG. 1B , the molding body 140 is formed on the carrier board 91 . The molding body 140 may cover the first wafer 110 .

In one embodiment, a molding material (not shown) may be formed on the carrier 91 . Moreover, after the molding material is solidified, a planarization process may be performed to form the molding body 140 . The planarization process can be, for example, grinding (grinding), polishing (polishing) or other suitable planarization steps. The molding body 140 may expose the upper surface 115 a of the metal bump 115 of the first chip 110 . That is, the molding surface 140 a of the molding body 140 may be coplanar with the upper surface 115 a of the metal bump 115 of the first chip 110 .

In one embodiment, since the first active surface 110a of the first wafer 110 has metal bumps 115, the possibility of damage to the first active surface 110a of the first wafer 110 can be reduced during the aforementioned planarization step. .

Referring to FIG. 1B to FIG. 1C , the redistribution wiring structure 150 is formed on the molding surface 140 a of the molding body 140 . The redistribution wiring structure 150 can be formed by commonly used semiconductor processes (such as: coating process, deposition process, lithography process and/or etching process), so it will not be described in detail here. In addition, the present invention does not limit the number of film layers and the layout design of the circuit in the redistribution circuit structure 150 . For example, in the diagram shown in FIG. 1D , the redistribution wiring structure 150 may include three insulating layers 151 , 153 , 155 and three conductive layers 152 , 154 , 156 .

In one embodiment, the material of the insulating layer 151, the insulating layer 153 and/or the insulating layer 155 may include an organic insulating material (such as polyimide (PI), but not limited thereto), but the present invention is not limited thereto. .

The upper surface 150 a of the redistribution wiring structure 150 (ie, the outer surface farthest from the molding surface 140 a ) has a groove G1 . The trench G1 at least penetrates the top insulating layer 155 . The trench G1 may expose the insulating layer 153 located below the top insulating layer 155 (for example: refer to the bottom of the drawing) and directly contacting the top insulating layer 155 .

In one embodiment, the trench G1 does not expose any conductive layer in the redistribution circuit structure 150 (because there is none, so it is not shown or marked), but the invention is not limited thereto.

In one embodiment, the formation method of the trench G1 of the redistribution wiring structure 150 is as follows. The insulating material can be formed on the insulating layer 153 by coating. The aforementioned insulating material includes, for example, materials that can be cured by light or by heat. Then, a portion of the insulating material coated on the insulating layer 153 may be cured. Then, the uncured insulating material is removed to form the insulating layer 155 . The insulating layer 155 has a groove G1 exposing a portion of the insulating layer 153 and an opening exposing a portion of the conductive layer 154 . Then, a conductive layer 156 is formed on the insulating layer 155 . Part of the conductive layer 156 can fill the opening of the insulating layer 155 to connect (including: electrically connect or directly connect) the conductive layer 154 .

Referring to FIG. 1C to FIG. 1D , after the redistribution wiring structure 150 is formed, the carrier 91 may be removed and/or a cutting step may be performed to form a plurality of preliminary structures 101 . The cutting step is, for example, cutting with a rotating blade or a laser beam, but the invention is not limited thereto. It should be noted that the order of removing the carrier board 91 and performing the cutting steps is not limited in the present invention.

It is worth noting that after the dicing step is performed, similar reference numerals will be used for the preliminary structure 101 after the dicing step. For example, a plurality of first wafers 110 (as shown in FIG. 1C ) can be a plurality of first wafers 110 (as shown in FIG. 1D ) after dicing, and the molded body 140 (as shown in FIG. 1C ) is cut It can be multiple molding bodies 140 (as shown in FIG. 1D ), and the redistribution circuit structure 150 (as shown in FIG. 1C ) can be multiple redistribution circuit structures 150 (as shown in FIG. 1D ) after cutting. The groove G1 (as shown in FIG. 1C ) after cutting may be a plurality of grooves G1 (as shown in FIG. 1D ), and so on. Components in other preliminary structures 101 will follow the same component notation rules as above, and will not be repeated or specifically shown here.

Referring to FIG. 1D to FIG. 1E , the second chip 120 can be disposed on the preliminary structure 101 and electrically connected to the redistribution circuit structure 150 . The second wafer 120 has a second active surface 120a. The second chip 120 is disposed on the redistribution wiring structure 150 with its second active surface 120 a facing the redistribution wiring structure 150 .

In one embodiment, the second chip 120 may include a control chip, but the invention is not limited thereto.

In one embodiment, the second chip 120 and the redistribution wiring structure 150 can be electrically connected by the second chip connector 125 . The second chip connector 125 is, for example, a solder ball, a conductive post or other suitable conductive connectors, and the present invention is not limited thereto.

Referring to FIG. 1D to FIG. 1E , the third chip 130 is disposed on the preliminary structure 101 and electrically connected to the redistribution circuit structure 150 . The third wafer 130 has a third active surface 130a. The third chip 130 is disposed on the redistribution wiring structure 150 with the third active surface 130 a facing the redistribution wiring structure 150 .

The third chip 130 has an optical signal transmission area 131 on the third active surface 130a. The optical signal transmission area 131 can be adapted to receive or transmit optical signals. In the direction D1 perpendicular to the molding surface 140 a , the optical signal transmission area 131 does not overlap the molding body 140 . That is to say, at least a part of the third chip 130 (eg, a part having the optical signal transmission region 131 ) is overhanging. In an embodiment, the third chip 130 may be called a silicon photonics integrated circuit (silicon photonics integrated circuit), a photonic integrated circuit (photonic integrated circuit; PIC) or an optical integrated circuit (integrated optical circuit), but this The invention is not limited thereto.

It should be noted that in FIG. 1E , the optical signal transmission area 131 is only shown as an example. The shape, film layer or material of the optical signal transmission region 131 can be adjusted according to its requirements, and the present invention is not limited thereto.

In one embodiment, the third chip 130 and the redistribution circuit structure 150 can be electrically connected by the third chip connector 135 . The third chip connector 135 is, for example, a solder ball, a conductive post or other suitable conductive connectors, and the present invention is not limited thereto.

It should be noted that the order of disposing the second chip 120 and the third chip 130 is not limited in the present invention.

Please continue to refer to FIG. 1F , the filling body 160 is formed on the redistribution wiring structure 150 . And, after disposing the second wafer 120 and the third wafer 130 on the preliminary structure 101 and forming the filling body 160, the filling body 160 is at least located between the third wafer 130 and the redistribution wiring structure 150; Between the two chips 120 and the redistribution circuit structure 150 . The filling body 160 is, for example, capillary underfill (CUF) or other suitable filling materials, but the invention is not limited thereto.

In this embodiment, the third chip 130 may be disposed on the preliminary structure 101 first, and then the filling body 160 is formed between the third chip 130 and the redistribution wiring structure 150 . For example, after disposing the third wafer 130 on the preliminary structure 101, the side 130c of the third wafer 130 ( Or, further from a side 120c of the second wafer 120; for example: from between the second wafer 120 and the third wafer 130, or, from the second wafer 120 away from the third wafer 130) inject suitable filling The material is on the upper surface 150 a of the redistribution wiring structure 150 , wherein the side surface 130 c of the third chip 130 is opposite to the optical signal transmission region 131 of the third chip 130 . The uncured filling material can be filled between the third chip 130 and the redistribution wiring structure 150 from the side surface 130c of the third chip 130, and further flows toward the groove G1. The filling speed and/or filling amount of the filling material can be controlled in a suitable way. Moreover, by redistribution of the trench G1 of the circuit structure 150 , the aforementioned filling material can be prevented from covering the optical signal transmission region 131 of the third chip 130 . Afterwards, the filling material can be cured in a suitable way to form the filling body 160 .

In this embodiment, the filler 160 can also cover part of the side surface 130 c of the third wafer 130 . In this way, the bonding between the third chip 130 and the redistribution wiring structure 150 can be improved, and the possibility that the partly suspended third chip 130 is peeled off from the redistribution wiring structure 150 can be reduced.

In this embodiment, the height range 160h of the filling body 160 covering part of the side surface 130c of the third wafer 130 may be greater than half of the thickness 130h of the third wafer 130 . In this way, the bonding between the third chip 130 and the redistribution wiring structure 150 can be further improved. In one embodiment, the filling body 160 may completely cover the side surface 130 c of the third wafer 130 .

In this embodiment, the range of the filler 160 covering the third active surface 130 a of the third wafer 130 may be greater than half of the third active surface 130 a of the third wafer 130 . In this way, the bonding between the third chip 130 and the redistribution wiring structure 150 can be further improved. However, it should be noted that the filler 160 does not cover the optical signal transmission region 131 of the third chip 130 . That is to say, the filler 160 does not completely cover the third active surface 130 a of the third wafer 130 .

In one embodiment, the height range 160h of the part of the side surface 130c covered by the filler 160 of the third wafer 130 may be greater than half of the thickness 130h of the third wafer 130, and the filler 160 covers the third active surface 130a of the third wafer 130. The range may be greater than half of the third active surface 130 a of the third wafer 130 .

In this embodiment, part of the filling body 160 may be located between the second wafer 120 and the third wafer 130 .

In an embodiment, the filler 160 may further cover part of the side surface 120c and/or part of the side surface 120d of the second wafer 120 . The side 120c of the second wafer 120 is away from the third wafer 130 . The side surface 120d of the second wafer 120 is close to the third wafer 130 .

In one embodiment, conductive terminals (not shown) may also be formed on the circuit structure 116 of the first chip 110 and electrically connected to corresponding circuits in the circuit structure 116 , but the invention is not limited thereto. The conductive terminals can be formed before or after the cutting process, and the invention is not limited thereto.

After the above process, the fabrication of the packaging structure 100 of this embodiment can be substantially completed.

Referring to FIG. 1E to FIG. 1G , the packaging structure 100 includes a first chip 110 , a second chip 120 , a third chip 130 , a molding body 140 , a redistribution circuit structure 150 and a filling body 160 . The first chip 110 includes a silicon substrate 111 and a through-silicon conductor 114 penetrating through the silicon substrate 111 . The molding body 140 covers the first chip 110 . The redistribution wiring structure 150 is located on the molding body 140 . The second chip 120 is disposed on the redistribution wiring structure 150 and is electrically connected to the redistribution wiring structure 150 . The third chip 130 is disposed on the redistribution wiring structure 150 and is electrically connected to the redistribution wiring structure 150 . The filler 160 is located between the second chip 120 and the redistribution wiring structure 150 and between the third chip 130 and the redistribution wiring structure 150 . The upper surface 150 a of the redistribution wiring structure 150 has a groove G1 . The upper surface 150a includes a first region 150a1 and a second region 150a2 located on opposite sides of the trench G1. The filling body 160 directly contacts the first region 150a1. The filling body 160 is far away from the second region 150a2.

In one embodiment, the first chip 110 may be, for example, an electrical integrated circuit (Electrical Integrated Circuit; EIC), an application-specific integrated circuit (Application-Specific Integrated Circuit; ASIC), a control chip or a chip including other suitable components, But the present invention is not limited thereto.

In this embodiment, the first chip 110 can perform signal and/or power transmission through its corresponding through-silicon conductor 114 , but the invention is not limited thereto.

In this embodiment, the second chip 120 can carry out signals and/or through the corresponding second chip connector 125, the corresponding circuit in the redistribution circuit structure 150, and the corresponding through-silicon conductor 114 in the first chip 110. or power transmission; and/or the second chip 120 can perform signal and/or power transmission with the first chip 110 through the corresponding second chip connector 125, the corresponding circuit in the redistribution circuit structure 150, but the present invention is not limited to this.

In this embodiment, the third chip 130 can carry out signals and/or through the corresponding third chip connector 135, the corresponding circuit in the redistribution circuit structure 150, and the corresponding through-silicon conductor 114 in the first chip 110. or power transmission; and/or the third chip 130 can perform signal and/or power transmission with the first chip 110 through the corresponding third chip connector 135, the corresponding circuit in the redistribution circuit structure 150, but the present invention is not limited to this.

In this embodiment, the second chip 120 and the third chip 130 can be connected to each other through the corresponding second chip connector 125, the corresponding circuit in the redistribution wiring structure 150 and the third chip connector 135 to carry out signals and/or power delivery.

In this embodiment, the second chip 120 and the third chip 130 may be arranged side by side. For example, the side 120d of the second chip 120 and the side 130c of the third chip 130 face each other.

In this embodiment, the groove G1 may be strip-shaped, but the invention is not limited thereto. The sidewall of the trench G1 may be a slope. In the extending direction D2 of the trench G1 , the dimension G1w of the trench G1 is greater than the dimension 130w of the third chip 130 . In one embodiment, the dimension G1w of the groove G1 may be smaller than the dimension 140w of the molding body 140 and/or the overall dimension 150w of the redistribution wiring structure 150 .

In this embodiment, the filling body 160 can also be filled into the groove G1. That is to say, the filling body 160 may directly contact the first region 150a1 and the trench G1, but not contact the second region 150a2. In this way, the filling body 160 between the third chip 130 and the redistribution wiring structure 150 can use the groove G1 as a boundary, preventing the filling body 160 from overflowing the edge of the redistribution wiring structure 150 and possibly further covering the optical signal transmission area 131. In this way, the packaging structure 100 can have better quality or yield.

In one embodiment, the filling body 160 may not fill or partially fill the trench G1, and the filling body 160 does not contact the second region 150a2.

In this embodiment, viewed in the direction D1 perpendicular to the molding surface 140a (as shown in FIG. 1G ), there is a groove between any point on the optical signal transmission region 131 and any point on the filling body 160 Slot G1. That is to say, when manufacturing the package structure 100 , the groove G1 can be used to ensure that the filler 160 does not cover the optical signal transmission region 131 of the third chip 130 .

In an embodiment, the package structure 100 may optionally further include conductive terminals (not shown). The conductive terminals can be disposed on the circuit structure 116 of the first chip 110 , so that the corresponding through-silicon conductors 114 in the first chip 110 can be electrically connected with external conductive elements through the conductive terminals.

It should be noted that in this embodiment, only one first chip 110, one second chip 120 and one third chip 130 are shown in the package structure 100 as an example, but the present invention is applicable to the configuration of the package structure 100 The numbers of the first chip 110 , the second chip 120 and the third chip 130 are not limited, and can be adjusted according to design requirements.

In this embodiment, the number of the grooves G1 may be the same as the number of the third wafer 130 , but the invention is not limited thereto.

In an exemplary application mode, the light guide element (such as: optical fiber, but not limited to) can be contacted (such as: in a direct contact manner; or, in an indirect contact manner through optical glue; or, a partial direct contact and part of the indirect contact) the optical signal transmission area 131 of the third chip 130 of the packaging structure 100, so that the third chip 130 can receive or transmit corresponding optical signals through the aforementioned light guide element. Therefore, through the arrangement of the filling body 160 (such as: making the filling body 160 have the above-mentioned manner of covering the third chip 130), when the light guide element contacts the optical signal transmission region 131 of the third chip 130 of the packaging structure 100, The possibility of delamination of the third wafer 130 from the redistribution wiring structure 150 is reduced. In addition, by redistribution of the trench G1 of the circuit structure 150 , the aforementioned filling material can be prevented from covering the optical signal transmission region 131 of the third chip 130 . In this way, the package structure 100 can have better quality.

FIG. 2 is a partial top view of a packaging structure according to a second embodiment of the present invention. The packaging structure 200 of this embodiment and its manufacturing method are similar to the packaging structure 100 and its manufacturing method of the first embodiment, and its similar components are denoted by the same reference numerals, and have similar functions, materials or formation methods, and descriptions are omitted .

Please refer to FIG. 2 , in this embodiment, the groove G2 is annular.

In this embodiment, viewed in the direction D1 perpendicular to the molding surface 140 a , the groove G2 may surround the third die connection member 135 .

In this embodiment, viewed from the direction D1 perpendicular to the molding surface 140a, the range of the filler 160 may be smaller than or equal to the range surrounded by the groove G2.

3A to 3C are partial cross-sectional schematic diagrams of a partial manufacturing method of a packaging structure according to a third embodiment of the present invention. The packaging structure 300 of this embodiment and its manufacturing method are similar to the packaging structure 100 and its manufacturing method of the first embodiment, and its similar components are denoted by the same reference numerals, and have similar functions, materials or formation methods, and descriptions are omitted . For example, FIG. 3A shows a partial cross-sectional schematic diagram of the manufacturing method of the packaging structure following the steps of FIG. 1B . The region shown in FIG. 3C may be similar to the region R1 in FIG. 1E .

In this embodiment, the formation method of the redistribution wiring structure 350 (shown in FIG. 3C ) having the groove G3 is as follows.

Referring to FIG. 3A , an insulating material can be formed on the insulating layer 151 by coating. The aforementioned insulating material includes, for example, materials that can be cured by light or by heat. Then, a portion of the insulating material coated on the insulating layer 151 may be cured. Then, the uncured insulating material is removed to form the insulating layer 353 . The insulation layer 353 has an opening OP1 exposing a portion of the insulation layer 151 and an opening OP1 exposing a portion of the conductive layer 152 . Then, a conductive layer 154 is formed on the insulating layer 353 . Part of the conductive layer 154 can fill the opening of the insulating layer 353 to connect (including: electrically connect or directly connect) the conductive layer 152 . Then, an insulating material 359 can be formed on the insulating layer 353 by coating. The insulating material 359 may fill the opening OP1 of the insulating layer 353 . The insulating material 359 includes, for example, a material that can be cured by light or by heat.

Referring to FIGS. 3A-3B , part of the insulating material 359 may be cured. Then, the uncured insulating material 359 is removed to form the insulating layer 355 . The insulation layer 355 has an opening OP2 corresponding to the opening OP1 and an opening exposing a portion of the conductive layer 154 . The opening area of the opening OP2 may be larger than the opening area of the opening OP1, and the opening range of the opening OP1 may be within the opening range of the opening OP2 in the direction D1 perpendicular to the molding surface 140a.

Please continue to refer to FIG. 3B , a conductive layer 156 is formed on the insulating layer 355 . Part of the conductive layer 156 can fill the opening of the insulating layer 355 to connect (including: electrically connect or directly connect) the conductive layer 154 .

Please continue to refer to FIG. 3B , the fabrication of the redistribution circuit structure 350 of this embodiment can be substantially completed after the above-mentioned manufacturing process. The trench G3 of the redistribution wiring structure 350 may be at least formed by the opening OP1 of the insulating layer 353 and the opening OP2 of the insulating layer 355 .

Please refer to FIG. 3B to FIG. 3C , after that, the manufacturing of the packaging structure 300 of this embodiment can be substantially completed by the same or similar steps as those shown in FIG. 1D to FIG. 1E .

It should be understood that FIG. 3C is an enlarged schematic view similar to the region R1 in FIG. 1E . Therefore, although some components or some film layers are not shown in FIG. 3C , there may be the same or similar components or film layers as shown in FIG. 1E in other unshown places.

Please refer to FIG. 3C, the packaging structure 300 includes a first chip 110, a second chip (not directly shown, it can be the second chip 120 of the previous embodiment), a third chip (not directly shown, it can be the same as the previous embodiment The third chip 130 ), the molding body 140 , the redistribution circuit structure 350 and the filling body 160 . The redistribution wiring structure 350 is located on the molding body 140 . The second chip is disposed on the redistribution wiring structure 350 and is electrically connected to the redistribution wiring structure 350 . The third chip is disposed on the redistribution circuit structure 350 and is electrically connected to the redistribution circuit structure 350 . The filler 160 is located between the second chip and the redistribution wiring structure 350 and between the third chip and the redistribution wiring structure 350 . The upper surface 350a of the redistribution wiring structure 350 has a groove G3. The upper surface 350a includes a first region 350a1 and a second region 350a2 located on opposite sides of the trench G3. The filling body 160 directly contacts the first region 350a1. The filling body 160 is far away from the second region 350a2.

In this embodiment, the sidewall of the trench G3 may have a stepped structure.

In this embodiment, the groove G3 of the packaging structure 300 may be strip-shaped (as shown in FIG. 1G ), but the invention is not limited thereto. In an embodiment, the trenches similar to the trench G3 (eg, trenches with sidewalls in a stepped structure) may be annular (as shown in FIG. 2 ).

4A to 4C are partial cross-sectional schematic diagrams of a partial manufacturing method of a packaging structure according to a fourth embodiment of the present invention. The packaging structure 400 of this embodiment and its manufacturing method are similar to the packaging structure 100 and its manufacturing method of the first embodiment, and its similar components are denoted by the same reference numerals, and have similar functions, materials or formation methods, and descriptions are omitted . For example, FIG. 4A shows a partial cross-sectional schematic diagram of the manufacturing method of the packaging structure following the steps of FIG. 1B . The region shown in FIG. 4C may be similar to the region R1 in FIG. 1E .

In this embodiment, the formation method of the redistribution wiring structure 450 (marked in FIG. 4C ) having the groove G4 is as follows.

Referring to FIG. 4A, the conductive layer 152 may include dummy pads dp. Then, the insulating layer 453 , the conductive layer 154 and the insulating layer 455 may be formed on the insulating layer 151 by means of deposition, lithography and/or etching processes.

In one embodiment, the material of the insulating layer 453 and/or the material of the insulating layer 455 may include silicon oxide, silicon nitride, silicon oxynitride or the above-mentioned combination, but the present invention is not limited thereto. In a possible embodiment, the material of the insulating layer 453 and/or the material of the insulating layer 455 may include polyimide (Polyimide; PI), polybenzoxazole (polybenzoxazole; PBO), benzocyclobutene ( benzocyclobutene; BCB), other suitable polymers or a combination of the above.

In one embodiment, the material of the insulating layer 453 and the material of the insulating layer 455 may be the same or similar, but the invention is not limited thereto.

Referring to FIGS. 4A-4B , an opening exposing a portion of the conductive layer 154 and the groove G4 may be formed by etching. The groove G4 may correspond to the dummy pad dp. In one embodiment, the dummy pad dp may be called an etching stop layer, but the invention is not limited thereto. Then, a conductive layer 156 is formed on the insulating layer 455 . Part of the conductive layer 156 can fill the opening of the insulating layer 455 to connect (including: electrically connect or directly connect) the conductive layer 154 .

In this embodiment, the dummy pad dp is a part of the conductive layer 152 , but the invention is not limited thereto. In one embodiment, the dummy pad dp may be a part of any conductive layer in the redistribution wiring structure 450 except the top conductive layer (eg, the conductive layer 156 ).

Please refer to FIG. 4B , the fabrication of the redistribution circuit structure 450 of this embodiment can be substantially completed after the above-mentioned manufacturing process. The groove G4 of the redistribution wiring structure 450 may be located on the dummy pad dp.

Please refer to FIG. 4B to FIG. 4C , and then, the manufacturing of the package structure 400 of this embodiment can be substantially completed through the same or similar steps shown in FIG. 1D to FIG. 1E .

It should be understood that FIG. 4C is an enlarged schematic view similar to the region R1 in FIG. 1E . Therefore, although some components or some film layers are not shown in FIG. 4C , there may be the same or similar components or film layers as shown in FIG. 1F in other unshown places.

Please refer to FIG. 4C, the packaging structure 400 includes a first chip 110, a second chip (not directly shown, may be the second chip 120 of the previous embodiment), a third chip (not directly shown, may be the same as the previous embodiment The third chip 130 ), the molding body 140 , the redistribution wiring structure 450 and the filling body 160 . The redistribution wiring structure 450 is located on the molding body 140 . The second chip is disposed on the redistribution wiring structure 450 and is electrically connected to the redistribution wiring structure 450 . The third chip is disposed on the redistribution wiring structure 450 and is electrically connected to the redistribution wiring structure 450 . The filler 160 is located between the second chip and the redistribution wiring structure 450 and between the third chip and the redistribution wiring structure 450 . The upper surface 450a of the redistribution wiring structure 450 has a groove G4. The upper surface 450a includes a first region 450a1 and a second region 450a2 located on opposite sides of the trench G4. The filling body 160 directly contacts the first region 450a1. The filling body 160 is far away from the second region 450a2.

In this embodiment, the groove G4 of the packaging structure 400 may be strip-shaped (as shown in FIG. 1G ), but the invention is not limited thereto. In an embodiment, a trench similar to the trench G4 (eg, a trench penetrating through a plurality of insulating layers and having sloped sidewalls) may be annular (as shown in FIG. 2 ).

In summary, the manufacturing method of the packaging structure of the present invention can make the packaging structure have better quality, and/or the packaging structure of the present invention can have better quality.

100, 200, 300, 400: package structure 101: Preliminary Structure 110: First Wafer 110a: the first active surface 110b: first back 111: Silicon substrate 112: chip connection pad 113: Wafer insulating layer 114: through silicon conductor 115: metal bump 115a: upper surface 116: Line structure 116a: insulating layer 116b: conductive layer 120: second chip 120a: the second active surface 120c, 120d: side 125: the second chip connector 130: The third chip 130a: the third active surface 130c: side 130h: Thickness 130w: size 131: Optical signal transmission area 135: the third chip connector 140: molding body 140a: molding surface 140w: size 150, 350, 450: Redistribute the circuit structure 151, 153, 155, 353, 355, 453, 455: insulating layer 152, 154, 156: conductive layer 150a: upper surface 150a1: District 1 150a2: Second District 150w: size 359: insulating material 160: filling body 160h: altitude range 91: carrier board 92: release layer D1, D2: direction G1, G2, G3, G4: Groove G1w: size OP1, OP2: opening R1: Region dp: dummy pad

1A to 1F are partial cross-sectional schematic diagrams of a partial manufacturing method of a packaging structure according to a first embodiment of the present invention. FIG. 1G is a schematic partial top view of a packaging structure according to the first embodiment of the present invention. FIG. 2 is a partial top view of a packaging structure according to a second embodiment of the present invention. 3A to 3C are partial cross-sectional schematic diagrams of a partial manufacturing method of a packaging structure according to a third embodiment of the present invention. 4A to 4C are partial cross-sectional schematic diagrams of a partial manufacturing method of a packaging structure according to a fourth embodiment of the present invention.

100: Package structure

101: Preliminary Structure

110: First Wafer

116: Line structure

116a: insulating layer

116b: conductive layer

120: second chip

120a: the second active surface

120c, 120d: side

125: the second chip connector

130: The third chip

130a: the third active surface

130c: side

130h: Thickness

131: Optical signal transmission area

135: the third chip connector

140: molding body

140a: molding surface

150:Redistribute the circuit structure

150a: upper surface

160: filling body

160h: altitude range

D1: Direction

G1: Groove

R1: Region

Claims (10)

A packaging structure, comprising: a first chip, including a silicon substrate and a through-silicon conductor penetrating through the silicon substrate; a molding body covering the first chip; a redistribution circuit structure located on the molding body; a second chip configured on the redistributed circuit structure and electrically connected to the redistributed circuit structure; a third chip configured on the redistributed circuit structure and electrically connected to the redistributed circuit structure, Wherein the third chip has an optical signal transmission area; and a filler, located between the second chip and the redistribution circuit structure and between the third chip and the redistribution circuit structure, wherein: the The upper surface of the redistribution circuit structure has a groove, and the upper surface includes a first region and a second region located on opposite sides of the groove; the filling directly contacts the first region; the filling is far away from the second region; and the groove includes a stripe region, and in the extending direction of the stripe region of the groove, the size of the stripe region of the groove is larger than the The size of the third chip, and the size of the strip region of the groove is smaller than the size of the molding body. The package structure according to claim 1, wherein the redistribution wiring structure is located on the molding surface of the molding body, and in a direction perpendicular to the molding surface, the The optical signal transmission area does not overlap the molding body. The package structure according to claim 1, wherein the filling body further covers a part of side surfaces of the third chip. The package structure according to claim 1, wherein the filler further fills the trench. The package structure according to claim 1, wherein the groove is a stripe groove having only the stripe region. The package structure according to claim 1, further comprising: a plurality of third chip connectors, located between the third chip and the redistribution wiring structure, and electrically connected to the third chip and the In the redistribution circuit structure, the groove is an annular groove including the strip region, and the annular groove surrounds the plurality of third chip connectors. The package structure according to claim 1, wherein the redistribution circuit structure comprises: a top insulating layer, wherein the trench penetrates the top insulating layer; and a top conductive layer, located on the top insulating layer, and partially The top conductive layer is further embedded in the top insulating layer. The package structure according to claim 1, wherein the sidewall of the trench is a slope. The package structure according to claim 1, wherein the sidewall of the trench has a stepped structure. A method of manufacturing a packaging structure, comprising: providing a preliminary structure, the preliminary structure comprising: The first chip includes a silicon substrate and a through-silicon conductor penetrating through the silicon substrate; a molded body covering the first chip; and a redistribution wiring structure located on the molded body and electrically connected to the silicon substrate. The first wafer, wherein the upper surface of the redistributed wiring structure has a groove, and the upper surface includes a first area and a second area located on opposite sides of the groove; the second wafer is arranged on the preliminary Structurally and electrically connected to the redistributed circuit structure; disposing a third chip on the preliminary structure and electrically connected to the redistributed circuit structure, wherein the third chip has an optical signal transmission area, wherein the The trench includes a strip region, and in the extending direction of the strip region of the trench, the size of the strip region of the trench is larger than the size of the third wafer, and the trench The size of the strip-shaped region of the groove is smaller than the size of the molding body; and forming a filling body between the second chip and the redistribution circuit structure and the third chip and the redistribution circuit structure Between, wherein the filling body directly contacts the first area, and the filling body is away from the second area.

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