TWI789582B - Memory device - Google Patents

Abstract

Provided is a memory device including a substrate, a stack structure, a first set of vertical channel structures, a second set of vertical channel structures, and a first slit. The stack structure is disposed on the substrate. The first and second sets of vertical channel structures are arranged along a Y direction and penetrate through the stack structure to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure to expose the substrate. The first slit includes a plurality of first sub-slits discretely disposed along a X direction.

Description

memory element

The present invention relates to a memory element.

As technology advances with each passing day, advances in electronic components have increased the need for greater storage capacity. In order to meet the demand of high storage density (high storage density), the size of memory components has become smaller and more densely packed. Therefore, the type of memory device has developed from a planar gate (2D memory device) structure to a 3D memory device (3D memory device) with a vertical channel (vertical channel, VC) structure. device).

However, as the number of stacked layers of the composite film stack increases, the bending phenomenon of the composite film stack with high aspect ratio becomes more and more serious. Severe bending can even cause a short circuit between the bit line and the top word line, thereby affecting the operation of the memory device. Therefore, how to develop a high-density memory element and its manufacturing method to reduce the bending phenomenon of the composite film stack will become an important issue in the future.

The invention provides a memory element and its manufacturing method, which divides the slit between two sets of vertical channel structures into multiple sub-slits to enhance the mechanical strength of the memory element and reduce the bending phenomenon of the stacked structure of the memory element.

The invention provides a memory element, including: a base, a stack structure, a first group of vertical channel structures, a second group of vertical channel structures and a first slit. The stack structure is configured on the base. The first group of vertical channel structures and the second group of vertical channel structures are arranged along the Y direction and penetrate through the stacked structure to contact the substrate. The first slit is disposed between the first set of vertical channel structures and the second set of vertical channel structures, and runs through the stacked structures to expose the base. The first slit includes a plurality of first sub-slits which are discretely arranged along the X direction.

In an embodiment of the present invention, the above-mentioned substrate includes an array area and a stepped area, and the first group of vertical channel structures and the second group of vertical channel structures are disposed on the substrate of the array area.

In an embodiment of the present invention, the above-mentioned memory device further includes a first string of selection line cuts located between a plurality of discrete first sub-slits.

In an embodiment of the present invention, the above-mentioned first series of selection line cuts at least extend beyond the first row of contact windows in the step region.

In an embodiment of the present invention, the above-mentioned stack structure includes a plurality of conductor layers and a plurality of dielectric layers alternately stacked along the Z direction, and the topmost conductor layer is a string selection line (SSL) to control the first group of vertical The channel structure switches with the second set of vertical channel structures.

In an embodiment of the present invention, the above-mentioned memory element further includes: a second string selection line cut, embedded in the string selection line, and extending along the X direction to divide the first set of vertical channel structures into two second string selection lines. a group; and a third string selection line cut embedded in the string selection line and extending along the X direction to divide the second group of vertical channel structures into two second groups.

In an embodiment of the present invention, the above-mentioned memory element further includes two second slits respectively disposed on the first side of the first group of vertical channel structures and on the second side of the second group of vertical channel structures opposite to the first side. two sides, and through the stack structure to expose the base, wherein the two second slits respectively extend continuously from the array area to the step area along the X direction.

In an embodiment of the present invention, the length of one of the above-mentioned two second slits is greater than the sum of the lengths of the plurality of first sub-slits.

In an embodiment of the present invention, the ratio of the sum of the lengths of the plurality of first sub-slits to the length of one of the two second slits is between 0.35 and 0.9.

In an embodiment of the present invention, the above-mentioned memory element further includes: a third group of vertical channel structures and a fourth group of vertical channel structures, arranged along the Y direction with the first group of vertical channel structures and the second group of vertical channel structures , and penetrate the stack structure to contact the substrate; the third slit is configured between the second group of vertical channel structures and the third group of vertical channel structures, and penetrates the stack structure to expose the substrate, wherein the third slit includes a plurality of The third sub-slits are discretely arranged along the X direction; and the fourth slits are arranged between the third group of vertical channel structures and the fourth group of vertical channel structures, and penetrate through the stacked structure to expose the substrate, wherein the fourth The slit includes a plurality of fourth sub-slits which are discretely arranged along the X direction.

In an embodiment of the present invention, the above-mentioned memory device further includes: a fourth string selection line cut, embedded in the string selection line, and located between the plurality of third sub-slits.

The invention provides a method for manufacturing a memory element, comprising: forming a stacked layer on a substrate, wherein the stacked layer includes a plurality of first materials and a plurality of second materials stacked alternately; The string selection line extending in the direction is cut; the first group of vertical channel structures and the second group of vertical channel structures are respectively formed on both sides of the string selection line cutting, which penetrate the stacked layer to contact the substrate; and the first group of vertical channel structures and the second group of vertical channel structures A first slit is formed between two sets of vertical channel structures, wherein the first slit penetrates the stacked layer to expose the substrate, the first slit includes a plurality of sub-slits discretely arranged along the X direction, and the string selection line is cut by the second A slit is divided into a plurality of first strings of selected wire cuts, wherein the plurality of first strings of selected wire cuts are located between the plurality of sub-slits and are discretely arranged along the X direction.

In an embodiment of the present invention, the above method of manufacturing a memory device further includes: performing an etching process to remove a plurality of second materials to form a plurality of gaps between the plurality of first materials; A plurality of conductor layers are formed, so that the plurality of conductor layers surround the first group of vertical channel structures and the second group of vertical channel structures.

In an embodiment of the present invention, the formation of the string selection line cut includes: forming a second string selection line cut to divide the first group of vertical channel structures into two first groups; and forming a third string selection line cut , to divide the second set of vertical channel structures into two second groups.

In an embodiment of the present invention, the above-mentioned substrate includes an array area and a stepped area, the first set of vertical channel structures and the second set of vertical channel structures are formed on the base of the stepped area, and a plurality of first string selection lines cutting and The first slit extends from the array area to the step area.

In an embodiment of the present invention, the above-mentioned forming of the first slit includes: respectively forming Two second slits, the two second slits penetrate through the stacked layer to expose the base, wherein the two second slits respectively extend continuously from the array area to the step area along the X direction.

In an embodiment of the present invention, the formation of the first set of vertical channel structures and the second set of vertical channel structures includes: forming a plurality of sets of virtual vertical channel structures penetrating through the stacked layers of the step region to contact the base of the step region.

In an embodiment of the present invention, the above-mentioned plurality of first string selective wire cuts and the plurality of second materials have different materials or materials with different etching selectivities.

The invention provides a memory element, including: a base, a stack structure, a first group of vertical channel structures, a second group of vertical channel structures and an isolation structure. The stack structure is configured on the base. The first group of vertical channel structures and the second group of vertical channel structures are arranged along the Y direction and penetrate through the stacked structure to contact the substrate. The isolation structure is disposed between the first group of vertical channel structures and the second group of vertical channel structures. The isolation structure includes a plurality of sub-slits and a plurality of string selection line cuts arranged alternately along the X direction.

In an embodiment of the present invention, the above-mentioned memory element further includes a second slit disposed on the first side of the first group of vertical channel structures, and penetrates through the stacked structure to expose the substrate, wherein the second slit is along the X direction extending continuously, and the length of the second slit is greater than the sum of the lengths of the multiple sub-slits.

Based on the above, the embodiment of the present invention replaces the continuously extending first slits with a plurality of first sub-slits discretely arranged along the X direction. In the case of a high aspect ratio stack structure, the first string of selective wire cuts between the first sub-slits and the partial stack structure can strengthen the mechanical strength of the entire memory device to withstand a series of processes (such as wet etching process , film deposition process and thermal process, etc.) to reduce the bending phenomenon of the stacked structure, thereby improving the yield and reliability of the memory device. In addition, the first sub-slit and the first series of selection line cuts therebetween can be regarded as an isolation structure to electrically separate the first group of vertical channel structures from the second group of vertical channel structures, thereby increasing the flexibility of the operation of the memory device.

The present invention will be described more fully with reference to the drawings of this embodiment. However, the present invention can also be embodied in various forms and should not be limited to the embodiments herein. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. The same or similar symbols indicate the same or similar elements, and the following paragraphs will not repeat them one by one.

FIG. 1 is a schematic top view of a memory device according to a first embodiment of the present invention. The memory element described in the following embodiments may be a NAND flash memory, but the present invention is not limited thereto. In other embodiments, the memory element may also be a Negative OR (NOR) flash memory, a Read Only (ROM) memory or other three-dimensional memory.

Please refer to FIG. 1, the memory element 1 of the first embodiment of the present invention includes: a substrate 100, a stack structure 202, a first set of vertical channel structures VC1, a second set of vertical channel structures VC2, multiple sets of dummy vertical channel structures DVC, a first The slit 12a and the second slit 12b. Specifically, the substrate 100 includes a first region R1 and a second region R2. In some embodiments, the first region R1 may be an array region having a memory array, hereinafter referred to as the array region R1. The second region R2 may be a stepped region, which has a plurality of contact windows to be electrically connected to the word lines respectively, and is referred to as the stepped region R2 hereinafter. The stack structure 202 is disposed on the substrate 100 (as shown in FIG. 2I ). The first group of vertical channel structures VC1 and the second group of vertical channel structures VC2 are disposed in the array region R1 and arranged along the Y direction. Although only two first set of vertical channel structures VC1 and two second set of vertical channel structures VC2 are shown in FIG. 1 , the present invention is not limited thereto. In other embodiments, the plurality of first set of vertical channel structures VC1 and the plurality of second set of vertical channel structures VC2 may be arranged along the Y direction. The first group of vertical channel structures VC1 and the second group of vertical channel structures VC2 include a plurality of vertical channel structures 120 . In some embodiments, the vertical channel structures 120 are arranged in the form of hexagonal closest packing to increase the density of the memory cells. The vertical channel structure 120 penetrates through the stacked structure 202 of the array region R1 to contact the substrate 100 (as shown in FIG. 2I ). In this embodiment, the vertical channel structure 120 can be electrically connected to the bit lines. On the other hand, multiple sets of dummy vertical channel structures DVC are arranged in the step region R2 and arranged along the Y direction. The multiple sets of virtual vertical channel structures DVC include a plurality of virtual vertical channel structures 220 . In some embodiments, the virtual vertical channel structures 220 are arranged in an m×n array. The dummy vertical channel structure 220 penetrates through the stacked structure 202 of the stepped region R2 to be in contact with the substrate 100 of the stepped region R2. In this embodiment, the virtual vertical channel structure 220 is electrically floating or not electrically connected to other external power sources (such as bit lines). In some embodiments, the arrangement density of the dummy vertical channel structures 220 is smaller than the arrangement density of the vertical channel structures 120 . The dummy vertical channel structure 220 can be used to support the strength of the stacked layers in the step region R2 to prevent the stacked layers from collapsing during the subsequent etching process of FIG. 2G to FIG. 2H .

In some embodiments, the first slit 12 a is disposed between the first set of vertical channel structures VC1 and the second set of vertical channel structures VC2 , and penetrates through the stack structure 202 to expose the substrate 100 (as shown in FIG. 2I ). As shown in FIG. 1 , the first slit 12 a extends from the array region R1 to the stepped region R2 along the X direction. It should be noted that the first slit 12a includes a plurality of first sub-slits 12a1, 12a2, 12a3, 12a4, 12a5, which are discretely arranged along the X direction. In addition, the memory device 1 further includes a first string of selection line cuts 105 a located between the first sub-slits 12 a 1 , 12 a 2 , 12 a 3 , 12 a 4 , and 12 a 5 . That is to say, the first sub-slits 12a1 , 12a2 , 12a3 , 12a4 , 12a5 are separated from the partial stack structure 202 by the first string selection line cut 105a in the X direction. In this case, the first series of selection line cuts 105a between the first sub-slits 12a1, 12a2, 12a3, 12a4, 12a5 and the partial stack structure 202 can strengthen the mechanical strength of the entire memory element 1, thereby reducing the mechanical strength of the memory element 1. The bending phenomenon of the stacked structure 202 . From another point of view, the first sub-slits 12a1, 12a2, 12a3, 12a4, 12a5 and the first string of selection line cuts 105a between them can be regarded as an isolation structure to separate the first group of vertical channel structures VC1 from the second Group vertical channel structure VC2. In some embodiments, the isolation structure (including the first sub-slits 12a1 , 12a2 , 12a3 , 12a4 , 12a5 and the first string of selection line cuts 105a arranged alternately along the X direction) extends from the array region R1 to the stepped region R2. In this embodiment, the first string of selection line cuts 105 a at least extends beyond the first column of contact windows (not shown) in the step region R2 .

In some embodiments, the second slits 12b are respectively arranged on the first side (for example, the upper side) of the first group of vertical channel structures VC1 and the second side (for example, the lower side) of the second group of vertical channel structures VC2 opposite to the first side. side). Specifically, the second slit 12b also penetrates the stacked structure 202 to expose the substrate 100 (as shown in FIG. 2I ). As shown in FIG. 1 , the second slit 12b extends continuously from the array region R1 to the stepped region R2 along the X direction.

In addition, the memory device 1 further includes a second string of selection line cuts 105b and a third string of selection line cuts 105c. As shown in FIG. 1 , the second string of selection line cuts 105 b extends from the array region R1 to the stepped region R2 along the X direction, so as to divide the first group of vertical channel structures VC1 into two first groups G1 . In some embodiments, each first group G1 has the same number of vertical channel structures 120 . In this embodiment, the second string of selection line cuts 105b at least extends beyond the first row of contact windows (not shown) in the stepped region R2. Similarly, the third string of selection line cuts 105c extends from the array region R1 to the stepped region R2 along the X direction, so as to divide the second group of vertical channel structures VC2 into two second groups G2. In some embodiments, each second group G2 has the same number of vertical channel structures 120 . In this embodiment, the third string of selection line cuts 105c at least extends beyond the first row of contact windows (not shown) in the stepped region R2.

In this embodiment, the first slit 12a extends discontinuously along the X direction; while the second slit 12b extends continuously along the X direction. Therefore, the length L2 of the second slit 12b is greater than the sum of the lengths L1 of the first sub-slits 12a1, 12a2, 12a3, 12a4, 12a5. In addition, the ratio of the total length L1 of the first sub-slits 12a1, 12a2, 12a3, 12a4, 12a5 to the length L2 of the second slit 12b may be between 0.35 and 0.9. Although the first sub-slits 12a1, 12a2, 12a3, 12a4, and 12a5 shown in FIG. 1 have the same length L1, the present invention is not limited thereto. In other embodiments, the first sub-slits 12a1 , 12a2 , 12a3 , 12a4 , 12a5 may also have different lengths and may be separated from each other by different distances.

2A to 2I are schematic cross-sectional views of the manufacturing process along the line A-A of FIG. 1 . FIG. 3 is a schematic cross-sectional view along the line B-B in FIG. 1 .

Referring to FIG. 2A , the manufacturing method of the memory element 10 (shown in FIG. 1 ) is as follows. First, a substrate 100 is provided. In one embodiment, the substrate 100 includes a semiconductor substrate, such as a silicon substrate.

Next, a stacked layer 102 is formed on the substrate 100 . Specifically, the stacked layer 102 includes a plurality of first materials 104 and a plurality of second materials 106 stacked on each other. In one embodiment, the first material 104 and the second material 106 may be different dielectric materials. For example, the first material 104 can be silicon oxide; the second material 106 can be silicon nitride. But the present invention is not limited thereto. In other embodiments, the first material 104 may be silicon oxide; the second material 106 may be polysilicon. In an embodiment, the number of the first material 104 and the second material 106 may be 8 layers, 16 layers, 32 layers, 64 layers, 72 layers or more.

Referring to FIG. 2B , a plurality of string selection line cuts 105 extending along the X direction are formed in the topmost second material 106t. In some embodiments, the method for forming the string selection line dicing 105 includes patterning the topmost second material 106t to form an opening; filling the opening with a dielectric material, wherein the dielectric material covers the topmost second material 106t; And a chemical mechanical polishing (CMP) process is performed to expose the topmost second material 106t. In some embodiments, the string selection wire dicing 105 has a different dielectric material than the second material 106 , such as silicon oxide, a high dielectric constant material (aluminum oxide), or a combination thereof.

Referring to FIG. 2C , a dielectric layer 108 is formed on the stacked layer 102 . In some embodiments, the material of the dielectric layer 108 includes a different dielectric material from the second material 106 , such as silicon oxide, high dielectric constant material (alumina) or a combination thereof. Next, a plurality of openings 10 are formed in the dielectric layer 108 and the stacked layer 102 . The openings 10 are located between the string selection line cuts 105 and penetrate through the stacked layers 102 , thereby exposing a portion of the substrate 100 . In one embodiment, the method for forming the opening 10 includes performing a patterning process on the dielectric layer 108 and the stacked layer 102 . In order to completely remove the bottom layer of the stacked layers 102 , part of the substrate 100 is removed during the patterning process. In this case, as shown in FIG. 2C , the bottom surface of the opening 10 may be lower than the top surface of the substrate 100 .

Referring to FIG. 2C and FIG. 2D , an epitaxial layer 110 is selectively epitaxially grown on the substrate 100 exposed in the opening 10 . In one embodiment, the material of the epitaxial layer 110 can be derived from the substrate 100 , such as epitaxial silicon. The epitaxial layer 110 can increase the conductive area to reduce the resistance value. Although the top surface of the epitaxial layer 110 shown in FIG. 2D is higher than the top surface of the substrate 100 , the present invention is not limited thereto. In other embodiments, the top surface of the epitaxial layer 110 may also be lower than or equal to the top surface of the substrate 100 .

Next, a charge storage structure 112 is formed in the opening 10 . In detail, a charge storage material (not shown) is formed on the substrate 100 . The charge storage material conformally covers the top surface of the dielectric layer 108 , the sidewalls of the stack layer 102 and the top surface of the epitaxial layer 110 . Afterwards, an etching process is performed to remove the charge storage material on the top surface of the epitaxial layer 110 and the top surface of the dielectric layer 108, so that the charge storage structure 112 is formed between the dielectric layer 108 and the stacked layers in a spacer-like form. 102 on the sidewall of the opening 10. In one embodiment, the charge storage structure 112 may be a composite layer of oxide layer/nitride layer/oxide layer (ONO). In one embodiment, the etching process includes an anisotropic etching process, such as a reactive ion etching (RIE) process.

Referring to FIG. 2E , a first channel material 116 is formed on the substrate 100 . The first channel material 116 conformally covers the top surface of the epitaxial layer 110 , the surface of the charge storage structure 112 and the top surface of the dielectric layer 108 . In one embodiment, the first channel material 116 includes a semiconductor material such as polysilicon. A method for forming the first channel material 116 is, for example, chemical vapor deposition (CVD).

Referring to FIG. 2E and FIG. 2F , a dielectric pillar 115 is formed in the opening 10 . The dielectric pillar 115 fills the opening 10 , and the top surface of the dielectric pillar 115 may be lower than the top surface of the dielectric layer 108 . That is to say, the dielectric pillar 115 does not fill the entire opening 10 . In one embodiment, the material of the dielectric pillar 115 includes spin-on dielectric (SOD). Afterwards, a second channel material 118 is formed on the dielectric pillar 115 to cover the top surface of the dielectric pillar 115 and extend to cover the top surface of the dielectric layer 108 . Next, the second channel material 118 and the first channel material 116 are patterned to form a vertical channel structure 120 . As shown in FIG. 2F , the vertical channel structure 120 includes a dielectric pillar 115 and a channel layer 114 composed of a first channel material 116 and a second channel material 118 , wherein the channel layer 114 encapsulates the dielectric pillar 115 . The charge storage structure 112 surrounds sidewalls of the vertical channel structure 120 . In one embodiment, the second channel material 118 includes a semiconductor material such as polysilicon. A method for forming the second channel material 118 is, for example, CVD.

Referring to FIG. 2F and FIG. 2G , a dielectric layer 122 is formed on the substrate 100 to cover the top surface of the dielectric layer 108 and the top surface of the vertical channel structure 120 . In one embodiment, the dielectric layer 122 includes but not limited to silicon oxide, and its formation method is, for example, CVD. After forming the dielectric layer 122 , a slit 12 is formed in the stacked layer 102 between two adjacent vertical channel structures 120 . The slit 12 penetrates through the dielectric layers 122 , 108 and the stacked layer 102 , and exposes a portion of the substrate 100 . In order to completely remove the lowest layer of the stacked layers 102 , part of the substrate 100 is removed when the slit 12 is formed. In this case, the bottom surface of the slit 12 may be lower than the top surface of the substrate 100 . Corresponding to the top view 1, the slit 12 includes a first slit 12a and a second slit 12b. The first slit 12a includes a plurality of first sub-slits 12a1, 12a2, 12a3, 12a4, 12a5 discretely arranged along the X direction. The first sub-slits 12 a 1 , 12 a 2 , 12 a 3 , 12 a 4 , 12 a 5 divide the string selection line cuts 105 extending continuously along the X direction into a plurality of first string selection line cuts 105 a, as shown in FIG. 1 . In some embodiments, the first sub-slits 12a1 , 12a2 , 12a3 , 12a4 , 12a5 can laterally expose the first string of selection line cuts 105a. Since part of the string selection line cut 105 has been replaced by the first slit 12a, the first string selection line cut 105a is not shown in the section of FIG. 2G. In this case, the string selection line cuts 105 shown in the cross section of FIG. 2G can be regarded as the second string selection line cuts 105b and the third string selection line cuts 105c. As shown in FIG. 1 , the second string of selection line cuts 105 b and the third string of selection line cuts 105 c continuously extend from the array region R1 to the stepped region R2 .

Referring to FIG. 2G and FIG. 2H , an etching process is performed to remove the second material 106 to form a plurality of voids 16 between the first materials 104 . The gap 16 laterally exposes a portion of the sidewall of the charge storage structure 112 . That is to say, the void 16 is defined by the first material 104 and the charge storage structure 112 . In one embodiment, the etching process may be a wet etching process. For example, when the second material 106 is silicon nitride, the etching process may use an etchant containing phosphoric acid and pour the etchant into the slit 12 to remove the second material 106 . Since the etchant has high etching selectivity for the second material 106 , the second material 106 can be completely removed, while the first material 104 and the charge storage structure 112 are not removed or only slightly removed. It should be noted that since the material of the string selection line 105 and the second material 106 have different etch selectivities, the string selection line 105 is not removed or only a small amount is removed. In this case, as shown in FIG. 2H , both the second string of selection line cuts 105 b and the third string of selection line cuts 105 c are exposed in the gap 16 .

Referring to FIG. 2H and FIG. 2I , a conductor layer 126 is formed in the gap 16 . In one embodiment, the method for forming the conductive layer 126 includes forming a conductive material (not shown) on the substrate 100 . The conductive material fills the void 16 and covers the sidewalls of the first material 104 and the sidewalls of the dielectric layers 108 , 122 . Afterwards, an etching process is performed to remove the conductive material on the sidewalls of the first material 104 and the sidewalls of the dielectric layers 108 , 122 . In order to completely remove the conductive material on the sidewalls of the first material 104 and the dielectric layers 108 , 122 , part of the conductive material in the gap 16 is removed during the etching process. In this case, as shown in FIG. 2I , the formed sidewall 126 s of the conductive layer 126 is recessed from the sidewall 104 s of the first material 104 . In one embodiment, the material of the conductive layer 126 includes metal, barrier metal, polysilicon or a combination thereof, and its formation may be by CVD or physical vapor deposition (PVD).

Referring to FIG. 2I and FIG. 3 , the memory device 1 of this embodiment includes: a substrate 100 , a stack structure 202 , a vertical channel structure 120 and a charge storage structure 112 . The stack structure 202 is disposed on the substrate 100 . The stack structure 202 includes a plurality of first materials (such as dielectric layers) 104 and a plurality of conductor layers 126 alternately stacked along the Z direction. The vertical channel structure 120 runs through the stack structure 202 . The charge storage structure 112 surrounds sidewalls of the vertical channel structure 120 . In an embodiment, the memory device 1 may be a gate-all-around (GAA) memory device. That is to say, the conductive layer 126 can be regarded as a gate or a word line, and the vertical channel structure 120 can be regarded as a current channel. In an alternative embodiment, memory element 1 may be a NAND memory element.

In some embodiments, the topmost conductive layer 126t can be used as a string select line (String Select Line, SSL). The string selection line SSL can be electrically connected with the selection transistor to control the switching of the surrounding vertical channel structure 120 . Although FIG. 2I and FIG. 3 only show one layer of string selection lines SSL, the present invention is not limited thereto. In other embodiments, both the topmost conductor layer 126t and the conductor layer 126 below it can be used as string selection lines. It is worth noting that the first string selection line cut 105a, the second string selection line cut 105b and the third string selection line cut 105c are embedded in the string selection line SSL to separate the string selection line SSL into four string selection lines. Lines SSL1, SSL2, SSL3, and SSL4, as shown in Figure 3. FIG. 3 is a schematic cross-sectional view along the line B-B in FIG. 1 . In this case, the string selection lines SSL1 , SSL2 , SSL3 , SSL4 are electrically isolated from each other. In detail, the string selection line SSL1 surrounds the vertical channel structure 120a and is used to control the switching of the vertical channel structure 120a. Similarly, the string selection line SSL2 surrounds the vertical channel structure 120b and is used to control the switching of the vertical channel structure 120b; the string selection line SSL3 surrounds the vertical channel structure 120c and is used to control the switching of the vertical channel structure 120c; and the string selection line SSL4 surrounds the vertical channel structure 120d is also used to control the switch of the vertical channel structure 120d. As shown in FIG. 1 and FIG. 3 , since the first sub-slits 12a1, 12a2, 12a3, 12a4, and 12a5 have the first string selection line cut 105a and the partial stack structure 202, it can strengthen the connection between the second slits. The mechanical strength of the entire memory element 1 further reduces the bending phenomenon of the stacked structure 202 of the memory element 1 . In addition, in some embodiments, the bottommost conductive layer 126b can be used as a ground select line (Ground Select Line, GSL) to be electrically connected to the ground transistor.

FIG. 4 is a schematic top view of a memory device according to a second embodiment of the present invention.

Referring to FIG. 4 , the memory device 2 of the second embodiment is similar to the memory device 1 of the first embodiment. The main difference between the above two is that the memory element 2 includes a third set of vertical channel structures VC3 , a fourth set of vertical channel structures VC4 , a third slit 12 c and a fourth slit 12 d. The first group of vertical channel structures VC1 , the second group of vertical channel structures VC2 , the third group of vertical channel structures VC3 and the fourth group of vertical channel structures VC4 are arranged along the Y direction. In some embodiments, the third set of vertical channel structures VC3 and the fourth set of vertical channel structures VC4 also include a plurality of vertical channel structures 120 . The vertical channel structure 120 penetrates through the stack structure 202 to be in contact with the substrate 100 .

As shown in FIG. 4 , the third slit 12 c is disposed between the second set of vertical channel structures VC2 and the third set of vertical channel structures VC3 , and penetrates through the stack structure 202 to expose the substrate 100 . The fourth slit 12 d is disposed between the third group of vertical channel structures VC3 and the fourth group of vertical channel structures VC4 , and penetrates through the stack structure 202 to expose the substrate 100 . Both the third slit 12c and the fourth slit 12d extend from the array region R1 to the stepped region R2 along the X direction. It should be noted that the third slit 12c includes a plurality of third sub-slits discretely arranged along the X direction, and the sixth string of selection line cuts 105f is located between the third sub-slits. The fourth slit 12d also includes a plurality of fourth sub-slits discretely arranged along the X direction, and the seventh string of selection line cuts 105g is located between the fourth sub-slits. In this case, the sixth string of selective wire cuts 105f between the third sub-slit and the partial stack structure 202 and the seventh string of selective wire cuts 105g and the partial stack structure 202 between the fourth sub-slit can further The mechanical strength of the entire memory element 2 is strengthened, thereby reducing the bending phenomenon of the stacked structure 202 of the memory element 2 . Although the first string of selection line cuts 105 a , the sixth string of selection line cuts 105 f , and the seventh string of selection line cuts 105 g shown in FIG. 4 correspond to each other, the present invention is not limited thereto. In other embodiments, the first string of selection line cuts 105 a , the sixth string of selection line cuts 105 f and the seventh string of selection line cuts 105 g may also be arranged in a staggered manner.

In addition, the memory device 2 further includes a fourth string of selection line cuts 105d and a fifth string of selection line cuts 105e. The fourth string of selection line cuts 105d extends along the X direction to divide the third group of vertical channel structures VC3 into two third groups G3. The fifth string of selection line cuts 105e extends along the X direction to divide the fourth group of vertical channel structures VC4 into two fourth groups G4. Each third group G3 or each fourth group G4 has the same number of vertical channel structures 120 .

To sum up, in the embodiment of the present invention, the continuously extending first slit is replaced by a plurality of first sub-slits discretely arranged along the X direction. In the case of a high aspect ratio stack structure, the first string of selective wire cuts between the first sub-slits and the partial stack structure can strengthen the mechanical strength of the entire memory device to withstand a series of processes (such as wet etching process , film deposition process and thermal process, etc.) to reduce the bending phenomenon of the stacked structure, thereby improving the yield and reliability of the memory device. In addition, the first sub-slit and the first series of selection line cuts therebetween can be regarded as an isolation structure to electrically separate the first group of vertical channel structures from the second group of vertical channel structures, thereby increasing the flexibility of the operation of the memory device.

1, 2: memory components 10: opening 12: Slit 12a: First slit 12a1, 12a2, 12a3, 12a4, 12a5: the first sub-slit 12b: Second slit 16: Gap 100: base 102:Stack layers 104: first material 104s: side wall 105: String selection wire cutting 105a: Select wire cutting for the first string 105b: The second string selects wire cutting 105c: The third string chooses wire cutting 105d: The fourth string chooses wire cutting 105e: The fifth string selects wire cutting 105f: The sixth string chooses wire cutting 106: Second material 108, 122: dielectric layer 110: epitaxial layer 112:Charge storage structure 114: Channel layer 115: Dielectric column 116: The first channel material 118:Second channel material 120, 120a, 120b, 120c, 120d: vertical channel structure 126: conductor layer 126t: the topmost conductor layer 126b: The bottom conductor layer 126s: side wall 202:Stack structure 220: Virtual vertical channel structure DVC: multi-group virtual vertical channel structure G1: The first group G2: The second group G3: The third group G4: The fourth group GSL: Ground Selection Line L1, L2: Length R1: array area R2: Ladder area SSL, SSL1, SSL2, SSL3, SSL4: string selection lines VC1: The first set of vertical channel structures VC2: The second set of vertical channel structures VC3: The third vertical channel structure VC4: The fourth vertical channel structure

FIG. 1 is a schematic top view of a memory device according to a first embodiment of the present invention. 2A to 2I are schematic cross-sectional views of the manufacturing process along the line A-A of FIG. 1 . FIG. 3 is a schematic cross-sectional view along the line B-B in FIG. 1 . FIG. 4 is a schematic top view of a memory device according to a second embodiment of the present invention.

1: memory element

12: Slit

12a: First slit

12a1, 12a2, 12a3, 12a4, 12a5: the first sub-slit

12b: Second slit

100: base

105: String selection wire cutting

105a: Select wire cutting for the first string

105b: The second string selects wire cutting

105c: The third string chooses wire cutting

120: Vertical channel structure

202:Stack structure

220: Virtual vertical channel structure

DVC: multi-group virtual vertical channel structure

G1: The first group

G2: The second group

L1, L2: Length

R1: array area

R2: Ladder area

VC1: The first set of vertical channel structures

VC2: The second set of vertical channel structures

Claims (10)

A memory element, comprising: a stack structure configured on a substrate; a first group of vertical channel structures and a second group of vertical channel structures arranged along the Y direction and penetrating through the stack structure to be in contact with the substrate; and a first a slit configured between the first group of vertical channel structures and the second group of vertical channel structures, and passing through the stacked structure to expose the base, wherein the first slit includes a plurality of first The sub-slits, the plurality of first sub-slits are discretely arranged along the X direction. The memory device according to claim 1, wherein the substrate includes an array area and a step area, and the first group of vertical channel structures and the second group of vertical channel structures are disposed on the substrate of the array area. The memory device according to claim 2, further comprising: a first string of selection line cuts located between the plurality of discrete first sub-slits. The memory device as claimed in claim 3, wherein the first string of selection line cuts extends at least beyond the first row of contact windows in the step region. The memory element according to claim 3, wherein the stack structure includes a plurality of conductor layers and a plurality of dielectric layers alternately stacked along the Z direction, and the topmost conductor layer is a string selection line to control the first group The vertical channel structures are switched with the second set of vertical channel structures. The memory element according to claim 5, further comprising: a second string selection line cut, embedded in the string selection line, and along the X direction extending to divide the first group of vertical channel structures into two first groups; and a third string selection line cut embedded in the string selection line and extending along the X direction to divide the The second group of vertical channel structures is divided into two second groups. The memory element according to claim 2, further comprising: two second slits respectively disposed on the first side of the first set of vertical channel structures and the second set of vertical channel structures relative to the first side, and penetrate through the stacked structure to expose the base, wherein the two second slits respectively extend continuously from the array area to the stepped area along the X direction. The memory device as claimed in claim 7, wherein a ratio of the sum of the lengths of the plurality of first sub-slits to the length of one of the two second slits is between 0.35 and 0.9. The memory element according to claim 1, further comprising: a third group of vertical channel structures and a fourth group of vertical channel structures, along with the first group of vertical channel structures and the second group of vertical channel structures along the Y aligned in a direction and penetrate through the stack structure to be in contact with the substrate; and a third slit is arranged between the second set of vertical channel structures and the third set of vertical channel structures and runs through the stack structure to expose the base, wherein the third slit includes a plurality of third sub-slits discretely arranged along the X direction. A memory element, comprising: a stack structure configured on a substrate; a first group of vertical channel structures and a second group of vertical channel structures arranged along the Y direction and penetrating through the stack structure to be in contact with the substrate; The first isolation structure is arranged between the first group of vertical channel structures and the second group of vertical channel structures, wherein the first isolation structure includes a plurality of sub-slits and a plurality of strings arranged alternately along the X direction selective wire cutting; and a second isolation structure is disposed on the first side of the first set of vertical channel structures and penetrates through the stacked structure to expose the substrate, wherein the second isolation structure is along the X direction extending continuously, and the length of the second isolation structure is greater than the sum of the lengths of the plurality of sub-slits.

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