TWI787032B - Integrated circuit and power control circuit thereof - Google Patents

Abstract

An integrated circuit and a power control circuit thereof are provided. The power control circuit includes a first switch, a second switch and a control signal generator. The first switch is coupled between a first power rail and a second power rail, and be turned-on or cut-off according to a first control signal. The second switch is coupled between a third power rail and a fourth power rail, and be turned-on or cut-off according to a second control signal. The control signal generator is coupled to the first switch and the second switch, and generated the first control signal and the second control signal according to an activation signal and a trigger signal, where the trigger signal is used to control a cut-off time point of the first switch and the second switch.

Description

Integrated circuit and its power control circuit

The present invention relates to an integrated circuit and its power control circuit, and in particular to an integrated circuit capable of reducing switching current and its power control circuit.

In integrated circuits, a subcritical current reduction circuit is often used to reduce the leakage current phenomenon that may occur in the circuit. In the sub-critical current reduction circuit, a switch is often used to set between the main power rail and the secondary power rail, and when the core circuit is not working, the switch can be cut off to prevent the leakage current of the core circuit. However, larger dimensions are often required as switches cut off the connection path between the power rails. Therefore, during the switching operation of the switch, it is often necessary to consume a large switching current. When the switching action is too frequent, the integrated circuit will consume too much switching current, resulting in waste of power.

The invention provides an integrated circuit and its power supply control circuit, which can effectively reduce switching current.

The power control circuit of the present invention includes a first switch, a second switch and a control signal generator. The first switch is coupled between the first power rail and the second power rail, and is turned on or off according to a first control signal. The second switch is coupled between the third power rail and the fourth power rail, and is turned on or off according to a second control signal. The control signal generator is coupled to the first switch and the second switch, and generates the first control signal and the second control signal according to the start signal and the trigger signal. The trigger signal is used to control the time point when the first switch and the second switch are cut off.

The integrated circuit of the present invention includes a first power rail, a second power rail, a third power rail, a fourth power rail and the power control circuit as described above.

Based on the above, the power control circuit of the present invention controls the switching frequency of the first switch and the second switch through the start signal and the trigger signal. Wherein, when the start signal is enabled, the first switch and the second switch can be used to control the switching time point according to the trigger signal. In this way, by controlling the period of the trigger signal, the leakage current generated when the first switch and the second switch are switched can be effectively reduced.

Please refer to FIG. 1 , which is a schematic diagram of a power control circuit according to an embodiment of the present invention. The power control circuit 100 includes a first switch SW1 , a second switch SW2 and a control signal generator 110 . The first switch SW1 is coupled between the power rails PWL1 and PWL2 and is controlled by the control signal ENB to be turned on or off. The second switch SW2 is coupled between the power rails PWL3 and PWL4 and is controlled by the control signal ENT to be turned on or off. In this embodiment, the first switch SW1 and the second switch SW2 are composed of transistors MP1 and MN1 respectively. Wherein, the transistor MP1 may be a P-type transistor, and the transistor MN1 may be an N-type transistor.

In this embodiment, the power rail PWL1 is used to receive the power voltage VDD, and the power rail PWL4 is used to receive the reference ground voltage VSS. And when the first switch SW1 is turned on according to the control signal ENB, the power rail PWL2 and the power rail PWL1 are electrically connected to each other through the first switch SW1 . At this time, the power rail PWL2 may deliver a power voltage VDDZ that is substantially the same as the power voltage VDD. When the second switch SW2 is turned on according to the control signal ENT, the power rail PWL3 and the power rail PWL4 are electrically connected to each other through the second switch SW2. At this time, the power rail PWL3 may transmit the reference ground voltage VSSZ which is substantially the same as the reference ground voltage VSS. That is to say, the power rails PWL1 and PWL4 in this embodiment can be the main power rails, and the power rails PWL2 and PWL3 can be the secondary power rails. The power rails PWL1 ˜ PWL4 are used to provide operating power to the core circuits 101 , 102 coupled thereto. By turning off the first switch SW1 and the second switch SW2 , the leakage phenomenon of the core circuits 101 and 102 coupled to the power rail PWL2 or PWL3 to generate a subthreshold current can be avoided.

In addition, the control signal generator 110 is coupled to the first switch SW1 and the second switch SW2. The control signal generator 110 receives an enable signal ACTT and a trigger signal TRIG. The control signal generator 110 is used for generating the control signals ENB and ENT according to the enable signal ACTT and the trigger signal TRIG. The control signal generator 110 transmits control signals ENB and ENT to the control terminals of the first switch SW1 and the second switch SW2 respectively, and are used to control the on or off state of the first switch SW1 and the second switch SW2.

In this embodiment, based on the fact that the first switch SW1 is constructed by a P-type transistor MP1, and the second switch SW2 is constructed by an N-type transistor MN1, the control signals ENB and ENT can be opposite signals to each other, and the first switch SW1 and the second switch SW2 can be turned on or turned off at the same time.

Please note here that in this embodiment, the activation signal ACTT can be used to activate the core circuits 101 , 102 coupled to the power rails PWL1 ˜ PWL4 . The trigger signal TRIG can be used to control the time point when the first switch SW1 and the second switch SW2 are turned off. Please refer to FIG. 1 and FIG. 2 synchronously below, wherein FIG. 2 shows a waveform diagram of a power control circuit according to an embodiment of the present invention. In FIG. 2 , the trigger signal TRIG may have a period TPD and pulses PS1 - PS3 . The length of the period TPD is greater than the width of each pulse PS1 - PS3 .

On the other hand, the activation signal ACTT is used to control the activation of the core circuits 101 and 102, wherein when the activation signal ACTT is at a logic high level, the control signal generator 110 makes the control signals ENB and ENT respectively at a logic low level and The logic level is high, and the first switch SW1 and the second switch SW2 are turned on to normally supply the power supply voltage VDD and the reference ground voltage VSS to the corresponding core circuits 101 , 102 . When the activation signal ACTT maintains a logic high level, the pulses PS1 and PS3 of the trigger signal TRIG do not affect the logic levels of the control signals ENB and ENT.

When the activation signal ACTT is switched to a logic low level, the core circuits 101 and 102 may first stop operating. At this time, the pulse PS2 of the trigger signal TRIG can make the logic levels of the control signals ENB and ENT transition, and change the first switch SW1 and the second switch SW2 to the cut-off state, and stop supplying the power supply voltage VDD , the reference ground voltage VSS to the corresponding core circuits 101 , 102 .

In this embodiment, the period TPD of the trigger signal TRIG can be set to have a longer value, for example, 10 microseconds (micro second). In this way, the first switch SW1 and the second switch SW2 will not be alternately turned on and off because the core circuits 101 and 102 frequently switch between activation and deactivation, resulting in unnecessary waste of electric energy.

Please refer to FIG. 3A and FIG. 3B below. FIG. 3A and FIG. 3B respectively illustrate schematic diagrams of different implementations of the control signal generator in the power control circuit of the embodiment of the present invention. In FIG. 3A , the control signal generator 310 includes a set/reset latch (S-R latch) SRLAT. The set/reset latch SRLAT has a reset terminal RT, a set terminal ST, an output terminal Q, and an inversion output terminal QB. The set/reset latch SRLAT includes NOR gates NO1, NO2 and an inverter IV1. One input terminal of the NOR gate NO1 is coupled to the setting terminal ST; the other input terminal of the NOR gate NO1 is coupled to the output terminal of the NOR gate NO2; the output terminal of the NOR gate NO1 is coupled to the output terminal of the NOR gate NO2 an input terminal. The other input terminal of the NOR gate NO2 is coupled to the reset terminal RT, and the output terminal of the NOR gate NO2 is coupled to the output terminal Q of the set/reset latch SRLAT and the input terminal of the inverter IV1. The output terminal of the inverter IV1 is coupled to the inverting output terminal QB of the set/reset latch SRLAT.

The set terminal ST of the set/reset latch SRLAT is used to receive the trigger signal TRIG, and the reset terminal RT of the set/reset latch SRLAT is used to receive the enable signal ACTT. The output terminal Q of the set/reset latch SRLAT is used to generate the control signal ENB, and the inverted output terminal QB of the set/reset latch SRLAT is used to generate the control signal ENT.

In this embodiment, when the activation signal ACTT is at a logic high level, the control signal ENB can be reset at a logic low level, and the control signal ENT can be at a logic high level. On the contrary, when the starting signal ACTT is logic low level, the positive pulse wave on the trigger signal TRIG can make the NOR gate NO2 generate a logic high level output signal, and make the control signal ENB be logic high level, so that the control The signal ENT is logic low level.

It is worth mentioning that the circuit structure of the set/reset latch SRLAT shown in FIG. 3A is just an example for illustration. Those skilled in the art know that the set/reset latch (S-R Latch) can also be constructed by other types of logic gates other than the inverse OR gate, and can also be used to implement the control signal generator 310 of the present invention. , without specific restrictions.

On the other hand, in FIG. 3B , the control signal generator 320 is constructed by a D-type flip-flop DFF1. The D-type flip-flop DFF1 has a data terminal D, a clock terminal CK, a reset terminal R, an output terminal Q, and an inverting output terminal QB. The data terminal D of the D-type flip-flop DFF1 receives the power supply voltage VDD; the clock terminal CK of the D-type flip-flop DFF1 receives the trigger signal TRIG; the reset terminal R of the D-type flip-flop DFF1 receives the start signal ACT; the D-type flip-flop DFF1 receives the start signal ACT; The output terminal Q and the inverted output terminal QB of the inverter DFF1 generate control signals ENB and ENT respectively.

When the activation signal ACT is at a logic high level, the D-type flip-flop DFF1 is reset and generates control signals ENB and ENT at a logic low level and a logic high level respectively. When the D-type flip-flop DFF1 is in the reset state, the control signals ENB and ENT generated by the output terminal Q and the reverse output terminal QB of the D-type flip-flop DFF1 respectively will not be changed by the trigger signal TRIG .

When the activation signal ACT is logic low level, when the clock terminal of the D-type flip-flop DFF1 receives the pulse wave of the trigger signal TRIG, the control signal ENB on the output terminal Q of the D-type flip-flop DFF1 can be controlled according to The data terminal of the D-type flip-flop DFF1 receives the power voltage VDD and is pulled up to a logic high level. Correspondingly, the control signal ENT on the inverting output terminal QB of the D-type flip-flop DFF1 is equal to a logic low level.

Incidentally, the circuit details of the D-type flip-flop DFF1 can be implemented by using any D-type flip-flop circuit known to those skilled in the art, without any specific limitation.

Please refer to FIG. 4 below. FIG. 4 is a schematic diagram of an integrated circuit according to an embodiment of the present invention. The integrated circuit 400 includes a power control circuit 410 , core circuits 420 , 430 and power rails PWL1 ˜ PWL4 . The power control circuit 410 includes a first switch SW1 , a second switch SW2 and a controller number generator 411 . The controller number generator 411 receives the activation signal ACT and the trigger signal TRIG, and generates the control signals ENB and ENT according to the activation signal ACT and the trigger signal TRIG. The first switch SW1 and the second switch SW2 are constructed by transistors MP1 and MN1 respectively. The first switch SW1 is coupled between the power rails PWL1 and PWL2 and is turned on or off according to the control signal ENB. The second switch SW2 is coupled between the power rails PWL3 and PWL3 and is turned on or off according to the control signal ENT.

The operation details of the controller number generator 411 and the first switch SW1 and the second switch SW2 are the same as those in the embodiment shown in FIG. 1 , and will not be repeated here.

In this embodiment, the core circuit 420 is coupled between the power rails PWL2 and PWL4 . The core circuit 430 is coupled between the power rails PWL1 and PWL3 . When both the first switch SW1 and the second switch SW2 are turned on, the core circuit 420 can receive the power supply voltage VDDZ substantially equal to the power supply voltage VDD from the power supply rail PWL2 to operate, and the core circuit 420 can also operate through the power supply rail PWL4. Receive reference ground voltage VSS. The core circuit 430 can receive the power voltage VDD through the power rail PWL1 , and can receive the reference ground voltage VSSZ substantially equal to the reference ground voltage VSS through the power rail PWL3 , and operate.

When the core circuits 420, 430 stop operating, the power control circuit 410 can cut off the first switch SW1 and the second switch SW2 according to whether the pulse wave of the trigger signal TRIG is received, and prevent the core circuits 420, 430 from generating a sub-critical current, Reduce the occurrence of leakage current.

In this embodiment, the core circuit 420 includes a buffer constructed by transistors MP2 and MN2, and the core circuit 430 includes a buffer constructed by transistors MP3 and MN3. The output terminal of the core circuit 420 can be coupled to the input terminal of the core circuit 430 .

Please note here that in this embodiment, the trigger signal TRIG is a periodic signal, and provides a positive pulse wave in a fixed period as a basis for whether to turn off the first switch SW1 and the second switch SW2. Under such conditions, by setting the period of the trigger signal TRIG, the frequency at which the first switch SW1 and the second switch SW2 change from on to off can be controlled, and the switching process of the first switch SW1 and the second switch SW2 can be effectively controlled. The required switching current can effectively reduce the waste of power.

To sum up, the power supply control circuit of the present invention is based on the pulse wave generated periodically by the trigger signal as the basis for cutting off the switch. In this way, by controlling the cycle of the trigger signal, the switching frequency of the switch can be effectively reduced, the switching current generated during the switching process of the switch can be effectively reduced, and the waste of electric power can be reduced.

100: Power control circuit

101, 102, 420, 430: core circuit

110, 310, 320, 411: control signal generator

400: Integrated circuit

ACTT: start signal

CK: clock terminal

D: data terminal

DFF1: D type flip-flop

ENT, ENB: control signal

IV1: Inverter

MP1~MP3, MN1~MN3: Transistor

NO1, NO2: reverse OR gate

PS1~PS3: pulse wave

PWL1~PWL4: power rail

Q: output terminal

QB: reverse output

RT, R: reset terminal

SRLAT: Set/Reset Latch

ST: setting terminal

SW1: first switch

SW2: Second switch

TPD: period

TRIG: trigger signal

VDD, VDDZ: power supply voltage

VSS, VSSZ: reference ground voltage

FIG. 1 is a schematic diagram of a power control circuit according to an embodiment of the present invention. FIG. 2 is a waveform diagram of a power control circuit according to an embodiment of the present invention. 3A and 3B are schematic diagrams of different implementations of the control signal generator in the power control circuit of the embodiment of the present invention. FIG. 4 is a schematic diagram of an integrated circuit according to an embodiment of the present invention.

100: Power control circuit

110: Control signal generator

101, 102: core circuit

ACTT: start signal

ENT, ENB: control signal

MP1, MN1: Transistor

PWL1~PWL4: power rail

SW1: first switch

SW2: Second switch

TRIG: trigger signal

VDD, VDDZ: power supply voltage

VSS, VSSZ: reference ground voltage

Claims (12)

A power supply control circuit, comprising: a first switch, coupled between a first power rail and a second power rail, to be turned on or off according to a first control signal; a second switch, coupled to Between a third power rail and a fourth power rail, it is turned on or off according to a second control signal; and a control signal generator is coupled to the first switch and the second switch, according to a A start signal and a trigger signal are used to generate the first control signal and the second control signal, wherein the trigger signal is used to control the time point at which the first switch and the second switch are cut off, and the first switch and the second switch are switched off. The second switches are turned on or turned off at the same time. The power supply control circuit according to claim 1, wherein when the enable signal is at a first logic level, the control signal generator generates the first control signal and the second control signal according to the pulse wave of the trigger signal to cut off the first switch and the second switch respectively. The power supply control circuit as claimed in item 2, wherein when the enable signal is at a second logic level, the control signal generator generates the first control signal and the second control signal according to the pulse wave of the trigger signal to respectively turn on the first switch and the second switch, wherein the first logic level is different from the second logic level. The power supply control circuit as described in claim 1, wherein the control signal generator is a set/reset latch, and the set/reset latch has a setting terminal, a reset terminal, an output terminal and a reverse output terminal, the reset terminal of the set/reset latch receives the start signal, the set terminal of the set/reset latch receives the trigger signal, the The inverting output terminal of the set/reset latch generates the second control signal, and the output terminal of the set/reset latch generates the first control signal. The power supply control circuit as described in claim 1, wherein the control signal generator is a D-type flip-flop, and the D-type flip-flop has a data terminal, a clock terminal, a reset terminal, an output terminal and an inverter. To the output terminal, wherein the data terminal of the D-type flip-flop receives a power supply voltage, the clock terminal of the D-type flip-flop receives the trigger signal, and the reset terminal of the D-type flip-flop receives the start signal, the output end of the D-type flip-flop generates the first control signal, and the inverting output end of the D-type flip-flop generates the second control signal. The power supply control circuit as claimed in item 1, wherein the first power supply rail and the second power supply rail are used to transmit a power supply voltage, and the third power supply rail and the fourth power supply rail are used to transmit a reference ground voltage. An integrated circuit, comprising: a first power rail, a second power rail, a third power rail, and a fourth power rail; and a power control circuit, including: a first switch coupled to Between a first power rail and a second power rail, it is turned on or off according to a first control signal; a second switch is coupled to a third power rail and a fourth power rail time, according to a second control signal to be turned on or off; and A control signal generator, coupled to the first switch and the second switch, generates the first control signal and the second control signal according to an activation signal and a trigger signal, wherein the trigger signal is used to control the first The time point at which the switch and the second switch are cut off. The integrated circuit as described in claim 7, further comprising: a first core circuit coupled between the second power rail and the fourth power rail; and a second core circuit coupled between the first power rail Between a power rail and the third power rail. The integrated circuit as claimed in claim 8, wherein the output terminal of the first core circuit is coupled to the input terminal of the second core circuit. The integrated circuit as claimed in item 7, wherein when the enable signal is at a first logic level, the control signal generator generates the first control signal and the second control signal according to the pulse wave of the trigger signal to cut off the first switch and the second switch respectively. The integrated circuit according to claim 10, wherein when the start signal is at a second logic level, the control signal generator generates the first control signal and the second control signal according to the pulse wave of the trigger signal to respectively turn on the first switch and the second switch, wherein the first logic level is different from the second logic level. The integrated circuit as claimed in item 7, wherein the first power supply rail and the second power supply rail are used to transmit a power supply voltage, and the third power supply rail and the fourth power supply rail are used to transmit a reference ground voltage.

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