TWI786831B - Three dimension memory device - Google Patents

Abstract

A three dimension memory device, such as a three dimension AND flash memory, is provided. The three dimension memory device includes a plurality of memory arrays, a plurality of bit line switches and a plurality of source line switches. The memory arrays have a plurality of memory cell rows coupled to a plurality of bit lines and source lines. The bit line switches and the source line switches are respectively implemented by a plurality of first transistors and a plurality of second transistors. The first transistors are coupled to a common bit line and the bit lines. The second transistors are coupled to a common source line and the source lines. The first transistors are P type transistors or N type transistors with three well substrate, the second transistors are P type transistors or N type transistors with three well substrate.

Description

3D memory device

The present invention relates to a three-dimensional memory device, and more particularly to a three-dimensional memory device capable of providing negative source line voltage or bit line voltage.

With the advancement of semiconductor process technology and the improvement of electronic product functions, it has become a trend to install high-density flash memory on electronic products.

In conventional three-dimensional NAND flash memory devices, bit line switches and source line switches are usually implemented by N-type transistors. In this case, the bit line switch and the source line switch can only provide positive word line voltage and source line voltage to the memory cell, and make the memory cell perform programming or erasing operations. However, since the memory cell is in the process of programming or erasing, it can be a selected memory cell or an unselected memory cell. In order to enable the selected memory cells to effectively perform programming or erasing operations, and to enable unselected memory cells to be shielded without interference, under the constraints of process conditions, how to provide an appropriate bias voltage for each memory cell becomes A difficult subject.

The invention provides a three-dimensional memory device, which can provide appropriate bit line voltage and source line voltage to each memory cell.

The three-dimensional memory device of the present invention includes a plurality of memory cell arrays, a plurality of bit line switches and a plurality of source line switches. The memory cell array has a plurality of corresponding memory cell rows, and the memory cell rows are respectively coupled to a plurality of source lines and a plurality of bit lines. The bit line switches are respectively composed of a plurality of first transistors. The first terminals of the first transistors are coupled to a common bit line, and the second terminals of the first transistors are respectively coupled to the bit lines. The source line switches are respectively composed of a plurality of second transistors. The second terminals of the second transistors are coupled to the common source line, and the second terminals of the second transistors are respectively coupled to the source lines. Wherein, the first transistor is a P-type transistor or an N-type transistor with a Mitsui base, and the second transistor is a P-type transistor or an N-type transistor with a Mitsui base.

Based on the above, the three-dimensional memory device of the present invention constructs source line switches and bit line switches through P-type transistors or N-type transistors with a Mitsui substrate. Wherein, in the three-dimensional memory device of the present invention, by controlling the voltage on the well region of the P-type transistor and/or the N-type transistor, the source or drain can pass a positive or negative voltage. In this way, the source line switch and the bit line switch can provide appropriate voltages to the selected and unselected memory cells, so that each memory cell can complete the operations of reading, programming and erasing.

Please refer to FIG. 1 , which is a schematic diagram of a three-dimensional memory device according to an embodiment of the present invention. The three-dimensional memory device 100 includes memory cell arrays 111 , 112 , bit line switches BLT0 - BLT3 , and source line switches SLT0 - SLT3 . The memory cell array 111 includes a plurality of memory cells MC1. The memory cell array 112 includes a plurality of memory cells MC2. In the memory cell array 111 , the memory cells MC1 are arranged into a plurality of memory cell rows and memory cell columns. In the memory cell array 112 , the memory cells MC2 are also arranged into a plurality of memory cell rows and memory cell columns. The multiple memory cell columns in the memory cell array 111 are respectively coupled to the word lines WL1_0˜WL1_1, and the multiple memory cell columns in the memory cell array 112 are respectively coupled to the word lines WL0_0˜WL0_1. In addition, a plurality of memory cell rows of the memory cell arrays 111 and 112 correspond to each other, and are respectively coupled to the bit lines LBL0 - LBL3 and the source lines LSL0 - LSL3 .

The bit line switches BLT0 ˜ BLT3 are disposed in the substrate 120 . The bit line switches BLT0~BLT3 are respectively composed of a plurality of transistors M11~M14. The source line switches SLT0 ˜ SLT3 are disposed in the substrate 130 . The source line switches SLT0-SLT3 are respectively composed of a plurality of transistors M21-M24. The transistors M11 - M14 are respectively controlled by the selection signals SEL_BLT0 - SEL_BLT3 to be turned on or off. The transistors M21 - M24 are respectively controlled by the selection signals SEL_SLT0 - SEL_SLT3 to be turned on or off.

In this embodiment, the transistors M11 - M14 may be P-type transistors, or may also be N-type transistors with a Mitsui base. Transistors M21-M24 may be P-type transistors, or N-type transistors with a Mitsui base.

Incidentally, the memory cell arrays 111 and 112 in this embodiment are AND type flash memory cell arrays. In addition, in the embodiment of the present invention, a single source line is only coupled to the common source line CSL through a corresponding single source line switch. A single bit line is coupled to the common bit line GBL only through a corresponding single bit line switch.

Please refer to FIG. 2 below. FIG. 2 is a schematic diagram of an implementation of an N-type transistor with a Mitsui substrate in a three-dimensional memory device according to an embodiment of the present invention. N-type transistor 200 includes N-type deep well region (DNW) 210, P-type well region (PWI) 220, N-type well region 230, N-type heavily doped regions (n+) 231, 232, P-type heavily doped regions ( p+) 233 and gate structure 250. The N-type deep well region 210 can be formed in a P-type substrate. The P-type well (PWI) 220 is formed on the N-type deep well 210 and surrounded by the N-type well 230 . The N-type heavily doped regions (n+) 231 and 232 and the P-type heavily doped region (p+) 233 are sequentially arranged on the P-type well region (PWI) 220 . Wherein, the N-type heavily doped region (n+) 232 and the P-type heavily doped region (p+) 233 can be isolated by an insulating structure 245 . A channel can be formed between the N-type heavily doped regions (n+) 231 and 232 , and the gate structure 250 covers the channel and part of the N-type heavily doped regions (n+) 231 and 232 .

In this embodiment, the bias voltage VPW can be transmitted to the P-type heavily doped region (p+) 233 through the connection structure CT, and applied to the P-type well region (PWI) 220 . By controlling the bias voltage VPW and the voltage on the N-type deep well region 210, the N-type heavily doped regions (n+) 231 and 232 used as the source and drain (or drain and source) of the transistor 200 can be used for Transmits negative or positive voltages.

Please refer to FIG. 3A to FIG. 3D below. FIG. 3A to FIG. 3D are schematic diagrams illustrating access operations of a three-dimensional memory device according to an embodiment of the present invention. In FIG. 3A, in the three-dimensional memory device 300, the transistors M21~M24 serving as the source line switches SLT0~SLT3 and the transistors M11~M14 serving as the bit line switches BLT0~BLT3 are N type transistor.

In the read operation, the bases (P-type wells) 320 of the transistors M11-M14 are applied with a bias voltage equal to 0 volts, and the bases (P-type wells) 330 of the transistors M21-M24 are also applied with a bias voltage equal to 0 volts. the bias voltage. Corresponding to the selected memory cell SMC, the bit line LBL2 and the source line LSL2 are respectively the selected bit line and the selected source line. The bit line switch BLT2 and the source line switch SLT2 are respectively a selected bit line switch and a selected source line switch, and are turned on. The remaining bit line switches BLT0, BLT1, BLT3 and the remaining source line switches SLT0, SLT1, SLT3 are turned off. At this time, the voltage on the common bit line GBL can be equal to the first voltage, and the turned-on bit line switch BLT2 can provide the first voltage to the bit line LBL2 of the selected memory cell SMC. In addition, at this time, the voltage on the common source line CSL is equal to the second voltage, and the turned-on source line switch SLT2 can provide the second voltage to the source line LSL2 corresponding to the selected memory cell SMC. Wherein, in this embodiment, the first voltage may be a positive value, and the first voltage is greater than the second voltage. For example, the first voltage can be 1 volt, and the second voltage can be 0 volts.

On the other hand, the word line electrical signal on the word line WL0_0 corresponding to the selected memory cell SMC may be equal to the read voltage (eg, 5-7 volts). The word line electrical signals on the other word lines WL0_1 , WL1_0 , WL1_1 not corresponding to the selected memory cell SMC may be equal to 0 volts.

In addition, since the bit line switches BLT0, BLT1, BLT3 and the source line switches SLT0, SLT1, SLT3 are all turned off, the bit lines LBL0, LBL1, LBL3, and the source lines LSL0, LSL1, LSL3 are all floating. connected to ground voltage.

The selected memory cell SMC can transmit current according to the stored data, and is sent to the sense amplifier (not shown) through the bit line LBL2. The sense amplifier can convert the current provided by the selected memory cell SMC into a voltage signal, and compare the voltage signal with a reference voltage to sense the data stored in the selected memory cell SMC.

In FIG. 3B , the 3D memory device 300 executes programmed actions. And through Fowler-Nordheim tunneling (Fowler-Nordheim tunneling) method to adjust the threshold voltage of the selected memory cell SMC, and execute programmed actions.

In the stylized action, the bases (P-type wells) 320 of the transistors M11-M14 and the bases (P-type wells) 330 of the transistors M21-M24 are all applied with a negative bias voltage (eg -7.5 volts ). In addition, the bit line switch BLT2 corresponding to the selected memory cell SMC is a selected bit line switch and is turned on. The remaining bit line switches BLT0, BLT1, BLT3 are turned off. The bit line switch BLT2 provides a negative first voltage to the bit line LBL2 corresponding to the selected memory cell SMC. The first voltage is, for example, -7.5 volts. In addition, the source line switch SLT2 corresponding to the selected memory cell SMC is set as the selected source line switch and turned off. The remaining source line switches SLT0 , SLT1 , SLT3 are turned on. Here, the voltage on the common source line CSL is equal to 6.5 volts, for example. Based on the body effect, the turned-on source line switches SLT0, SLT1, SLT3 can provide a positive second voltage (for example equal to 3.5 volts) to the source lines LSL0, LSL1, LSL3 corresponding to the unselected memory cells . The second voltage is used as an inhibit voltage. Here, the source line LSL2 is in a floating state.

In addition, the word line voltage on the word line WL0_0 corresponding to the selected memory cell SMC can be set to 12.5 volts, and the word line voltages on the other word lines WL1_0 , WL1_1 , WL0_1 can be set to -1.5 volts. In this way, the selected memory cell SMC can withstand a programming bias voltage of up to 20 volts (the voltage difference between the word line and the bit line (or source line) corresponding to the memory cell during the programming action), which can effectively Executes a programmed action.

Regarding other unselected memory cells, memory cells corresponding to unselected bit lines, unselected source lines, and unselected word lines can be programmed with a bias voltage of -5 volts; corresponding to unselected bits The memory cells of the cell line, unselected source line, and selected word line can be programmed with a bias voltage of 9 volts; corresponding to the selected bit line, selected source line, and unselected word line memory cells, Its programming bias can be 6 volts. The above-mentioned unselected memory cells can be effectively masked without being disturbed by stylized actions.

In FIG. 3C , the 3D memory device 300 performs a byte erase operation. The selected memory cell SMC is selected to perform an erase operation based on FN tunneling.

In the byte erasing operation, the bases (P-type wells) 320 of the transistors M11-M14 and the bases (P-type wells) 330 of the transistors M21-M24 are both applied with a negative bias voltage (eg -3.5 Volts). In addition, the bit line switch BLT2 corresponding to the selected memory cell SMC is a selected bit line switch and is turned on. The remaining bit line switches BLT0, BLT1, BLT3 are turned off. The bit line switch BLT2 provides a positive first voltage to the bit line LBL2 corresponding to the selected memory cell SMC according to the voltage on the common bit line GBL. Wherein the voltage on the common bit line GBL is, for example, equal to 10.5 volts, based on the substrate effect, the bit line switch BLT2 can provide the first voltage, for example, equal to 7.5 volts to the bit line LBL2.

In addition, the source line switch SLT2 corresponding to the selected memory cell SMC is set as the selected source line switch and turned off. The remaining source line switches SLT0 , SLT1 , SLT3 are turned on. Here, the voltage on the common source line CSL is equal to -3.5 volts, for example. The turned-on source line switches SLT0 , SLT1 , SLT3 can respectively provide a negative second voltage (eg, equal to −3.5 volts) to the source lines LSL0 , LSL1 , LSL3 . Here, the source line LSL2 is in a floating state.

In addition, the word line voltage on the word line WL0_0 corresponding to the selected memory cell SMC can be set to -12.5 volts, and the word line voltages on the other word lines WL1_0 , WL1_1 , WL0_1 can be set to 1.5 volts. In this way, the selected memory cell SMC can withstand an erase bias voltage of -20 volts (during the erase operation, the voltage difference between the word line and the bit line (or source line) corresponding to the memory cell), it can Efficiently perform the action of erasing.

Regarding other unselected memory cells, the memory cells corresponding to unselected bit lines, unselected source lines and unselected word lines can have an erase bias of 5 volts; corresponding to unselected bit lines line, unselected source line and selected word line memory cell, its erase bias can be -9 volts; corresponding to the selected bit line, selected source line and unselected word line memory cell, Its erase bias can be -6 volts. The above-mentioned unselected memory cells can be effectively covered without being disturbed by the erasing action.

In FIG. 3D , the 3D memory device 300 performs a block erase operation. Multiple memory cells in the selected memory cell block SMB are simultaneously selected to perform an erasing action.

During the block erase operation, the bases (P-type wells) 320 of the transistors M11 - M14 and the bases (P-type wells) 330 of the transistors M21 - M24 are both applied with a bias voltage of 0 volts. The voltage on the common bit line GBL and the common source line CSL may be about 13 volts.

In addition, the source line switches SLT0 - SLT3 and the bit line switches BLT0 - BLT3 are all turned on. Based on the substrate effect, the voltages on the source lines LSL0 - LSL3 and the bit lines LBL0 - LBL3 are all positive 10V.

In addition, the word line voltages on the word lines WL0_0 and WL0_1 of the selected memory cell block SMB can be set to -10 volts, and the word line voltages on the other word lines WL1_0 and WL1_1 can be set to 4 volts . In this way, the memory cells in the selected memory cell block SMB can bear the erasing bias voltage up to -20 volts, and can effectively execute the erasing operation. The remaining memory cells that have not been erased can withstand an erase bias of -6 volts and can be shielded from being disturbed by the erase operation.

Please refer to FIG. 4A to FIG. 4D below. FIG. 4A to FIG. 4D are schematic diagrams illustrating access operations of a three-dimensional memory device according to another embodiment of the present invention. In FIG. 4A, in the three-dimensional memory device 400, the transistors M21~M24 serving as the source line switches SLT0~SLT3 are P-type transistors, and the transistors M11~M14 serving as the bit line switches BLT0~BLT3 have N-type transistors on the base of Mitsui Ward.

In the read operation, the bases (P-type wells) 420 of transistors M11-M14 are applied with a bias voltage equal to 0 volts, and the bases (N-type wells) 430 of transistors M21-M24 are applied with a bias voltage equal to, for example, 1.8 volts. the bias voltage. Corresponding to the selected memory cell SMC, the bit line LBL2 and the source line LSL2 are respectively the selected bit line and the selected source line, and the bit line switch BLT2 and the source line switch SLT2 are respectively the selected bit line switch and The source line switch is selected and turned on. Bit line switches BLT0, BLT1, BLT3 and source line switches SLT0, SLT1, SLT3 are turned off. At this time, the voltage on the common bit line GBL can be equal to the first voltage, and the turned-on bit line switch BLT2 can provide the first voltage to the bit line LBL2 of the selected memory cell SMC. In addition, at this time, the voltage on the common source line CSL is equal to the second voltage, and the turned-on source line switch SLT2 can provide the second voltage to the source line LSL2 corresponding to the selected memory cell SMC. Wherein, in this embodiment, the first voltage may be a positive value, and the first voltage is greater than the second voltage. For example, the first voltage can be 1 volt, and the second voltage can be 0 volts.

On the other hand, the word line electrical signal on the word line WL0_0 corresponding to the selected memory cell SMC may be equal to the read voltage (eg, 5-7 volts). The word line electrical signals on the other word lines WL0_1 , WL1_0 , WL1_1 not corresponding to the selected memory cell SMC may be equal to 0 volts.

In addition, since the bit line switches BLT0, BLT1, BLT3 and the source line switches SLT0, SLT1, SLT3 are all turned off, the bit lines LBL0, LBL1, LBL3, and the source lines LSL0, LSL1, LSL3 are all floating. connected to ground voltage.

The selected memory cell SMC can transmit current according to the stored data, and is sent to the sense amplifier (not shown) through the bit line LBL2. The sense amplifier can convert the current provided by the selected memory cell SMC into a voltage signal, and compare the voltage signal with a reference voltage to sense the data stored in the selected memory cell SMC.

In FIG. 4B , the 3D memory device 400 executes programmed actions. And through Fowler-Nordheim tunneling (Fowler-Nordheim tunneling) method to adjust the threshold voltage of the selected memory cell SMC, and execute programmed actions.

In the stylized action, the bases (P-type wells) 420 of the transistors M11~M14 are applied with a negative bias voltage (for example -10.5 volts), and the bases (N-type wells) 430 of the transistors M21~M24 are A bias voltage (eg 3.5 volts) is applied as a positive value. In addition, the bit line switch BLT2 corresponding to the selected memory cell SMC is a selected bit line switch and is turned on. The remaining bit line switches BLT0, BLT1, BLT3 are turned off. The bit line switch BLT2 provides a negative first voltage to the bit line LBL2 corresponding to the selected memory cell SMC. The first voltage is, for example, -10.5 volts. In addition, the source line switch SLT2 corresponding to the selected memory cell SMC is set as the selected source line switch and turned off. The remaining source line switches SLT0 , SLT1 , SLT3 are turned on. The turned-on source line switches SLT0 , SLT1 , SLT3 can provide a positive second voltage approximately equal to 3.5 volts to the source lines LSL0 , LSL1 , LSL3 . The second voltage is used as an inhibit voltage. Here, the source line LSL2 is in a floating state.

In addition, the word line voltage on the word line WL0_0 corresponding to the selected memory cell SMC can be set to 12.5 volts, and the word line voltages on the other word lines WL1_0 , WL1_1 , WL0_1 can be set to -1.5 volts. In this way, the selected memory cell SMC can withstand a programming bias voltage of up to 23 volts (the voltage difference between the word line and the bit line (or source line) corresponding to the memory cell during the programming action), which can effectively Executes a programmed action.

Regarding other unselected memory cells, memory cells corresponding to unselected bit lines, unselected source lines, and unselected word lines can be programmed with a bias voltage of -5 volts; corresponding to unselected bits The memory cells of the cell line, unselected source line, and selected word line can be programmed with a bias voltage of 9 volts; corresponding to the selected bit line, selected source line, and unselected word line memory cells, Its programming bias can be 9 volts. The above-mentioned unselected memory cells can be effectively masked without being disturbed by stylized actions.

In FIG. 4C , the 3D memory device 400 performs a byte erase operation. The selected memory cell SMC is selected to perform an erase operation based on FN tunneling.

In the byte erasing operation, the bases (P-type wells) 420 of transistors M11~M14 are applied with a negative bias voltage (for example -6.5 volts), and the bases (N-type wells) of transistors M21-M24 ) 430 are applied with a positive bias voltage (eg, 7.5 volts). In addition, the bit line switch BLT2 corresponding to the selected memory cell SMC is a selected bit line switch and is turned off. The remaining bit line switches BLT0, BLT1, BLT3 are turned on. The bit line switches BLT0 , BLT1 , BLT3 provide a positive first voltage to bit lines LBL0 , LBL1 , LBL3 corresponding to a plurality of unselected memory cells according to the voltage on the common bit line GBL. The voltage on the common bit line GBL is, for example, equal to -6.5 volts. Bit line switches BLT0 , BLT1 , BLT3 may provide a negative first voltage, eg equal to -6.5 volts, to bit lines LBL0 , LBL1 , LBL3 . The bit line LBL2 is in a floating state.

In addition, the source line switch SLT2 corresponding to the selected memory cell SMC is set as the selected source line switch and turned on. The remaining source line switches SLT0, SLT1, SLT3 are turned off. Here, the voltage on the common source line CSL is equal to 7.5 volts, for example. The turned-on source line switch SLT2 may provide the source line LSL2 with a positive second voltage (equal to 7.5 volts). Here, the source lines LSL0 , LSL1 , and LSL3 are in a floating state.

In addition, the word line voltage on the word line WL0_0 corresponding to the selected memory cell SMC can be set to -12.5 volts, and the word line voltages on the other word lines WL1_0 , WL1_1 , WL0_1 can be set to 1.5 volts. In this way, the selected memory cell SMC can withstand an erase bias voltage of -20 volts (during the erase operation, the voltage difference between the word line and the bit line (or source line) corresponding to the memory cell), it can Efficiently perform the action of erasing.

Regarding other unselected memory cells, the memory cells corresponding to unselected bit lines, unselected source lines and unselected word lines can have an erase bias of 8 volts; corresponding to unselected bit lines line, unselected source line and selected word line memory cell, its erase bias can be -6 volts; corresponding to the selected bit line, selected source line and unselected word line memory cell, Its erase bias can be -6 volts. The above-mentioned unselected memory cells can be effectively covered without being disturbed by the erasing action.

In FIG. 4D , the 3D memory device 400 performs a block erase operation. Multiple memory cells in the selected memory cell block SMB are simultaneously selected to perform an erasing action.

In the block erase operation, the bases (P-type well regions) 420 of the transistors M11 - M14 can be applied with a bias voltage of 0 volts. The bases (N-type well regions) 430 of the transistors M21 - M24 can be applied with a bias voltage of 10 volts. The voltage on the common bit line GBL can be about 13 volts, and the voltage on the common source line CSL can be about 10 volts.

In addition, the source line switches SLT0 - SLT3 and the bit line switches BLT0 - BLT3 are all turned on. The voltages on the source lines LSL0~LSL3 are all positive 10 volts. And based on the floor effect, the voltage on the bit lines LBL0 - LBL3 can also be a positive value of 10 volts.

In addition, the word line voltages on the word lines WL0_0 and WL0_1 of the selected memory cell block SMB can be set to -10 volts, and the word line voltages on the other word lines WL1_0 and WL1_1 can be set to 4 volts . In this way, the memory cells in the selected memory cell block SMB can bear the erasing bias voltage up to -20 volts, and can effectively execute the erasing operation. The remaining memory cells that have not been erased can withstand an erase bias of -6 volts and can be shielded from being disturbed by the erase operation.

Please refer to FIG. 5A to FIG. 5D below. FIG. 5A to FIG. 5D are schematic diagrams illustrating access operations of a three-dimensional memory device according to another embodiment of the present invention. In FIG. 5A, in the three-dimensional memory device 500, the transistors M21~M24 serving as the source line switches SLT0~SLT3 are N-type transistors with a Mitsui base, and the transistors M11 serving as the bit line switches BLT0~BLT3 ~M14 is a P-type transistor.

In the read operation, the bases (N-type wells) 420 of transistors M11-M14 are applied with a bias voltage equal to 1.8 volts, and the bases (P-type wells) 430 of transistors M21-M24 are applied with a bias voltage equal to, for example, 0 volts. the bias voltage. Corresponding to the selected memory cell SMC, the bit line LBL2 and the source line LSL2 are respectively the selected bit line and the selected source line, and the bit line switch BLT2 and the source line switch SLT2 are respectively the selected bit line switch and The source line switch is selected and turned on. Bit line switches BLT0, BLT1, BLT3 and source line switches SLT0, SLT1, SLT3 are turned off. At this time, the voltage on the common bit line GBL can be equal to the first voltage, and the turned-on bit line switch BLT2 can provide the first voltage to the bit line LBL2 of the selected memory cell SMC. In addition, at this time, the voltage on the common source line CSL is equal to the second voltage, and the turned-on source line switch SLT2 can provide the second voltage to the source line LSL2 corresponding to the selected memory cell SMC. Wherein, in this embodiment, the first voltage may be a positive value, and the first voltage is greater than the second voltage. For example, the first voltage can be 1 volt, and the second voltage can be 0 volts.

On the other hand, the word line electrical signal on the word line WL0_0 corresponding to the selected memory cell SMC may be equal to the read voltage (eg, 5-7 volts). The word line electrical signals on the other word lines WL0_1 , WL1_0 , WL1_1 not corresponding to the selected memory cell SMC may be equal to 0 volts.

In addition, since the bit line switches BLT0, BLT1, BLT3 and the source line switches SLT0, SLT1, SLT3 are all turned off, the bit lines LBL0, LBL1, LBL3, and the source lines LSL0, LSL1, LSL3 are all floating. connected to ground voltage.

The selected memory cell SMC can transmit current according to the stored data, and is sent to the sense amplifier (not shown) through the bit line LBL2. The sense amplifier can convert the current provided by the selected memory cell SMC into a voltage signal, and compare the voltage signal with a reference voltage to sense the data stored in the selected memory cell SMC.

In FIG. 5B , the 3D memory device 500 executes programmed actions. And through Fowler-Nordheim tunneling (Fowler-Nordheim tunneling) method to adjust the threshold voltage of the selected memory cell SMC, and execute programmed actions.

In the stylized action, the bases (N-type wells) 420 of the transistors M11~M14 are applied with a positive bias voltage (for example, 3.5 volts), and the bases (P-type wells) 430 of the transistors M21~M24 are applied A negative bias voltage (eg -10.5 volts). In addition, the bit line switch BLT2 corresponding to the selected memory cell SMC is a selected bit line switch and is turned off. The remaining bit line switches BLT0, BLT1, BLT3 are turned on. The bit line switches BLT0 , BLT1 , BLT3 provide a positive first voltage to the bit lines LBL0 , LBL1 , LBL3 corresponding to the unselected memory cells. The first voltage is, for example, 3.5 volts. In addition, the source line switch SLT2 corresponding to the selected memory cell SMC is set as the selected source line switch and turned on. The remaining source line switches SLT0, SLT1, SLT3 are turned off. The turned-on source line switch SLT2 may provide a second voltage approximately equal to a negative value (eg, equal to −10.5 volts) to the source line LSL2 . The above-mentioned first voltage is used as an inhibit voltage. Here, bit line LBL2 is in a floating state.

In addition, the word line voltage on the word line WL0_0 corresponding to the selected memory cell SMC can be set to 12.5 volts, and the word line voltages on the other word lines WL1_0 , WL1_1 , WL0_1 can be set to -1.5 volts. In this way, the selected memory cell SMC can withstand a programming bias voltage of up to 23 volts (the voltage difference between the word line and the bit line (or source line) corresponding to the memory cell during the programming action), which can effectively Executes a programmed action.

Regarding other unselected memory cells, memory cells corresponding to unselected bit lines, unselected source lines, and unselected word lines can be programmed with a bias voltage of -5 volts; corresponding to unselected bits The memory cells of the cell line, unselected source line, and selected word line can be programmed with a bias voltage of 9 volts; corresponding to the selected bit line, selected source line, and unselected word line memory cells, Its programming bias can be 9 volts. The above-mentioned unselected memory cells can be effectively masked without being disturbed by stylized actions.

In FIG. 5C , the 3D memory device 500 performs a byte erase operation. The selected memory cell SMC is selected to perform an erase operation based on FN tunneling.

In the byte erasing operation, the bases (N-type wells) 420 of transistors M11~M14 are applied with a positive bias voltage (for example, 7.5 volts), and the bases (P-type wells) of transistors M21~M24 430 are each applied with a negative bias voltage (eg -4.5 volts). In addition, the bit line switch BLT2 corresponding to the selected memory cell SMC is a selected bit line switch and is turned on. The remaining bit line switches BLT0, BLT1, BLT3 are turned off. The bit line switch BLT2 provides a positive first voltage to the bit line LBL2 corresponding to the selected memory cell SMC according to the voltage on the common bit line GBL. The voltage on the common bit line GBL is equal to 7.5 volts, for example. The bit line switch BLT2 can provide a positive first voltage (eg equal to 7.5V) to the bit line LBL2. The bit lines LBL0, LBL1, and LBL3 are in a floating state.

In addition, the source line switch SLT2 corresponding to the selected memory cell SMC is set as the selected source line switch and turned off. The remaining source line switches SLT0 , SLT1 , SLT3 are turned on. Here, the voltage on the common source line CSL is equal to -4.5 volts, for example. The turned-on source line switches SLT0 , SLT1 , SLT3 can provide a negative second voltage (for example equal to -4.5 volts) to the source lines LSL0 , LSL1 , LSL3 corresponding to the unselected memory cells. Here, the source line LSL2 is in a floating state.

In addition, the word line voltage on the word line WL0_0 corresponding to the selected memory cell SMC can be set to -12.5 volts, and the word line voltages on the other word lines WL1_0 , WL1_1 , WL0_1 can be set to 1.5 volts. In this way, the selected memory cell SMC can withstand an erasing bias voltage of -20 volts (during the erasing operation, the voltage difference between the word line and the bit line (or source line) corresponding to the memory cell), it can Efficiently perform the action of erasing.

Regarding other unselected memory cells, the memory cells corresponding to unselected bit lines, unselected source lines and unselected word lines can have an erase bias of 6 volts; corresponding to unselected bit lines line, unselected source line and selected word line memory cell, its erase bias can be -8 volts; corresponding to the selected bit line, selected source line and unselected word line memory cell, Its erase bias can be -6 volts. The above-mentioned unselected memory cells can be effectively covered without being disturbed by the erasing action.

In FIG. 5D , the 3D memory device 500 performs a block erase operation. Multiple memory cells in the selected memory cell block SMB are simultaneously selected to perform an erasing action.

In the block erase operation, the bases (N-type well regions) 420 of the transistors M11 - M14 may be applied with a bias voltage of 10 volts. The bases (P-type well regions) 430 of the transistors M21 - M24 can be applied with a bias voltage of 0 volts. The voltage on the common bit line GBL may be about 10 volts, and the voltage on the common source line CSL may be 13 volts.

In addition, the source line switches SLT0 - SLT3 and the bit line switches BLT0 - BLT3 are all turned on. The voltages on the source lines LSL0~LSL3 are all positive 10 volts. And based on the floor effect, the voltage on the bit lines LBL0 - LBL3 can also be a positive value of 10 volts.

In addition, the word line voltages on the word lines WL0_0 and WL0_1 of the selected memory cell block SMB can be set to -10 volts, and the word line voltages on the other word lines WL1_0 and WL1_1 can be set to 4 volts . In this way, the memory cells in the selected memory cell block SMB can bear the erasing bias voltage up to -20 volts, and can effectively execute the erasing operation. The remaining memory cells that have not been erased can withstand an erase bias of -6 volts and can be shielded from being disturbed by the erase operation.

Please refer to FIG. 6A to FIG. 6D below. FIG. 6A to FIG. 6D are schematic diagrams illustrating access operations of a three-dimensional memory device according to another embodiment of the present invention. In FIG. 6A, in the three-dimensional memory device 600, the transistors M21-M24 serving as the source line switches SLT0-SLT3 and the transistors M11-M14 serving as the bit line switches BLT0-BLT3 are all P-type transistors.

In the read operation, the bases (N-type wells) 420 of the transistors M11-M14 are applied with a bias voltage equal to 1.8 volts, and the bases (N-type wells) 430 of the transistors M21-M24 can also be applied, for example, equal to 1.8 volt bias voltage. Corresponding to the selected memory cell SMC, the bit line LBL2 and the source line LSL2 are respectively the selected bit line and the selected source line, and the bit line switch BLT2 and the source line switch SLT2 are respectively the selected bit line switch and The source line switch is selected and turned on. Bit line switches BLT0, BLT1, BLT3 and source line switches SLT0, SLT1, SLT3 are turned off. At this time, the voltage on the common bit line GBL can be equal to the first voltage, and the turned-on bit line switch BLT2 can provide the first voltage to the bit line LBL2 of the selected memory cell SMC. In addition, at this time, the voltage on the common source line CSL is equal to the second voltage, and the turned-on source line switch SLT2 can provide the second voltage to the source line LSL2 corresponding to the selected memory cell SMC. Wherein, in this embodiment, the first voltage may be a positive value, and the first voltage is greater than the second voltage. For example, the first voltage can be 1 volt, and the second voltage can be 0 volts.

On the other hand, the word line electrical signal on the word line WL0_0 corresponding to the selected memory cell SMC may be equal to the read voltage (eg, 5-7 volts). The word line electrical signals on the other word lines WL0_1 , WL1_0 , WL1_1 not corresponding to the selected memory cell SMC may be equal to 0 volts.

In addition, since the bit line switches BLT0, BLT1, BLT3 and the source line switches SLT0, SLT1, SLT3 are all turned off, the bit lines LBL0, LBL1, LBL3, and the source lines LSL0, LSL1, LSL3 are all floating. connected to ground voltage.

The selected memory cell SMC can transmit current according to the stored data, and is sent to the sense amplifier (not shown) through the bit line LBL2. The sense amplifier can convert the current provided by the selected memory cell SMC into a voltage signal, and compare the voltage signal with a reference voltage to sense the data stored in the selected memory cell SMC.

In FIG. 6B , the 3D memory device 600 executes programmed actions. And through Fowler-Nordheim tunneling (Fowler-Nordheim tunneling) method to adjust the threshold voltage of the selected memory cell SMC, and execute programmed actions.

In the programming operation, the bases of the transistors M11 - M14 and the bases (N-type wells) 420 of the transistors M21 - M24 can be applied with a positive bias voltage (for example, 3.5V). In addition, the bit line switch BLT2 corresponding to the selected memory cell SMC is a selected bit line switch and is turned on. The remaining bit line switches BLT0, BLT1, BLT3 are turned off. The bit line switch BLT2 provides a positive first voltage to the bit line LBL2 corresponding to the selected memory cell SMC. The first voltage is, for example, -7.5 volts. In addition, the source line switch SLT2 corresponding to the selected memory cell SMC is set as the selected source line switch and turned off. The remaining source line switches SLT0 , SLT1 , SLT3 are turned on. The turned-on source line switches SLT0 , SLT1 , SLT3 may provide a second voltage with a positive value approximately equal to 10V (eg equal to 3.5 volts) to the source lines LSL0 , LSL1 , LSL3 . The above-mentioned second voltage is used as an inhibit voltage. Here, the source line LSL2 is in a floating state.

In addition, the word line voltage on the word line WL0_0 corresponding to the selected memory cell SMC can be set to 12.5 volts, and the word line voltages on the other word lines WL1_0 , WL1_1 , WL0_1 can be set to -1.5 volts. In this way, the selected memory cell SMC can withstand a programming bias voltage of up to 20 volts (the voltage difference between the word line and the bit line (or source line) corresponding to the memory cell during the programming action), which can effectively Executes a programmed action.

Regarding other unselected memory cells, memory cells corresponding to unselected bit lines, unselected source lines, and unselected word lines can be programmed with a bias voltage of -5 volts; corresponding to unselected bits The memory cells of the cell line, unselected source line, and selected word line can be programmed with a bias voltage of 9 volts; corresponding to the selected bit line, selected source line, and unselected word line memory cells, Its programming bias can be 6 volts. The above-mentioned unselected memory cells can be effectively masked without being disturbed by stylized actions.

In FIG. 6C , the 3D memory device 600 performs a byte erase operation. The selected memory cell SMC is selected to perform an erase operation based on FN tunneling.

In the byte erase operation, the bases (N-type well regions) 420 and 430 of the transistors M11 - M14 and the transistors M21 - M24 are all applied with a positive bias voltage (for example, 7.5 volts). In addition, the bit line switch BLT2 corresponding to the selected memory cell SMC is a selected bit line switch and is turned on. The remaining bit line switches BLT0, BLT1, BLT3 are turned off. The bit line switch BLT2 provides a positive first voltage to the bit line LBL2 corresponding to the selected memory cell SMC according to the voltage on the common bit line GBL. The voltage on the common bit line GBL is equal to 7.5 volts, for example. The bit line switch BLT2 can provide a positive first voltage (eg equal to 7.5V) to the bit line LBL2. The bit lines LBL0, LBL1, and LBL3 are in a floating state.

In addition, the source line switch SLT2 corresponding to the selected memory cell SMC is set as the selected source line switch and turned off. The remaining source line switches SLT0 , SLT1 , SLT3 are turned on. Here, the voltage on the common source line CSL is equal to -6.5 volts, for example. Based on the base effect, the turned-on source line switches SLT0 , SLT1 , SLT3 can provide a negative second voltage (for example equal to -3.5 volts) to the source lines LSL0 , LSL1 , LSL3 corresponding to the unselected memory cells. Here, the source line LSL2 is in a floating state.

In addition, the word line voltage on the word line WL0_0 corresponding to the selected memory cell SMC can be set to -12.5 volts, and the word line voltages on the other word lines WL1_0 , WL1_1 , WL0_1 can be set to 1.5 volts. In this way, the selected memory cell SMC can withstand an erase bias voltage of -20 volts (during the erase operation, the voltage difference between the word line and the bit line (or source line) corresponding to the memory cell), it can Efficiently perform the action of erasing.

Regarding other unselected memory cells, the memory cells corresponding to unselected bit lines, unselected source lines and unselected word lines can have an erase bias of 5 volts; corresponding to unselected bit lines line, unselected source line and selected word line memory cell, its erase bias can be -9 volts; corresponding to the selected bit line, selected source line and unselected word line memory cell, Its erase bias can be -6 volts. The above-mentioned unselected memory cells can be effectively covered without being disturbed by the erasing action.

In FIG. 6D , the 3D memory device 600 performs a block erase operation. Multiple memory cells in the selected memory cell block SMB are simultaneously selected to perform an erasing action.

In the block erase operation, the bases (N-type well regions) 420 and 430 of the transistors M11 - M14 and the transistors M21 - M24 are all applied with a bias voltage of 10 volts. The voltages on the common bit line GBL and the common source line CSL may both be approximately 10 volts.

In addition, the source line switches SLT0 - SLT3 and the bit line switches BLT0 - BLT3 are all turned on. The voltages on the source lines LSL0~LSL3 are all positive 10 volts. The voltage on the bit lines LBL0-LBL3 can also be a positive value of 10 volts.

In addition, the word line voltages on the word lines WL0_0 and WL0_1 of the selected memory cell block SMB can be set to -10 volts, and the word line voltages on the other word lines WL1_0 and WL1_1 can be set to 4 volts . In this way, the memory cells in the selected memory cell block SMB can bear the erasing bias voltage up to -20 volts, and can effectively execute the erasing operation. The remaining memory cells that have not been erased can withstand an erase bias of -6 volts and can be shielded from being disturbed by the erase operation.

Please note here that the values of the voltages mentioned in the above-mentioned embodiments are only provided for the convenience of illustration, and are not intended to limit the implementation scope of the present invention. Those skilled in the art can set various related voltage values according to the process parameters of the integrated circuit and the voltage range of the operating power supply of the three-dimensional memory device, without any special limitation.

To sum up, in the three-dimensional memory device of the present invention, the bit line switch and the word line switch can be constructed by using a P-type transistor or an N-type transistor with a Mitsui substrate. And by applying the appropriate substrate voltage, the bit line switch and the word line switch can pass positive or negative bit line voltage and source line voltage. In this way, when the memory cell access operation is performed, appropriate voltages can be effectively applied to the selected and unselected memory cells to ensure that the access operation can be performed correctly.

100, 300, 400, 500, 600: three-dimensional memory device 111, 112: memory cell array 120, 130, 320, 330, 420, 430, 520, 530, 620, 630: Base 200: N-type transistor 210: N-type deep well area 220: P-type well area 230:N type well area 231, 232: N-type heavily doped regions 233: P-type heavily doped region 245: Insulation structure 250:Gate structure BLT0~BLT3: bit line switch CSL: common source line CT: connection structure GBL: common bit line LBL0~LBL3: bit line LSL0~LSL3: source line M11~M24: Transistor MC1, MC2: memory cells SEL_BLT0~SEL_BLT3, SEL_SLT0~SEL_SLT3: selection signal SLT0~SLT3: Source line switch SMB: Select memory cell block SMC: selected memory cell WL0_0~WL1_1: word line

FIG. 1 is a schematic diagram of a three-dimensional memory device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an implementation of an N-type transistor with a Mitsui substrate in a three-dimensional memory device according to an embodiment of the present invention. 3A to 3D are schematic diagrams illustrating the access operations of the three-dimensional memory device according to the embodiment of the present invention. 4A to 4D are schematic diagrams illustrating access operations of a three-dimensional memory device according to another embodiment of the present invention. 5A to 5D are schematic diagrams illustrating access operations of a three-dimensional memory device according to another embodiment of the present invention. 6A to 6D are schematic diagrams illustrating access operations of a three-dimensional memory device according to another embodiment of the present invention.

100: Three-dimensional memory device

111, 112: memory cell array

120, 130: base

BLT0~BLT3: bit line switch

CSL: common source line

GBL: common bit line

LBL0~LBL3: bit line

LSL0~LSL3: source line

M11~M24: Transistor

MC1, MC2: memory cells

SEL_BLT0~SEL_BLT3, SEL_SLT0~SEL_SLT3: selection signal

SLT0~SLT3: Source line switch

WL0_0~WL1_1: word line

Claims (20)

A three-dimensional memory device, comprising: a plurality of memory cell arrays, the memory cell arrays have a plurality of corresponding memory cell rows, and the memory cell rows are respectively coupled to a plurality of source lines and a plurality of bit lines; A plurality of bit line switches are respectively composed of a plurality of first transistors, the first terminals of the first transistors are coupled to a common bit line, and the second terminals of the first transistors are respectively coupled to to the bit lines; and A plurality of source line switches are respectively composed of a plurality of second transistors, the first terminals of the second transistors are coupled to a common source line, and the second terminals of the second transistors are respectively coupled to to the source lines, Wherein, the first transistors are P-type transistors or N-type transistors with a Mitsui base, and the second transistors are P-type transistors or N-type transistors with a Mitsui base. The three-dimensional memory device as claimed in item 1, wherein the first transistors are controlled by a plurality of first selection signals to be turned on or off, and the second transistors are controlled by a plurality of second selection signals to be turned on or off. The three-dimensional memory device as claimed in claim 1, wherein the on/off states of the bit line switches and the source line switches corresponding to the same memory cell row are the same. The three-dimensional memory device according to claim 1, wherein the memory cell arrays are divided into a plurality of memory cell rows, and the memory cell rows respectively receive a plurality of word line signals. The three-dimensional memory device according to claim 4, wherein in the read operation, a selected bit line switch corresponding to a selected memory cell is turned on and provides a first voltage to the selected memory cell, corresponding to the selected memory cell A selected source line switch of the selected memory cell is turned on and provides a second voltage to the selected memory cell, wherein the first voltage is greater than the second voltage. The three-dimensional memory device as described in claim 4, wherein each of the first transistors and each of the second transistors is an N-type transistor with a Mitsui region substrate, and corresponds to a selected memory cell in the programming action A selected bit line switch of the selected memory cell is turned on and provides a negative first voltage to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, and the remaining multiple unselected The middle source line switch is turned on and provides a second voltage with a positive value to a plurality of unselected memory cells. Among the word line signals, the selected word signal corresponding to the selected memory cell is the third with a positive value. voltage, and the remaining multiple unselected character signals are negative fourth voltages. The three-dimensional memory device as described in claim item 4, wherein each of the first transistors and each of the second transistors is an N-type transistor with a Mitsui base, and in the byte erasing operation, corresponding to a selected A selected bit line switch of the middle memory cell is turned on and a first positive voltage is provided to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, and a plurality of The unselected source line switch is turned on and provides a second negative voltage to a plurality of unselected memory cells. Among the word line signals, the selected word signal corresponding to the selected memory cell is negative. The third voltage is a fourth voltage in which the plurality of unselected character signals are positive. The three-dimensional memory device as described in claim 4, wherein each of the first transistors and each of the second transistors is an N-type transistor with a Mitsui base, and in the block erase operation, the bits Both the line switches and the source line switches are turned on, and respectively provide a positive first voltage to the memory cells, and a plurality of selected character signals corresponding to a selected memory cell block are negative. The second voltage is a third voltage corresponding to a plurality of selected word signals of at least one unselected memory cell block being positive. The three-dimensional memory device as described in claim 4, wherein each of the first transistors is an N-type transistor with a Mitsui base, and each of the second transistors is a P-type transistor. In the stylized action, corresponding to a A selected bit line switch of the selected memory cell is turned on and a first negative voltage is provided to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, and a plurality of The unselected source line switch is turned on and provides a second positive voltage to a plurality of unselected memory cells. Among the word line signals, the selected word signal corresponding to the selected memory cell is positive. The third voltage is a fourth voltage in which the plurality of unselected character signals are negative. The three-dimensional memory device as described in claim 4, wherein each of the first transistors is an N-type transistor with a Mitsui base, each of the second transistors is a P-type transistor, and in the byte erasing operation , a selected bit line switch corresponding to a selected memory cell is turned off, a plurality of unselected bit line switches are turned on and a first voltage of a negative value is provided to a plurality of unselected memory cells, corresponding to the selected A selected source line switch of the middle memory cell is turned on and provides a second positive voltage to the selected memory cell. Among the word line signals, the selected word signal corresponding to the selected memory cell is The third voltage is a negative value, and the plurality of unselected character signals are a fourth voltage with a positive value. The three-dimensional memory device as described in claim 4, wherein each of the first transistors is an N-type transistor with a Mitsui base, each of the second transistors is a P-type transistor, and in the block erase operation, The bit line switches and the source line switches are all turned on, and provide a positive first voltage to the memory cells respectively, and a plurality of selected character signals corresponding to a selected memory cell block are as follows: A second voltage with a negative value corresponds to a third voltage with a positive value for the plurality of selected character signals of at least one unselected memory cell block. The three-dimensional memory device as described in claim 4, wherein each of the first transistors is a P-type transistor, and each of the second transistors is an N-type transistor with a Mitsui base, and in the stylized action, corresponding to a A selected bit line switch of the selected memory cell is turned on and provides a positive first voltage to the selected memory cell, and a selected source line switch corresponding to the selected memory cell is turned on and provided as a negative voltage. A second voltage of value to the selected memory cell, among the word line signals, the selected word signal corresponding to the selected memory cell is a third voltage with a positive value, and a plurality of unselected word signals are negative The fourth voltage. The three-dimensional memory device as described in claim 4, wherein each of the first transistors is a P-type transistor, and each of the second transistors is an N-type transistor with a Mitsui base, and in the byte erasing operation , a selected bit line switch corresponding to a selected memory cell is turned on and a first positive voltage is provided to the selected memory cell, and a selected source line switch corresponding to the selected memory cell is turned off open, a plurality of unselected source line switches are turned on and provide a second negative voltage to a plurality of unselected memory cells, among the word line signals, the selected word signal corresponding to the selected memory cell The third voltage is a negative value, and the plurality of unselected character signals are a fourth voltage with a positive value. The three-dimensional memory device as claimed in item 4, wherein each of the first transistors is a P-type transistor, each of the second transistors is an N-type transistor with a Mitsui base, and in the block erase operation, The bit line switches and the source line switches are all turned on, and provide a positive first voltage to the memory cells respectively, and a plurality of selected character signals corresponding to a selected memory cell block are as follows: A second voltage with a negative value corresponds to a third voltage with a positive value for the plurality of selected character signals of at least one unselected memory cell block. The three-dimensional memory device as described in claim 4, wherein the first transistors and the second transistors are all P-type transistors, and in the programming action, they correspond to a selected bit of a selected memory cell The source line switch is turned on and provides a negative first voltage to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, and a plurality of unselected source line switches are turned on And provide a second voltage with a positive value to a plurality of unselected memory cells. Among the word line signals, the selected word signal corresponding to the selected memory cell is a third voltage with a positive value. The character signal is a fourth voltage with a negative value. The three-dimensional memory device as described in claim 4, wherein the first transistors and the second transistors are all P-type transistors, and in the byte erasing operation, one corresponding to a selected memory cell The selected bit line switch is turned on and provides a positive first voltage to the selected memory cell, a selected source line switch corresponding to the selected memory cell is turned off, and a plurality of unselected sources The line switch is turned on and provides a negative second voltage to a plurality of unselected memory cells. Among the word line signals, the third voltage corresponding to the selected word signal of the selected memory cell is a negative value. A fourth voltage with a positive value for the unselected character signal. The three-dimensional memory device according to claim 4, wherein the first transistors and the second transistors are all P-type transistors, and in block erase operation, the bit line switches and the The source line switches are all turned on, and respectively provide a first voltage with a positive value to the memory cells, corresponding to a second voltage with a negative value corresponding to a plurality of selected character signals of a selected memory cell block The plurality of selected character signals of at least one unselected memory cell block is a third voltage with a positive value. The three-dimensional memory device according to claim 1, wherein the memory cell arrays are NAND flash memory cell arrays. The three-dimensional memory device as claimed in claim 1, wherein each of the source lines is coupled to the common source line only through the corresponding source line switches, and each of the bit lines is only coupled to the corresponding source line Each of the bit line switches is coupled to the common bit line. The three-dimensional memory device as claimed in claim 1, wherein each of the second transistors that are N-type transistors with a Mitsui base includes: - N-type deep well area; A P-type well area formed on the N-type deep well area; An N-type well formed on the side of the P-type well; A first N-type heavily doped region, a second N-type heavily doped region and a P-type heavily doped region are formed on the P-type well region, the first N-type heavily doped region and the second N-type heavily doped region The N-type heavily doped region forms a channel, and the P-type heavily doped region is used to receive a bias voltage; and A gate structure is formed on the first N-type heavily doped region, the second N-type heavily doped region and the channel.

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