TWI785773B - Three dimension memory device and ternary content addressable memory cell thereof - Google Patents

Abstract

A three dimension memory device and a ternary content addressable memory cell are provided. The ternary content addressable memory cell includes a first memory cell, a second memory cell, a first search switch and a second search switch. The first memory is disposed in a first AND flash memory line. The second memory is disposed in a second AND flash memory line. The first search switch is coupled between a first bit line corresponding to the first AND flash memory line and a match line, and controlled by a first search signal to be turned on or cut-off. The second search switch is coupled between a second bit line corresponding to the second AND flash memory line and the match line, and controlled by a first search signal to be turned on or cut-off.

Description

Three-dimensional memory device and its three-state content-addressable memory cell

The present invention relates to a three-dimensional memory device and its tri-state content-addressable memory cell, and in particular to a three-dimensional memory device and its tri-state content-addressable memory cell which can save power consumption during a search operation .

In electronic devices, in order to provide high-expression look-up tables, high-density and high-speed 3-state content addressable memory cells have become an important architecture.

The use of non-volatile memory to construct 3-state content-addressable memory cells is a common choice. However, the electrical characteristics of non-volatile memory, such as bit error rate, is an important parameter to consider.

In the conventional technical field, it is common to use a Negative OR (NOR) type flash memory to construct a three-state content-addressable memory cell. However, due to the limitation of the circuit structure of the NOR flash memory, it is difficult to use the NOR flash memory to set up a three-state content addressable memory cell with a high enough density.

The invention provides a three-dimensional memory device and its three-state content addressable memory cell, which can reduce the power consumption required for searching.

The three-state content addressable memory cell of the present invention includes a first memory cell, a second memory cell, a first search switch and a second search switch. The first memory cell is set in the first and second flash memory cell rows. The second memory cell is arranged in the second and second flash memory cell rows. The first search switch is coupled between the first bit line and the match line corresponding to the first and type flash memory cell rows, and the first search switch is controlled by the first search signal to be turned on or off. The second search switch is coupled between the second bit line and the match line corresponding to the second and type flash memory cell rows, and the second search switch is controlled by the second search signal to be turned on or off.

The three-dimensional memory device of the present invention includes a flash memory bank and at least one tri-state content-addressable memory cell. The flash memory bank includes at least one memory cell array block. The tri-state content addressable memory cells include a first memory cell, a second memory cell, a first search switch and a second search switch. The first memory cell is set in the first and second flash memory cell rows. The second memory cell is arranged in the second and second flash memory cell rows. The first search switch is coupled between the first bit line and the match line corresponding to the first and type flash memory cell rows, and the first search switch is controlled by the first search signal to be turned on or off. The second search switch is coupled between the second bit line and the match line corresponding to the second and type flash memory cell rows, and the second search switch is controlled by the second search signal to be turned on or off.

Based on the above, the present invention combines two memory cells in different NAND-type flash memory cell rows in a three-dimensional memory device, and cooperates with corresponding bit line switches to form a three-state content addressable memory cell. Wherein, the bit line switch is used as a search switch, which can reduce the power consumption required by the three-state content addressable memory cell during the search operation. Moreover, using the bit line switch as a search switch not only saves layout area, but also improves reliability and effectively improves the overall performance of the three-state content addressable memory cell.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a tri-state content-addressable memory cell according to an embodiment of the present invention. The tri-state content addressable memory cell 100 is disposed in an AND type flash memory device. The tri-state content addressable memory cell 100 includes memory cells MC1 , MC2 , search switches BLT1 , BLT2 , and source line switches SLT1 and SLT2 . In this embodiment, the search switches BLT1 and BLT2 and the source line switches SLT1 and SLT2 can be constructed using transistors, such as N-type transistors. The memory cells MC1 and MC2 can be flash memory cells.

The memory cells MC1 and MC2 are respectively arranged in different flash memory cell rows 110 and 120 . The search switch BLT1 is coupled between the bit line LBL1 corresponding to the NAND flash memory cell row 110 and the match line ML. The search switch BLT2 is coupled between the bit line LBL2 corresponding to the NAND flash memory cell row 120 and the match line ML. In this embodiment, the search switches BLT1 and BLT2 are bit line switches of a flash memory device, and the match line ML can be a global bit line. The search switch BLT1 is controlled by the search signal SL to be turned on or off, and the search switch BLT2 is controlled by the search signal SLB to be turned on or off. Wherein, based on different search conditions, the search signals SL and SLB can be different voltage combinations. For example, when performing a search operation for a first logic state (for example, logic 1), the search signals SL and SLB can be logic high voltage and logic low voltage respectively; when performing a search operation for a second logic state (for example, logic 0) , the search signals SL and SLB can be logic low voltage and logic high voltage respectively; when performing the search action of the third logic state (for example, don’t care), the search signals SL and SLB can both be logic low Voltage.

On the other hand, the source line switch SLT1 is coupled between the source line LSL1 corresponding to the flash memory cell row 110 and the reference ground voltage VSS. The source line switch SLT2 is coupled between the source line LSL2 corresponding to the flash memory cell row 120 and the reference ground voltage VSS. The source line switches SLT1 and SLT2 are controlled by control signals CT1 and CT2 respectively. When the search operation of the tri-state content addressable memory cell 100 is in progress, the source line switches SLT1, SLT2 can be turned on according to the control signals CT1, CT2. Wherein, the source line switches SLT1 and SLT2 may be coupled to a common source line and receive the reference ground voltage VSS through the common source line.

In this embodiment, the memory cells MC1 and MC2 are coupled to the same word line WL0. In other embodiments of the present invention, the memory cells MC1 and MC2 may also be respectively coupled to different word lines, without any limitation.

Please refer to FIG. 2 below. FIG. 2 shows a schematic diagram of an equivalent circuit of the tri-state content addressable memory cell 100 of the embodiment of the present invention shown in FIG. 1 . When the search operation is performed, since the source line switches SLT1 and SLT2 are both turned on, one terminal of the memory cells MC1 and MC2 can receive the reference ground voltage VSS. The other ends of the memory cells MC1 and MC2 are respectively coupled to the search switches BLT1 and BLT2. The search switches BLT1 and BLT2 are coupled between the memory cells MC1 and MC2 and the match line ML. Wherein, the search switches BLT1 and BLT2 are respectively controlled by the search signals SL and SLB.

For the details of the search operation, please refer to FIGS. 3A to 5C . FIGS. 3A to 5C are respectively schematic diagrams illustrating the implementation of the search operation of the 3-state content addressable memory cell according to the embodiment of the present invention. In FIGS. 3A to 3C , the tri-state content-addressable memory cell 300 records data in the first logic state, wherein the memory cell MC1 is in the state of being programmed, and the memory cell MC2 is in the state of being erased ( Erase). In an initial time period before the search operation of the first logic state is performed, the match signal on the match line ML may be precharged to a reference voltage, wherein the reference voltage is greater than the reference ground voltage VSS.

In FIG. 3A , when the search operation of the first logic state is in progress, the search signal SL is at a logic high voltage, and the search signal SLB is at a logic low voltage. At this time, since the memory cell MC1 is turned off and the search switch BLT2 is also turned off, there is no conduction path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML is essentially can remain unchanged at the level of the reference voltage. At this point, it may be determined that the search result of the search action in the first logic state is a match.

In FIG. 3B , when the search operation of the second logic state is in progress, the search signal SL is at a logic low voltage, and the search signal SLB is at a logic high voltage. At this time, based on the state that both the memory cell MC2 and the search switch BLT2 are turned on, the memory cell MC2 and the search switch BLT2 form a conduction path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML can drop to be equal to the reference ground voltage VSS. At this point, it may be determined that the search result of the search action in the second logic state is an un-match.

In FIG. 3C , when the search operation of the third logic state is in progress, the search signal SL is at a logic low voltage, and the search signal SLB is also at a logic low voltage. At this time, since the memory cell MC1, the search switches BLT2 and BLT1 are all in the off state, there is no conduction path between the match line ML and the reference ground voltage VSS, therefore, the match signal on the match line ML can be substantially maintained at The level of the reference voltage does not change. At this point, it may be determined that the search result of the search action in the third logic state is a match.

In FIGS. 4A to 4C , the tri-state content-addressable memory cell 400 records data in the second logic state, wherein the memory cell MC2 is in the programmed state, and the memory cell MC1 is in the erased state. In an initial time interval before the search operation of the first logic state is performed, the match signal on the match line ML may be precharged to a reference voltage. Wherein, the reference voltage is greater than the reference ground voltage VSS.

In FIG. 4A , when the search operation of the first logic state is in progress, the search signal SL is at a logic high voltage, and the search signal SLB is at a logic low voltage. At this time, based on the state that both the memory cell MC1 and the search switch BLT1 are turned on, the memory cell MC1 and the search switch BLT1 form a conduction path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML can drop to be equal to the reference ground voltage VSS. At this time, it may be determined that the search result of the search action in the second logic state is mismatch.

In FIG. 4B , when the search operation of the second logic state is in progress, the search signal SL is at a logic low voltage, and the search signal SLB is at a logic high voltage. At this time, since both the memory cell MC2 and the search switch BLT1 are turned off, there is no conduction path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML can remain equal to the reference voltage without changing. At this point, it may be determined that the search result of the search action in the second logic state is a match.

In FIG. 4C , when the search operation of the third logic state is in progress, the search signal SL is at a logic low voltage, and the search signal SLB is also at a logic low voltage. At this time, since the memory cell MC2, the search switches BLT2 and BLT1 are all turned off, there is no conduction path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML can be substantially maintained at The level of the reference voltage does not change. At this point, it may be determined that the search result of the search action in the third logic state is a match.

In FIG. 5A to FIG. 5C , the tri-state content-addressable memory cell 500 records the data in the third logical state, and the memory cells MC1 and MC2 are both programmed. In an initial time interval before the search operation of the third logic state is performed, the match signal on the match line ML may be precharged to a reference voltage, wherein the reference voltage is greater than the reference ground voltage VSS.

In FIG. 5A , when the search operation of the first logic state is in progress, the search signal SL is at a logic high voltage, and the search signal SLB is at a logic low voltage. At this time, since both the memory cells MC1 and MC2 are turned off, and the search switch BLT2 is also turned off, there is no conduction path between the matching line ML and the reference ground voltage VSS. Therefore, the matching line ML The matching signal can substantially maintain the level of the reference voltage unchanged. At this point, it may be determined that the search result of the search action in the first logic state is a match.

In FIG. 5B , when the search operation of the second logic state is in progress, the search signal SL is at a logic low voltage, and the search signal SLB is at a logic high voltage. At this time, since the memory cells MC1, MC2 and the search switch BLT1 are all turned off, there is no conduction path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML can be substantially maintained at The level of the reference voltage does not change. At this point, it may be determined that the search result of the search action in the third logic state is a match.

In FIG. 5C , when the search operation of the third logic state is in progress, the search signal SL is at a logic low voltage, and the search signal SLB is also at a logic low voltage. At this time, since the memory cells MC1, MC2, the search switches BLT2 and BLT1 are all turned off, there is no conduction path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML can be substantially turned off. The level of the reference voltage remains unchanged. At this point, it may be determined that the search result of the search action in the third logic state is a match.

It is worth mentioning that in the embodiments shown in FIG. 3A to FIG. 5C , the first logic state is complementary to the second logic state, and the third logic state is don't care. In detail, the first logic state may be logic 1 (or logic 0), and the second logic state may be logic 0 (or logic 1).

In addition, in other embodiments of the present invention, in various states of the search operation, the setting of the voltage values of the search signals SL and SLB may be different from the above description. in. In other embodiments of the present invention, in the search operation of the first logic state, the search signals SL and SLB can be logic low voltage and logic high voltage respectively; in the search operation of the second logic state, the search signals SL and SLB can be respectively are logic high voltage and logic low voltage; in the search action of the third logic state, the search signals SL and SLB can be respectively logic high voltage. In addition, when the three-state content-addressable memory cell records the data of the third logic state, the memory cells MC1 and MC2 are both in the state of being erased. Under such conditions, in the search action of the logic state, when the matching signal on the matching line ML remains equal to the reference voltage, it indicates that the search result is a mismatch; and when the matching signal on the matching line ML drops to the reference ground voltage , indicating that the search result is a match.

Please refer to FIG. 6A and FIG. 6B below. FIG. 6A and FIG. 6B are schematic diagrams illustrating different implementations of the three-dimensional memory device and the arrangement of the search switch of the three-state content addressable memory cell according to the embodiment of the present invention. In FIG. 6A , the three-dimensional memory device 600 has a memory bank (bank), and the memory bank includes a plurality of memory cell array blocks (tiles) TL1 and TL2 . The memory cell array blocks TL1, TL2 have corresponding bit line switch areas 610, 620, respectively. The bit line switch area 610 has bit line switches BLT5 - BLT8 , and the bit line switch area 620 has bit line switches BLT1 - BLT4 .

Wherein, one or more three-state content-addressable memory cells can be set in the three-dimensional memory device 600 . In this embodiment, corresponding to one of the three-state content addressable memory cells, the bit line switches BLT1 and BLT2 can be used as two search switches of the three-state content addressable memory cell. That is to say, two search switches corresponding to the same tri-state content addressable memory cell can be set in the same memory cell array block TL2. Wherein, the bit line switches BLT1 and BLT2 are respectively controlled by the search signals SL and SLB.

It is worth mentioning that, in this embodiment, the bit line switches BLT1 - BLT4 and the bit line switches BLT5 - BLT8 can be commonly coupled to the common bit line GBL.

In FIG. 6B , the two search switches corresponding to a tri-state content addressable memory cell can be bit line switches BLT1 and BLT5 . That is to say, the two search switches corresponding to the same tri-state content-addressable memory cell can also be respectively disposed in different memory cell array blocks TL1 and TL2 . Wherein, the bit line switches BLT1 and BLT5 are respectively controlled by the search signals SL and SLB.

Please refer to FIG. 7 below. FIG. 7 shows a schematic diagram of different implementations of the three-dimensional memory device and the arrangement of the three-state content addressable memory cells according to the embodiment of the present invention. In FIG. 7 , the three-dimensional memory device 700 has a memory bank (bank), and the memory bank includes a plurality of memory cell array blocks (tiles) TL1 and TL2 . The memory cell array blocks TL1, TL2 have corresponding bit line switch areas 710, 720, respectively. The bit line switch area 710 has bit line switches BLT51~BLT81 and BLT52~BLT82, and the bit line switch area 720 has bit line switches BLT11~BLT41 and BLT12~BLT42.

In this embodiment, a plurality of tri-state content-addressable memory cells can be set in the three-dimensional memory device 700 . Wherein, the first tri-state content-addressable memory cell includes memory cells MC1 and MC2. The memory cells MC1 and MC2 are arranged in the same memory cell array block TL2. Moreover, the memory cells MC1 and MC2 are arranged in pairs on two adjacent memory cell rows. Corresponding to the memory cells MC1 and MC2, the bit line switches BT21 and BT31 can be used as search switches. The bit line switches BT21 and BT31 are commonly coupled to a common bit line GBL. Wherein, the common bit line GBL can be used as a match line of the tri-state content-addressable memory cell.

In addition, the second tri-state content-addressable memory cell includes memory cells MC3 and MC4. The memory cells MC3 and MC4 are arranged in different memory cell array blocks TL1 and TL2 respectively. Corresponding to the memory cells MC3 and MC4, the bit line switches BT12 and BT52 can be used as search switches. It should be noted that the bit line switches BT12 and BT52 are commonly coupled to the common bit line GBL, wherein the common bit line GBL can be used as a match line of the tri-state content addressable memory cell.

It is worth mentioning that, in the embodiment of the present invention, one or more tri-state content addressable memory cells may be set in the three-dimensional memory device. A three-dimensional memory device may have multiple memory cell array blocks. A plurality of tri-state content addressable memory cells can all be arranged in a single memory cell array block; or, they can also be distributed in a plurality of different memory cell array blocks, without certain limitation.

To sum up, the tri-state content addressable memory cell of the present invention is disposed in a flash memory device. By using bit line switches as search switches and using common bit lines as match lines. In this way, the voltage of the search signal received by the search switch can be lower than the voltage of the corresponding word line, which can save the required power consumption. Alternatively, a single bit line switch can be implemented using a single transistor. Moreover, under the premise that the voltage of the search signal does not need to be increased, the setting of a voltage shifter (level shifter) circuit can be dispensed with, thereby effectively reducing the circuit area. In addition, in the search operation, the search switch provides at most one current path to pass through the corresponding bit line, which effectively improves the reliability of the circuit.

100, 300, 400, 500: three-state content addressable memory cells 110, 120: NAND flash memory cell row 600, 700: three-dimensional memory device 610, 620, 710, 720: bit line switch area BLT1, BLT2: search switch/bit line switch BLT3~BLT8, BLT51~BLT81, BLT52~BLT82: bit line switch CT1, CT2: control signal GBL: common bit line LBL1, LBL2: bit line LSL1, LSL2: source line MC1, MC2: memory cells ML: Matching Line SL, SLB: search signal SLT1, SLT2: Source line switch TL1, TL2: memory cell array block VSS: reference ground voltage WL0: word line

FIG. 1 is a schematic diagram of a tri-state content addressable memory cell according to an embodiment of the present invention. FIG. 2 is a schematic diagram of an equivalent circuit of the tri-state content-addressable memory cell 100 of the embodiment of the present invention shown in FIG. 1 . FIG. 3A to FIG. 5C are schematic diagrams respectively showing the implementation manners of the search operation of the tri-state content-addressable memory cell according to the embodiment of the present invention. FIG. 6A and FIG. 6B are schematic diagrams of different implementations of the arrangement of the search switches of the three-dimensional memory device and the three-state content-addressable memory cells of the embodiment of the present invention. FIG. 7 is a schematic diagram of different implementations of a three-dimensional memory device and three-state content-addressable memory cells according to an embodiment of the present invention.

100: Tri-state content addressable memory cell

110, 120: NAND flash memory cell row

BLT1, BLT2: search switch

CT1, CT2: control signal

LBL1, LBL2: bit line

LSL1, LSL2: source line

MC1, MC2: memory cells

ML: Matching Line

SL, SLB: search signal

SLT1, SLT2: Source line switch

VSS: reference ground voltage

WL0: word line

Claims (10)

A tri-state content addressable memory cell comprising: A first memory cell, arranged in a first and second flash memory cell row; A second memory cell, arranged in a second flash memory cell row; A first search switch, coupled between a first bit line and a match line corresponding to the first and type flash memory cell rows, the first search switch is controlled by a first search signal to be turned on or disconnect; and A second search switch, coupled between a second bit line corresponding to the second and type flash memory cell row and the match line, the second search switch is controlled by a second search signal to be turned on or disconnect. The tri-state content-addressable memory cell described in claim 1 further includes: a first source line switch, coupled between a first source line corresponding to the first and the second flash memory cell row and a reference ground voltage, the first source line switch is controlled by a control signal to is turned on or off; and A second source line switch, coupled between a second source line corresponding to the second and type flash memory cell row and the reference ground voltage, the second source line switch is controlled by the control signal to is turned on or off. The tri-state content addressable memory cell as claimed in claim 1, wherein the first memory cell and the second memory cell are coupled to the same word line, or respectively coupled to two different word lines. The tri-state content addressable memory cell as recited in claim 1, wherein the first seek switch comprises: A first transistor, the first terminal of the first transistor is coupled to the first bit line, the second terminal of the first transistor is coupled to the matching line, and the control terminal of the first transistor receives to the first search signal, Wherein the second search switch includes: A second transistor, the first terminal of the second transistor is coupled to the second bit line, the second terminal of the second transistor is coupled to the matching line, and the control terminal of the second transistor receives to the second search signal. The tri-state content addressable memory cell as claimed in claim 1, wherein a match signal on the match line is precharged to a reference voltage during an initial time period during which a search operation is performed. The tri-state content-addressable memory cell according to claim 1, wherein the matching line is a common bit line of a flash memory bank. A three-dimensional memory device, comprising: a flash memory bank comprising at least one memory cell array block; and At least one tri-state content-addressable memory cell, including: A first memory cell, arranged in a first and second flash memory cell row; A second memory cell, arranged in a second flash memory cell row; A first search switch, coupled between a first bit line and a match line corresponding to the first and type flash memory cell rows, the first search switch is controlled by a first search signal to be turned on or disconnect; and A second search switch, coupled between a second bit line corresponding to the second and type flash memory cell row and the match line, the second search switch is controlled by a second search signal to be turned on or disconnect. The three-dimensional memory device as claimed in claim 7, wherein the first and type flash memory cell rows and the second and type flash memory cell rows are located in the same first memory cell array block, or, The first and type flash memory cell row and the second and type flash memory cell row are respectively located in a different first memory cell array block and a second memory cell array block. The three-dimensional memory device according to claim 7, wherein the first search switch and the second search switch are set in the same first memory cell array block, or are respectively set in different first memory cells The array block and the second memory cell array block. The three-dimensional memory device as claimed in claim 7, wherein the at least one tri-state content-addressable memory cell further comprises: a first source line switch, coupled between a first source line corresponding to the first and the second flash memory cell row and a reference ground voltage, the first source line switch is controlled by a control signal to is turned on or off; and A second source line switch, coupled between a second source line corresponding to the second and type flash memory cell row and the reference ground voltage, the second source line switch is controlled by the control signal to is turned on or off.

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