TWI785773B - Three dimension memory device and ternary content addressable memory cell thereof - Google Patents
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本發明是有關於一種三維記憶體裝置及其三態內容可定址記憶胞,且特別是有關於一種在搜尋動作中,可更節省功耗的三維記憶體裝置及其三態內容可定址記憶胞。The present invention relates to a three-dimensional memory device and its tri-state content-addressable memory cell, and in particular to a three-dimensional memory device and its tri-state content-addressable memory cell which can save power consumption during a search operation .
在電子裝置中,為了提供高表現度的查找表,高密度以及高速度的三態內容可定址記憶胞成為一種重要的架構。In electronic devices, in order to provide high-expression look-up tables, high-density and high-speed 3-state content addressable memory cells have become an important architecture.
利用非揮發性記憶體來建構三態內容可定址記憶胞是一種常見的選擇。然而,非揮發性記憶體的電氣特性,例如位元錯誤率,是一個需要考慮的重要參數。The use of non-volatile memory to construct 3-state content-addressable memory cells is a common choice. However, the electrical characteristics of non-volatile memory, such as bit error rate, is an important parameter to consider.
習知技術領域中,常見利用反或(NOR)型快閃記憶體來建構三態內容可定址記憶胞。然而,受限於反或型快閃記憶體的電路架構,利用反或型快閃記憶體設置具有足夠高密度的三態內容可定址記憶胞列,有一定的難度。In the conventional technical field, it is common to use a Negative OR (NOR) type flash memory to construct a three-state content-addressable memory cell. However, due to the limitation of the circuit structure of the NOR flash memory, it is difficult to use the NOR flash memory to set up a three-state content addressable memory cell with a high enough density.
本發明提供一種三維記憶體裝置及其三態內容可定址記憶胞,可降低搜尋動作時所需要的功率消耗。The invention provides a three-dimensional memory device and its three-state content addressable memory cell, which can reduce the power consumption required for searching.
本發明的三態內容可定址記憶胞包括第一記憶胞、第二記憶胞、第一搜尋開關以及第二搜尋開關。第一記憶胞設置在第一及式快閃記憶胞行中。第二記憶胞設置在第二及式快閃記憶胞行中。第一搜尋開關耦接在第一及式快閃記憶胞行對應的第一位元線以及匹配線間,第一搜尋開關受控於第一搜尋信號以被導通或斷開。第二搜尋開關耦接在第二及式快閃記憶胞行對應的第二位元線以及匹配線間,第二搜尋開關受控於第二搜尋信號以被導通或斷開。The three-state content addressable memory cell of the present invention includes a first memory cell, a second memory cell, a first search switch and a second search switch. The first memory cell is set in the first and second flash memory cell rows. The second memory cell is arranged in the second and second flash memory cell rows. The first search switch is coupled between the first bit line and the match line corresponding to the first and type flash memory cell rows, and the first search switch is controlled by the first search signal to be turned on or off. The second search switch is coupled between the second bit line and the match line corresponding to the second and type flash memory cell rows, and the second search switch is controlled by the second search signal to be turned on or off.
本發明的三維記憶體裝置包括及式快閃記憶庫以及至少一三態內容可定址記憶胞。及式快閃記憶庫包括至少一記憶胞陣列區塊。三態內容可定址記憶胞包括第一記憶胞、第二記憶胞、第一搜尋開關以及第二搜尋開關。第一記憶胞設置在第一及式快閃記憶胞行中。第二記憶胞設置在第二及式快閃記憶胞行中。第一搜尋開關耦接在第一及式快閃記憶胞行對應的第一位元線以及匹配線間,第一搜尋開關受控於第一搜尋信號以被導通或斷開。第二搜尋開關耦接在第二及式快閃記憶胞行對應的第二位元線以及匹配線間,第二搜尋開關受控於第二搜尋信號以被導通或斷開。The three-dimensional memory device of the present invention includes a flash memory bank and at least one tri-state content-addressable memory cell. The flash memory bank includes at least one memory cell array block. The tri-state content addressable memory cells include a first memory cell, a second memory cell, a first search switch and a second search switch. The first memory cell is set in the first and second flash memory cell rows. The second memory cell is arranged in the second and second flash memory cell rows. The first search switch is coupled between the first bit line and the match line corresponding to the first and type flash memory cell rows, and the first search switch is controlled by the first search signal to be turned on or off. The second search switch is coupled between the second bit line and the match line corresponding to the second and type flash memory cell rows, and the second search switch is controlled by the second search signal to be turned on or off.
基於上述,本發明透過使三維記憶體裝置中,不同的及式快閃記憶胞行中的兩個記憶胞相互結合,搭配對應的位元線開關以形成三態內容可定址記憶胞。其中,位元線開關用以作為搜尋開關,可降低搜尋動作中,三態內容可定址記憶胞所需要的功率消耗。並且,透過位元線開關來做為搜尋開關,不但可節省佈局面積上,還可提升可靠度,有效提升三態內容可定址記憶胞的整體效能。Based on the above, the present invention combines two memory cells in different NAND-type flash memory cell rows in a three-dimensional memory device, and cooperates with corresponding bit line switches to form a three-state content addressable memory cell. Wherein, the bit line switch is used as a search switch, which can reduce the power consumption required by the three-state content addressable memory cell during the search operation. Moreover, using the bit line switch as a search switch not only saves layout area, but also improves reliability and effectively improves the overall performance of the three-state content addressable memory cell.
請參照圖1,圖1繪示本發明一實施例的三態內容可定址記憶胞的示意圖。三態內容可定址記憶胞100設置在一及式(AND type)快閃記憶裝置中。三態內容可定址記憶胞100包括記憶胞MC1、MC2、搜尋開關BLT1、BLT2以及源極線開關SLT1以及SLT2。在本實施例中,搜尋開關BLT1、BLT2以及源極線開關SLT1以及SLT2皆可應用電晶體來建構,例如為N型電晶體。記憶胞MC1、MC2則可以為快閃記憶胞。Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a tri-state content-addressable memory cell according to an embodiment of the present invention. The tri-state content
記憶胞MC1、MC2分別被設置在不相同的及式快閃記憶胞行110以及120中。搜尋開關BLT1耦接在及式快閃記憶胞行110對應的位元線LBL1以及匹配線ML間。搜尋開關BLT2則耦接在及式快閃記憶胞行120對應的位元線LBL2以及匹配線ML間。在本實施例中,搜尋開關BLT1以及BLT2為及式快閃記憶裝置的位元線開關(bit line switch),匹配線ML則可以為一共同位元線(global bit line)。搜尋開關BLT1受控於搜尋信號SL以被導通或斷開,搜尋開關BLT2則受控於搜尋信號SLB以被導通或斷開。其中,基於不同的搜尋狀況,搜尋信號SL以及SLB可以為不同的電壓組合。例如,當進行第一邏輯狀態(例如為邏輯1)的搜尋動作時,搜尋信號SL以及SLB可以分別為邏輯高電壓以及邏輯低電壓;當進行第二邏輯狀態(例如為邏輯0)的搜尋動作時,搜尋信號SL以及SLB可以分別為邏輯低電壓以及邏輯高電壓;當進行第三邏輯狀態(例如為不在乎(don’t care))的搜尋動作時,搜尋信號SL以及SLB可以皆為邏輯低電壓。The memory cells MC1 and MC2 are respectively arranged in different flash
在另一方面,源極線開關SLT1耦接在及式快閃記憶胞行110對應的源極線LSL1以及參考接地電壓VSS間。源極線開關SLT2則耦接在及式快閃記憶胞行120對應的源極線LSL2以及參考接地電壓VSS間。源極線開關SLT1、SLT2分別受控於控制信號CT1、CT2。當三態內容可定址記憶胞100的搜尋動作進行時,源極線開關SLT1、SLT2可根據控制信號CT1、CT2而被導通。其中,源極線開關SLT1、SLT2可耦接至共同源極線(common source line),並透過共同源極線以接收參考接地電壓VSS。On the other hand, the source line switch SLT1 is coupled between the source line LSL1 corresponding to the flash
在本實施例中,記憶胞MC1、MC2耦接至相同的字元線WL0。在本發明其他實施例中,記憶胞MC1、MC2也可分別耦接至不相同的字元線,沒有一定的限制。In this embodiment, the memory cells MC1 and MC2 are coupled to the same word line WL0. In other embodiments of the present invention, the memory cells MC1 and MC2 may also be respectively coupled to different word lines, without any limitation.
以下請參照圖2,圖2繪示本發明圖1實施例的三態內容可定址記憶胞100的等效電路示意圖。在搜尋動作被執行時,基於源極線開關SLT1、SLT2皆被導通,記憶胞MC1、MC2的一端可接收參考接地電壓VSS。記憶胞MC1、MC2的另一端則分別耦接至搜尋開關BLT1、BLT2。搜尋開關BLT1、BLT2則耦接在記憶胞MC1、MC2與匹配線ML間。其中,搜尋開關BLT1、BLT2分別受控於搜尋信號SL以及SLB。Please refer to FIG. 2 below. FIG. 2 shows a schematic diagram of an equivalent circuit of the tri-state content
關於搜尋動作的細部動作,請參照圖3A至圖5C,圖3A至圖5C分別繪示本發明實施例的三態內容可定址記憶胞的搜尋動作的實施方式的示意圖。在圖3A至圖3C中,三態內容可定址記憶胞300記錄為第一邏輯狀態的資料,其中的記憶胞MC1為被程式化(program)的狀態,而記憶胞MC2則為被抹除(Erase)的狀態。當第一邏輯狀態的搜尋動作進行前的一初始時間區間中,匹配線ML上的匹配信號可以被預充電至一參考電壓,其中參考電壓大於參考接地電壓VSS。For the details of the search operation, please refer to FIGS. 3A to 5C . FIGS. 3A to 5C are respectively schematic diagrams illustrating the implementation of the search operation of the 3-state content addressable memory cell according to the embodiment of the present invention. In FIGS. 3A to 3C , the tri-state content-
在圖3A中,當第一邏輯狀態的搜尋動作進行時,搜尋信號SL為邏輯高電壓,搜尋信號SLB為邏輯低電壓。此時,基於記憶胞MC1為被截止的狀態,且搜尋開關BLT2也為被截止的狀態,匹配線ML與參考接地電壓VSS間不存在有導通的路徑,因此,匹配線ML上的匹配信號實質上可維持在參考電壓的準位上不改變。此時,可以判定第一邏輯狀態的搜尋動作的搜尋結果為匹配(match)。In FIG. 3A , when the search operation of the first logic state is in progress, the search signal SL is at a logic high voltage, and the search signal SLB is at a logic low voltage. At this time, since the memory cell MC1 is turned off and the search switch BLT2 is also turned off, there is no conduction path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML is essentially can remain unchanged at the level of the reference voltage. At this point, it may be determined that the search result of the search action in the first logic state is a match.
在圖3B中,當第二邏輯狀態的搜尋動作進行時,搜尋信號SL為邏輯低電壓,搜尋信號SLB為邏輯高電壓。此時,基於記憶胞MC2以及搜尋開關BLT2皆為被導通的狀態,記憶胞MC2以及搜尋開關BLT2形成在匹配線ML與參考接地電壓VSS間的一導通路徑。也因此,匹配線ML上的匹配信號可下降至等於參考接地電壓VSS。此時,可以判定第二邏輯狀態的搜尋動作的搜尋結果為不匹配(un-match)。In FIG. 3B , when the search operation of the second logic state is in progress, the search signal SL is at a logic low voltage, and the search signal SLB is at a logic high voltage. At this time, based on the state that both the memory cell MC2 and the search switch BLT2 are turned on, the memory cell MC2 and the search switch BLT2 form a conduction path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML can drop to be equal to the reference ground voltage VSS. At this point, it may be determined that the search result of the search action in the second logic state is an un-match.
在圖3C中,當第三邏輯狀態的搜尋動作進行時,搜尋信號SL為邏輯低電壓,搜尋信號SLB也為邏輯低電壓。此時,基於記憶胞MC1、搜尋開關BLT2以及BLT1皆為被截止的狀態,匹配線ML與參考接地電壓VSS間不存在有導通的路徑,因此,匹配線ML上的匹配信號實質上可維持在參考電壓的準位上不改變。此時,可以判定第三邏輯狀態的搜尋動作的搜尋結果為匹配。In FIG. 3C , when the search operation of the third logic state is in progress, the search signal SL is at a logic low voltage, and the search signal SLB is also at a logic low voltage. At this time, since the memory cell MC1, the search switches BLT2 and BLT1 are all in the off state, there is no conduction path between the match line ML and the reference ground voltage VSS, therefore, the match signal on the match line ML can be substantially maintained at The level of the reference voltage does not change. At this point, it may be determined that the search result of the search action in the third logic state is a match.
在圖4A至圖4C中,三態內容可定址記憶胞400記錄為第二邏輯狀態的資料,其中的記憶胞MC2為被程式化的狀態,而記憶胞MC1則為被抹除的狀態。當第一邏輯狀態的搜尋動作進行前的一初始時間區間中,匹配線ML上的匹配信號可以被預充電至一參考電壓。其中,參考電壓大於參考接地電壓VSS。In FIGS. 4A to 4C , the tri-state content-
在圖4A中,當第一邏輯狀態的搜尋動作進行時,搜尋信號SL為邏輯高電壓,搜尋信號SLB為邏輯低電壓。此時,基於記憶胞MC1以及搜尋開關BLT1皆為被導通的狀態,記憶胞MC1以及搜尋開關BLT1形成在匹配線ML與參考接地電壓VSS間的一導通路徑。也因此,匹配線ML上的匹配信號可下降至等於參考接地電壓VSS。此時,可以判定第二邏輯狀態的搜尋動作的搜尋結果為不匹配。In FIG. 4A , when the search operation of the first logic state is in progress, the search signal SL is at a logic high voltage, and the search signal SLB is at a logic low voltage. At this time, based on the state that both the memory cell MC1 and the search switch BLT1 are turned on, the memory cell MC1 and the search switch BLT1 form a conduction path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML can drop to be equal to the reference ground voltage VSS. At this time, it may be determined that the search result of the search action in the second logic state is mismatch.
在圖4B中,當第二邏輯狀態的搜尋動作進行時,搜尋信號SL為邏輯低電壓,搜尋信號SLB為邏輯高電壓。此時,基於記憶胞MC2以及搜尋開關BLT1皆為被截止的狀態,匹配線ML與參考接地電壓VSS間不存在導通路徑。也因此,匹配線ML上的匹配信號可維持等於參考電壓而不改變。此時,可以判定第二邏輯狀態的搜尋動作的搜尋結果為匹配。In FIG. 4B , when the search operation of the second logic state is in progress, the search signal SL is at a logic low voltage, and the search signal SLB is at a logic high voltage. At this time, since both the memory cell MC2 and the search switch BLT1 are turned off, there is no conduction path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML can remain equal to the reference voltage without changing. At this point, it may be determined that the search result of the search action in the second logic state is a match.
在圖4C中,當第三邏輯狀態的搜尋動作進行時,搜尋信號SL為邏輯低電壓,搜尋信號SLB也為邏輯低電壓。此時,基於記憶胞MC2、搜尋開關BLT2以及BLT1皆為被截止的狀態,匹配線ML與參考接地電壓VSS間不存在有導通的路徑,因此,匹配線ML上的匹配信號實質上可維持在參考電壓的準位上不改變。此時,可以判定第三邏輯狀態的搜尋動作的搜尋結果為匹配。In FIG. 4C , when the search operation of the third logic state is in progress, the search signal SL is at a logic low voltage, and the search signal SLB is also at a logic low voltage. At this time, since the memory cell MC2, the search switches BLT2 and BLT1 are all turned off, there is no conduction path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML can be substantially maintained at The level of the reference voltage does not change. At this point, it may be determined that the search result of the search action in the third logic state is a match.
在圖5A至圖5C中,三態內容可定址記憶胞500記錄為第三邏輯狀態的資料,其中的記憶胞MC1、MC2均為被程式化的狀態。當第三邏輯狀態的搜尋動作進行前的一初始時間區間中,匹配線ML上的匹配信號可以被預充電至一參考電壓,其中參考電壓大於參考接地電壓VSS。In FIG. 5A to FIG. 5C , the tri-state content-
在圖5A中,當第一邏輯狀態的搜尋動作進行時,搜尋信號SL為邏輯高電壓,搜尋信號SLB為邏輯低電壓。此時,基於記憶胞MC1、MC2均為被截止的狀態,且搜尋開關BLT2也為被截止的狀態,匹配線ML與參考接地電壓VSS間不存在有導通的路徑,因此,匹配線ML上的匹配信號實質上可維持在參考電壓的準位上不改變。此時,可以判定第一邏輯狀態的搜尋動作的搜尋結果為匹配。In FIG. 5A , when the search operation of the first logic state is in progress, the search signal SL is at a logic high voltage, and the search signal SLB is at a logic low voltage. At this time, since both the memory cells MC1 and MC2 are turned off, and the search switch BLT2 is also turned off, there is no conduction path between the matching line ML and the reference ground voltage VSS. Therefore, the matching line ML The matching signal can substantially maintain the level of the reference voltage unchanged. At this point, it may be determined that the search result of the search action in the first logic state is a match.
在圖5B中,當第二邏輯狀態的搜尋動作進行時,搜尋信號SL為邏輯低電壓,搜尋信號SLB為邏輯高電壓。此時,基於記憶胞MC1、MC2以及搜尋開關BLT1皆為被截止的狀態,匹配線ML與參考接地電壓VSS間不存在有導通的路徑,因此,匹配線ML上的匹配信號實質上可維持在參考電壓的準位上不改變。此時,可以判定第三邏輯狀態的搜尋動作的搜尋結果為匹配。In FIG. 5B , when the search operation of the second logic state is in progress, the search signal SL is at a logic low voltage, and the search signal SLB is at a logic high voltage. At this time, since the memory cells MC1, MC2 and the search switch BLT1 are all turned off, there is no conduction path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML can be substantially maintained at The level of the reference voltage does not change. At this point, it may be determined that the search result of the search action in the third logic state is a match.
在圖5C中,當第三邏輯狀態的搜尋動作進行時,搜尋信號SL為邏輯低電壓,搜尋信號SLB也為邏輯低電壓。此時,基於記憶胞MC1、MC2、搜尋開關BLT2以及BLT1皆為被截止的狀態,匹配線ML與參考接地電壓VSS間不存在有導通的路徑,因此,匹配線ML上的匹配信號實質上可維持在參考電壓的準位上不改變。此時,可以判定第三邏輯狀態的搜尋動作的搜尋結果為匹配。In FIG. 5C , when the search operation of the third logic state is in progress, the search signal SL is at a logic low voltage, and the search signal SLB is also at a logic low voltage. At this time, since the memory cells MC1, MC2, the search switches BLT2 and BLT1 are all turned off, there is no conduction path between the match line ML and the reference ground voltage VSS. Therefore, the match signal on the match line ML can be substantially turned off. The level of the reference voltage remains unchanged. At this point, it may be determined that the search result of the search action in the third logic state is a match.
值得一提的,在圖3A至圖5C的實施方式中,第一邏輯狀態與第二邏輯狀態互補,第三邏輯狀態為不在乎。細節上,第一邏輯狀態可以為邏輯1(或邏輯0),第二邏輯狀態可以為邏輯0(或邏輯1)。It is worth mentioning that in the embodiments shown in FIG. 3A to FIG. 5C , the first logic state is complementary to the second logic state, and the third logic state is don't care. In detail, the first logic state may be logic 1 (or logic 0), and the second logic state may be logic 0 (or logic 1).
此外,在本發明其他實施例中,在各種狀態的搜尋動作中,搜尋信號SL、SLB的電壓值的設定可以與上述說明不相同。其中。在本發明其他實施例,第一邏輯狀態的搜尋動作中,搜尋信號SL、SLB可以分別為邏輯低電壓以及邏輯高電壓;在第二邏輯狀態的搜尋動作中,搜尋信號SL、SLB則可以分別為邏輯高電壓以及邏輯低電壓;在第三邏輯狀態的搜尋動作中,搜尋信號SL、SLB則可以分別為邏輯高電壓。另外,當三態內容可定址記憶胞記錄為第三邏輯狀態的資料時,記憶胞MC1、MC2均為被抹除的狀態。在這樣的條件下,在邏輯狀態的搜尋動作中,當匹配線ML上的匹配信號維持等於參考電壓時,表示搜尋結果為不匹配;而當匹配線ML上的匹配信號下降至參考接地電壓時,表示搜尋結果為匹配。In addition, in other embodiments of the present invention, in various states of the search operation, the setting of the voltage values of the search signals SL and SLB may be different from the above description. in. In other embodiments of the present invention, in the search operation of the first logic state, the search signals SL and SLB can be logic low voltage and logic high voltage respectively; in the search operation of the second logic state, the search signals SL and SLB can be respectively are logic high voltage and logic low voltage; in the search action of the third logic state, the search signals SL and SLB can be respectively logic high voltage. In addition, when the three-state content-addressable memory cell records the data of the third logic state, the memory cells MC1 and MC2 are both in the state of being erased. Under such conditions, in the search action of the logic state, when the matching signal on the matching line ML remains equal to the reference voltage, it indicates that the search result is a mismatch; and when the matching signal on the matching line ML drops to the reference ground voltage , indicating that the search result is a match.
以下請參照圖6A以及圖6B,圖6A以及圖6B繪示本發明實施例的三維記憶體裝置及三態內容可定址記憶胞的搜尋開關的配置方式的不同實施方式的示意圖。在圖6A中,三維記憶體裝置600具有一記憶庫(bank),且記憶庫中包括多個記憶胞陣列區塊(tile)TL1、TL2。記憶胞陣列區塊TL1、TL2分別具有對應的位元線開關區610、620。位元線開關區610中具有位元線開關BLT5~BLT8,位元線開關區620中則具有位元線開關BLT1~BLT4。Please refer to FIG. 6A and FIG. 6B below. FIG. 6A and FIG. 6B are schematic diagrams illustrating different implementations of the three-dimensional memory device and the arrangement of the search switch of the three-state content addressable memory cell according to the embodiment of the present invention. In FIG. 6A , the three-
其中,三維記憶體裝置600中可設定一個或多個三態內容可定址記憶胞。在本實施例中,對應其中的一三態內容可定址記憶胞,位元線開關BLT1、BLT2可以做為三態內容可定址記憶胞的二搜尋開關。也就是說,對應同一三態內容可定址記憶胞的二搜尋開關可以設置在相同的記憶胞陣列區塊TL2中。其中,位元線開關BLT1、BLT2分別受控於搜尋信號SL以及SLB。Wherein, one or more three-state content-addressable memory cells can be set in the three-
值得一提的,在本實施例中,位元線開關BLT1~BLT4以及位元線開關BLT5~BLT8可共同耦接至共同位元線GBL。It is worth mentioning that, in this embodiment, the bit line switches BLT1 - BLT4 and the bit line switches BLT5 - BLT8 can be commonly coupled to the common bit line GBL.
在圖6B中,對應一三態內容可定址記憶胞的二搜尋開關則可以為位元線開關BLT1以及BLT5。也就是說,對應同一三態內容可定址記憶胞的二搜尋開關也可以分別設置在不相同的記憶胞陣列區塊TL1以及TL2中。其中,位元線開關BLT1、BLT5分別受控於搜尋信號SL以及SLB。In FIG. 6B , the two search switches corresponding to a tri-state content addressable memory cell can be bit line switches BLT1 and BLT5 . That is to say, the two search switches corresponding to the same tri-state content-addressable memory cell can also be respectively disposed in different memory cell array blocks TL1 and TL2 . Wherein, the bit line switches BLT1 and BLT5 are respectively controlled by the search signals SL and SLB.
以下請參照圖7,圖7繪示本發明實施例的三維記憶體裝置及三態內容可定址記憶胞的配置方式的不同實施方式的示意圖。在圖7中,三維記憶體裝置700具有一記憶庫(bank),且記憶庫中包括多個記憶胞陣列區塊(tile)TL1、TL2。記憶胞陣列區塊TL1、TL2分別具有對應的位元線開關區710、720。位元線開關區710中具有位元線開關BLT51~BLT81以及BLT52~BLT82,位元線開關區720中則具有位元線開關BLT11~BLT41以及BLT12~BLT42。Please refer to FIG. 7 below. FIG. 7 shows a schematic diagram of different implementations of the three-dimensional memory device and the arrangement of the three-state content addressable memory cells according to the embodiment of the present invention. In FIG. 7 , the three-
本實施例中,三維記憶體裝置700中可設置多個三態內容可定址記憶胞。其中,第一個三態內容可定址記憶胞包括記憶胞MC1以及MC2。記憶胞MC1以及MC2設置在相同的記憶胞陣列區塊TL2中。並且,記憶胞MC1以及MC2成對的排列在相鄰的二記憶胞行上。對應記憶胞MC1以及MC2,位元線開關BT21以及BT31可以做為搜尋開關。位元線開關BT21以及BT31共同耦接至共同位元線GBL。其中,共同位元線GBL可作為三態內容可定址記憶胞的匹配線。In this embodiment, a plurality of tri-state content-addressable memory cells can be set in the three-
另外,第二個三態內容可定址記憶胞包括記憶胞MC3以及MC4。記憶胞MC3以及MC4分別配置在不同的記憶胞陣列區塊TL1、TL2中。對應記憶胞MC3以及MC4,位元線開關BT12以及BT52可以做為搜尋開關。值得注意的,位元線開關BT12以及BT52共同耦接至共同位元線GBL,其中,共同位元線GBL可作為此三態內容可定址記憶胞的匹配線。In addition, the second tri-state content-addressable memory cell includes memory cells MC3 and MC4. The memory cells MC3 and MC4 are arranged in different memory cell array blocks TL1 and TL2 respectively. Corresponding to the memory cells MC3 and MC4, the bit line switches BT12 and BT52 can be used as search switches. It should be noted that the bit line switches BT12 and BT52 are commonly coupled to the common bit line GBL, wherein the common bit line GBL can be used as a match line of the tri-state content addressable memory cell.
值得一提的,在本發明實施例中,三維記憶體裝置中可以設置一個至多個三態內容可定址記憶胞。三維記憶體裝置可具有多個記憶胞陣列區塊。而多個的三態內容可定址記憶胞可以全部設置在單一個記憶胞陣列區塊中;或者,也可以散佈在多個不同的記憶胞陣列區塊中,沒有一定的限制。It is worth mentioning that, in the embodiment of the present invention, one or more tri-state content addressable memory cells may be set in the three-dimensional memory device. A three-dimensional memory device may have multiple memory cell array blocks. A plurality of tri-state content addressable memory cells can all be arranged in a single memory cell array block; or, they can also be distributed in a plurality of different memory cell array blocks, without certain limitation.
綜上所述,本發明的三態內容可定址記憶胞設置在及式快閃記憶體裝置中。透過利用位元線開關以作為搜尋開關,並利用共同位元線以作為匹配線。如此一來,搜尋開關所接收的搜尋信號的電壓,可以小於對應的字元線上的電壓,可節省所需的功率消耗。另外,單一位元線開關可利用單一電晶體來建構。並且,在不需要提升搜尋信號的電壓的前提下,可免除電壓偏移(level shifter)電路的設置,有效減低電路面積。另外,在搜尋動作中,搜尋開關至多提供一個電流路徑以通過對應的位元線,有效提升電路的可靠度。To sum up, the tri-state content addressable memory cell of the present invention is disposed in a flash memory device. By using bit line switches as search switches and using common bit lines as match lines. In this way, the voltage of the search signal received by the search switch can be lower than the voltage of the corresponding word line, which can save the required power consumption. Alternatively, a single bit line switch can be implemented using a single transistor. Moreover, under the premise that the voltage of the search signal does not need to be increased, the setting of a voltage shifter (level shifter) circuit can be dispensed with, thereby effectively reducing the circuit area. In addition, in the search operation, the search switch provides at most one current path to pass through the corresponding bit line, which effectively improves the reliability of the circuit.
100、300、400、500:三態內容可定址記憶胞
110、120:及式快閃記憶胞行
600、700:三維記憶體裝置
610、620、710、720:位元線開關區
BLT1、BLT2:搜尋開關/位元線開關
BLT3~BLT8、BLT51~BLT81、BLT52~BLT82:位元線開關
CT1、CT2:控制信號
GBL:共同位元線
LBL1、LBL2:位元線
LSL1、LSL2:源極線
MC1、MC2:記憶胞
ML:匹配線
SL、SLB:搜尋信號
SLT1、SLT2:源極線開關
TL1、TL2:記憶胞陣列區塊
VSS:參考接地電壓
WL0:字元線100, 300, 400, 500: three-state content
圖1繪示本發明一實施例的三態內容可定址記憶胞的示意圖。
圖2繪示本發明圖1實施例的三態內容可定址記憶胞100的等效電路示意圖。
圖3A至圖5C分別繪示本發明實施例的三態內容可定址記憶胞的搜尋動作的實施方式的示意圖。
圖6A以及圖6B繪示本發明實施例的三維記憶體裝置及三態內容可定址記憶胞的搜尋開關的配置方式的不同實施方式的示意圖。
圖7繪示本發明實施例的三維記憶體裝置及三態內容可定址記憶胞的配置方式的不同實施方式的示意圖。
FIG. 1 is a schematic diagram of a tri-state content addressable memory cell according to an embodiment of the present invention.
FIG. 2 is a schematic diagram of an equivalent circuit of the tri-state content-
100:三態內容可定址記憶胞 100: Tri-state content addressable memory cell
110、120:及式快閃記憶胞行 110, 120: NAND flash memory cell row
BLT1、BLT2:搜尋開關 BLT1, BLT2: search switch
CT1、CT2:控制信號 CT1, CT2: control signal
LBL1、LBL2:位元線 LBL1, LBL2: bit line
LSL1、LSL2:源極線 LSL1, LSL2: source line
MC1、MC2:記憶胞 MC1, MC2: memory cells
ML:匹配線 ML: Matching Line
SL、SLB:搜尋信號 SL, SLB: search signal
SLT1、SLT2:源極線開關 SLT1, SLT2: Source line switch
VSS:參考接地電壓 VSS: reference ground voltage
WL0:字元線 WL0: word line
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US6256216B1 (en) * | 2000-05-18 | 2001-07-03 | Integrated Device Technology, Inc. | Cam array with minimum cell size |
US6339540B1 (en) * | 2000-12-05 | 2002-01-15 | Tower Semiconductor Ltd. | Content-addressable memory for virtual ground flash architectures |
US7177183B2 (en) * | 2003-09-30 | 2007-02-13 | Sandisk 3D Llc | Multiple twin cell non-volatile memory array and logic block structure and method therefor |
US20090190404A1 (en) * | 2008-01-25 | 2009-07-30 | Roohparvar Frankie F | Nand flash content addressable memory |
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US6256216B1 (en) * | 2000-05-18 | 2001-07-03 | Integrated Device Technology, Inc. | Cam array with minimum cell size |
US6339540B1 (en) * | 2000-12-05 | 2002-01-15 | Tower Semiconductor Ltd. | Content-addressable memory for virtual ground flash architectures |
US7177183B2 (en) * | 2003-09-30 | 2007-02-13 | Sandisk 3D Llc | Multiple twin cell non-volatile memory array and logic block structure and method therefor |
US20090190404A1 (en) * | 2008-01-25 | 2009-07-30 | Roohparvar Frankie F | Nand flash content addressable memory |
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